Pulse perforation ablation control circuit

Abstract

The invention discloses a pulse perforation ablation control circuit which comprises a detection unit, an output unit and a comparison unit, the detection unit is connected with a configuration unit and the output unit, the detection unit detects a pulse waveform signal Vi < n >, and the comparison unit outputs the pulse waveform signal Vi < n >. When the initial low level state of the pulse waveform signal Vi n is converted into the high level and the high level is converted into the low level, pulse detection is carried out and the pulse waveform signal Vi n is fed back to the output unit and Vout2, the output unit carries out chopping and then feeds back Vout1, the Vout1 and / or the Vout2 are / is input to the comparison unit, and the comparison unit carries out detection and then outputs an alarm signal Vout3.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse ablation, and in particular to a pulse perforation ablation control circuit. Background Art

[0002] Pulsed electric field ablation refers to the application of intermittent high-intensity pulsed electric fields in a very short period of time, causing irreversible damage to the cell membrane through electroporation. The basis for the effect of electroporation on tissues is the electric field strength. The stronger the transmitted electric field, the greater the impact on the target tissue. However, as the electric field strength increases, the risk of heat generation will also increase, leading to a shift in thermal effects. Different power plant voltages correspond to different pulse durations. An increase in pulse duration will produce a greater electroporation effect on cells. The relationship between the two is not linear. A lower voltage is required to maintain a longer pulse. For the same number of electroporated cells, when the pulse duration is less than 1 millisecond, a higher voltage is required to achieve the same effect. For example, when the electric field strength is 137V / cm, a 100ms pulse can cause cell electroporation. When the electric field increases to 575V / cm, 100μs can cause cell electroporation. When the electric field strength rises to 10kV / cm, only a 150ns pulse is needed to achieve the same effect. Under the condition that the power plant voltage is guaranteed, the longer the pulse duration, the greater the possibility of irreversible injury and thermal damage. Therefore, the duration needs to be precisely controlled. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a pulse perforation ablation control circuit, including a detection unit, an output unit, and a comparison unit. The detection unit is connected to the configuration unit and the output unit. The detection unit detects the pulse waveform signal Vin, performs pulse detection and feeds back to the output unit and Vout_2 when the initial low level state of the pulse waveform signal Vin turns into a high level and the high level turns into a low level. The output unit feeds back Vout_1 after chopping, and Vout_1 and / or Vout_2 are input to the comparison unit. The comparison unit outputs an alarm signal Vout_3 after detection.

[0004] Further, the detection unit includes a trigger U1, an operational amplifier U2, an operational amplifier U3, a digital potentiometer U4, an inverter U5, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R11, a resistor R12, a resistor R13, a resistor R14, and a resistor R15;

[0005] The first pin and the fourth pin of the trigger U1, the first pin and the eighth pin of the digital potentiometer U4, and one end of the resistor R7 are connected to the power supply; the second pin and the sixth pin of the trigger U1 are connected, the third pin and one end of the resistor R11 and the output end of the inverter U5 are connected, the fifth pin and one end of the resistor R12 and the seventh pin of the digital potentiometer U4 are connected; the in-phase end of the operational amplifier U2, one end of the resistor R5 and Vi n is connected, the output end is connected to the second pin of the digital potentiometer U4, the input end of the inverter U5, and one end of the resistor R13; the in-phase end of the operational amplifier U3 is connected to one end of the resistor R6 and one end of the resistor R15, the inverting end is connected to one end of the resistor R8 and one end of the resistor R14, and the output end is connected to the other end of the resistor R14; the third pin of the digital potentiometer U4 is connected to the other end of the resistor R7 and the other end of the resistor R8; the fourth pin, the fifth pin, the sixth pin of the digital potentiometer U4, the other end of the resistor R5, the other end of the resistor R11, the other end of the resistor R12, the other end of the resistor R13, the other end of the resistor R15 and the ground are connected.

[0006] Further, the output unit includes a transistor Q1, a resistor R9, a resistor R10, and a capacitor C1;

[0007] The collector of the transistor Q1 is connected to the power supply, the base is connected to the output end of the operational amplifier U3, and the emitter is connected to one end of the resistor R9; the other end of the resistor R9, one end of the resistor R10, one end of the capacitor C1 are connected to Vout_1; the other end of the resistor R10, the other end of the capacitor C1 are connected to the ground.

[0008] Furthermore, the detection unit also includes a counter U6, a transistor Q2, a transistor Q3, a resistor R16, a resistor R17, and a diode D1;

[0009] The collector of the transistor Q2, the emitter of the transistor Q3, and the sixteenth pin of the counter U6 are connected to the power supply; the fifteenth pin of the counter U6 is connected to the tenth pin and the base of the transistor Q2 through Port, and the fourteenth pin is connected to Vin; the base of the transistor Q3 is connected to the emitter of the transistor Q2 and one end of the resistor R16, and the collector is connected to one end of the resistor R17 and the first pin of the trigger U1; the anode of the diode D1 is connected to the second pin of the trigger U1, and the cathode is connected to the fourth pin of the trigger U1; the eighth pin of the counter U6, the thirteenth pin, the other end of the resistor R16, the other end of the resistor R17 and the ground are connected.

[0010] Further, the comparison unit includes an operational amplifier U7;

[0011] The operational amplifier U7 has a non-inverting terminal connected to Vref, an inverting terminal connected to Vout_1, and an output terminal connected to Vout_3.

[0012] Furthermore, the comparison unit also includes a field effect transistor Q4;

[0013] The source of the field effect tube Q4 is connected to the output terminal of the operational amplifier U7, the gate is connected to the Port, and the drain is connected to Vout_3.

[0014] Further, the configuration unit includes a resistor R1, a resistor R2, a resistor R3, and a resistor R4;

[0015] One end of the resistor R2 and one end of the resistor R3 are connected to the power supply; the other end of the resistor R2 is connected to one end of the resistor R1 and the inverting end of the operational amplifier U2; the other end of the resistor R3 is connected to one end of the resistor R4 and the other end of the resistor R6; the other end of the resistor R1 and the other end of the resistor R4 are connected to the ground.

[0016] Furthermore, the indicating unit is connected to the comparing unit and is used for indicating the status after the comparing unit outputs.

[0017] Furthermore, the resistor R1 or the resistor R2 is an adjustable resistor.

[0018] Furthermore, the resistor R3 or the resistor R4 is an adjustable resistor.

[0019] The beneficial effects of the present invention compared with the prior art are:

[0020] The present invention can detect the full waveform of the discharge pulse, reduce the possibility of irreversible damage and thermal damage, and also provide a sampling method that can adjust the sampling accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 This is a circuit diagram of the detection unit and output unit provided by the present invention.

[0023] Figure 2 This is another circuit diagram of the detection unit and the output unit provided by the present invention.

[0024] Figure 3 This is a schematic diagram of a comparison unit circuit provided by the present invention.

[0025] Figure 4 Another circuit diagram of the comparison unit provided by the present invention. DETAILED DESCRIPTION

[0026] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0027] The present invention discloses a pulse perforation ablation control circuit, including a detection unit, an output unit, and a comparison unit. The detection unit is connected to a configuration unit and an output unit. The detection unit detects a pulse waveform signal Vin, performs pulse detection and feeds back to the output unit and Vout_2 when the initial low level state of the pulse waveform signal Vin changes to a high level and when the high level changes to a low level. The output unit feeds back Vout_1 after chopping, and Vout_1 and / or Vout_2 are input to the comparison unit. The comparison unit outputs an alarm signal Vout_3 after detection.

[0028] Specifically, the detection unit includes a trigger U1, an operational amplifier U2, an operational amplifier U3, a digital potentiometer U4, an inverter U5, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R11, a resistor R12, a resistor R13, a resistor R14, and a resistor R15;

[0029] The first pin and the fourth pin of the trigger U1, the first pin and the eighth pin of the digital potentiometer U4, and one end of the resistor R7 are connected to the power supply; the second pin and the sixth pin of the trigger U1 are connected, the third pin and one end of the resistor R11 and the output end of the inverter U5 are connected, the fifth pin and one end of the resistor R12 and the seventh pin of the digital potentiometer U4 are connected; the in-phase end of the operational amplifier U2, one end of the resistor R5 and Vi n is connected, the output end is connected to the second pin of the digital potentiometer U4, the input end of the inverter U5, and one end of the resistor R13; the in-phase end of the operational amplifier U3 is connected to one end of the resistor R6 and one end of the resistor R15, the inverting end is connected to one end of the resistor R8 and one end of the resistor R14, and the output end is connected to the other end of the resistor R14; the third pin of the digital potentiometer U4 is connected to the other end of the resistor R7 and the other end of the resistor R8; the fourth pin, the fifth pin, the sixth pin of the digital potentiometer U4, the other end of the resistor R5, the other end of the resistor R11, the other end of the resistor R12, the other end of the resistor R13, the other end of the resistor R15 and the ground are connected.

[0030] Specifically, the output unit includes a transistor Q1, a resistor R9, a resistor R10, and a capacitor C1;

[0031] The collector of the transistor Q1 is connected to the power supply, the base is connected to the output end of the operational amplifier U3, and the emitter is connected to one end of the resistor R9; the other end of the resistor R9, one end of the resistor R10, one end of the capacitor C1 are connected to Vout_1; the other end of the resistor R10, the other end of the capacitor C1 are connected to the ground.

[0032] Specifically, the detection unit also includes a counter U6, a transistor Q2, a transistor Q3, a resistor R16, a resistor R17, and a diode D1;

[0033] The collector of the transistor Q2, the emitter of the transistor Q3, and the sixteenth pin of the counter U6 are connected to the power supply; the fifteenth pin of the counter U6 is connected to the tenth pin and the base of the transistor Q2 through Port, and the fourteenth pin is connected to Vin; the base of the transistor Q3 is connected to the emitter of the transistor Q2 and one end of the resistor R16, and the collector is connected to one end of the resistor R17 and the first pin of the trigger U1; the anode of the diode D1 is connected to the second pin of the trigger U1, and the cathode is connected to the fourth pin of the trigger U1; the eighth pin of the counter U6, the thirteenth pin, the other end of the resistor R16, the other end of the resistor R17 and the ground are connected.

[0034] Specifically, the comparison unit includes an operational amplifier U7;

[0035] The operational amplifier U7 has a non-inverting terminal connected to Vref, an inverting terminal connected to Vout_1, and an output terminal connected to Vout_3.

[0036] Specifically, the comparison unit also includes a field effect transistor Q4;

[0037] The source of the field effect tube Q4 is connected to the output terminal of the operational amplifier U7, the gate is connected to the Port, and the drain is connected to Vout_3.

[0038] Specifically, the configuration unit includes a resistor R1, a resistor R2, a resistor R3, and a resistor R4;

[0039] One end of the resistor R2 and one end of the resistor R3 are connected to the power supply; the other end of the resistor R2 is connected to one end of the resistor R1 and the inverting end of the operational amplifier U2; the other end of the resistor R3 is connected to one end of the resistor R4 and the other end of the resistor R6; the other end of the resistor R1 and the other end of the resistor R4 are connected to the ground.

[0040] Specifically, the indicating unit is connected to the comparing unit and is used for indicating the status after the comparing unit outputs.

[0041] Specifically, the resistor R1 or the resistor R2 is an adjustable resistor.

[0042] Specifically, the resistor R3 or the resistor R4 is an adjustable resistor.

[0043] In one embodiment, a method for detecting a pulse waveform to reduce the possibility of irreversible damage and thermal damage is provided, wherein Vin inputs the current pulse waveform signal, Vout_1 feeds back the current pulse waveform width voltage signal, the Vin signal is fed back to the in-phase terminal of the operational amplifier U2, and when the pulse is at a low level, it is pulled down by the resistor R5, and the inverting terminal of the operational amplifier U2 sets a reference signal, and the reference signal is greater than Vin without input and less than Vi n input voltage signal, when there is no input at the in-phase terminal of op amp U2, op amp U2 is cut off, and the output signal of op amp U2 is fed back to pin 2 of digital potentiometer U4. Pin 2 is the adjustment pin, which is used to adjust the adjustment direction of pin 5 of digital potentiometer U4 from pin 3 or pin 6. Pin 3 of digital potentiometer U4 is connected in series with resistor R7. After the input of pin 2 of digital potentiometer U4, the voltage at the connection terminal of pin 3 of digital potentiometer U4 and resistor R7 is adjusted, and after negative feedback from resistors R8 and R14, it is input to the inverting terminal of op amp U3. The in-phase terminal of op amp U3 inputs the maximum adjustment voltage at the connection terminal of digital potentiometer U4 and resistor R7 through resistor R6, and is divided by resistor R15, that is, Vi at the initial power-on. The low-level stage from low to high makes the maximum adjustment voltage of the operational amplifier U2 when there is no output. In the low-level stage, the operational amplifier U3 has no output, the transistor Q1 cuts off the capacitor C1 through the resistor R10 loop, and there is no voltage at the capacitor C1 end. At the same time, the output signal of the operational amplifier U2 is also inverted by the inverter U5 and input to the third pin of the trigger U1. In the initial state, the inverter U5 outputs, the 5th pin of the trigger U1 is cut off, and the 6th pin of the trigger U1 is fed back to the 2nd pin. This stage is the waiting stage for the input of Vin. After n is input, when it changes from low level to high level, the output of operational amplifier U2 controls the reverse adjustment of digital potentiometer U4, and the voltage at the connection end of pin 3 of digital potentiometer U4 and resistor R7 drops. At the same time, inverter U5 is turned off, and pin 3 of trigger U1 is pulled down through resistor R11. As the high level ends, it enters the low level process. Operational amplifier U3 gradually outputs differential signals to the base of transistor Q1. The collector power supply of transistor Q1 is input to capacitor C1 through the emitter and resistor R9. The voltage at the end of capacitor C1 rises. After the high level ends and enters the low level again, operational amplifier U2 is turned off, and inverter U5 is input again. Pin 3 of trigger U1 has the function of changing from low level to high level. Pin 5 of trigger U1 inputs the signal to pin 7 of digital potentiometer U4. Pin 7 is a sleep pin and is enabled when the level is high. Digital potentiometer U4 is turned off, and the output of operational amplifier U3 is fixed. Capacitor C1 passes through the resistor R10 circuit and changes with Vi When n changes from low level to high level again, the inverter U5 is turned off, and the 3-pin of the trigger U1 is connected through the resistor R11 loop. When it changes from high level to low level, the inverter U5 outputs, the 5-pin of the trigger U1 is turned off, the digital potentiometer U4 is called back, the operational amplifier U3 is differential again, the transistor Q1 reduces the amplification factor, and the capacitor C1 chops the high and low level widths in this process, and its effective voltage is fed back to Vout_1.The comparison unit compares Vout_1 with the preset pulse waveform width voltage to determine whether the current exceeds the preset pulse waveform width. This method is full pulse input waveform sampling, that is, the low-level and high-level pulse waveform widths are sampled from the initial state-high-low-high-low respectively. After passing through the above circuit, the capacitor C1 completes the chopped output. When the high-level width is too high, the capacitor C1 voltage rises, and the comparison unit outputs an alarm after comparison. ,

[0044] In one embodiment, based on the above embodiment, another method for detecting the pulse waveform to reduce the possibility of irreversible damage and thermal damage is provided. Compared with the above method, the difference is that the sampling accuracy is adjustable. This embodiment feeds back the current pulse waveform width voltage signal through Vout_2, and at the same time, the 4th pin and the 1st pin of the trigger U1 are connected in series with the resistor R18 and the resistor R17 respectively. The 4th pin and the 1st pin are set pins. The 1st pin of the trigger U1 is controlled by the transistor Q3 to be set. The 4th pin of the trigger U1 locks the initial state of the inverter U5 through the diode D1, and then the 5th pin of the trigger U1 is output again. The sampling accuracy is selected at the right output end of the counter U6. The attached figure shows the 1 / 4 waveform sampling accuracy. That is, the 3rd pin, the 2nd pin, the 4th pin, and the 7th pin of the counter U6 are detected, and the 10th pin is reset. When Vi After the waveform of the input of VI n changes from the initial low level state to the low level state again, the 5th pin of the trigger U1 is output, and the 4th pin of the trigger U1 is set to the high level output state through the resistor R18 loop. The 7th pin of the digital potentiometer U4 is input enable sleep, the digital potentiometer U4 is cut off, and the output is output to Vout_2 after the differential of the operational amplifier U3. The comparison unit compares the differential value output by the operational amplifier U3 to confirm whether it exceeds the set pulse waveform width. At the same time, the waveform output by VI n is also fed back to the 14th pin of the counter U6. n conversion makes the right output pin of counter U6 jump to pin 10 in turn, and then one path is fed back to pin 15 through Port to reset counter U6, and the other path is input to the base of transistor Q2. The power supply signal of transistor Q2 is input to the base of transistor Q3 through the collector and emitter of transistor Q2, and transistor Q3 is cut off. Pin 1 of trigger U1 sets pin 5 of trigger U1 to a low level cut-off state through the resistor R17 loop, and pin 6 of trigger U1 outputs a signal again and is fed back to pin 4 through diode D1, and trigger U1 is reset. During this period, digital potentiometer U4 is always in the cut-off state. After pin 15 of counter U6 is input, the right output pin of counter U6 becomes pin 3 input, waiting for Vin to be input again. When other sampling accuracy is required, the connection position of the right pin of counter U6 with Port can be changed. For example, when 1 / 8 waveform sampling is used, pin 10 of counter U6 is removed from being connected to Port, and pin 9 is changed to be connected to Port. The number of bits is increased by 1. First, the fixed output of pin 3 of counter U6 when Vin has no input in the initial state is removed.

[0045] When full-waveform pulse sampling is adopted in the comparison unit, the preset pulse waveform width signal is input to the in-phase terminal of the operational amplifier U7 through Vref, and the operational amplifier U7 outputs the alarm signal Vout_3 after comparing the in-phase terminal and the inverting terminal; when adjustable precision is adopted, the operational amplifier U7 and the alarm signal Vout_3 are connected in series with a field effect tube Q4, and the gate of the field effect tube Q4 is connected to the Port. When the counter U6 outputs the reset stage, the output of Vout_3 is stopped, and the inverting terminal of the operational amplifier U7 is used to set a conversion switch, and the two input terminals of the conversion switch are connected to Vout_1 and Vout_2, and the output terminal is connected to the inverting terminal of the operational amplifier U7. The conversion switch is not shown in the attached figure; in addition to the voltage divider setting, the signals of the inverting terminal of the operational amplifier U2 and the input terminal of the resistor R6 can also be input through the upper-level chip, wherein either the resistor R1 or the resistor R2 can be replaced with an adjustable resistor, and either the resistor R3 or the resistor R4 can be replaced with an adjustable resistor.

[0046] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A pulse perforation ablation control circuit, characterized in that: It includes a detection unit, an output unit, and a comparison unit. The detection unit is connected to the configuration unit and the output unit. The detection unit detects the pulse waveform signal Vin, performs pulse detection when the initial low level state of the pulse waveform signal Vin changes to a high level and when the high level changes to a low level, and feeds back the pulse to the output unit and Vout_2. The output unit feeds back Vout_1 after chopping, and Vout_1 and / or Vout_2 are input to the comparison unit. The comparison unit outputs an alarm signal Vout_3 after detection.

2. The pulse perforation ablation control circuit according to claim 1, characterized in that: The detection unit includes a trigger U1, an operational amplifier U2, an operational amplifier U3, a digital potentiometer U4, an inverter U5, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R11, a resistor R12, a resistor R13, a resistor R14, and a resistor R15; The first pin and the fourth pin of the trigger U1, the first pin and the eighth pin of the digital potentiometer U4, and one end of the resistor R7 are connected to the power supply; the second pin and the sixth pin of the trigger U1 are connected, the third pin and one end of the resistor R11 and the output end of the inverter U5 are connected, the fifth pin and one end of the resistor R12 and the seventh pin of the digital potentiometer U4 are connected; the in-phase end of the operational amplifier U2 and one end of the resistor R5 are connected to Vin, and the output end is connected to the second pin of the digital potentiometer U4, the input end of the inverter U5, and the resistor R13. The first end is connected to the output terminal of the operational amplifier U3; the non-inverting end is connected to one end of the resistor R6 and one end of the resistor R15, the inverting end is connected to one end of the resistor R8 and one end of the resistor R14, and the output terminal is connected to the other end of the resistor R14; the third pin of the digital potentiometer U4 is connected to the other end of the resistor R7 and the other end of the resistor R8; the fourth pin, the fifth pin, the sixth pin of the digital potentiometer U4, the other end of the resistor R5, the other end of the resistor R11, the other end of the resistor R12, the other end of the resistor R13, the other end of the resistor R15 and the ground terminal are connected.

3. The pulse perforation ablation control circuit according to claim 1, characterized in that: The output unit includes a transistor Q1, a resistor R9, a resistor R10, and a capacitor C1; The collector of the transistor Q1 is connected to the power supply, the base is connected to the output end of the operational amplifier U3, and the emitter is connected to one end of the resistor R9; the other end of the resistor R9, one end of the resistor R10, one end of the capacitor C1 are connected to Vout_1; the other end of the resistor R10, the other end of the capacitor C1 are connected to the ground.

4. The pulse perforation ablation control circuit according to claim 2, characterized in that: The detection unit also includes a counter U6, a transistor Q2, a transistor Q3, a resistor R16, a resistor R17, and a diode D1; The collector of the transistor Q2, the emitter of the transistor Q3, and the sixteenth pin of the counter U6 are connected to the power supply; the fifteenth pin of the counter U6 is connected to the tenth pin and the base of the transistor Q2 through Port, and the fourteenth pin is connected to Vin; the base of the transistor Q3 is connected to the emitter of the transistor Q2 and one end of the resistor R16, and the collector is connected to one end of the resistor R17 and the first pin of the trigger U1; the anode of the diode D1 is connected to the second pin of the trigger U1, and the cathode is connected to the fourth pin of the trigger U1; the eighth pin of the counter U6, the thirteenth pin, the other end of the resistor R16, the other end of the resistor R17 and the ground are connected.

5. The pulse perforation ablation control circuit according to claim 1, characterized in that: The comparison unit includes an operational amplifier U7; The operational amplifier U7 has a non-inverting terminal connected to Vref, an inverting terminal connected to Vout_1, and an output terminal connected to Vout_3.

6. The pulse perforation ablation control circuit according to claim 5, characterized in that: The comparison unit also includes a field effect transistor Q4; The source of the field effect tube Q4 is connected to the output terminal of the operational amplifier U7, the gate is connected to the Port, and the drain is connected to Vout_3.

7. The pulse perforation ablation control circuit according to claim 1, characterized in that: It also includes a configuration unit, the configuration unit includes a resistor R1, a resistor R2, a resistor R3, and a resistor R4; One end of the resistor R2 and one end of the resistor R3 are connected to the power supply; the other end of the resistor R2 is connected to one end of the resistor R1 and the inverting end of the operational amplifier U2; the other end of the resistor R3 is connected to one end of the resistor R4 and the other end of the resistor R6; the other end of the resistor R1 and the other end of the resistor R4 are connected to the ground.

8. The pulse perforation ablation control circuit according to claim 1, characterized in that: It also includes an indication unit, which is connected to the comparison unit and is used for indicating the status after the comparison unit outputs.

9. The pulse perforation ablation control circuit according to claim 7, characterized in that: The resistor R1 or the resistor R2 is an adjustable resistor.

10. The pulse perforation ablation control circuit according to claim 7, characterized in that: The resistor R3 or the resistor R4 is an adjustable resistor.

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