Circuit for enhancing input impedance of chopper amplifier and control method thereof

Abstract

The invention discloses a circuit for enhancing the input impedance of a chopper amplifier and a control method of the circuit. The circuit comprises an OTA operational amplifier module, a chopper module, an input capacitor, a feedback capacitor, a peak value detector, a valley value detector, a subtracter, a comparison integrator and a variable capacitor. The method comprises the following steps: acquiring a differential input signal and carrying out chopping and amplification processing to obtain an output signal; carrying out peak detection processing to obtain a positive peak voltage and a negative peak voltage; performing subtraction calculation to obtain a peak-to-peak value of the OTA signal; carrying out integral operation and ripple filtering processing to obtain a direct current voltage signal with amplitude information; and the differential input signal is converted into a direct current signal with amplitude information, and current compensation is carried out on the differential input signal through a positive feedback loop. According to the embodiment of the invention, on-chip parasitic capacitance can be accurately compensated, so that the current of a signal source is not absorbed, and the input impedance of the chopping capacitance coupling instrument amplifier is enhanced. The method can be widely applied to the technical field of analog integrated circuit design.

Description

Technical Field

[0001] The present application relates to the technical field of analog integrated circuit design, and in particular to a circuit for enhancing the input impedance of a chopper amplifier and a control method thereof. Background Art

[0002] Capacitor-coupled instrumentation amplifier structures have been widely used in wearable medical devices due to their low noise and high energy efficiency. Chopper stabilization technology is often used to assist capacitor-coupled instrumentation amplifiers to reduce flicker noise, thereby improving the system's noise-to-energy ratio. However, in the input stage of this combined structure, the chopper periodically charges and discharges the amplifier's input capacitance, causing the amplifier's input impedance to be significantly reduced, which will cause the common-mode rejection ratio to degrade and the signal amplitude to be severely attenuated. At the same time, the input impedance of the instrumentation amplifier is also limited by the influence of the chip's internal pin parasitics and input stage. The chip's internal pin parasitics usually come from the parasitic capacitance of the printed circuit board (PCB), PAD, and on-chip ESD, and the chip's internal parasitics mainly exist between the parasitic capacitance of the amplifier input and other nodes in the chip. These parasitics may cause the input impedance to decrease, causing signal loss, phase shift, and circuit instability, which is also the reason why the amplifier's operating frequency band becomes narrower.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a circuit and a control method for enhancing the input impedance of a chopper amplifier, which can accurately compensate for on-chip parasitic capacitance, thereby not drawing current from a signal source and enhancing the input impedance of a chopper capacitor-coupled instrument amplifier.

[0005] To achieve the above-mentioned purpose, an embodiment of the present application provides a circuit for enhancing the input impedance of a chopper amplifier, the circuit comprising an OTA operational amplifier module, a chopper module, an input capacitor, a feedback capacitor, a peak detector, a valley detector, a subtractor, a comparison integrator and a variable capacitor, the chopper module comprising a first-stage chopper, a second-stage chopper, a third-stage chopper and a fourth-stage chopper, the second end of the first-stage chopper is respectively connected to the first end of the input capacitor and the first end of the variable capacitor, the second end of the input capacitor is respectively connected to the first end of the feedback capacitor and the first end of the OTA operational amplifier module, the second end of the feedback capacitor is respectively connected to the The first end of the third-stage chopper is connected, the second end of the OTA op amp module is connected to the first end of the second-stage chopper, the second end of the variable capacitor is connected to the first end of the fourth-stage chopper, the second end of the fourth-stage chopper, the second end of the third-stage chopper, the second end of the second-stage chopper, the input end of the peak detector and the input end of the valley detector are connected, the output end of the peak detector and the output end of the valley detector are both connected to the input end of the subtractor, the output end of the subtractor is connected to the input end of the comparison integrator, and the output end of the comparison integrator is connected to the input end of the variable capacitor, wherein:

[0006] The chopper module is used to perform chopping processing on the input differential signal to obtain a chopped input differential signal;

[0007] The OTA operational amplifier module is used to amplify the chopped input differential signal to obtain an amplified input differential signal;

[0008] The peak detector and the valley detector are used to perform peak detection processing on the amplified input differential signal to obtain a positive peak voltage and a negative peak voltage;

[0009] The subtractor is used to perform subtraction calculation on the positive peak voltage and the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0010] The comparison integrator is used to perform integration operation on the peak-to-peak value of the OTA signal and filter out ripples to obtain a DC voltage signal with amplitude information;

[0011] The input capacitor, the feedback capacitor and the variable capacitor are used to convert the DC voltage signal with amplitude information and compensate the input differential signal.

[0012] In some embodiments, the peak detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor, and a first ammeter, wherein a source of the first transistor, a source of the second transistor, a source of the third transistor, a source of the fourth transistor, a source of the fifth transistor, a source of the sixth transistor, a source of the seventh transistor, and a source of the eighth transistor are connected, a gate of the first transistor, a gate of the second transistor, and a drain of the second transistor are connected to a drain of the tenth transistor, and a drain of the first transistor, a drain of the ninth transistor, a drain of the third transistor, and a gate of the third transistor are connected to a drain of the fourth transistor. The gate of the first transistor is connected to the gate of the second transistor, the source of the ninth transistor, the source of the tenth transistor and the drain of the thirteenth transistor are connected, the source of the thirteenth transistor, the second end of the first ammeter, the second end of the first capacitor and the source of the fourteenth transistor are connected, the drain of the fourth transistor, the gate of the tenth transistor, the first end of the first ammeter, the drain of the fifth transistor, the first end of the first capacitor and the gate of the eleventh transistor are connected, the gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor and the drain of the twelfth transistor are connected, the gate of the seventh transistor, the drain of the seventh transistor and the gate of the eighth transistor are connected to the drain of the eleventh transistor, and the source of the eleventh transistor and the source of the twelfth transistor are connected to the drain of the fourteenth transistor.

[0013] In some embodiments, the valley detector includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a second capacitor, and a second ammeter, wherein a source of the fifteenth transistor, a source of the sixteenth transistor, a first end of the second capacitor, and a first end of the second ammeter are connected, a drain of the fifteenth transistor, a source of the seventeenth transistor are connected to a source of the eighteenth transistor, a drain of the seventeenth transistor, a drain of the twenty-first transistor, a drain of the twenty-third transistor, and a gate of the twenty-third transistor are connected to a gate of the twenty-fourth transistor, and a drain of the eighteenth transistor, a drain of the twenty-second transistor, and a gate of the twenty-first transistor are connected to a gate of the twenty-second transistor. The gate of the eighteenth transistor, the second end of the second capacitor, the second end of the second ammeter, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor and the gate of the nineteenth transistor are connected, the drain of the nineteenth transistor, the drain of the twenty-seventh transistor, and the gate of the twenty-eighth transistor are connected, the drain of the twenty-sixth transistor and the source of the nineteenth transistor are connected to the source of the twentieth transistor, the drain of the twentieth transistor, the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-fifth transistor are connected to the gate of the twenty-sixth transistor, the source of the twenty-first transistor, the source of the twenty-second transistor, the source of the twenty-third transistor, the source of the twenty-fourth transistor, the source of the twenty-fifth transistor, the source of the twenty-sixth transistor, the source of the twenty-seventh transistor and the source of the twenty-eighth transistor are connected.

[0014] In some embodiments, the subtractor includes a first operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the second end of the third resistor and the first end of the fourth resistor are connected to the negative input terminal of the first operational amplifier, the second end of the first resistor and the first end of the second resistor are connected to the positive input terminal of the first operational amplifier, the second end of the fourth resistor is connected to the output terminal of the first operational amplifier, and the second resistor is grounded.

[0015] In some embodiments, the comparison integrator includes a second operational amplifier, a fifth resistor, a sixth resistor and a third capacitor, wherein the second end of the fifth resistor, the first end of the sixth resistor, and the first end of the third capacitor are connected to the negative input terminal of the second operational amplifier, and the second end of the sixth resistor and the second end of the third capacitor are connected to the output terminal of the second operational amplifier.

[0016] In some embodiments, the variable capacitor includes a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor and a MOS varactor, wherein the second end of the fourth capacitor, the second end of the seventh resistor and the first end of the MOS varactor are connected, and the second end of the MOS varactor, the second end of the eighth resistor and the first end of the fifth capacitor are connected.

[0017] To achieve the above object, another aspect of an embodiment of the present application provides a control method for a circuit for enhancing the input impedance of a chopper amplifier, the method comprising the following steps:

[0018] Acquire a differential input signal and perform chopping and amplification processing to obtain a first output signal and a second output signal;

[0019] Performing peak detection processing on the first output signal and the second output signal to obtain a positive peak voltage and a negative peak voltage;

[0020] Subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0021] Performing integration operation on the peak-to-peak value of the OTA signal and filtering out ripples to obtain a DC voltage signal with amplitude information;

[0022] The DC voltage signal with amplitude information is converted into a DC current signal with amplitude information, and current compensation is performed on the differential input signal through a positive feedback loop.

[0023] In some embodiments, the step of integrating the peak-to-peak value of the OTA signal and filtering out the ripple to obtain a DC voltage signal with amplitude information includes:

[0024] Set the reference voltage of the comparison integrator according to the ideal amplitude of the amplifier;

[0025] Integrate the peak-to-peak value of the OTA signal with the reference voltage to obtain a control voltage;

[0026] The control voltage is subjected to ripple filtering to obtain the DC voltage signal with amplitude information.

[0027] In some embodiments, the expression of the DC voltage signal with amplitude information is:

[0028]

[0029] In the above formula, V ouf Represents a DC voltage signal with amplitude information, V inf- Represents the peak-to-peak value of the OTA signal, V REF Indicates the reference voltage, C 3 Represents the third capacitance value, R 5 represents the fifth resistance value.

[0030] In some embodiments, the positive feedback loop includes a positive feedback loop and a negative feedback loop, the positive feedback loop is composed of an input capacitor and a variable capacitor, and the negative feedback loop is composed of an input capacitor and a feedback capacitor.

[0031] The embodiments of the present application include at least the following beneficial effects: The present application provides a circuit for enhancing the input impedance of a chopper amplifier and a control method thereof. The scheme is based on oscillation detection, and automatic calibration is achieved by introducing a comparison integrator. An input capacitor, a feedback capacitor and a variable capacitor are further introduced to form a positive feedback loop to compensate for the input differential signal. The on-chip parasitic capacitance can be compensated by adjusting the strength of the positive feedback by detecting the oscillation amplitude. The variable capacitor is further introduced to achieve decoupling of the control signal and the input signal. The circuit has high linearity and a wide tuning range, and can accurately compensate for the on-chip parasitic capacitance, thereby not drawing current from the signal source, and enhancing the input impedance of the chopper capacitor-coupled instrument amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic structural diagram of a circuit for enhancing the input impedance of a chopper amplifier provided in an embodiment of the present application;

[0033] Figure 2 It is a schematic diagram of the steps of a control method of a circuit for enhancing the input impedance of a chopper amplifier provided in an embodiment of the present application;

[0034] Figure 3 Schematic diagram of the circuit principle of the peak detector provided in the embodiment of the present application;

[0035] Figure 4 Schematic diagram of the circuit principle of the valley detector provided in the embodiment of the present application;

[0036] Figure 5 Schematic diagram of the circuit principle of the subtractor provided in the embodiment of the present application;

[0037] Figure 6 is a schematic diagram of the circuit principle of the comparison integrator provided in an embodiment of the present application;

[0038] Figure 7 is a schematic diagram of the circuit principle of a variable capacitor provided in an embodiment of the present application;

[0039] Figure 8 is a schematic diagram of the structure of a MOS varactor diode provided in an embodiment of the present application;

[0040] Fig. 9 is the control voltage V provided in the embodiment of the present application C Schematic diagram of the relationship with capacitance value.

[0041] Figure numerals: 1. OTA op amp module; 201. first-stage chopper; 202. second-stage chopper; 203. third-stage chopper; 204. fourth-stage chopper; 3. input capacitor; 4. feedback capacitor; 5. peak detector; 6. valley detector; 7. subtractor; 8. comparison integrator; 9. variable capacitor. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0043] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0044] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0046] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0047] Chopper and input capacitor C IN The combination of can be regarded as an equivalent resistor, and this resistance value is the input impedance Z of the instrumentation amplifier. IN , which can be expressed as:

[0048]

[0049] where f chop is the chopping frequency. The input impedance is inversely proportional to the input capacitor size and the chopping frequency. In an instrumentation amplifier, the input capacitor should be large enough to minimize the total system noise and closed-loop gain error caused by parasitic capacitance, but large input capacitors reduce the input impedance. In addition, the chopping frequency should be much higher than the intersection of flicker noise and thermal noise to mitigate residual flicker noise, which further reduces the input impedance. This makes it difficult to achieve a high-impedance, low-noise instrumentation amplifier without using enhancement techniques.

[0050] There are some shortcomings in the related art, such as the use of a positive feedback loop to increase the input impedance of the amplifier. This is because most of the charging current is provided by the feedback loop and does not draw the signal source current, so that a larger signal voltage can be obtained at the input of the instrumentation amplifier. However, this technology is not ideal in high-gain amplifiers because it is difficult to achieve high-precision low-value capacitors in the process. And for amplifiers with different gains, the value of the positive feedback capacitor needs to be reconfigured to adapt to the gain of different instrumentation amplifiers. Another impedance enhancement technology is to use an auxiliary pre-charge buffer, which increases the input impedance by providing the required charging current in each switching interval. However, these buffers work in a duty cycle manner, which introduces additional noise and gain mismatch, resulting in performance degradation of the instrumentation amplifier.

[0051] In view of this, a circuit for enhancing the input impedance of a chopper amplifier is provided in an embodiment of the present application. Calibration based on oscillation detection can realize automatic calibration without manual fine-tuning. The compensation of on-chip parasitic capacitance can be realized by adjusting the strength of positive feedback by detecting the oscillation amplitude. The decoupling of the control signal and the input signal is realized by the variable capacitor, and the circuit has high linearity and wide tuning range characteristics. Furthermore, a capacitance resolution exceeding femtofarads can be realized, so that the circuit will not be limited by the traditional capacitor array LSB. Moreover, since the on-chip parasitic capacitance is accurately compensated, the current of the signal source will not be drawn, and the ultra-high input impedance of the chopper capacitor-coupled instrument amplifier can be realized, and additional noise and gain mismatch will not be introduced. The circuit is suitable for instrument amplifiers with different gains.

[0052] Reference Figure 1 , Figure 1 A schematic diagram of a circuit for enhancing the input impedance of a chopper amplifier provided by an embodiment of the present invention, referring to Figure 1 The circuit includes an OTA operational amplifier module 1, a chopper module, an input capacitor 3, a feedback capacitor 4, a peak detector 5, a valley detector 6, a subtractor 7, a comparison integrator 8 and a variable capacitor 9. The chopper module includes a first-stage chopper 201, a second-stage chopper 202, a third-stage chopper 203 and a fourth-stage chopper 204. The second end of the first-stage chopper is respectively connected to the first end of the input capacitor and the first end of the variable capacitor, the second end of the input capacitor is respectively connected to the first end of the feedback capacitor and the first end of the OTA operational amplifier module, and the second end of the feedback capacitor is connected to the fourth-stage chopper 204. The first end of the three-stage chopper is connected, the second end of the OTA op amp module is connected to the first end of the second-stage chopper, the second end of the variable capacitor is connected to the first end of the fourth-stage chopper, the second end of the fourth-stage chopper, the second end of the third-stage chopper, the second end of the second-stage chopper, the input end of the peak detector and the input end of the valley detector are connected, the output end of the peak detector and the output end of the valley detector are both connected to the input end of the subtractor, the output end of the subtractor is connected to the input end of the comparison integrator, and the output end of the comparison integrator is connected to the input end of the variable capacitor, wherein:

[0053] The chopper module is used to chop the input differential signal to obtain a chopped input differential signal;

[0054] The OTA operational amplifier module is used to amplify the chopped input differential signal to obtain an amplified input differential signal;

[0055] The peak detector and the valley detector are used to perform peak detection processing on the amplified input differential signal to obtain a positive peak voltage and a negative peak voltage;

[0056] In this embodiment, if Figure 3 As shown, the peak detector includes a first transistor M1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 , the seventh transistor M 7 , the eighth transistor M 8 , the ninth transistor M 9 , the tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the first capacitor C 1 and the first ammeter I b1 , wherein the source of the first transistor, the source of the second transistor, the source of the third transistor, the source of the fourth transistor, the source of the fifth transistor, the source of the sixth transistor, the source of the seventh transistor and the source of the eighth transistor are connected, the gate of the first transistor, the gate of the second transistor, the drain of the second transistor and the drain of the tenth transistor are connected, the drain of the first transistor, the drain of the ninth transistor, the drain of the third transistor, the gate of the third transistor and the gate of the fourth transistor are connected, the source of the ninth transistor, the source of the tenth transistor and the drain of the thirteenth transistor are connected, the source of the thirteenth transistor, the gate of the first transistor and the drain of the ninth transistor are connected. The second end of the ammeter, the second end of the first capacitor and the source of the fourteenth transistor are connected, the drain of the fourth transistor, the gate of the tenth transistor, the first end of the first ammeter, the drain of the fifth transistor, the first end of the first capacitor and the gate of the eleventh transistor are connected, the gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor and the drain of the twelfth transistor are connected, the gate of the seventh transistor, the drain of the seventh transistor, the gate of the eighth transistor and the drain of the eleventh transistor are connected, and the source of the eleventh transistor, the source of the twelfth transistor and the drain of the fourteenth transistor are connected.

[0057] Further, if Figure 4 As shown, the valley detector includes a fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 , the eighteenth transistor M 18 , the nineteenth transistor M 19 , the twentieth transistor M 20 , the twenty-first transistor M 21 , the twenty-second transistor M 22 , the twenty-third transistor M 23 , the twenty-fourth transistor M 24 25th transistor M25 , the twenty-sixth transistor M 26 , the twenty-seventh transistor M 27 , the twenty-eighth transistor M 28 , the second capacitor C 2 and the second ammeter I b2 , wherein the source of the fifteenth transistor, the source of the sixteenth transistor, the first end of the second capacitor and the first end of the second ammeter are connected, the drain of the fifteenth transistor, the source of the seventeenth transistor and the source of the eighteenth transistor are connected, the drain of the seventeenth transistor, the drain of the twenty-first transistor, the drain of the twenty-third transistor, the gate of the twenty-third transistor and the gate of the twenty-fourth transistor are connected, the drain of the eighteenth transistor, the drain of the twenty-second transistor, the gate of the twenty-first transistor and the gate of the twenty-second transistor are connected, the gate of the eighteenth transistor, the second end of the second capacitor, the second end of the second ammeter, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor and the nineteenth transistor are connected The gates of the transistors are connected, the drain of the nineteenth transistor, the drain of the twenty-seventh transistor, the gate of the twenty-seventh transistor and the gate of the twenty-eighth transistor are connected, the drain of the twenty-sixth transistor, the source of the nineteenth transistor and the source of the twentieth transistor are connected, the drain of the twentieth transistor, the drain of the twenty-eighth transistor, the drain of the twenty-sixth transistor, the gate of the twenty-fifth transistor and the gate of the twenty-sixth transistor are connected, the source of the twenty-first transistor, the source of the twenty-second transistor, the source of the twenty-third transistor, the source of the twenty-fourth transistor, the source of the twenty-fifth transistor, the source of the twenty-sixth transistor, the source of the twenty-seventh transistor and the source of the twenty-eighth transistor are connected.

[0058] The subtractor is used to subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0059] In this embodiment, if Figure 5 As shown, the subtractor includes a first operational amplifier A1, a first resistor R 1 , the second resistor R 2 , the third resistor R 3 With the fourth resistor R 4 , wherein the second end of the third resistor and the first end of the fourth resistor are connected to the negative input terminal of the first operational amplifier, the second end of the first resistor and the first end of the second resistor are connected to the positive input terminal of the first operational amplifier, the second end of the fourth resistor is connected to the output terminal of the first operational amplifier, and the second resistor is grounded.

[0060] The comparison integrator is used to integrate the peak-to-peak value of the OTA signal and filter out the ripple to obtain a DC voltage signal with amplitude information;

[0061] In this embodiment, if Figure 6As shown, the comparison integrator includes a second operational amplifier A2, a fifth resistor R 5 , the sixth resistor R 6 and the third capacitor C 3 , wherein the second end of the fifth resistor, the first end of the sixth resistor, and the first end of the third capacitor are connected to the negative input terminal of the second operational amplifier, and the second end of the sixth resistor and the second end of the third capacitor are connected to the output terminal of the second operational amplifier.

[0062] The input capacitor, the feedback capacitor and the variable capacitor are used to convert the DC voltage signal with amplitude information and to compensate the input differential signal.

[0063] In this embodiment, if Figure 7 As shown, the variable capacitor includes a seventh resistor R 7 , the eighth resistor R 8 , the fourth capacitor C 4 , the fifth capacitor C 5 and MOS varactor diode C V , wherein the second end of the fourth capacitor, the second end of the seventh resistor and the first end of the MOS varactor are connected, and the second end of the MOS varactor, the second end of the eighth resistor and the first end of the fifth capacitor are connected.

[0064] See also Figure 2 The embodiment of the present application further provides a control method for a circuit for enhancing the input impedance of a chopper amplifier, which can implement the above-mentioned circuit for enhancing the input impedance of a chopper amplifier, and the method includes:

[0065] S100, obtaining a differential input signal and performing chopping and amplification processing to obtain a first output signal and a second output signal;

[0066] In some embodiments, the differential input signal is transmitted through V IN+ and V IN- Entering the instrumentation amplifier, after passing through the first stage chopper, it is converted into a frequency of f in the time domain. chop The square wave is modulated to f in the frequency domain. chop After being amplified by the OTA amplifier, the signal comes to the second stage chopper and demodulates the modulated signal back to a low frequency and outputs it through the first output signal V OUT+ The second output signal V OUT- In this invention, the input capacitor C IN With the feedback capacitor C FU To form a negative feedback loop, the input capacitor C IN With variable capacitor C IBL Form a positive feedback loop.

[0067] S200, performing peak detection processing on the first output signal and the second output signal to obtain a positive peak voltage and a negative peak voltage;

[0068] In some specific embodiments, the peak detector and the valley detector are used as amplitude detectors to detect the first output signal V OUT+ The second output signal V OUT- The peak detector has a differential input and single-ended output structure.

[0069] Among them, the first transistor M 1 , the second transistor M 2 , the ninth transistor M 9 , the tenth transistor M 10 , the thirteenth transistor M 13 and the seventh transistor M 7 , the eighth transistor M 8 , the eleventh transistor M 11 , the twelfth transistor M 12 , the fourteenth transistor M 14 For the feedback amplifier, the third transistor M 3 , the fourth transistor M 4 and the fifth transistor M 5 , the sixth transistor M 6 For the current mirror, the first capacitor C 1 To maintain the capacitance, the first ammeter I b1 The differential output of the OTA is the differential input of the peak detector. The left and right sides are mirrored, and the left side is used to detect the in-phase output signal V of the instrument amplifier. OUT+ The peak value on the right is used to detect the reverse output signal V OUT- The output V o1 Output peak voltage, charge the capacitors on both sides, once every half cycle.

[0070] The basic principle is as follows: Taking the left side as an example, the first transistor M 1 , the second transistor M 2 , the ninth transistor M 9 , the tenth transistor M 10 , the thirteenth transistor M 13 It is a classic 5-tube op amp used to compare the input signal V in1+ The peak voltage V o1 When the diode is turned on, the feedback amplifier acts as a buffer stage, which can both isolate the input and speed up the output. 1 and the ninth transistor M 9 The current flows from the feedback amplifier into the third transistor M of the current mirror. 3 and the fourth transistor M4 When the current mirror is turned on, the diode is forward-conducted and the current is copied to the fourth transistor M 4 When the current mirror is turned off, the diode is reversed and cut off, and the fourth transistor M 4 There is no current in the branch and the capacitor maintains the peak voltage.

[0071] Specifically, when the input signal V in1+ Rising, the ninth transistor M 9 The gate voltage is higher than the output V o1 Output peak voltage, input tube M 9 The small signal current will increase, but due to the current mirror first transistor M 1 and the second transistor M 2 The first transistor M has a clamping effect on the branch current. 1 The current of the first transistor M remains unchanged. 1 and the ninth transistor M 9 The KCL equation of the drain node of the transistor M shows that the increased small signal current can only come from the third transistor M 3 The third transistor M 3 The increased current is then transferred to the third transistor M by the current mirror 3 , the fourth transistor M 4 This current will be copied to the output branch and will affect the first capacitor C 1 Charging is performed and the output voltage rises.

[0072] On the contrary, when the input signal V in1+ Descending, input pipe M 9 The gate voltage is lower than the output V o1 Output peak voltage, input tube M 9 The small signal current of the tenth transistor M will decrease. 10 The gate voltage of the tenth transistor M rises. 10 The current increases through the first transistor M of the current mirror 1 , the second transistor M 2 The current copied to the input branch increases, so that the first transistor M 1 , the ninth transistor M 9 The drain node of the third transistor M is no longer required 3 The third transistor M 3 The first transistor M only provides current but does not consume current. 1 , the ninth transistor M 9 The drain node potential will be pulled up to VDD, and the third transistor M 3 The fourth transistor M is turned off. 4When it is cut off, the circuit enters a short equilibrium state, and the output is the peak value of the current signal. The peak detector always detects the maximum value of the signal.

[0073] Similarly, the valley detector is always detecting the minimum value of the signal. The valley detector has the opposite function to the peak detector, and the circuit structure is upside down. The principle of the valley detector detecting the negative peak is the same as the principle of the peak detector detecting the positive peak, so it will not be repeated here.

[0074] Usually, when the capacitor C is charged and discharged, its speed depends on 1 / RC, R is the discharge current source I b The larger the impedance, the larger the R, the larger the C, and the faster the charging and discharging speed. This can be expressed by the conversion rate SR:

[0075]

[0076] The conversion rate SR can be adjusted by adjusting the discharge current and the size of the holding capacitor. The faster the SR speed, the greater the slope, and the better it can track signals with drastic changes in amplitude. b The size of the capacitor makes it have a faster tracking speed and contributes less ripple.

[0077] The non-inverting input of the peak detector V in1+ Connect to the OTA's common-mode output terminal V OUT+ , the negative input terminal V in1- Connect to the reverse output terminal V of OTA OUT- The peak detector output V o1 The positive peak voltage of the signal is obtained, and the output of the valley detector V o2 The negative peak voltage of the signal is obtained. Therefore, the positive peaks of the in-phase and inverting output signals of the instrumentation amplifier are detected by the peak detector, and the negative peaks of the in-phase and inverting output signals are detected by the valley detector.

[0078] S300, subtracting the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal;

[0079] In some specific embodiments, the subtractor is used to subtract the positive peak value detected by the peak detector from the negative peak value detected by the valley detector to obtain the peak-to-peak value of the OTA signal. For example, if the positive peak value of the signal detected by the peak detector is 1V and the negative peak value of the signal detected by the valley detector is 0.2V, then the peak-to-peak value output by the subtractor is 0.8V. pp .

[0080] A1 represents an operational amplifier. The non-inverting input terminal V i+ Connect to the output V of the previous peak detector o1 , inverting input terminal V i- Connect to the output V of the previous valley detectoro2 , output terminal V o Connect to the inverting input of the next stage integrator. Connect 4 resistors R between the input and output of the op amp. 1 ~R 4 A closed-loop feedback form is formed to realize the function of subtracting two differential inputs.

[0081] S400, performing an integration operation on the peak-to-peak value of the OTA signal and filtering out ripples to obtain a DC voltage signal with amplitude information;

[0082] It should be noted that, in some embodiments, step S400 may include: S410, setting the reference voltage of the integrator according to the ideal amplitude of the amplifier; S420, integrating the peak-to-peak value of the OTA signal with the reference voltage to obtain a control voltage; S430, filtering the control voltage to remove ripple to obtain a DC voltage signal with amplitude information.

[0083] In some specific embodiments, the integrator is used to perform integration operation and filter out ripple. inf- The amplitude of the output of the previous subtractor is connected, and the in-phase input terminal is connected to a 0.1V reference voltage V REF , output terminal V ouf Connect to the voltage control terminal of the variable capacitor of the next stage. Add resistors and capacitors between the input and output of the operational amplifier to form a closed-loop feedback form, thereby realizing the function of the integrator.

[0084] The principle is as follows: The integrator first converts the input V inf- With the preset reference voltage V REF For comparison. Among them, the input V inf- is the peak-to-peak value of the OTA op amp output of the subtractor, V REF Set to the ideal amplitude of the instrumentation amplifier. Then, the integrator integrates the difference between the two inputs, and the integrated voltage V ouf It is the control voltage V of the positive feedback loop. C , and supplies it to the variable capacitor to adjust the gain. According to the virtual short and virtual disconnection, the current flows through the integral capacitor C 3 The current is

[0085]

[0086] The integrator output voltage is:

[0087]

[0088] Since the integrator input V inf- And the reference voltage V REF are all DC voltages that do not change with time t, which can be simplified as:

[0089]

[0090] Among them, the integrator capacitor C 3 A feedback resistor R is connected in parallel 6 , realizing a low-pass filter to filter out high-frequency components. Therefore, the output voltage V ouf It is a DC voltage with amplitude information, which can be used as a control voltage to tune the capacitance value of the variable capacitor.

[0091] The stability boundary of the instrumentation amplifier is detected by the amplitude detector. In this process, if the instrumentation amplifier oscillates and the signal amplitude exceeds the reference voltage V REF , then the integrator is triggered to perform integral tuning control voltage V C Therefore, a feedback current is provided in the feedback loop with a variable capacitor until the output amplitude of the instrumentation amplifier remains below the reference voltage V REF voltage.

[0092] S500, converting a DC voltage signal with amplitude information into a DC current signal with amplitude information, and performing current compensation on the differential input signal through a positive feedback loop;

[0093] In some specific embodiments, the variable capacitor circuit C 4 and C 5 The variable capacitor of the present invention can decouple the signal node from the control node, where V C is the control voltage, V A 、V B It is a signal node. MOS varactor diode C V It is made of accumulation type varactor diode, which can achieve higher capacitance density by replacing p+ doping diffusion with n+ in typical MOS. Figure 8 As shown in the figure, the capacitance seen from the gate is the oxide capacitance. As the amplitude increases, it usually indicates that the feedback loop is overcompensated, and the value of the variable capacitor needs to be reduced to reduce the degree of compensation. Therefore, the control voltage V generated by the integrator is C The control voltage V is inversely proportional to the capacitance value of the variable capacitor. C At different bias V bias The capacitance value is as follows Fig. 9 shown.

[0094] This voltage-controlled variable capacitor positive feedback topology has two advantages: first, it can realize capacitors with resolution exceeding femtofarad without being limited by the LSB of traditional capacitor arrays. Second, the way of adjusting the capacitance value by voltage will not change the size of the parasitic capacitance at the input end compared to the switch matrix.

[0095] The variable capacitor and chopper are connected in the positive feedback path between the input and output of the instrumentation amplifier, which converts the output voltage into a current and injects it back into the input node. This current compensates for the voltage caused by the chopping frequency f. chop and input capacitor C IN The current drawn from the signal source by the switch capacitor resistance compensates for the signal source current drawn by the on-chip parasitic capacitance, thereby greatly increasing the input impedance of the instrumentation amplifier.

[0096] In summary, the signal gain of the instrumentation amplifier is determined by the ratio of the input capacitance to the feedback capacitance, that is, Gain = C IN / C FB In order to ensure that the gain accuracy of the instrumentation amplifier is higher than 0.1%, the gain of the OTA should be greater than 100dB. Therefore, the present invention uses a two-stage OTA op amp with Miller compensation. The offset and 1 / f noise of the OTA op amp are moved to high frequency by the chopper module without affecting the signal baseband.

[0097] The enhancement technique in the present invention utilizes the stability criterion of the positive feedback loop, that is, overcompensation of the positive feedback will cause OTA output oscillation. In order to find the stability boundary in the calibration mode, a small signal pulse can be applied to the input of the instrumentation amplifier to observe the output waveform. When the variable capacitor C IBL When it is small, there is weak positive feedback in the loop, the instrumentation amplifier works normally and the loop is stable. On the other hand, when the variable capacitor C IBL When it is too large, the instrumentation amplifier will exhibit oscillations with increasing amplitude due to the strong regenerative nature of the positive feedback. Therefore, the stability of the amplifier loop can be determined by observing the output at the end of the input pulse.

[0098] In the present invention, an amplitude detector is used to monitor whether the amplifier is in an output oscillation state, and then the feedback strength of the positive feedback loop is adjusted according to the output amplitude information until the output of the OTA changes from an oscillation state to a stable state. Among them, the variable capacitor plays a compensation role and provides a positive feedback gain, which is controlled by the control voltage V C Adjustment, V C Generated by the monitoring loop. In this monitoring loop, the peak detector and valley detector are used to detect the positive and negative peak values ​​of the OTA output respectively; the subtractor subtracts the positive peak value from the negative peak value to obtain the peak-to-peak value of the instrumentation amplifier output signal; the integrator compares the peak-to-peak value with the reference voltage V REF After comparison, the difference is integrated and the control voltage V is output C The reference voltage in the present invention is 100mV, that is, when the loop detects that the amplitude gradually changes from oscillation to less than 100mV, V C No longer changes to provide a certain capacitance value C IBL .

[0099] The present invention detects the oscillation amplitude of the OTA output and adjusts the variable capacitor C accordingly. IBL The size of the instrumentation amplifier is small enough to achieve marginal stability and almost completely compensate the parasitic capacitance at the input of the instrumentation amplifier to achieve maximum input impedance.

[0100] It can be understood that the contents of the above method embodiments are all applicable to the present circuit embodiment, the functions specifically implemented by the present circuit embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0101] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A circuit for increasing the input impedance of a chopper amplifier. It is characterized in that The circuit includes an OTA operational amplifier module, a chopper module, an input capacitor, a feedback capacitor, a peak detector, a valley detector, a subtractor, a comparison integrator and a variable capacitor. The chopper module includes a first-stage chopper, a second-stage chopper, a third-stage chopper and a fourth-stage chopper. The second end of the first-stage chopper is respectively connected to the first end of the input capacitor and the first end of the variable capacitor. The second end of the input capacitor is respectively connected to the first end of the feedback capacitor and the first end of the OTA operational amplifier module. The second end of the feedback capacitor is connected to the first end of the third-stage chopper. The second end of the operational amplifier module is connected to the first end of the second-stage chopper, the second end of the variable capacitor is connected to the first end of the fourth-stage chopper, the second end of the fourth-stage chopper, the second end of the third-stage chopper, the second end of the second-stage chopper, the input end of the peak detector and the input end of the valley detector are connected, the output end of the peak detector and the output end of the valley detector are both connected to the input end of the subtractor, the output end of the subtractor is connected to the input end of the comparison integrator, and the output end of the comparison integrator is connected to the input end of the variable capacitor, wherein: The chopper module is used to perform chopping processing on the input differential signal to obtain a chopped input differential signal; The OTA operational amplifier module is used to amplify the chopped input differential signal to obtain an amplified input differential signal; The peak detector and the valley detector are used to perform peak detection processing on the amplified input differential signal to obtain a positive peak voltage and a negative peak voltage; The subtractor is used to perform subtraction calculation on the positive peak voltage and the negative peak voltage to obtain the peak-to-peak value of the OTA signal; The comparison integrator is used to perform integration operation on the peak-to-peak value of the OTA signal and filter out ripples to obtain a DC voltage signal with amplitude information; The input capacitor, the feedback capacitor and the variable capacitor are used to convert the DC voltage signal with amplitude information and compensate the input differential signal.

2. The circuit according to claim 1, It is characterized in that The peak detector includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first capacitor and a first ammeter, wherein a source of the first transistor, a source of the second transistor, a source of the third transistor, a source of the fourth transistor, a source of the fifth transistor, a source of the sixth transistor, a source of the seventh transistor and a source of the eighth transistor are connected, a gate of the first transistor, a gate of the second transistor and a drain of the second transistor are connected to a drain of the tenth transistor, and a drain of the first transistor, a drain of the ninth transistor, a drain of the third transistor and a gate of the fourth transistor are connected. The source of the ninth transistor, the source of the tenth transistor and the drain of the thirteenth transistor are connected, the source of the thirteenth transistor, the second end of the first ammeter, the second end of the first capacitor and the source of the fourteenth transistor are connected, the drain of the fourth transistor, the gate of the tenth transistor, the first end of the first ammeter, the drain of the fifth transistor, the first end of the first capacitor and the gate of the eleventh transistor are connected, the gate of the fifth transistor, the gate of the sixth transistor, the drain of the sixth transistor, the drain of the eighth transistor and the drain of the twelfth transistor are connected, the gate of the seventh transistor, the drain of the seventh transistor, and the gate of the eighth transistor are connected to the drain of the eleventh transistor, and the source of the eleventh transistor and the source of the twelfth transistor are connected to the drain of the fourteenth transistor.

3. The circuit according to claim 1, It is characterized in that The valley detector includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a second capacitor and a second ammeter, wherein a source of the fifteenth transistor, a source of the sixteenth transistor, a first end of the second capacitor and a first end of the second ammeter are connected, a drain of the fifteenth transistor and a source of the seventeenth transistor are connected to a source of the eighteenth transistor, a drain of the seventeenth transistor, a drain of the twenty-first transistor, a drain of the twenty-third transistor, and a gate of the twenty-third transistor are connected to a gate of the twenty-fourth transistor, a drain of the eighteenth transistor, a drain of the twenty-second transistor, and a gate of the twenty-first transistor are connected to a gate of the twenty-second transistor, and The gate of the eighteenth transistor, the second end of the second capacitor, the second end of the second ammeter, the drain of the twenty-fourth transistor, the drain of the twenty-fifth transistor and the gate of the nineteenth transistor are connected, the drain of the nineteenth transistor, the drain of the twenty-seventh transistor, and the gate of the twenty-seventh transistor are connected to the gate of the twenty-eighth transistor, the drain of the twenty-sixth transistor and the source of the nineteenth transistor are connected to the source of the 20th transistor, the drain of the 20th transistor, the drain of the 28th transistor, the drain of the 26th transistor, and the gate of the 25th transistor are connected to the gate of the 26th transistor, and the source of the twenty-first transistor, the source of the twenty-second transistor, the source of the twenty-third transistor, the source of the twenty-fourth transistor, the source of the twenty-fifth transistor, the source of the twenty-sixth transistor, the source of the twenty-seventh transistor and the source of the twenty-eighth transistor are connected.

4. The circuit according to claim 1, It is characterized in that The subtractor includes a first operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein the second end of the third resistor and the first end of the fourth resistor are connected to the negative input terminal of the first operational amplifier, the second end of the first resistor and the first end of the second resistor are connected to the positive input terminal of the first operational amplifier, the second end of the fourth resistor is connected to the output terminal of the first operational amplifier, and the second resistor is grounded.

5. The circuit according to claim 1, It is characterized in that The comparison integrator includes a second operational amplifier, a fifth resistor, a sixth resistor and a third capacitor, wherein the second end of the fifth resistor, the first end of the sixth resistor and the first end of the third capacitor are connected to the negative input terminal of the second operational amplifier, and the second end of the sixth resistor and the second end of the third capacitor are connected to the output terminal of the second operational amplifier.

6. The circuit according to claim 1, It is characterized in that The variable capacitor includes a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor and a MOS varactor, wherein the second end of the fourth capacitor, the second end of the seventh resistor and the first end of the MOS varactor are connected, and the second end of the MOS varactor, the second end of the eighth resistor and the first end of the fifth capacitor are connected.

7. A control method for a circuit for enhancing the input impedance of a chopper amplifier, It is characterized in that The method comprises the following steps: Acquire a differential input signal and perform chopping and amplification processing to obtain a first output signal and a second output signal; Performing peak detection processing on the first output signal and the second output signal to obtain a positive peak voltage and a negative peak voltage; Subtract the positive peak voltage from the negative peak voltage to obtain the peak-to-peak value of the OTA signal; Performing integration operation on the peak-to-peak value of the OTA signal and filtering out ripples to obtain a DC voltage signal with amplitude information; The DC voltage signal with amplitude information is converted into a DC current signal with amplitude information, and current compensation is performed on the differential input signal through a positive feedback loop.

8. The method according to claim 7, It is characterized in that The step of integrating the peak-to-peak value of the OTA signal and filtering out the ripple to obtain a DC voltage signal with amplitude information includes: Set the reference voltage of the comparison integrator according to the ideal amplitude of the amplifier; Integrate the peak-to-peak value of the OTA signal with the reference voltage to obtain a control voltage; The control voltage is subjected to ripple filtering to obtain the DC voltage signal with amplitude information.

9. The method according to claim 7, It is characterized in that The expression of the DC voltage signal with amplitude information is: In the above formula, V ouf Represents a DC voltage signal with amplitude information, V inf- Represents the peak-to-peak value of the OTA signal, V REF Indicates the reference voltage, C 3 Represents the third capacitance value, R 5 represents the fifth resistance value.

10. The method according to claim 7, It is characterized in that The positive feedback loop includes a positive feedback loop and a negative feedback loop. The positive feedback loop is composed of an input capacitor and a variable capacitor, and the negative feedback loop is composed of an input capacitor and a feedback capacitor.

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