A method for flexibly configuring terminal devices on a server based on a PCIe switch

Abstract

The application discloses a kind of based on PCIe Switch's server flexible configuration terminal equipment's method, by adding label in Switchmfg configuration page, and indicate each label information, then after firmware initialization, it is enumerated to PCIe device, finally special information ChassisPhysslotNum is attached to each station.After BIOS power-on initial, it is enumerated to equipment, Switch Bridge and Bridge under PCIe device and endpoint equipment directly hung under Host are classified, PCIe relevant information is reported to BMC by IPMI, and BMC receives information and is parsed and transferred to Web UI or Redfish after receiving information.The application supports multiple working modes of Switch, and firmware file can also be signed to prevent malicious attacks.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and more specifically to a method for flexibly configuring terminal devices on a server based on a PCIe switch. Background Technology

[0002] Customers may connect their PCIe devices directly to the host via the PCIe bus, or they may be bridged to a PCIe switch, with PCIe end devices connected to the switch. When a device malfunctions, it's difficult for customers on servers with PCIe switch modules to identify which port is affected through the BMC interface. During maintenance, customers can only disassemble the device or use other methods to gradually locate the port. This disrupts the problem-solving process and hinders analysis.

[0003] Therefore, there is an urgent need for a method for flexibly configuring terminal devices on servers. Summary of the Invention

[0004] To address the problems in the prior art, this invention proposes a method for flexibly configuring terminal devices on a server based on a PCIe Switch.

[0005] This invention is specifically achieved through the following technical solution:

[0006] A method for flexibly configuring terminal devices on a server based on a PCIe switch, the method comprising:

[0007] Configure the port attribute slot number for the PCIe Switch. Specifically, first add a configuration port attribute Label in the firmware mfg xml configuration, then configure the attributes of all ports, and then configure the ChassisPhysSlotNum for all ports.

[0008] When the switch and host are powered on simultaneously, the switch executes the firmware-related boot program, the BIOS performs the corresponding initialization, enumerates PCIe devices to obtain the total number of all PCIe devices, and then configures the space of each PCIe device. When the type of the read configuration space is determined, it is determined whether it is a switch bridge device or an endpoint device. If it is a switch bridge device, its slot information is marked and the corresponding slot number is obtained. This process is repeated for all devices. Finally, the PCIe-related information is reported to the BMC via IPMI. The BMC receives the corresponding information, parses it, and presents it to the Web UI or to Redfish.

[0009] As a further improvement of the present invention, obtaining the corresponding slot number specifically includes: after the Switch is powered on and the device is activated, the Switch firmware is first initialized, then the firmware thread is started, the PCIeManager switch configuration and global configuration page is obtained, the platform overlay configuration PCIe Manager switch and global options are obtained, then the Port attribute is read, and finally the PCIe slot control physical slot is attached to the port.

[0010] As a further improvement of the present invention, the Port attribute includes port number, port type, and ChassisPhysslotNum.

[0011] As a further improvement of the present invention, the hardware connection of the PCIe Switch includes: connecting several NVMe storage devices directly to the backplane, and then connecting the backplane directly to ST3 of the first PCIe Switch and / or the second PCIe Switch; other X16, X8, X4 PCIe devices are connected to ST2, ST4, ST5, ST6, ST7, ST8 of the first PCIe Switch and / or the second PCIe Switch; ST0 and ST1 of the first PCIe Switch and the second PCIe Switch are connected to the first CPU and the second CPU respectively via MCIO as the upstream of the Switch.

[0012] As a further improvement of the present invention, the host hardware links include: the BIOS connecting to the NVMe storage device through the PCH control board, the BIOS directly connecting to other PCIe endpoints through the PCIe bus, and the CPUs being linked through the UPI bus.

[0013] As a further improvement of the present invention, the method is adapted to PCIe devices connected to a PCIe Switch, including network cards, graphics cards, SSDs, and NVMe devices.

[0014] As a further improvement of the present invention, the method is adaptable to all working modes, including basic mode and comprehensive mode.

[0015] As a further improvement of the present invention, the method also includes RSA signing of the configuration file and firmware.

[0016] The beneficial effects of this invention are as follows: Compared with existing technologies, this invention adds a label to the Switchmfg configuration page, specifying the port index, number, type, and ChassisPhysslotNum for each label information. After firmware initialization, PCIe devices are enumerated, and each station is assigned the special information ChassisPhysslotNum. Upon BIOS power-on, device enumeration categorizes PCIe devices under the Switch Bridge and Bridge, as well as endpoint devices directly connected to the Host. PCIe-related information is reported to the BMC via IPMI. The BMC receives and parses the information, then passes it to the Web UI or Redfish, displaying the PCIe device's health status, location, silkscreen, and other information. This invention allows configuring multiple uplink ends on a PCIe Switch, enabling the Switch to connect to multiple NVMe devices while accurately locating NVMe device status information; it also solves the problem of bandwidth and speed drops for multiple downlink connected PCIe devices. This invention supports multiple Switch operating modes and can also sign firmware files to prevent malicious attacks. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the PCIe Switch hardware connection and Host hardware connection of the present invention;

[0018] Figure 2 This is a flowchart illustrating the configuration of the Port attribute slot number according to the present invention.

[0019] Figure 3 This is a flowchart illustrating the process of reading the PCIe device slot number according to the present invention.

[0020] Figure 4 This is a diagram of the present invention. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] Glossary

[0023] BIOS: Basic Input Output System, mainly used for the initialization and detection of various hardware devices during the computer startup process.

[0024] PCH: Platform Controller Hub, Intel's integrated southbridge.

[0025] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.

[0026] NVME: Nonvolatile Memory Express.

[0027] MCIO: Mini Cool Edge IO, multi-channel input / output.

[0028] ST: station, workstation.

[0029] PCIe Switch: Peripheral Component Interconnect Express Switch. A PCIe switch is a device used to build a PCIe bus topology. It allows multiple PCIe devices to connect to the host system through a single PCIe root port and enables data routing and switching between these devices as needed. PCIe switches play a crucial role in building high-performance computer systems, servers, network devices, and other applications requiring high-speed data transmission.

[0030] IPMI: Intelligent Platform Management Interface. IPMI is a standard hardware management interface specification designed to provide the ability to remotely manage and monitor server hardware, including remote power on / off, monitoring system temperature, voltage, fan speed, and other parameters, as well as performing diagnostic and maintenance tasks.

[0031] ChassisPhysSlotNum: The number of physical slots inside the computer case. These slots are used to install various hardware components, such as CPUs, memory modules, expansion cards, etc. Each slot has its specific purpose and standard; for example, PCIe slots are used to install expansion hardware such as graphics cards and network cards, while DIMM slots are used to install RAM memory modules.

[0032] like Figure 1As shown, the Switch hardware connection and server Host hardware connection of this invention involve directly connecting four NVMe storage devices to a backplane, which is then directly connected to ST3 of the first PCIe Switch (SWITCH1) and / or the second PCIe Switch (SWITCH2). Other x16, x8, and x4 PCIe devices are connected to ST2, ST4, ST5, ST6, ST7, and ST8 of the first and / or second PCIe Switches. ST0 and ST1 of SWITCH1 and SWITCH2 act as upstream connections to CPU1 and CPU2 respectively via MCIO. The server's BIOS bootloader connects to the NVMe storage devices via the PCH control board. The BIOS is directly connected to other PCIe endpoints, such as x16 and x8 devices, via the PCIe bus. CPUs are connected via the UPI bus.

[0033] Switch programming:

[0034] The process for configuring the Port attribute slot number is as follows: Figure 2 As shown: First, add a configuration port attribute Label in the firmware mfg xml configuration, configure the attributes of all ports, including port number index, port type type, number, clock, etc. Finally, configure the ChassisPhysSlotNum corresponding to all ports, and build a map mapping table with station id, port, and ChassisPhysSlotNum.

[0035] The process for reading the PCIe device slot number is as follows: Figure 3 As shown: After the Switch is powered on and the device is locked, the Switch's firmware is first initialized, then the firmware thread is started to obtain the PCIe Manager switch configuration and global configuration page, then obtain the platform overlay configuration PCIe Manager switch and global options, then read the Port property (including port number, port type, ChassisPhysslotNum), and finally set the PCIe slot control physical slot to be attached to the port.

[0036] BIOS programming:

[0037] When the switch and host power on simultaneously, the switch executes the firmware-related bootloader, the BIOS performs corresponding initialization, enumerates PCIe devices to obtain the total number of all PCIe devices, and then, based on the configuration space of each PCIe device, if the read configuration space type is 1, it is considered a switch bridge device; otherwise, it is an endpoint device. If it is a switch bridge device, its slot information is marked as 0xff, and the corresponding slot number is obtained. This process is repeated for all devices. Finally, the PCIe-related information is reported to the BMC via IPMI. The BMC receives the corresponding information, parses it, and presents it to the Web UI or provides it to Redfish.

[0038] The solution of this invention is compatible with all PCIe devices (including network cards, graphics cards, SSDs, NVMe drives) connected to a PCIe Switch, and also compatible with all working modes (including basic mode and comprehensive mode, etc.).

[0039] The method of the present invention also includes RSA signing of the configuration file and firmware to prevent malicious attacks.

[0040] The method of this invention designs multiple uplink ports on a PCIe switch and configures the bandwidth, speed, etc. of the uplink and downlink ports. The CPU can remap the ports according to the XML parameters configured in the design.

[0041] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered within the protection scope of the present invention.

Claims

1. A method for flexibly configuring terminal devices on a server based on a PCIe switch, characterized in that... The method includes: Configure the port attribute slot number for the PCIe Switch. Specifically, this involves: first, adding a configuration label for the port attribute in the firmware MFG XML configuration; configuring all port attributes, including port number (index), port type (type), number, and clock; and finally, configuring the corresponding ChassisPhysSlotNum for all ports, creating a map mapping table between the station ID, port, and ChassisPhysSlotNum. When the Switch and Host are powered on simultaneously, the Switch executes the firmware-related bootloader, the BIOS performs corresponding initialization, enumerates PCIe devices to obtain the total number of PCIe devices, and then configures the space for each PCIe device. Based on the read configuration space type, it determines whether it is a Switch bridge device or an endpoint device. If it is a Switch bridge device, it marks its slot information and obtains the corresponding slot number. This process continues until all devices are updated. Finally, the PCIe-related information is reported to the BMC via IPMI. The BMC receives the information, parses it, and presents it to the Web UI or Redfish. The specific steps for obtaining the corresponding slot number are as follows: After the Switch is powered on and the device is activated, the Switch firmware is first initialized, then the firmware thread is started, the PCIe Manager switch configuration and global configuration page are obtained, the platform overwrite configuration PCIe Manager switch and global options are obtained, then the Port attribute is read, and finally the PCIe slot control physical slot is attached to the port.

2. The method according to claim 1, wherein, The hardware connections of the PCIe Switch include: connecting several NVMe storage devices directly to the backplane, and then connecting the backplane directly to ST3 of the first PCIe Switch and / or the second PCIe Switch; other X16, X8, and X4 PCIe devices are connected to ST2, ST4, ST5, ST6, ST7, and ST8 of the first PCIe Switch and / or the second PCIe Switch; ST0 and ST1 of the first and second PCIe Switches are connected to the first CPU and the second CPU respectively via MCIO as the upstream of the Switch.

3. The method according to claim 1, wherein, Host hardware connections include: BIOS connecting to NVMe storage devices via PCH control board, BIOS directly connecting to other PCIe endpoints via PCIe bus, and CPUs connecting to each other via UPI bus.

4. The method according to claim 1, wherein, The method is compatible with PCIe devices connected to a PCIe Switch, including network cards, graphics cards, SSDs, and NVMe devices.

5. The method according to claim 1, wherein, The method is compatible with all working modes, including basic mode and comprehensive mode.

6. The method according to claim 1, wherein, The method also includes RSA signing of the configuration file and firmware.

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