I2C bus system for multiple circuit structure configurations

Abstract

The invention discloses an I2C bus system for configuration of a plurality of circuit structures, the I2C bus system comprises a plurality of circuit structures connected to an I2C bus, and the circuit structures are used for configuring I2C address device information according to detection pins set by the circuit structures; the I2C address device information comprises device addresses, and the device addresses configured by any two circuit structures are different; wherein the mapping relations about the I2C address equipment information used by the plurality of circuit structures are the same. By providing corresponding detection pins in the circuit structures connected to the I2C bus and detecting signals at the pins in real time, I2C master-slave roles and device addresses of all the circuit structures are automatically configured, and personnel in related technical fields do not need to burn matched firmware for all the circuit structures according to set welding positions when leaving a factory. Even if the welding position is wrong, the correct device address configuration of each circuit structure in the I2C bus is not influenced, and the production process of the chip supporting I2C communication is simplified.

Description

Technical Field

[0001] The present application relates to the electronic technical field of I2C bus, and in particular to an I2C bus system for configuring multiple circuit structures. Background Art

[0002] In the prior art, I2C communication is a relatively common communication control protocol, and the hardware support structure built into the integrated circuit is a multi-machine single-ended two-wire communication interface, which is configured to use a bus including a serial data line (SDA) and a serial clock line (SCL) to serially send or receive information from an I2C master device to an I2C slave device. The I2C master device may include a microcontroller or other electronic device configured to issue a clock and address a slave device, and the I2C slave device may include a peripheral device such as an analog digital controller (ADC), a digital analog controller (DAC), or one or more other peripheral devices configured to receive a clock and an address.

[0003] Each device connected to the I2C bus has an independent device address. The I2C master device can use the device address to access different I2C slave devices. For an I2C system with multiple independent device addresses, it is necessary to configure the same number of programmable IDs as the independent device addresses. In addition, the master and slave roles and device addresses of the chip need to be set when the chip leaves the factory. Each device address needs to be burned with a corresponding firmware program, and the firmware programs burned between different device addresses are different.

[0004] The existing I2C system requires more than two independent device addresses, and the chips connected to the I2C bus need to be soldered and installed on the circuit board according to fixed positions. For example, some chips that need to be burned with firmware are host chips, and another part of chips that need to be burned with firmware are slave chips. When configuring the logical functions of each chip, multiple firmware needs to be burned. Therefore, when burning firmware, relevant technical personnel need to distinguish the soldering positions of each chip circuit and adjust the firmware according to the different soldering positions. This is very cumbersome and prone to errors in application, and the control of the chip is more complicated, which is not conducive to the design and application of I2C bus circuits. Summary of the invention

[0005] The present application discloses an I2C bus system for multiple circuit structure configurations, and the specific technical solutions are as follows:

[0006] An I2C bus system for configuring multiple circuit structures, the I2C bus system includes multiple circuit structures connected to the I2C bus, the circuit structures are used to configure I2C address device information according to the detection pins set thereon; the I2C address device information includes device addresses, and the device addresses configured by any two of the circuit structures are different; wherein the mapping relationship regarding the I2C address device information used by the multiple circuit structures is the same. In summary, the technical solution automatically configures the I2C master-slave role and device address of each circuit structure by providing a corresponding pin foot (referring to the detection pin, or a specific pin of a chip inside the circuit structure) in the circuit structure connected to the I2C bus and detecting the signal at the pin foot in real time. There is no need for relevant technical personnel to burn matching firmware for each circuit structure according to the established welding position before leaving the factory. Even if the welding position is wrong, it will not affect the configuration of the correct device address of each circuit structure in the I2C bus, and there will be no recognition failure or communication error in the connected I2C bus. The process of producing chips that support I2C communication is simplified, and the tediousness of burning different firmware due to the need to configure the master-slave role and device address can be simplified, which is beneficial to I2C bus circuit design and data communication applications.

[0007] Furthermore, multiple circuit structures support burning the same firmware; after multiple circuit structures are burned with the same firmware, each circuit structure is used to configure the corresponding I2C address device information according to the signal at the detection pin set by each circuit structure; under the mapping relationship of the I2C address device information, the signals at the detection pins set by any two circuit structures are different, and the I2C address device information corresponding to any two circuit structures is different. Therefore, when configuring the logical functions of each circuit structure, after completing the configuration of the chip that plays the role of the host, it is not necessary to burn the chip that plays the role of the slave by modifying the firmware. The same firmware burned by multiple circuit structures can be used to configure the respective I2C address device information, so as to realize the configuration of the device addresses required by different circuit structures and the master and slave roles they play according to the same mapping relationship, and it is not necessary to pre-burn different firmware according to the difference of the device addresses on the same I2C bus, thereby reducing the cumbersomeness of external configuration of the I2C bus.

[0008] Further, each of the circuit structures includes a chip and a detection resistor; the resistance values ​​of the detection resistors set inside any two of the circuit structures are different; in the circuit structure, the chip is provided with a serial data line pin, a serial clock line pin and the detection pin; the serial data line pin is connected to the serial data line of the I2C bus, and the serial data line pin is used to receive a data signal from the serial data line; the serial clock line pin is connected to the serial clock line of the I2C bus, and the serial clock line pin is used to receive a clock signal from the serial clock line; the detection pin is connected to the first end of the detection resistor, and the detection pin is used to collect the voltage signal generated by the first end of the detection resistor and configure the collected voltage signal as the voltage signal at the detection pin; wherein the voltage value of the voltage signal at the detection pin is proportional to the resistance value of the detection resistor connected to the detection pin, forming a mapping relationship between the voltage signal at the detection pin and the detection resistor. Based on the circuit structure disclosed in the technical solution and the chip inside it, the setting of I2C address device information (including I2C address or device address) and the control of master and slave roles can be realized through a completely software-based operation mode. The difficulty of configuring the mapping relationship between the voltage signal at the detection pin and the detection resistor is reduced, and the process of producing a chip supporting I2C communication is accelerated.

[0009] Furthermore, the chip includes a control unit, an I2C address device configuration module and a current source; the current source is connected to the first end of the detection resistor, and the second end of the detection resistor is grounded; the detection resistor is used to receive the current output by the current source and generate a voltage signal at the detection pin at its first end; the current source is used to generate a constant current so that the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor; the I2C address device configuration module is connected to the control unit; the control unit is used to detect the voltage signal at the detection pin generated by the first end of the detection resistor, and then, based on the determination of the voltage signal at the detection pin, call the I2C address from the I2C address device configuration module according to the mapping relationship of the I2C address device information. Device information, and then configure the called I2C address device information as the I2C address device information of the circuit structure where the control unit is located, so as to configure the I2C address device information according to the detection pin set by it; wherein, the mapping relationship of the I2C address device information is compatible with all chips connected to the I2C bus; the I2C address device configuration module is used to store the mapping relationship of the I2C address device information, and the mapping relationship of the I2C address device information includes the mapping relationship between the I2C address device information and the detection resistor, and the mapping relationship between the I2C address device information and the detection resistor includes the mapping relationship between the voltage signal at the detection pin and the detection resistor, and the mapping relationship between the I2C address device information and the voltage signal at the detection pin. Based on the chip disclosed in the present technical solution, it is usually only necessary to retain a port for the detection resistor, and it is not necessary to provide multiple components for users to weld and debug, and the setting of the I2C address device information (including the I2C address or device address) and the control of the master-slave role can be realized through a completely software-based operation mode. Since the mapping relationship of I2C address device information is compatible with all chips connected to the I2C bus, all chips can be burned with the same firmware. There is no need to burn different firmware according to different device addresses. This simplifies the tedious process of burning different firmware due to the need to configure master-slave roles and device addresses, and greatly improves the process of producing chips that support I2C communication.

[0010] Furthermore, the chip also includes an analog-to-digital converter; the detection pin is connected to the collection end of the analog-to-digital converter; the analog-to-digital converter is used to collect the voltage signal at the detection pin generated by the first end of the detection resistor, and convert the collected voltage signal into a voltage identification value; the control unit is connected to the conversion output end of the analog-to-digital converter; the control unit is used to receive the voltage identification value and transmit it to the I2C address device configuration module, so as to detect the voltage signal generated by the first end of the detection resistor through the analog-to-digital converter; the control unit is used to call the I2C address device information corresponding to the voltage identification value from the I2C address device configuration module according to the voltage identification value; wherein the mapping relationship between the I2C address device information and the voltage identification value is the mapping relationship between the I2C address device information and the converted voltage signal. This technical solution converts the voltage signal at the detection pin into a digital signal that is easy for the control unit to identify and encode in real time through the analog-to-digital converter, thereby improving the efficiency of voltage value comparison and mapping.

[0011] Furthermore, the control unit calls the I2C address device information from the I2C address device configuration module according to the mapping relationship about the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is less than the preset target voltage value, the control unit calls the corresponding role configuration information from the I2C address device configuration module, and then configures the chip where the control unit is located as an I2C host chip according to the called role configuration information, and configures the circuit structure where the control unit is located as a host device; and, the control unit calls the corresponding device address from the I2C address device configuration module according to the host address identification voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C host address, forming the device address of the host device or the device address of the I2C host chip, so that other chips connected to the I2C bus can access the currently configured I2C host chip. In each circuit structure, based on the fact that the voltage value of the voltage signal at the detection pin is proportional to the resistance value of the detection resistor connected to the detection pin, and the mapping relationship between the device address of the host device and the voltage signal at the detection pin, the control unit can configure the I2C address device information according to the detection resistor. When the circuit structure is configured as a host device, it also configures the device address of the host device or the device address of the I2C host chip, so that other chips connected to the I2C bus can access the currently configured I2C host chip.

[0012] Further, a host identification voltage range corresponds to the role configuration information of a host device, forming a mapping relationship between the role configuration information of the host device and the voltage signal at the detection pin; wherein, the preset target voltage value is the upper limit value of the host identification voltage range; a host identification voltage range is divided into multiple host address identification voltage ranges, wherein, a host address identification voltage range corresponds to an I2C host address, forming a mapping relationship between the device address of the host device and the voltage signal at the detection pin; wherein, the mapping relationship between the I2C address device information and the voltage signal at the detection pin includes the mapping relationship between the role configuration information of the host device and the voltage signal at the detection pin, and the mapping relationship between the device address of the host device and the voltage signal at the detection pin; in different chips, the host address identification voltage ranges of the voltage signals at the respective detection pins are different, so that the chips included in the multiple host devices are assigned different device addresses; wherein, the I2C address device information includes the role configuration information of the host device and its corresponding device address. Therefore, within the voltage range of identifying the host device, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board and whether it is identified as a master or slave in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a host address recognition voltage range, the role configuration information and the device address can be determined by the sensing voltage at its detection pin (specifically the voltage signal generated by the external detection resistor).

[0013] Furthermore, the number of host address identification voltage ranges divided by a host identification voltage range is equal to the number of circuit structures configured as host devices connected to the I2C bus, and the voltage change value covered by each host address identification voltage range is equal; in the circuit structure configured as a host device, the detection resistor included in each circuit structure is configured to correspond to a host detection resistance adjustment range; the number of host detection resistance adjustment ranges corresponding to the detection resistor is equal to the number of divided host address identification voltage ranges; the resistance change value covered by each host detection resistance adjustment range is equal. It is realized that the device addresses corresponding to any two circuit structures configured as host devices in the I2C bus system are different. On this basis, all chips connected to the I2C bus can be burned with unified firmware, and there is no need to distinguish the position order when pasting chips, and they can be pasted at will; only after the I2C bus system is powered on, whenever the firmware detects that the voltage value of the voltage signal at the detection pin falls into a host address identification voltage range, the firmware can judge the master-slave role configuration information and the device address according to the set mapping relationship through the resistance value of the detection resistor, thereby improving the production efficiency of chips supporting I2C communication.

[0014] Furthermore, the control unit calls the I2C address device information from the I2C address device configuration module according to the mapping relationship about the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is greater than or equal to the preset target voltage value, the control unit calls the corresponding role configuration information from the I2C address device configuration module, and then configures the chip where the MCU is located as an I2C slave chip according to the called role configuration information, and configures the circuit structure where the control unit is located as a slave device; and, the control unit calls the corresponding device address from the I2C address device configuration module according to the slave address identification voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C slave address, forming the device address of the slave device or the device address of the I2C slave chip, so that other chips connected to the I2C bus can access the currently configured I2C slave chip. In each circuit structure, based on the fact that the voltage value of the voltage signal at the detection pin is proportional to the resistance value of the detection resistor connected to the detection pin, and the mapping relationship between the device address of the slave device and the voltage signal at the detection pin, the control unit can configure the I2C address device information according to the detection resistor. When the circuit structure is configured as a slave device, it also configures the device address of the slave device or the device address of the I2C slave chip, so that other chips connected to the I2C bus can access the currently configured I2C slave chip. Furthermore, based on the same mapping relationship pre-stored in the I2C address device configuration module, the device addresses of each slave device connected to the I2C bus can be addressed, and each slave device is assigned an address, so that when multiple host devices communicate with the slave device, the data sent by the slave device can be accurately transmitted to the corresponding host device, and even when the same firmware is burned, the conflict of the pin outputs of multiple circuit structures or multiple chips can be prevented.

[0015] Further, a slave identification voltage range corresponds to the role configuration information of a slave device, forming a mapping relationship between the role configuration information of the slave device and the voltage signal at the detection pin; wherein the preset target voltage value is the lower limit value of the slave identification voltage range; a slave identification voltage range is divided into multiple slave address identification voltage ranges, wherein a slave address identification voltage range corresponds to an I2C slave address, forming a mapping relationship between the device address of the slave device and the voltage signal at the detection pin; wherein the mapping relationship between the I2C address device information and the voltage value of the voltage signal at the detection pin includes the mapping relationship between the role configuration information of the slave device and the voltage signal at the detection pin, and the mapping relationship between the device address of the slave device and the voltage signal at the detection pin; in different chips, the slave address identification voltage ranges of the voltage signals at the respective detection pins are different, so that the chips included in the multiple slave devices are assigned different device addresses; wherein the I2C address device information includes the role configuration information of the slave device and its corresponding device address. Therefore, within the voltage range for identifying slave devices, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board, whether it is identified as a master slave in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a slave address identification voltage range, the device address of the I2C slave chip can be determined by the sensed voltage at its detection pin (specifically the voltage signal generated by the external detection resistor).

[0016] Furthermore, the number of slave address identification voltage ranges divided from a slave identification voltage range is equal to the number of circuit structures configured as slave devices connected to the I2C bus; among the circuit structures configured as slave devices, the detection resistor included in each of the circuit structures is configured to correspond to a slave detection resistor adjustment range; the number of slave detection resistor adjustment ranges corresponding to the detection resistor is equal to the number of divided slave address identification voltage ranges. It is achieved that the device addresses corresponding to any two circuit structures configured as slave devices in the I2C bus system are different.

[0017] Further, the I2C address device configuration module includes a register; the mapping relationship stores the voltage value of the voltage signal at each detection pin and its corresponding I2C address device information in the form of register mapping, a host address identification voltage range or a slave address identification voltage range in the register is mapped to the storage address range of its corresponding role configuration information in the register, and a host address identification voltage range or a slave address identification voltage range in the register is mapped to the storage address range of the device address in the register group; the mapping relationship also stores the resistance value of each detection resistor and the voltage value of the voltage signal at the detection pin to which each detection resistor is connected in the form of register mapping, the storage address range of the resistance value of a detection resistor in the register is mapped to the storage address range of the voltage signal at the detection pin to which a detection resistor is connected, and the storage address range of the voltage value of the voltage signal at a detection pin in the register falls within a host address identification voltage range or a slave address identification voltage range in the register. The mapping relationship is thereby implemented in the form of register mapping to enumerate the resistance value of the detection resistor, the voltage value of the voltage signal at the detection pin, the host address identification voltage range, the slave address identification voltage range, and the I2C address device information, so as to use registers to configure the mapping relationship for the control unit / chip / circuit structure, so as to automatically map the role configuration information and the device address when the control unit detects the voltage value of the corresponding voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram generally shows an I2C system in the prior art.

[0019] Figure 2 It is a schematic diagram of the internal component modules of the circuit structure disclosed in this application.

[0020] Figure 3 Schematic diagram of an I2C bus system for multiple circuit structure configurations disclosed in the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0022] Figure 1 The general diagram shows an example of a general I2C system, which includes an I2C master (represented by chip 1), multiple I2C slaves (in Figure 1In the figure, from left to right, I2C slave 1, I2C slave 2, I2C slave 3 are represented, and chip 2, chip 3 and chip 4 are represented, respectively) and pull-up resistors 101 and 102. Pull-up resistors 101 and 102 are configured to pull up SDA and SCL of the bus to the power supply voltage (3.3V voltage), respectively. In the prior art, I2C communication is a common communication control protocol.

[0023] If multiple ICs are to be used on the bus at the same time, relevant technical personnel must set the device address of each IC separately. For example, the I2C address of a chip is 1010ABC, where A, B, and C are the custom address values ​​of the chip. Then the I2C slave address of the chip can be set to a total of 8 different values. A total of 8 such ICs can be used on the same bus. Each IC is soldered to the circuit board according to a preset position (for example, a chip with a host role is soldered on one side, and a chip with a slave role is soldered on the other side). When the logical functions of each IC are configured, the firmware programs burned between different ICs are different. Therefore, when burning the firmware, relevant technical personnel need to distinguish the soldering positions of each IC and adjust the firmware according to the different soldering positions (actually the different device addresses). This is very cumbersome and error-prone in application, and the control of the chip is more complicated, which is not conducive to the design and application of I2C bus circuits.

[0024] In response to the aforementioned technical problems, the present application discloses an I2C bus system for configuring multiple circuit structures, the I2C bus system including multiple circuit structures connected to the I2C bus, the specific connection method being that the relevant data clock pins of the chips built into each circuit structure are connected to the I2C bus; the circuit structure is used to configure the I2C address device information according to the detection pins set therein, specifically, each circuit structure is used to configure the corresponding I2C address device information according to the detection pins set therein, including configuring the corresponding I2C address device information according to the current change, voltage change or connected resistance value change at the detection pins set therein, and automatically configuring the master-slave role configuration information and the device address according to the real-time detection results. During this configuration process, the configuration is automatically performed according to the signal at the detection pin, without externally distinguishing the position of the circuit structure, without increasing or decreasing the number of related pins, and without modifying the firmware program stored in part or all of the circuit structure.

[0025] The I2C address device information includes the device address. The device addresses configured by any two of the circuit structures are different, which also determines that the corresponding circuit structure in the same I2C bus will act as a host device or an I2C host chip, and the other circuit structures will act as slave devices or I2C slave chips; in one example, a circuit structure is a chip, or a connection structure of components connected to the chip's detection pins, and each circuit structure can have a unique address (for example, the ID of the I2C slave chip), so that several circuit structures (for example, multiple I2C slave chips, etc.) can use different addresses and coexist on the same two-wire bus (SDA and SCL of the I2C bus).

[0026] Indicatively, if Figure 3 As shown, in the I2C bus system, multiple circuit structures connected to the SDA and SCL of the I2C bus are circuit structure 1, circuit structure 2, circuit structure 3, and circuit structure 4 from left to right, wherein the detection pins provided in the circuit structures are detection pins of the chips provided in the circuit structures, specifically, in the same circuit structure, at the connection node between the chip and the detection circuit ( Figure 3 Not shown), the chip configures the corresponding I2C address device information according to the voltage signal change at the connection node, including whether the device is a host or a slave, and the specific assigned device address), the device addresses configured to circuit structure 1, circuit structure 2, circuit structure 3 and circuit structure 4 are different, and the roles they play are not necessarily the same. There is a part that is configured as a host device and the other part that is configured as a slave device.

[0027] The mapping relationships of the I2C address device information used by the multiple circuit structures are all the same, and these mapping relationships and the parameters required to be used, the mapped results and the mapped variables are all pre-stored in the storage unit provided in the circuit structure, so that each circuit structure is supported to burn the same firmware. In some mapping implementations, the mapping relationship of the I2C address device information includes the mapping relationship between the I2C address device information and the voltage signal at the detection pin, and the mapping relationship between the I2C address device information and the voltage signal at the detection pin is extracted from the mapping relationship between the I2C address device information and the detection resistor, and the mapping relationship between the I2C address device information and the detection resistor can be divided into the mapping relationship between the voltage signal at the detection pin and the detection resistor, and the mapping relationship between the I2C address device information and the voltage signal at the detection pin.

[0028] In summary, this embodiment automatically configures the I2C master-slave role and device address of each circuit structure by providing a corresponding pin foot (referring to a detection pin, or a specific pin of a chip inside the circuit structure) in the circuit structure connected to the I2C bus and detecting the signal at the pin foot in real time. There is no need for relevant technical personnel to burn matching firmware for each circuit structure according to the established welding position before leaving the factory. Even if the welding position is wrong, it will not affect the configuration of the correct device address of each circuit structure in the I2C bus, and there will be no identification failure or communication error in the connected I2C bus. The process of producing chips that support I2C communication is simplified, and the tediousness of burning different firmware due to the need to configure the master-slave role and device address can be simplified, which is beneficial to I2C bus circuit design and data communication applications.

[0029] In the above embodiment, multiple circuit structures all support burning the same firmware; after multiple circuit structures are burned with the same firmware, each circuit structure is used to configure the corresponding I2C address device information according to the signal at the detection pin set by each circuit structure, so that the circuit structure can be recognized by the I2C bus after configuring each I2C address device information, wherein the signal at the detection pin includes a voltage signal or a current signal, preferably a voltage signal generated at one end of the resistor connected to the detection pin, or a current signal flowing from one end of the resistor to the other end of the resistor. Under the mapping relationship of the I2C address device information, the signals at the detection pins set by any two circuit structures are different, and the I2C address device information corresponding to the configuration of any two circuit structures is different, forming a mapping relationship between the I2C address device information and the signal at the detection pin, which is applicable to all circuit structures, wherein the signal at the detection pin is the voltage signal at the detection pin; in addition, the mapping relationship between the I2C address device information and the detection resistor used by the multiple circuit structures is the same. The circuit structure may be an integrated circuit structure, including components connected to the detection pins; or, the circuit structure may be a PCB board-level circuit structure, and the circuit structure may be composed of a chip and components connected to the detection pins set on the chip.

[0030] It should be noted that, because the mapping relationship of the I2C address device information used by the multiple circuit structures is the same, the firmware burned for the multiple circuit structures in the factory state can be the same. Then, under the same mapping relationship of the I2C address device information, each circuit structure configures the corresponding I2C address device information according to the signal at the detection pin set by each circuit structure. The signals at the detection pins set by different circuit structures are different, and the configured I2C address device information is also different, specifically, the configured device addresses are different. In addition, configuring the corresponding I2C address device information according to the signal at the detection pin set by the circuit structure is the logical function configured by the same firmware to the circuit structure, so that the mapping relationship of the I2C address device information used by the multiple circuit structures is the same.

[0031] Therefore, when configuring the logical functions of each circuit structure, after completing the configuration of the chip that plays the role of the host, there is no need to modify the firmware before burning the chip that plays the role of the slave. The same firmware burned by multiple circuit structures can be used to configure the respective I2C address device information, thereby realizing the configuration of the device addresses required by different circuit structures and the master and slave roles they play according to the same mapping relationship. There is no need to pre-burn different firmware according to the difference in device addresses on the same I2C bus, thereby reducing the complexity of external I2C bus configuration.

[0032] As an example, combining Figure 2 and Figure 3 It can be seen that each of the circuit structures includes a chip and a detection resistor, and the resistance values ​​of the detection resistors set in any two of the circuit structures are different; corresponding to Figure 3 In the figure, circuit structure 1 includes chip 1 and detection resistor R1, circuit structure 2 includes chip 2 and detection resistor R2, circuit structure 3 includes chip 3 and detection resistor R3, and circuit structure 4 includes chip 4 and detection resistor R4, wherein detection resistor R1, detection resistor R2, detection resistor R3 and detection resistor R4 are not equal to each other.

[0033] In one of the circuit structures, a chip is provided with a serial data line pin, a serial clock line pin and a detection pin; the serial data line pin is connected to the serial data line SDA of the I2C bus, and the serial data line pin is used to receive a data signal from the serial data line SDA; the serial clock line pin is connected to the serial clock line SCL of the I2C bus, and the serial clock line pin is used to receive a clock signal from the serial clock line SCL, thereby connecting the circuit structure where the chip is located to the I2C bus.

[0034] See also Figure 2It can be seen that the detection pin is connected to the first end of the detection resistor, and the detection pin is used to collect the voltage signal generated by the first end of the detection resistor and configure the collected voltage signal as the voltage signal at the detection pin. The voltage value of the voltage signal at the detection pin is directly proportional to the resistance value of the detection resistor connected to the detection pin, forming a mapping relationship between the voltage signal at the detection pin and the detection resistor. Since there is a mapping relationship between the I2C address device information and the voltage signal at the detection pin, a mapping relationship between the I2C address device information and the detection resistor is formed, and it is applicable to all the circuit structures in the I2C bus system, so that the mapping relationship of the I2C address device information used by the multiple circuit structures is the same. In this embodiment, when the current value flowing through the detection resistor remains unchanged, the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor connected to the detection pin, so that the voltage value of the voltage signal at the detection pin can feedback the resistance value of the detection resistor in real time. As long as the chip is mounted on the circuit board (not limited to the specific position, nor distinguished from other chips) and powered on, since there is a mapping relationship between the I2C address device information and the detection resistor, the chip can directly configure the corresponding I2C address device information according to the external resistance value of the detection pin. Based on the circuit structure disclosed in this application and the chip inside it, the setting of the I2C address device information (including the I2C address or device address) and the control of the master-slave role can be realized through a completely software operation mode. Reduce the difficulty of configuring the mapping relationship between the voltage signal at the detection pin and the detection resistor, and speed up the process of producing chips that support I2C communication.

[0035] As an example, Figure 2As shown, the chip includes a control unit, an I2C address device configuration module and a current source, wherein the detection resistor is equivalent to an external resistor of the chip and is connected to a detection pin provided on the chip; the control unit may be a microcontroller (MCU), as a control core embedded in the chip. The current source is connected to the first end of the detection resistor, and the second end of the detection resistor is grounded; the detection resistor is used to receive the current output by the current source and generate a voltage signal at the detection pin at its first end. The current source is used to generate a constant current so that the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor. In some embodiments, a current source of 100uA flowing through the detection resistor will generate a voltage value U on the detection pin, that is, U=100uA×R0, where U is the voltage value of the voltage signal at the detection pin, and R0 is the resistance value of the detection resistor. The control unit will collect the voltage value U generated on the detection pin through the analog-to-digital converter, and thus configure the master-slave role and the device address according to the mapping relationship of the I2C address device information. In actual application, the chip can distinguish the master-slave role and the device address according to the resistance value of the detection resistor connected to its detection pin or the voltage value of the voltage signal at the detection pin, wherein the I2C address device information includes the master-slave role configuration information and the device address.

[0036] The I2C address device configuration module is connected to the control unit; the control unit is used to detect the voltage signal at the detection pin generated by the first end of the detection resistor, and then based on the determination of the voltage signal at the detection pin, the I2C address device information is called from the I2C address device configuration module according to the mapping relationship of the I2C address device information, and then the called I2C address device information is configured as the I2C address device information of the circuit structure where the control unit is located, so as to configure the I2C address device information according to the detection pin set by it, and the I2C address device information can be the configuration information of the circuit structure or the configuration information of the chip, and the mapping relationship of the I2C address device information is compatible with all chips connected to the I2C bus. To support other circuit structures or chips connected to the same I2C bus to identify the corresponding device address and access it through the I2C bus, and all chips connected to the I2C bus are configured with the corresponding I2C address device information through the same mapping relationship (the corresponding relationship agreed in advance in the I2C address device configuration module).

[0037] It should be noted that the I2C address device configuration module is used to store the mapping relationship of the I2C address device information, and the mapping relationship in each chip belongs to a pre-agreed corresponding relationship. The mapping relationship of the I2C address device information includes the mapping relationship between the I2C address device information and the detection resistor, and the mapping relationship between the I2C address device information and the detection resistor includes the mapping relationship between the voltage signal at the detection pin and the detection resistor, and the mapping relationship between the I2C address device information and the voltage signal at the detection pin. The mapping relationship of the I2C address device information is compatible with all chips connected to the I2C bus; thereby, in each chip connected to the I2C bus, a mapping relationship between the I2C address device information and the detection resistor and the voltage signal at the detection pin is constructed, which is compatible with the mapping relationship of all chips connected to the I2C bus, and improves the functional logic of each control unit controlling the detection resistor and the voltage signal at the detection pin to map the corresponding I2C address device information.

[0038] In summary, the I2C address device configuration module is provided with a mapping relationship between the I2C address device information and the voltage signal at the detection pin, or a mapping relationship between the I2C address device information and the detection resistor; then the control unit uses the voltage signal at the detection pin to configure the corresponding I2C address device information based on the mapping relationship. Therefore, based on the chip disclosed in this embodiment, usually only one detection resistor port needs to be reserved, and there is no need to provide multiple components for users to weld and debug, and the setting of the I2C address device information (including the I2C address or device address) and the control of the master and slave roles can be realized through a completely software-based operation mode.

[0039] Since the mapping relationship of I2C address device information is compatible with all chips connected to the I2C bus, all chips can be burned with the same firmware. There is no need to burn different firmware according to different device addresses. This simplifies the tedious process of burning different firmware due to the need to configure master-slave roles and device addresses, and greatly improves the process of producing chips that support I2C communication.

[0040] Preferably, the chip further includes an analog-to-digital converter; the detection pin is connected to the collection end of the analog-to-digital converter; the analog-to-digital converter is used to collect the voltage signal at the detection pin generated by the first end of the detection resistor, and convert the collected voltage signal into a voltage identification value, which is equivalent to converting the analog voltage at the first end of the detection resistor into a digital voltage encoding value as the voltage sampling information of the chip at the detection pin. Figure 2It can be seen that the control unit is connected to the conversion output end of the analog-to-digital converter; the control unit is used to receive the voltage identification value and transmit it to the I2C address device configuration module, so as to detect the voltage signal generated by the first end of the detection resistor through the analog-to-digital converter. The control unit is used to call the I2C address device information corresponding to the voltage identification value from the I2C address device configuration module according to the voltage identification value; wherein the mapping relationship between the I2C address device information and the voltage identification value is the mapping relationship between the I2C address device information and the converted voltage signal, and the current source is used to generate a constant current so that the voltage identification value is proportional to the resistance value of the detection resistor. This embodiment converts the voltage signal at the detection pin into a digital signal that is easy for the control unit to identify and encode in real time through the analog-to-digital converter, thereby improving the efficiency of voltage value comparison and mapping.

[0041] As an embodiment of configuring a host device, the control unit calls the I2C address device information from the I2C address device configuration module according to the mapping relationship of the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is less than the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and the basis for the call is the mapping relationship between the role configuration information and the voltage signal at the detection pin; then, according to the called role configuration information, the chip where the control unit is located is configured as an I2C host chip, and the circuit structure where the control unit is located is configured as a host device; and, the control unit detects the voltage value of the voltage signal at the detection pin and determines which host address identification voltage range it falls into; the control unit calls the corresponding device address from the I2C address device configuration module according to the host address identification voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C host address to form the device address of the host device or I 2C host chip, the basis for calling at this time is the mapping relationship between the device address of the host device and the voltage signal at the detection pin; in summary, the control unit uses the voltage signal from the detection resistor detected in real time to configure the corresponding I2C address device information based on the mapping relationship pre-stored in the I2C address device configuration module, so as to configure the circuit structure where the control unit is located as a host device, and configure its device address in the I2C bus as an I2C host address; it can be understood that, in each circuit structure, based on the voltage value of the voltage signal at the detection pin and the resistance value of the detection resistor connected to the detection pin being in direct proportion, and the mapping relationship between the device address of the host device and the voltage signal at the detection pin, the control unit can configure the I2C address device information according to the detection resistor, and the circuit structure is configured as a host device, while also configuring the device address of the host device or the device address of the I2C host chip, so that other chips connected to the I2C bus can access the currently configured I2C host chip.

[0042] Furthermore, based on the same mapping relationship pre-stored in the I2C address device configuration module, the device addresses of each host device connected to the I2C bus can be addressed, and each host device is assigned an address, so that when the host device communicates with multiple slave devices, the data sent by the host device can be accurately transmitted to the corresponding slave device. Even when the same firmware is burned, conflicts among the pins of multiple circuit structures or the pin outputs of multiple chips can be prevented.

[0043] In some embodiments, the mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is as described in Table 1 below:

[0044]

[0045] In the aforementioned embodiment, a host identification voltage range corresponds to the role configuration information of a host device, forming a mapping relationship between the role configuration information of the host device and the voltage signal at the detection pin, wherein the preset target voltage value is the upper limit value of the host identification voltage range, preferably 1.35 V. A host identification voltage range is divided into multiple host address identification voltage ranges, wherein the host identification voltage range is preferably 0 to 1.35 V. As described in Table 1, when the voltage signal at the detection pin falls within the host identification voltage range of 0 to 1.35 V, the circuit structure is configured as a host device, corresponding to the above Table 1, the role configuration information of the circuit structure is the host, that is, the role configuration information of the host device.

[0046] Combined with Table 1, it can be seen that the host recognition voltage range of 0 to 1.35V is divided into 0.0000 to 0.3375V, 0.3375 to 0.6750V, 0.6750 to 1.0125V and 1.0125 to 1.3500V respectively. A host address identification voltage range corresponds to an I2C host address, forming a mapping relationship between the device address of the host device and the voltage signal at the detection pin, where the I2C host address is the device address of the host device; as described in Table 1, the host address identification voltage range of 0.0000 to 0.3375V corresponds to an address value of 0 of an I2C host address, the host address identification voltage range of 0.3375 to 0.6750V corresponds to an address value of 1 of an I2C host address, the host address identification voltage range of 0.6750 to 1.0125V corresponds to an address value of 2 of an I2C host address, and the host address identification voltage range of 1.0125 to 1.3500V corresponds to an address value of 3 of an I2C host address. Among them, the I2C address device information includes the role configuration information of the host device and its corresponding device address. In summary, whenever the boundary value (upper limit or lower limit) of the host address recognition voltage range increases by 0.3375V, the address value of the corresponding mapped I2C host address increases by 1, and starts from address value 0 until it increases to address value 4.

[0047] In Table 1, the mapping relationship between the I2C address device information and the voltage signal at the detection pin includes the mapping relationship between the role configuration information of the host device and the voltage signal at the detection pin, and the mapping relationship between the device address of the host device and the voltage signal at the detection pin. In different chips, the voltage values ​​of the voltage signals at the respective detection pins are in different host address identification voltage ranges, so that the chips included in multiple host devices are assigned different device addresses. For example, Figure 3The voltage value generated by the detection resistor R1 collected by the chip 1 shown falls into the host address recognition voltage range of 0.0000 to 0.3375V, which is mapped to the address value 0 of the I2C host address. The chip 1 is configured as an I2C host chip, and its device address is assigned to the address value 0; furthermore, Figure 3 The voltage value generated by the detection resistor R2 collected by the chip 2 shown falls into the host address identification voltage range of 0.3375 to 0.6750V, which is mapped to the address value 1 of the I2C host address. The chip 2 is configured as an I2C host chip, and its device address is assigned to the address value 1.

[0048] Therefore, within the voltage range of identifying the host device, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board and whether it is identified as a master or slave in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls within a host address recognition voltage range, the role configuration information and the device address can be determined by the sensing voltage at its detection pin (specifically the voltage signal generated by the external detection resistor).

[0049] Based on the above embodiments, combined with Table 1, it can be seen that the number of host address identification voltage ranges divided by a host identification voltage range is equal to the number of circuit structures configured as host devices connected to the I2C bus, and is also equal to the number of I2C host chips. The voltage change value covered by each host address identification voltage range is equal, and the specific value is equal to 0.3375V; corresponding to Table 1, the number of circuit structures configured as host devices is 4, and the number of I2C host chips is also 4.

[0050] In the circuit structure configured as a host device, the detection resistor included in each of the circuit structures is configured to correspond to a host detection resistance adjustment range. Corresponding to Table 1, the host detection resistance adjustment ranges are 0.000 to 3.375 kΩ, 3.375 to 6.750 kΩ, 6.750 to 10.125 kΩ, and 10.125 to 13.500 kΩ, respectively. Corresponding to the mapping relationship, the host address identification voltage range of 0.0000 to 0.3375V corresponds to a host detection resistance adjustment range of 0.000 to 3.375kΩ, and the ratio between the two values ​​can be regarded as the current value of 100uA output by the current source, and the voltage value of the voltage signal at the detection pin is directly proportional to the resistance value of the detection resistor; similarly, the host address identification voltage range of 0.3375 to 0.6750V corresponds to a host detection resistance adjustment range of 3.375 to 6.750kΩ, the host address identification voltage range of 0.6750 to 1.0125V corresponds to a host detection resistance adjustment range of 6.750 to 10.125kΩ, and the host address identification voltage range of 1.0125 to 1.3500V corresponds to a host detection resistance adjustment range of 10.125 to 13.500kΩ. Among them, the resistance change value covered by each host detection resistor adjustment range is equal, and the specific value is equal to 3.375kΩ. The number of host detection resistor adjustment ranges corresponding to the detection resistor is equal to the number of divided host address identification voltage ranges, and the resistance change value covered by each host detection resistor adjustment range is equal. Corresponding to Table 1, in the I2C bus system, the number of host detection resistor adjustment ranges corresponding to the detection resistor is 4, and the number of detection resistors connected to the detection pins of the I2C host chip is 4; in a circuit structure, when the resistance value of the detection resistor is in a host detection resistor adjustment range, the voltage value of the voltage signal generated by the first end of the detection resistor is in a corresponding host address identification voltage range. It is realized that the device addresses corresponding to any two circuit structures configured as host devices in the I2C bus system are different.

[0051] Preferably, for the voltage signal at the detection pin, within the voltage range where the voltage value is less than the preset target voltage value, there are multiple different host address identification voltage ranges, and each host address identification voltage range supports burning the same firmware, that is, accepting the mapping relationship disclosed in Table 1, so that by connecting the corresponding resistance value detection resistor to the chip that needs to play the same role or different roles, the circuit structure is triggered to recognize in real time and configure the corresponding role configuration information and the corresponding device address in the I2C bus for the chip set therein, and the circuit structure is also configured with the corresponding role configuration information and assigned to the corresponding device address. Therefore, all chips connected to the I2C bus can be burned with a unified firmware, and there is no need to distinguish the position order when pasting the chip, and it can be pasted at will; only after the I2C bus system is powered on, whenever the firmware detects that the voltage value of the voltage signal at the detection pin falls into a host address identification voltage range, the firmware can judge the master-slave role configuration information and the device address according to the set mapping relationship through the resistance value of the detection resistor, thereby improving the production efficiency of chips supporting I2C communication.

[0052] Preferably, the I2C address device configuration module includes a register, and the I2C address device configuration module can be a register group connected by multiple registers; the mapping relationship mentioned in the above embodiment stores the voltage value of the voltage signal at each detection pin and its corresponding I2C address device information in the form of register mapping, which can form a mapping table in the register; a host address identification voltage range in the register is mapped to its corresponding role configuration information in the storage address range of the register, and a host address identification voltage range in the register is mapped to the device address in the register. The mapping relationship also stores the resistance value of each detection resistor and the voltage value of the voltage signal at the detection pin connected to each detection resistor in the form of register mapping, and the storage address range of the resistance value of a detection resistor in the register is mapped to the storage address range of the voltage signal at the detection pin connected to a detection resistor in the register, and the storage address range of the voltage value of the voltage signal at a detection pin in the register falls within the storage address range of a host address identification voltage range in the register. Thus, the mapping relationship is realized in the form of register mapping to enumerate the resistance value of the detection resistor, the voltage value of the voltage signal at the detection pin, the host address identification voltage range, and the I2C address device information, so as to use the register to configure the mapping relationship for the control unit / chip / circuit structure, so that when the control unit detects the voltage value of the corresponding voltage signal, the role configuration information and the device address are automatically mapped. This mapping facilitates the access operation to the register.

[0053] In some embodiments, the control unit includes an address selector, which is used to identify the voltage range of the host address into which the voltage value of the voltage signal at the detection pin falls, and select the corresponding I2C host address (i.e., the device address of the host device or the I2C host chip) for the host device or the I2C host chip based on the aforementioned mapping relationship. The corresponding device address may be selected for the host device in the mapping table set in the I2C address device configuration module.

[0054] As an embodiment of configuring a slave device, the control unit calls the I2C address device information from the I2C address device configuration module according to the mapping relationship of the I2C address device information, including: when the control unit detects that the voltage value of the voltage signal at the detection pin is greater than or equal to the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and the basis for the call at this time is the mapping relationship between the role configuration information and the voltage signal at the detection pin; then, according to the called role configuration information, the chip where the control unit is located is configured as an I2C slave chip, and the circuit structure where the control unit is located is configured as a slave device; and the control unit detects the voltage value of the voltage signal at the detection pin and determines which slave address identification voltage range it falls into; the control unit calls the corresponding device address from the I2C address device configuration module according to the slave address identification voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C slave address to form the device address of the slave device or the device address of the I2C slave chip, and the basis for calling at this time is the mapping relationship between the device address of the slave device and the voltage signal at the detection pin; in summary, the control unit uses the voltage signal from the detection resistor detected in real time to configure the corresponding I2C address device information based on the mapping relationship pre-stored in the I2C address device configuration module, so as to configure the circuit structure where the control unit is located as a slave device, and configure its device address in the I2C bus as the I2C slave address; it can be understood that, in each circuit structure, based on the voltage value of the voltage signal at the detection pin and the resistance value of the detection resistor connected to the detection pin being in direct proportion, and the mapping relationship between the device address of the slave device and the voltage signal at the detection pin, the control unit can configure the I2C address device information according to the detection resistor, and the circuit structure is configured as a slave device, and the device address of the slave device or the device address of the I2C slave chip is also configured, so that other chips connected to the I2C bus can access the currently configured I2C slave chip. Furthermore, based on the same mapping relationship pre-stored in the I2C address device configuration module, the device addresses of each slave device connected to the I2C bus can be addressed, and each slave device is assigned an address, so that when multiple host devices communicate with the slave device, the data sent by the slave device can be accurately transmitted to the corresponding host device. Even when the same firmware is burned, conflicts among the pins of multiple circuit structures or the pin outputs of multiple chips can be prevented.

[0055] In some embodiments, the mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is as described in Table 2 below:

[0056]

[0057]

[0058] A slave identification voltage range corresponds to the role configuration information of a slave device, forming a mapping relationship between the role configuration information of the slave device and the voltage signal at the detection pin, wherein the preset target voltage value is the lower limit of the slave identification voltage range, preferably 1.35V. A slave identification voltage range is divided into multiple slave address identification voltage ranges, wherein the slave identification voltage range is preferably 1.35 to 2.7V. As described in Table 2, when the voltage signal at the detection pin falls within the slave identification voltage range of 1.35 to 2.7V, the circuit structure is configured as a slave device, corresponding to Table 2 above, the role configuration information of the circuit structure is a slave, that is, the role configuration information of the slave device.

[0059] Combined with Table 2, it can be seen that the slave identification voltage range of 1.35 to 2.7V is divided into 1.3500 to 1.6875V, 1.6875 to 2.0250V, 2.0250 to 2.3625V and 2.3625 to 2.7000V. A slave address identification voltage range corresponds to an I2C slave address, forming a mapping relationship between the device address of the slave device and the voltage signal at the detection pin, where the I2C slave address is the device address of the slave device; as described in Table 2, the slave address identification voltage range of 1.3500 to 1.6875V corresponds to an I2C slave address value of 4, the slave address identification voltage range of 1.6875 to 2.0250V corresponds to an I2C slave address value of 5, the slave address identification voltage range of 2.0250 to 2.3625V corresponds to an I2C slave address value of 6, and the slave address identification voltage range of 2.3625 to 2.7000V corresponds to an I2C slave address value of 6. Among them, the I2C address device information includes the role configuration information of the slave device and its corresponding device address. In summary, whenever the boundary value (upper limit or lower limit) of the slave address recognition voltage range increases by 0.3375V, the address value of the corresponding mapped I2C slave address increases by 1, and starts from address value 4.

[0060] In Table 2, the mapping relationship between the I2C address device information and the voltage signal at the detection pin includes the mapping relationship between the role configuration information of the slave device and the voltage signal at the detection pin, and the mapping relationship between the device address of the slave device and the voltage signal at the detection pin. In different chips, the voltage values ​​of the voltage signals at the respective detection pins are in different slave address identification voltage ranges, so that the chips included in the multiple slave devices are assigned different device addresses. For example, Figure 3 The voltage value generated by the detection resistor R3 collected by the chip 3 shown falls into the slave address recognition voltage range of 1.6875 to 2.0250V, which is mapped to the address value 5 of the I2C slave address. The chip 3 is configured as an I2C slave chip, and its device address is assigned to the address value 5; furthermore, Figure 3 The chip 4 shown collects the voltage value generated by the detection resistor R4 and falls into the slave address identification voltage range of 2.0250 to 2.3625V, which is mapped to the address value 6 of the I2C slave address. The chip 4 is configured as an I2C slave chip, and its device address is assigned to the address value 6. Therefore, within the voltage range of identifying the slave device, a mapping relationship between the detection resistor, the voltage signal at the detection pin, the role configuration information and the device address is established and solidified into the chip. No matter where the chip is mounted on the circuit board, whether it is identified as a master slave in advance, whenever the chip detects that the voltage value of the voltage signal at the detection pin falls into a slave address identification voltage range, the device address of the I2C slave chip can be determined by the sensed voltage at its detection pin (specifically, the voltage signal generated by the external detection resistor).

[0061] Based on the above embodiment, combined with Table 2, it can be known that the number of slave address identification voltage ranges divided by a slave identification voltage range is equal to the number of circuit structures configured as slave devices connected to the I2C bus, and is also equal to the number of I2C slave chips. The voltage change value covered by each slave address identification voltage range is equal, and the specific value is equal to 0.3375V; corresponding to Table 2, the number of circuit structures configured as slave devices is 4, and the number of I2C slave chips is also 4. Among the circuit structures configured as slave devices, the detection resistor included in each of the circuit structures is configured to correspond to a slave detection resistor adjustment range. Corresponding to Table 2, the slave detection resistor adjustment ranges are 13.500 to 16.875kΩ, 16.875 to 20.250kΩ, 20.250 to 23.625kΩ, and 23.625 to 27.000kΩ, respectively. Corresponding to the mapping relationship, the slave address identification voltage range of 1.3500 to 1.6875V corresponds to a slave detection resistance adjustment range of 13.500 to 16.875kΩ, and the ratio between the two values ​​can be regarded as the current value of 100uA output by the current source, and the voltage value of the voltage signal at the detection pin is directly proportional to the resistance value of the detection resistor; similarly, the slave address identification voltage range of 1.6875 to 2.0250V corresponds to a slave detection resistance adjustment range of 16.875 to 20.250kΩ, the host address identification voltage range of 2.0250 to 2.3625V corresponds to a slave detection resistance adjustment range of 20.250 to 23.625kΩ, and the host address identification voltage range of 2.3625 to 2.7000V corresponds to a slave detection resistance adjustment range of 23.625 to 27.000kΩ. Among them, the resistance change value covered by each slave detection resistor adjustment range is equal, and the specific value is equal to 3.375kΩ. The number of slave detection resistor adjustment ranges corresponding to the detection resistor is equal to the number of slave address identification voltage ranges divided, and the resistance change value covered by each slave detection resistor adjustment range is equal. Corresponding to Table 2, in the I2C bus system, the number of slave detection resistor adjustment ranges corresponding to the detection resistor is 4, and the number of detection resistors connected to the detection pins of the I2C slave chip is 4; in a circuit structure, when the resistance value of the detection resistor is in a slave detection resistor adjustment range, the voltage value of the voltage signal generated by the first end of the detection resistor is in a corresponding slave address identification voltage range. It is realized that the device addresses corresponding to any two circuit structures configured as host devices in the I2C bus system are different.

[0062] Preferably, for the voltage signal at the detection pin, within the voltage range where the voltage value is greater than or equal to the preset target voltage value, there are multiple different slave address identification voltage ranges, and each slave address identification voltage range supports burning the same firmware, that is, accepting the mapping relationship disclosed in Table 2, so that by connecting the detection resistor of the corresponding resistance value to the chip that needs to play the same role or different roles, the circuit structure is triggered to recognize in real time and configure the corresponding role configuration information and the corresponding device address in the I2C bus for the chip set therein, and the circuit structure is also configured with the corresponding role configuration information and assigned to the corresponding device address. Therefore, all chips connected to the I2C bus can be burned with a unified firmware, and there is no need to distinguish the position order when pasting the chip, and it can be pasted at will; only after the I2C bus system is powered on, whenever the firmware detects that the voltage value of the voltage signal at the detection pin falls into a slave address identification voltage range, the firmware can judge the slave role configuration information and the device address according to the set mapping relationship through the resistance value of the detection resistor, thereby improving the production efficiency of chips supporting I2C communication.

[0063] Preferably, the I2C address device configuration module includes a register, and the I2C address device configuration module can be a register group connected by multiple registers; the mapping relationship mentioned in the above embodiment stores the voltage value of the voltage signal at each detection pin and its corresponding I2C address device information in the form of register mapping, which can form a mapping table in the register; a storage address range of a slave address identification voltage range in the register is mapped to the storage address range of its corresponding role configuration information in the register, and a storage address range of a slave address identification voltage range in the register is mapped to the storage address range of the device address in the register. The mapping relationship also stores the resistance value of each detection resistor and the voltage value of the voltage signal at the detection pin connected to each detection resistor in the form of register mapping, and the storage address range of the resistance value of a detection resistor in the register is mapped to the storage address range of the voltage signal at the detection pin connected to a detection resistor in the register, and the storage address range of the voltage value of the voltage signal at a detection pin in the register falls within the storage address range of a slave address identification voltage range in the register. Thus, the mapping relationship is realized in the form of register mapping to enumerate the resistance value of the detection resistor, the voltage value of the voltage signal at the detection pin, the slave address identification voltage range, and the I2C address device information, so as to use the register to configure the mapping relationship for the control unit / chip / circuit structure, so that when the control unit detects the voltage value of the corresponding voltage signal, the role configuration information and the device address are automatically mapped. This mapping facilitates the access operation to the register.

[0064] In some embodiments, the control unit includes an address selector, which is used to identify the voltage range of the host address into which the voltage value of the voltage signal at the detection pin falls, and select the corresponding I2C slave address (i.e., the device address of the slave device or the I2C slave chip) for the slave device or the I2C slave chip based on the aforementioned mapping relationship. The corresponding device address may be selected for the slave device in the mapping table set in the I2C address device configuration module.

[0065] It should be added that Figure 3 As shown, the serial data line SDA of the I2C bus is pulled up to the power supply voltage 3.3V through the pull-up resistor R6, and the serial clock line SCL of the I2C bus is pulled up to the power supply voltage 3.3V through the pull-up resistor R5; thus, in the process of configuring the I2C address device information for the circuit structure, normal I2C communication is not affected.

[0066] Preferably, among the plurality of circuit structures, at least one circuit structure is configured as a host device, and at least one circuit structure is configured as a slave device, corresponding to Figure 3 In the example, when chip 1 and chip 2 are configured as I2C host chips, chip 3 and chip 4 are configured as I2C slave chips, that is, when circuit structure 1 and circuit structure 2 are configured as host devices, circuit structure 3 and circuit structure 4 are configured as slave devices. Of course, the role configuration of circuit structure 1 to circuit structure 4 is not unique, and no specific restrictions are made here. Accordingly, the role configuration of chip 1 to chip 2 is not unique but consistent with the circuit structure in which it is located. The configured host device accesses other devices connected to the I2C bus, or the configured slave device accesses other devices connected to the I2C bus.

[0067] The above embodiments are only for full disclosure rather than limitation of the present invention. Any replacement of equivalent technical features based on the creative purpose of the present invention without creative work should be regarded as the scope disclosed by this application.

Claims

1. An I2C bus system for multiple circuit configurations, characterized in that: The I2C bus system includes a plurality of circuit structures connected to the I2C bus, wherein the circuit structures are used to configure I2C address device information according to detection pins set thereon; The I2C address device information includes a device address, and the device addresses configured by any two of the circuit structures are different; Among them, the mapping relationship of the I2C address device information used by the multiple circuit structures is the same.

2. The I2C bus system according to claim 1, characterized in that: A plurality of the circuit structures all support burning the same firmware; After the same firmware is burned into the plurality of circuit structures, each circuit structure is used to configure the corresponding I2C address device information according to the signal at the detection pin set by the respective circuit structure; Under the mapping relationship of the I2C address device information, the signals at the detection pins set by any two circuit structures are different, and the I2C address device information corresponding to the configured any two circuit structures is different.

3. The I2C bus system according to claim 2, characterized in that: Each of the circuit structures comprises a chip and a detection resistor; the resistance values ​​of the detection resistors arranged inside any two of the circuit structures are different; In the circuit structure, the chip is provided with a serial data line pin, a serial clock line pin and the detection pin; The serial data line pin is connected to the serial data line of the I2C bus, and the serial data line pin is used to receive a data signal from the serial data line; the serial clock line pin is connected to the serial clock line of the I2C bus, and the serial clock line pin is used to receive a clock signal from the serial clock line; The detection pin is connected to the first end of the detection resistor, and the detection pin is used to collect the voltage signal generated by the first end of the detection resistor and configure the collected voltage signal as the voltage signal at the detection pin; The voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor connected to the detection pin, thereby forming a mapping relationship between the voltage signal at the detection pin and the detection resistor.

4. The I2C bus system according to claim 3, characterized in that: The chip includes a control unit, an I2C address device configuration module, and a current source; The current source is connected to the first end of the detection resistor, and the second end of the detection resistor is grounded; the detection resistor is used to receive the current output by the current source and generate a voltage signal at the detection pin at its first end; The current source is used to generate a constant current so that the voltage value of the voltage signal at the detection pin is in direct proportion to the resistance value of the detection resistor; The I2C address device configuration module is connected to the control unit; the control unit is used to detect the voltage signal at the detection pin generated by the first end of the detection resistor, and then call the I2C address device information from the I2C address device configuration module according to the mapping relationship of the I2C address device information on the basis of determining the voltage signal at the detection pin, and then configure the called I2C address device information as the I2C address device information of the circuit structure where the control unit is located, so as to configure the I2C address device information according to the detection pin set by it; wherein the mapping relationship of the I2C address device information is compatible with all chips connected to the I2C bus; The I2C address device configuration module is used to store the mapping relationship about the I2C address device information, the mapping relationship about the I2C address device information includes the mapping relationship between the I2C address device information and the detection resistor, the mapping relationship between the I2C address device information and the detection resistor includes the mapping relationship between the voltage signal at the detection pin and the detection resistor, and the mapping relationship between the I2C address device information and the voltage signal at the detection pin.

5. The I2C bus system according to claim 4, characterized in that: The chip also includes an analog-to-digital converter; The detection pin is connected to the collection end of the analog-to-digital converter; the analog-to-digital converter is used to collect the voltage signal at the detection pin generated by the first end of the detection resistor, and convert the collected voltage signal into a voltage identification value; The control unit is connected to the conversion output end of the analog-to-digital converter; the control unit is used to receive the voltage identification value and transmit it to the I2C address device configuration module, so as to detect the voltage signal generated by the first end of the detection resistor through the analog-to-digital converter; The control unit is used to call the I2C address device information corresponding to the voltage identification value from the I2C address device configuration module according to the voltage identification value; wherein the mapping relationship between the I2C address device information and the voltage identification value is the mapping relationship between the I2C address device information and the converted voltage signal.

6. The I2C bus system according to claim 4, characterized in that: The control unit calls the I2C address device information from the I2C address device configuration module according to the mapping relationship of the I2C address device information, including: When the control unit detects that the voltage value of the voltage signal at the detection pin is less than the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and then the chip where the control unit is located is configured as an I2C host chip according to the called role configuration information, and the circuit structure where the control unit is located is configured as a host device; and the control unit calls the corresponding device address from the I2C address device configuration module according to the host address recognition voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C host address, forming the device address of the host device or the device address of the I2C host chip, so that other chips connected to the I2C bus can access the currently configured I2C host chip.

7. The I2C bus system according to claim 6, characterized in that: One host identification voltage range corresponds to one host device role configuration information, forming a mapping relationship between the host device role configuration information and the voltage signal at the detection pin; wherein the preset target voltage value is the upper limit value of the host identification voltage range; A host identification voltage range is divided into a plurality of host address identification voltage ranges, wherein one host address identification voltage range corresponds to one I2C host address, forming a mapping relationship between a device address of a host device and a voltage signal at the detection pin; wherein the mapping relationship between the I2C address device information and the voltage signal at the detection pin includes a mapping relationship between the role configuration information of the host device and the voltage signal at the detection pin, and a mapping relationship between the device address of the host device and the voltage signal at the detection pin; In different chips, the host address identification voltage ranges of the voltage signals at the respective detection pins are different, so that the chips included in the multiple host devices are assigned different device addresses; The I2C address device information includes the role configuration information of the host device and its corresponding device address.

8. The I2C bus system according to claim 7, characterized in that: The number of host address identification voltage ranges divided by one host identification voltage range is equal to the number of circuit structures configured as host devices connected to the I2C bus, and the voltage change value covered by each host address identification voltage range is equal; In a circuit structure configured as a host device, the detection resistor included in each of the circuit structures is configured to correspond to a host detection resistor adjustment range; the number of host detection resistor adjustment ranges corresponding to the detection resistor is equal to the number of divided host address identification voltage ranges; and the resistance change value covered by each host detection resistor adjustment range is equal.

9. The I2C bus system according to claim 4, characterized in that: The control unit calls the I2C address device information from the I2C address device configuration module according to the mapping relationship of the I2C address device information, including: When the control unit detects that the voltage value of the voltage signal at the detection pin is greater than or equal to the preset target voltage value, the corresponding role configuration information is called from the I2C address device configuration module, and then the chip where the MCU is located is configured as an I2C slave chip according to the called role configuration information, and the circuit structure where the control unit is located is configured as a slave device; and the control unit calls the corresponding device address from the I2C address device configuration module according to the slave address recognition voltage range into which the voltage value of the voltage signal at the detection pin falls, and then configures the called device address as the I2C slave address, forming the device address of the slave device or the device address of the I2C slave chip, so that other chips connected to the I2C bus can access the currently configured I2C slave chip.

10. The I2C bus system according to claim 9, characterized in that: One slave identification voltage range corresponds to one role configuration information of a slave device, forming a mapping relationship between the role configuration information of the slave device and the voltage signal at the detection pin; wherein the preset target voltage value is the lower limit value of the slave identification voltage range; A slave identification voltage range is divided into a plurality of slave address identification voltage ranges, wherein one slave address identification voltage range corresponds to one I2C slave address, forming a mapping relationship between the device address of the slave device and the voltage signal at the detection pin; The mapping relationship between the I2C address device information and the voltage value of the voltage signal at the detection pin includes the mapping relationship between the role configuration information of the slave device and the voltage signal at the detection pin, and the mapping relationship between the device address of the slave device and the voltage signal at the detection pin; In different chips, the voltage signals at the respective detection pins are located in different slave address identification voltage ranges, so that the chips included in the multiple slave devices are assigned different device addresses; The I2C address device information includes the role configuration information of the slave device and its corresponding device address.

11. The I2C bus system according to claim 10, characterized in that: The number of slave address identification voltage ranges divided by one slave identification voltage range is equal to the number of circuit structures configured as slave devices connected to the I2C bus; In the circuit structure configured as a slave device, the detection resistor included in each of the circuit structures is configured to correspond to a slave detection resistor adjustment range; the number of slave detection resistor adjustment ranges corresponding to the detection resistor is equal to the number of divided slave address identification voltage ranges.

12. The I2C bus system according to claim 7 or 10, characterized in that: The I2C address device configuration module includes registers; The mapping relationship stores the voltage value of the voltage signal at each detection pin and its corresponding I2C address device information in the form of register mapping, a host address identification voltage range or a slave address identification voltage range in the register is mapped to the storage address range of its corresponding role configuration information in the register, and a host address identification voltage range or a slave address identification voltage range in the register is mapped to the storage address range of the device address in the register group; The mapping relationship also stores the resistance value of each detection resistor and the voltage value of the voltage signal at the detection pin to which each detection resistor is connected in the form of register mapping, and the storage address range of the resistance value of a detection resistor in the register is mapped to the storage address range of the voltage value of the voltage signal at the detection pin to which a detection resistor is connected in the register, and the storage address range of the voltage value of the voltage signal at the detection pin in the register falls within a host address identification voltage range or a slave address identification voltage range in the storage address range in the register.

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