A quantum bit mapping method

Abstract

The application provides a quantum bit mapping method, and the technical scheme of the application converts a hardware error rate into an estimated correct rate similar to a distance on a physical topology by constructing a noisy distance matrix, adds the estimated correct rate of the corresponding circuit executed on the basis of the topology distance between each two physical bits, thereby considering the error rate information of the hardware and improving the execution success rate of the final circuit; after selecting a swap gate to be inserted according to a nearest neighbor heuristic function, it is judged whether the swap gate is repeated within a preset insertion number, if yes, the construction mode of the swap gate is temporarily changed, a two-bit gate is selected from the previous layer, a shortest path is found for the two-bit gate according to the current mapping in the topology constraint graph, the swap gate is constructed along the shortest path to make the selected two-bit gate satisfy the topology constraint, and the constructed swap gate is inserted into the optimization structure information; in this way, the occurrence of a large number of repeated swap gates in a short period of time can be avoided, and the depth of the final circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, in particular to the technical field of quantum circuit compilation, and more particularly to a quantum bit mapping method. BACKGROUND

[0002] Quantum computing adopts an information processing and computing method based on the principles of quantum mechanics, and its outstanding processing capability has attracted great interest in the scientific research and industrial communities. Quantum bits can be in a superposition of multiple states, which, as a core feature of quantum mechanics, gives quantum computers unique computing advantages. In specific applications, quantum computing has been proven to be superior to traditional computing in many fields, including but not limited to machine learning, encryption technology, solving linear equations, and simulation research of quantum chemistry. Considering the acceleration capability of quantum computers, in the past few decades, related technologies, algorithms, and devices have undergone extensive and in-depth exploration and development.

[0003] Quantum bit mapping refers to mapping a logical circuit onto a physical circuit: when designing a quantum algorithm circuit, algorithm designers often assume that all quantum bits can directly act on two-bit gates, but in actual quantum hardware, only specific physical bits can directly act on two-bit gates. Mapping represents the current location of logical bits in a logical circuit on a physical device, which is a one-to-one mapping from logical bits to physical bits.

[0004] In this case, in order to enable the logical circuit to be executed on the physical hardware, additional swap gates are generally introduced in the logical circuit to exchange the positions of the logical bits, so that the two-bit gates that need to be acted on satisfy the topological constraint graph.

[0005] Currently, the mainstream method for processing quantum bit mapping algorithms is to use a heuristic algorithm based on a nearest neighbor function. Among them, the SABRE algorithm (SWAP-based BidiREctional heuristic search algorithm, a bidirectional search heuristic algorithm based on swap gates, literature: ASPLOS'19, Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices) is currently the best quantum bit mapping heuristic algorithm in terms of performance and effect.

[0006] In the quantum bit mapping process, according to the execution dependency relationship of quantum gates, the algorithm divides the two-bit gates to be executed into the following three categories:

[0007] 1. Pre-layer two-bit gates, representing the set of all executable two-bit gates in the current state;

[0008] 2. The expansion layer two-bit gates, a constant set of two-bit gates that are closest to the previous layer two-bit gates in the breadth-first search topological order;

[0009] 3. Other irrelevant two-bit gates.

[0010] The function used by this algorithm to evaluate the current mapping is the sum of the weighted distances of the two-bit gates in the previous layer and the expansion layer. This distance refers to the distance between the two bits of the two-bit gate on the physical topology constraint graph; all gates in the previous layer have the same weight, and all gates in the expansion set have the same weight, but the weight of the gates in the expansion set is lower than the weight of the gates in the previous layer.

[0011] The reason for using distance as the heuristic function is that the distance between bits on the physical topology constraint graph determines how many switch gates need to be introduced to make them adjacent.

[0012] The reason why only the front layer and the expansion layer are considered and the weights of the gates in the expansion layer are lower than those of the gates in the front layer is that the two-bit gates on the quantum circuit must be executed in a certain order and have dependencies. The first gate to be executed is the gate in the front layer, and the subsequent gates can only be executed after the predecessor gates on which they depend are executed.

[0013] Because inserting a swap gate changes the current mapping, the algorithm can select the swap gate with the best score (lower scores indicate shorter distances, so lower scores are better) based on the resulting score changes. The algorithm continues to introduce swap gates when no executable two-bit gates exist until an executable two-bit gate emerges. After execution, the algorithm updates the previous and expanded layers, and repeats the above steps until the entire circuit executes successfully.

[0014] Indicatively, see Figure 1 , giving a simple example of quantum bit mapping:

[0015] 1) Figure 1 Figure a shows a quantum logic circuit, which includes 5 logical bits, q1 to q5, and 5 quantum gates, CNOT(q2,q1), CNOT(q5,q5), CNOT(q2,q3), CNOT(q1,q3), CNOT(q3,q4);

[0016] 2) Figure 1Figure b shows a quantum physics hardware topology constraint diagram, which includes 5 physical bits, namely Q1 to Q5. Two-bit gates can only be directly used between physical bits connected by edges in the topology constraint diagram. If it is assumed that the length of each edge is 1, the distance matrix D can be obtained, and the values ​​of the elements in it are: D[1][2]=1,D[1][3]=2,D[1][4]=2,D[1][5]=3,D[2][3]=1,D[2][4]=1,D[2][5]=2,D[3][4]=2,D[3][5]=3,D[4][5]=1;

[0017] 3) For simplicity, assume that the initial generated mapping is a one-to-one mapping, that is, π(q i )=Q i ;

[0018] 4) The quantum gates that can be initially attempted include CNOT(q2,q1) and CNOT(q4,q5). Since π(q2)=Q2 and π(q1)=Q1 are directly connected, the first gate can satisfy the topological constraint, and the second gate also satisfies the topological constraint.

[0019] 5) After executing these two gates, CNOT(q2,q3) can also be attempted. Similarly, if the topological constraints are met, it can be executed;

[0020] 6) CNOT(q1,q3) can also be tried, but π(q1)=Q1 and π(q3)=Q3 are not directly connected, so a swap gate can be inserted. Assume that the positions of q2 and q3 are swapped by inserting a swap gate.

[0021] 7) After inserting the exchange gate to update the current mapping, it is found that all subsequent gates can be executed, and then we get Figure 2 In the final circuit shown, the gates with an X across their ends are swap gates.

[0022] However, the prior art has the following defects:

[0023] Defect 1: Switch gates are selected based solely on the topological distance determined by the topological constraint graph, resulting in poor performance of the final circuit.

[0024] Defect 2: During the insertion of the switch gate, some repetitive insertion actions may be performed, which may result in a higher depth of the final circuit.

[0025] It should be noted that this background information is intended solely to introduce relevant information related to the present invention to facilitate understanding of the present invention's technical solution. It does not necessarily constitute prior art. Relevant information submitted and disclosed together with the present invention's solution should not be considered prior art unless there is evidence that the relevant information was disclosed prior to the filing date of the present invention. SUMMARY

[0026] Therefore, the purpose of the present application is to overcome the defects of the prior art, to provide a quantum bit mapping method.

[0027] The purpose of the present application is achieved by the following technical solutions:

[0028] According to the first aspect of the present application, a quantum bit mapping method is provided, comprising the steps of: S1: obtaining design structure information of a quantum logic circuit, a topology constraint graph of quantum hardware and error rate information, wherein the design structure information includes a plurality of logical bits and a quantum gate sequence constructed based on the logical bits, the topology constraint graph includes the connection relationship between the physical bits of the two-bit gate that can act on the quantum hardware, and the error rate information includes the error rate after introducing a two-bit gate between each pair of physical bits of the two-bit gate that can act; S2: generating a first matrix according to the topology constraint graph, which includes the topological distance between each two physical bits on the quantum hardware; S3: generating a second matrix according to the error rate information, which includes the estimated correct rate of circuit execution between each two physical bits; S4: fusing the first matrix and the second matrix to obtain a noisy distance matrix, and generating an initial mapping relationship between each logical bit and physical bit and initial optimization structure information without quantum gate; S5: selecting quantum gates from the design structure information according to execution timing and execution dependency to update the preset front layer and expansion layer, respectively judging whether each quantum gate of the front layer satisfies the topology constraint, if yes, the quantum gate satisfying the topology constraint is sequentially added to the optimization structure information and transferred to S9, otherwise, when only two-bit gates that do not satisfy the topology constraint are left in the quantum gates of the front layer, it is transferred to S6; S6: using a nearest neighbor heuristic function to determine a plurality of candidate swap gates according to the noisy distance matrix, the front layer and the expansion layer, and randomly selecting a swap gate to be inserted from them; S7: for the swap gate to be inserted, performing an insertion repeated swap gate checking strategy to judge whether the swap gate is repeated within a preset insertion number, if yes, it is transferred to S8, if not, the swap gate is sequentially inserted into the optimization structure information to update the current mapping and transferred to S9; S8: selecting a two-bit gate from the front layer, finding a shortest path for it in the topology constraint graph according to the current mapping, constructing a swap gate along the shortest path to make the selected two-bit gate satisfy the topology constraint, and inserting the constructed swap gate into the optimization structure information; S9: judging whether there is a quantum gate in the design structure information that has not been added to the optimization structure information, if yes, it is transferred to S5, otherwise, the initial mapping relationship and the final optimization structure information are obtained.

[0029] Optionally, the second matrix is generated by determining the correctness rate between each pair of physical bits of the two-qubit gate according to the error rate information, determining the path between each two physical bits according to the topology constraint graph, determining the estimated correctness rate of the circuit executed between each two physical bits according to the correctness rate between each pair of physical bits on the path between the two physical bits, and constructing the second matrix according to the number of physical bits, each element of the second matrix recording the estimated correctness rate of the circuit executed between the corresponding physical bits.

[0030] Optionally, the noisy distance matrix is obtained by:

[0031] D N = ω1D d + ω2D ESP

[0032] wherein, D N represents the noisy distance matrix, D d represents the first matrix, D ESP represents the second matrix, ω1 represents the weight of D d , ω2 represents the weight of D ESP , and ω1 and ω2 are positive real numbers.

[0033] Optionally, in step S5, the front layer is a set of quantum gates whose execution timing is the earliest in the sequence of quantum gates in the current state and whose optimization structure information has not been added, and the extended layer is a set of quantum gates closest to a preset number of quantum gates in the front layer in the breadth-first search topology sequence.

[0034] Optionally, step S6 includes:

[0035] S61: simulate setting a plurality of swap gates, and for each simulated swap gate, calculate the corresponding nearest neighbor function value by using the nearest neighbor heuristic function in the following manner:

[0036]

[0037] wherein, |F| represents the number of two-qubit gates in the front layer F, g represents a two-qubit gate in the front layer F, D N represents the noisy distance matrix, g.q0 represents one logical bit q0 in the two-qubit gate g, g.q1 represents another logical bit q1 in the two-qubit gate g, [π(g.q0)] represents the number of the physical bit corresponding to q0 obtained by the simulated mapping π changed by the simulated swap gate, [π(g.q1)] represents the number of the physical bit corresponding to q1 obtained by the simulated mapping π changed by the simulated swap gate, |E| represents the number of two-qubit gates in the extended layer E, and W represents a preset weight;

[0038] S62: selecting a preset number of swap gates from all the swap gates of the simulation settings in the order of the nearest neighbor function values from small to large, and determining the smallest nearest neighbor function value;

[0039] S63: determining the absolute value of the difference between the nearest neighbor function value corresponding to the preset number of swap gates and the smallest nearest neighbor function value, and reserving the swap gate with an absolute value less than 1;

[0040] S64: randomly selecting a swap gate to be inserted from the reserved swap gates.

[0041] Preferably, the preset number is 4.

[0042] Optionally, step S8 comprises: constructing a swap gate according to the shortest path to move the two endpoints of the selected two-bit gate to the center of the shortest path, and finally applying the selected two-bit gate at the intersection point.

[0043] According to a second aspect of the present application, a computer program product is provided, comprising computer programs / instructions which, when executed by a processor, implement the steps of the method of the first aspect.

[0044] According to a third aspect of the present application, an electronic device is provided, comprising: one or more processors; and a memory, wherein the memory is configured to store executable instructions; and the one or more processors are configured to implement the steps of the method of the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF DRAWINGS

[0045] The embodiments of the present application will be further described below with reference to the accompanying drawings, in which:

[0046] Figure 1 An exemplary quantum logic circuit and a schematic diagram of a topological constraint graph;

[0047] Figure 2 A schematic diagram of changing the current mapping after inserting a swap gate in a logic circuit;

[0048] Figure 3 A flowchart of a quantum bit mapping method according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose of the present application clearer, the technical solutions and advantages will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0050] As mentioned in the background technology section, the existing technology has the following defects: Defect 1: The switching gate is selected only based on the topological distance determined by the topological constraint graph, resulting in the performance of the final circuit to be improved; Defect 2: In the process of inserting the switching gate, some repetitive insertion actions may be performed, which may result in a higher depth of the final circuit.

[0051] The first drawback is primarily due to the fact that existing quantum-inspired algorithms lack hardware error rate information and offer no means of evaluating the circuit's final execution accuracy. This approach addresses this issue by constructing a noisy distance matrix, converting hardware error rates into "estimated accuracy" distances similar to physical topological distances. This approach then incorporates the estimated accuracy of the corresponding circuit execution into the topological distance between each two physical bits, thereby accounting for hardware error rate information and improving the final circuit execution success rate.

[0052] The second defect is mainly due to the fact that the existing quantum heuristic algorithm selects the exchange gate only from the perspective of the nearest neighbor function value. After the exchange gate is selected, it is directly inserted into the sequence. This method may repeatedly insert some identical exchange gates (with the same endpoints) in a short period of time, resulting in a higher depth of the final circuit. In response to this, the present invention selects the exchange gate to be inserted according to the nearest neighbor heuristic function, first determines whether the exchange gate is repeated within a preset number of insertions. If so, it temporarily changes the construction method of the exchange gate, selects a two-bit gate from the front layer, finds the shortest path for it in the topological constraint graph based on the current mapping, constructs an exchange gate along the shortest path so that the selected two-bit gate meets the topological constraints, and inserts the constructed exchange gate into the optimized structure information; in this way, it can focus on processing a two-bit gate in the front layer first, avoiding the occurrence of a large number of repeated exchange gates in the short term, thereby being able to update the front layer and expansion layer information in advance, thereby optimizing the heuristic algorithm and reducing the depth of the final circuit.

[0053] Before describing the embodiments of the present invention in detail, some of the terms used therein are explained as follows:

[0054] A logical bit, also called a logical qubit, is a quantum bit in a quantum logic circuit.

[0055] A physical bit, also called a physical quantum bit, is a quantum bit in quantum hardware (such as a quantum chip).

[0056] Quantum gates include single-qubit gates and two-qubit gates (two-qubit gates).

[0057] A single-qubit gate is a gate operation that acts on a single qubit and is used to change the state of a single qubit.

[0058] Two-qubit gates are quantum gates that operate on two qubits. They can implement quantum entanglement, quantum error correction, and complex quantum computing operations. Common two-qubit gates include the controlled-NOT gate (CNOT gate), the swap gate (SWAP gate), and the controlled-Z gate (CZ gate), among others.

[0059] According to one embodiment of the present application, referring to Figure 1 , a quantum bit mapping method is provided, comprising steps S1-S9. For a better understanding of the present application, each step will be described in detail below in conjunction with specific embodiments.

[0060] Step S1: Obtain the design structure information of the quantum logic circuit, the topology constraint graph of the quantum hardware, and the error rate information, wherein the design structure information includes a plurality of logical bits and a sequence of quantum gates constructed based on the logical bits, the topology constraint graph includes the connection relationship between the physical bits of the two-qubit gates that can be applied on the quantum hardware, and the error rate information includes the error rate of each pair of physical bits of the two-qubit gates after introducing a two-qubit gate.

[0061] According to one embodiment of the present application, the design structure information (or data structure information) of the quantum logic circuit is a combined storage format of the description of the logical quantum bits and the sequence of quantum gates (or the arrangement queue of quantum gates), wherein the quantum gates include single-qubit gates and two-qubit gates. The quantum logic circuit includes n logical bits and T quantum gates, and the quantum hardware includes N physical bits, wherein n, T, and N are all positive integers. The number of quantum bits and the number of quantum gates contained in the quantum logic circuit can be defined by the implementer, but the number of physical bits is required to be greater than or equal to the number of logical bits, i.e., N≥T.

[0062] According to one embodiment of the present application, the topology constraint graph of the quantum hardware includes a plurality of nodes and edges, each node represents a physical bit, and the edges are used to connect the nodes corresponding to the physical bits of the two-qubit gates that can be applied. Therefore, the topology constraint graph describes which quantum bits can have a two-qubit gate applied between them.

[0063] According to one embodiment of the present application, the error rate information describes the error rate of each pair of quantum bits of the two-qubit gates after introducing a two-qubit gate between them. This error rate information can be determined in advance by the manufacturer, researcher, or implementer of the quantum hardware through experiments.

[0064] Step S2: Generate a first matrix according to the topology constraint graph, which includes the topological distance between every two physical bits on the quantum hardware.

[0065] According to one embodiment of the present application, assuming that the distance between each two directly connected nodes in the topological constraint graph is d (for example, set as 1, of course, the implementer can also set other values), the shortest distance between each two physical bits is calculated as the topological distance using the all-source shortest path algorithm, which is expressed in the form of a matrix, constituting a first matrix, which can be represented by the letter D d . d [i][j] represents the topological distance between the physical bits Q i and Q j .

[0066] Step S3: generating a second matrix according to the error rate information, which includes the estimated correctness rate of the circuit executed between each two physical bits.

[0067] According to one embodiment of the present application, the manner of generating the second matrix includes: determining the correctness rate between each pair of physical bits on which the two-bit gate can act according to the error rate information; determining the path between each two physical bits according to the topological constraint graph; determining the estimated correctness rate of the circuit executed between each two physical bits according to the correctness rate between each pair of physical bits on the path between the two physical bits; and constructing the second matrix according to the number of physical bits, each element of which records the estimated correctness rate of the circuit executed between the corresponding physical bits. The second matrix can also be called the estimated correctness rate matrix, or the estimated success rate distance matrix, which is represented by the letter D ESP . EsP [i][j] represents the estimated correctness rate between the physical bits Q i and Q j .

[0068] Illustratively, the error rate of the two-bit gate refers to the probability of introducing an error after introducing a two-bit gate, and the estimated correctness rate (estimated success rate) is the result of multiplying the correctness rates of all two-bit gates on the circuit, which can be used to estimate the final correctness probability of the circuit.

[0069] Assuming that the two-bit gate acting on the physical bits Q i and Q j has an execution path wherein and the execution path represents the two-bit gates involved in making the logical bits on the physical bits adjacent by using the exchange gate and acting on the two-bit gate. Then the estimated correctness rate generated by this substructure is the multiplication of the correctness rates of these two-bit gates. Assuming that the letter E[Q a ][Q b ] represents the error rate of the two-bit gate acting on the adjacent quantum bits Q a and Q b , then the estimated correctness rate generated in this process is:

[0070]

[0071] But the formula is multiplication, and the estimation accuracy calculated by the formula is slightly poor in the fusion effect of the topological distance. Therefore, according to the property of logarithmic addition, the logarithm of both sides of the calculation formula can be taken and a negative sign is added, to obtain the estimation accuracy between two physical bits:

[0072]

[0073] wherein m represents the total number of physical bits contained in the path between any two physical bits Q i and Q j , represents the error rate introduced after the two-bit gate between the physical bits and ,

[0074] The formula has a similar form to the expression of the path distance. Then, in the case of a given topological constraint graph, the estimation accuracy can be defined.

[0075] For adjacent physical bits Q a and Q b that can directly perform a two-bit gate, m = 2, and the estimation accuracy is -log(1-E[Q a ][Q b ]); for non-adjacent physical bits, the estimation accuracy between any two points can also be calculated by the all-source shortest path algorithm; thus, the estimation accuracy matrix can be defined.

[0076] Step S4: fuse the first matrix and the second matrix to obtain a noisy distance matrix, and generate an initial mapping relationship between each logical bit and a physical bit and initial optimization structure information without a quantum gate.

[0077] According to an embodiment of the present application, the manner of obtaining the noisy distance matrix comprises:

[0078] D N = ω1D d + ω2D ESP

[0079] wherein D N represents the noisy distance matrix, D d represents the first matrix, D ESP represents the second matrix, ω1 represents the weight of D d , ω2 represents the weight of D ESP , and ω1 and ω2 are both positive real numbers. The distance simultaneously considers the size of the final circuit and the estimation success rate

[0080] According to another embodiment of the present application, the way to obtain the noisy distance matrix can also take other forms, for example, define a positive real number ω, let D N = D d + ωD ESP .

[0081] After obtaining the noisy distance matrix, a random initial mapping relationship is generated as the current mapping π. Of course, the implementer can also select one from one or more preset mapping relationships as the initial mapping relationship.

[0082] Step S5: Select quantum gate update preset front layer and expansion layer from the design structure information according to execution timing and execution dependency relationship, respectively judge whether each quantum gate of the front layer satisfies the topological constraint, if yes, add the quantum gate satisfying the topological constraint to the optimization structure information in sequence and go to S9, otherwise go to S6 when the quantum gate of the front layer is only left the two-bit gate not satisfying the topological constraint.

[0083] According to an embodiment of the present application, in step S5, the front layer is a set of quantum gates whose execution timing is the earliest in the quantum gate sequence in the current state and which have not been added to the optimization structure information, and the expansion layer is a set of quantum gates closest to the preset number of quantum gates in the front layer in the breadth-first search topological sequence. The definition of the front layer and the expansion layer can also refer to the existing quantum bit mapping algorithm, such as the SABRE algorithm. Since the quantum gate is divided into single quantum bit gate and two-bit gate, when judging whether each quantum gate of the front layer satisfies the topological constraint, for the single quantum bit gate, it is directly regarded as satisfying the topological constraint (because it only needs to act on one physical bit); for the two-bit gate, it needs to see whether the two logical bits corresponding to the two-bit gate under the current mapping correspond to adjacent physical bits (directly connected on the topological constraint graph), if yes, the two-bit gate satisfies the topological constraint, the two-bit gate is added to the optimization structure information and removed from the front layer; if not, the two-bit gate does not satisfy the topological constraint, the two-bit gate is retained in the front layer, and whether the next quantum gate satisfies the topological constraint is judged.

[0084] Step S6: Determine a plurality of candidate swap gates according to the noisy distance matrix, the front layer and the expansion layer by using the nearest neighbor heuristic function, and randomly select one to be inserted from them.

[0085] According to an embodiment of the present application, step S6 includes:

[0086] S61: Simulate a plurality of swap gates, for each simulated swap gate, calculate the corresponding nearest neighbor function value by using the nearest neighbor heuristic function in the following manner:

[0087]

[0088] wherein |F| represents the number of two-bit gates in the preceding layer F, g represents a two-bit gate in the preceding layer F, D N represents a noisy distance matrix, g.q0 represents one logical bit q0 in the two-bit gate g, g.q1 represents another logical bit q1 in the two-bit gate g, [π(g.q0)] represents the number of the physical bit corresponding to q0 obtained by the analog mapping π changed by the swap gate set by analogy, [π(g.q1)] represents the number of the physical bit corresponding to q1 obtained by the analog mapping π changed by the swap gate set by analogy, |E| represents the number of two-bit gates in the extended layer E, and W represents a preset weight;

[0089] S62: selecting N (N is greater than 2, for example, 3, 4 or 5, preferably 4) swap gates from all the swap gates set by analogy in the order of the nearest neighbor function value from small to large and determining the smallest nearest neighbor function value;

[0090] S63: respectively determining the absolute value of the difference between the nearest neighbor function value corresponding to each of the N swap gates and the smallest nearest neighbor function value, and retaining the swap gates with an absolute value less than 1;

[0091] S64: randomly selecting one swap gate to be inserted from the retained swap gates.

[0092] The technical scheme of the embodiment can at least achieve the following beneficial technical effects: the N swap gates are selected in the embodiment to ensure that the randomness of the mapping method is not destroyed and different routes can be explored in multiple runs, and only those swap gates close to the lowest function value are retained to improve the effectiveness of the screening process.

[0093] Of course, step S6 can also take other ways to select the swap gate to be inserted.

[0094] According to another embodiment of the application, step S6 comprises:

[0095] S61', which is the same as step S61 and will not be repeated here;

[0096] S62': selecting a preset number of swap gates (for example, M swap gates) from all the swap gates set by analogy in the order of the nearest neighbor function value from small to large;

[0097] S63': randomly selecting one swap gate to be inserted from the preset number of swap gates.

[0098] Step S7: performing an insertion repeated swap gate checking strategy on the swap gate to be inserted to determine whether the swap gate is repeated within a preset number of insertions, if yes, going to S8, and if no, inserting the swap gate into the optimization structure information in order to update the current mapping and going to S9.

[0099] The prior art does not check the inserted swap gates, which results in inserting some repeated swap gates in a short time, especially when the two endpoints of some two-bit gates are far apart, more repeated swap gates can be inserted, and the depth of the final circuit is high. Therefore, the present application considers improving the way of constructing swap gates when repeated swap gates are found.

[0100] According to one embodiment of the present application, the preset insertion number C is set to 4, 5, 6 or 7. During the process of continuously inserting swap gates, if the swap gates are repeated within the preset insertion number, i.e. the two endpoints of two swap gates are the same within the preset insertion number, go to S8. For example, if C is set to 5, the first three swap gates inserted do not have repeated cases, and the fourth swap gate to be inserted is the same as the first swap gate of the first three swap gates, go to S8.

[0101] Step S8: Select a two-bit gate from the previous layer, find a shortest path for it according to the current mapping in the topology constraint graph, construct a swap gate along the shortest path to make the selected two-bit gate meet the topology constraint, and insert the constructed swap gate into the optimization structure information.

[0102] According to one embodiment of the present application, step S8 includes: according to the shortest path, constructing a swap gate to make the two endpoints of the selected two-bit gate move to the center of the shortest path, and finally acting the selected two-bit gate at the intersection. In this step, the two-bit gate related to the sequence of the swap gates inserted before going to S8 can be found in the previous layer, a two-bit gate is selected from the related two-bit gates, then a shortest path of the selected two-bit gate on the topology constraint graph is found and executed, and in order to ensure that the final result has a small depth, the way of acting the swap gate is to move the bits from the two endpoints of the two-bit gate to the center of the path, and act the two-bit gate at the intersection.

[0103] Step S9: Determine whether there is a quantum gate in the design structure information that has not been added to the optimization structure information, if yes, go to S5, otherwise, obtain the initial mapping relationship and the final optimization structure information.

[0104] According to one embodiment of the present application, if there is a quantum gate that has not been added to the optimization structure information, step S5 needs to be repeated, otherwise, the initial mapping relationship and the final optimization structure information corresponding to the quantum logic circuit can be obtained. The final optimization structure information is still a sequence of quantum gates, which includes the quantum gates in the design structure information and the inserted swap gates.

[0105] In summary, compared with the prior art, the method of the embodiment of the present application has a significant improvement in improving the circuit depth of the final circuit and the estimation accuracy. The method of the embodiment of the present application detects the repeated swap gates in time by inserting the repeated swap gate checking strategy, timely switches the way of constructing the swap gate, and constructs the substructure with the minimum depth according to the shortest path, thereby significantly reducing the depth of the final circuit on various test circuits and quantum topology constraint graphs. Experiments on quantum Fourier transform circuits, quantum approximate optimization algorithm circuits and random circuits show that, compared with the most widely used SABRE algorithm at present, the algorithm combined with the strategy reduces the depth by up to 19%, 40% and 20% respectively. In terms of the success rate of quantum circuit execution, the method of the embodiment of the present application generates a noisy distance matrix by combining quantum hardware error rate information and a quantum topology constraint graph, and uses the noisy distance matrix for a quantum mapping heuristic algorithm, thereby improving the estimated success rate of the final circuit. Experiments on heavy hexagonal lattice and two-dimensional lattice topology constraint graphs show that, compared with the most advanced algorithm at present, the method of the embodiment of the present application improves the estimated success rate of the circuit by up to 9% and 12% respectively.

[0106] It should be noted that although the above describes the steps in a specific order, it does not mean that the steps must be performed in the above specific order. In fact, some of the steps can be performed concurrently or even in a changed order, as long as the desired function can be achieved.

[0107] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0108] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or punched tape, a magneto-optical or other optical device, a portable memory stick, a machine-readable readable storage device incorporating a suitable non-transitory computer-readable medium having instructions from this application for implementing the combined action, or any suitable combination of the foregoing. A non-transitory computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or punched tape, a magneto-optical or other optical device, a portable memory stick, a machine-readable readable storage device incorporating a suitable non-transitory computer-readable medium having instructions from this application for implementing the combined action, or any suitable combination of the foregoing.

[0109] Having described various embodiments of the application, it is to be understood that the above description is meant not to limit and not to encompass all of the possible embodiments covered by the claims. Many modifications and variations of this application can be apparent to those of ordinary skill in the art without departing from the spirit and scope of the described embodiments. It is intended that the scope of the application should only be limited by the appended claims.

Claims

1. A quantum bit mapping method, characterized in that: Including steps: S1: Obtaining the design structure information of the quantum logic circuit, the topological constraint graph of the quantum hardware, and error rate information. The design structure information includes multiple logical bits and a sequence of quantum gates constructed based on the logical bits. The topological constraint graph includes the connection relationship between the physical bits on the quantum hardware that can act as a two-bit gate. The error rate information includes the error rate after introducing a two-bit gate between each pair of physical bits that can act as a two-bit gate. S2: Generate a first matrix according to the topological constraint graph, which includes the topological distance between every two physical bits on the quantum hardware; S3: generating a second matrix according to the error rate information, wherein the second matrix includes the estimated correct rate of the circuit executed between each two physical bits; S4: Fusing the first matrix and the second matrix to obtain a noisy distance matrix, and generating the initial mapping relationship between each logical bit and the physical bit and the initial optimized structure information without quantum gates; S5: Select quantum gates from the design structure information according to the execution sequence and execution dependency to update the preset front layer and expansion layer, and judge whether each quantum gate in the front layer meets the topological constraint. If so, add the quantum gates that meet the topological constraint to the optimized structure information in order and go to S9. Otherwise, if the quantum gates in the front layer only have two-bit gates that do not meet the topological constraint, go to S6. S6: using the nearest neighbor heuristic function to determine multiple candidate swap gates according to the noisy distance matrix, the previous layer, and the expansion layer, and randomly selecting a swap gate to be inserted; S7: For the swap gate to be inserted, execute the insertion duplicate swap gate check strategy to determine whether the swap gate is repeated within the preset insertion times. If so, go to S8; if not, insert the swap gate into the optimized structure information in order to update the current mapping and go to S9; S8: Select a two-bit gate from the previous layer, find the shortest path for it in the topology constraint graph according to the current mapping, construct a switch gate along the shortest path so that the selected two-bit gate meets the topology constraint, and insert the constructed switch gate into the optimized structure information; S9: Determine whether there is a quantum gate in the design structure information that has not been added with the optimized structure information. If so, go to S5; otherwise, obtain the initial mapping relationship and the final optimized structure information.

2. The method according to claim 1, characterized in that Ways to generate the second matrix include: Determine the accuracy rate between each pair of physical bits that can act on the two-bit gate based on the error rate information; Determine the path between every two physical bits according to the topology constraint graph; Determine an estimated accuracy rate of circuit execution between each two physical bits according to an accuracy rate between each pair of physical bits on a path between each two physical bits; According to the number of physical bits, a second matrix is ​​constructed, each element of which records the estimated accuracy of the circuit execution between the corresponding physical bits.

3. The method according to claim 2, characterized in that Ways to obtain a noisy distance matrix include: D N =ω1D d +ω2D ESP Among them, D N represents the noisy distance matrix, D d Denotes the first matrix, D ESP represents the second matrix, ω1 represents D d The weight of D ESP The weights of , ω1 and ω2 are both positive real numbers.

4. The method according to claim 1, wherein In step S5, the front layer is a set of quantum gates that are at the front of the quantum gate sequence in the current state and have not been added with optimized structure information, and the expansion layer is a set of quantum gates that are closest to the preset number of quantum gates in the front layer in the breadth-first search topological order.

5. The method according to claim 1, wherein Step S6 includes: S61: Simulate and set multiple exchange gates. For each exchange gate set in the simulation, use the nearest neighbor heuristic function to calculate the corresponding nearest neighbor function value in the following manner: Where |F| represents the number of two-bit gates in the previous layer F, g represents the two-bit gates in the previous layer F, and D N represents the noisy distance matrix, g.q0 represents a logical bit q0 in the two-bit gate g, g.q1 represents another logical bit q1 in the two-bit gate g, [π(g.q0)] represents the number of the physical bit corresponding to q0 obtained by the analog mapping π after the switching gate in the simulation setting is changed, [π(g.q1)] represents the number of the physical bit corresponding to q1 obtained by the analog mapping π after the switching gate in the simulation setting is changed, |E| represents the number of two-bit gates in the extension layer E, and W represents the preset weight; S62: selecting a preset number of exchange gates from all exchange gates set in simulation in ascending order of nearest neighbor function values ​​and determining the minimum nearest neighbor function value; S63: Determine the absolute value of the difference between the nearest neighbor function value corresponding to a preset number of exchange gates and the minimum nearest neighbor function value, and retain the exchange gates whose absolute value is less than 1; S64: Randomly select a switch gate to be inserted from the reserved switch gates.

6. The method according to claim 5, characterized in that The preset number is 4.

7. The method according to any one of claims 1 to 6, characterized in that Step S8 includes: constructing a switching gate according to the shortest path to move the two endpoints of the selected two-bit gate toward the center of the shortest path, and finally acting on the selected two-bit gate at the intersection.

8. A computer program product comprising a computer program / instruction, which implements the steps of the method according to any one of claims 1 to 7 when executed by a processor.

9. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as a memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1 to 7 by executing the executable instructions.

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