Data reading circuit, data reading method, chip, graphics card and electronic device

Abstract

The disclosed embodiment discloses a data reading circuit, a data reading method, a chip, a graphics card and an electronic device, wherein the circuit includes a request sending module, a memory and a data collector, wherein the memory includes a plurality of storage queues, the data collector includes a plurality of first buffers, a plurality of selectors corresponding to the plurality of first buffers one by one, and a plurality of second buffers, wherein each selector corresponds to a group of second buffers; the request sending module is used to send the read request information of each data to be read in the instruction information of the data reading instruction to the corresponding storage queue respectively; the storage queue is used to read the data according to the received read request information, and transmit the read target data to the corresponding first buffer; the selector is used to select a target data from the plurality of first buffers and store it in the target buffer in the corresponding group of second buffers within a single clock cycle. In this way, the circuit wiring congestion problem can be improved and the circuit area consumption can be reduced.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of electronic technology, and in particular to a data reading circuit, a data reading method, a chip, a graphics card and an electronic device. Background Art

[0002] In the related art, the data reading circuit of the chip is usually designed with more devices, which leads to the problem of congestion in the back-end logic integrated wiring and also causes the phenomenon of waste of circuit area. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure at least provide a data reading circuit, a data reading method, a chip, a graphics card, and an electronic device.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] The present disclosure provides a data reading circuit, including:

[0006] A request sending module, a memory and a data collector, wherein the memory includes a plurality of storage queues, the data collector includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond one-to-one to the plurality of storage queues, and each of the selectors corresponds to a group of the second buffers; wherein,

[0007] The request sending module is used to: obtain instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the first read request information set includes read request information of a plurality of data to be read; and send the read request information of each of the data to be read to a corresponding storage queue respectively;

[0008] The storage queue is used to read data according to the received read request information, and transmit the read target data to the corresponding first buffer;

[0009] The selector is used to: select a target data from multiple first buffers within a single clock cycle, and store the target data in a target buffer in a corresponding group of second buffers, and the target buffer corresponds to the read request information of the target data.

[0010] The embodiment of the present disclosure provides a data reading method, which is applied to a data reading circuit. The data reading circuit includes a request sending module, a memory and a data collector. The memory includes a plurality of storage queues. The data collector includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers. The plurality of first buffers correspond to the plurality of storage queues one by one, and each of the selectors corresponds to a group of the second buffers. The method includes:

[0011] The request sending module obtains instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the first read request information set includes read request information of a plurality of data to be read;

[0012] The request sending module sends the read request information of each of the to-be-read data to the corresponding storage queue respectively;

[0013] The storage queue reads data according to the received read request information, and transmits the read target data to the corresponding first buffer;

[0014] The selector selects a target data from the plurality of the first buffers within a single clock cycle, and stores the target data in a target buffer in a corresponding group of second buffers, wherein the target buffer corresponds to the read request information of the target data.

[0015] An embodiment of the present disclosure provides a chip, wherein the chip includes the data reading circuit in the above embodiment.

[0016] An embodiment of the present disclosure provides a graphics card, which includes the chip in the above embodiment.

[0017] An embodiment of the present disclosure provides an electronic device, which includes the chip in the above embodiment.

[0018] In the disclosed embodiment, the data reading circuit includes a request sending module, a memory and a data collector, the memory includes a plurality of storage queues, the data collector includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond to the plurality of storage queues one by one, and each selector corresponds to a group of second buffers; the request sending module is used to obtain the instruction information of the data reading instruction, and send the read request information of each data to be read in the instruction information to the corresponding storage queue respectively; the storage queue is used to read the data according to the received read request information, and transmit the read target data to the corresponding first buffer; the selector is used to select a target data from the plurality of first buffers in a single clock cycle and store it in a target buffer in a corresponding group of second buffers, and the target buffer corresponds to the read request information of the target data. In this way, since each selector can correspond to a group of second buffers, and selects the target data from the plurality of first buffers in a single clock cycle and stores it in the target buffer in the group of second buffers, compared with the solution in the related art that each selector corresponds to a second buffer respectively, the number of selectors can be reduced, thereby improving the problem of data collector wiring congestion, and reducing the circuit area consumption of the data reading circuit.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0021] Figure 1 A schematic diagram of a data reading circuit provided in an embodiment of the present disclosure Figure 1 ;

[0022] Figure 2 A schematic diagram of an implementation flow of a data reading method provided in an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of a data reading circuit provided in an embodiment of the present disclosure Figure 2 ;

[0024] Figure 4 A schematic diagram of a data reading circuit provided in an embodiment of the present disclosure Figure 3 ;

[0025] Figure 5 A schematic diagram of a data reading circuit provided in an embodiment of the present disclosure Figure 4 ;

[0026] Fig. 6A A schematic diagram of the overall structure of an operand reading circuit of a related technology provided by an embodiment of the present disclosure;

[0027] Figure 6B A schematic diagram of an implementation flow of an operand reading method of a related technology provided by an embodiment of the present disclosure;

[0028] Figure 6C A schematic diagram of an implementation flow of an operand reading method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0030] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the present disclosure and are not intended to limit the present disclosure.

[0033] The present disclosure provides a data reading circuit. Figure 1 A schematic diagram of a data reading circuit provided in an embodiment of the present disclosure Figure 1 .like Figure 1 As shown, the data reading circuit includes: a request sending module 1, a memory 2 and a data collector 3, the memory 2 includes a plurality of storage queues, the data collector 3 includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond one-to-one to the plurality of storage queues, and each selector corresponds to a group of second buffers; wherein:

[0034] The request sending module 1 is used to: obtain instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the read request information set includes read request information of a plurality of data to be read; and send the read request information of each data to be read to a corresponding storage queue respectively;

[0035] A storage queue, used for reading data according to the received read request information, and transmitting the read target data to the corresponding first buffer;

[0036] The selector is used to: select a target data from multiple first buffers in a single clock cycle, and store the target data in a target buffer in a corresponding group of second buffers, where the target buffer corresponds to the read request information of the target data.

[0037] Here, the number of storage queues in the memory 2, the number of first buffers in the data collector 3, the number of selectors, and the number of second buffers can be set according to actual conditions, and the embodiment of the present disclosure does not limit this. Figure 1, the memory 2 includes N storage queues, such as storage queue 21, storage queue 22, ..., storage queue 2N, where N is an integer greater than 1. The data collector 3 includes N first buffers, P selectors, and P groups of second buffers, where P is a positive integer less than N. The first buffer 311, the first buffer 312, ..., the first buffer 31N correspond one-to-one to the storage queue 21, the storage queue 22, ..., the storage queue 2N. Each selector corresponds to a group of second buffers, for example, the selector 321 corresponds to the second buffer 3211, ..., the second buffer 321Q, the selector 322 corresponds to the second buffer 3221, ..., the second buffer 322Q, and the selector 32P corresponds to the second buffer 32P1, ..., the second buffer 32PQ.

[0038] The instruction information of the data read instruction may include multiple read request information, each of which is used to read a piece of data to be read. It is understandable that, according to the read request information of the data to be read, the storage queue corresponding to the data to be read can be determined, that is, the storage queue storing the data to be read. For example, the read request information may include the read address of the data to be read in the memory, and according to the read address, the storage queue corresponding to the data to be read can be determined.

[0039] In some embodiments, the number of first buffers in the data collector 3 is related to the instruction information of the data read instruction obtained in the request sending module 1; the number of storage queues corresponding to the plurality of data to be read can be determined through the instruction information of the data read instruction, that is, the number of first buffers can be determined. For example, if the number of storage queues corresponding to the plurality of data to be read is 3, the number of first buffers is also 3.

[0040] In some embodiments, the number of selectors may be less than the number of data to be read corresponding to the instruction information of the data read instruction. For example, the number of selectors may be half of the number of data to be read corresponding to the instruction information of the data read instruction, and the number of second buffers may be equal to the number of data to be read corresponding to the instruction information of the data read instruction; wherein each data to be read may correspond to one second buffer, and every two data to be read may correspond to one selector.

[0041] In some embodiments, the request sending module can receive instruction information of a data read instruction, and obtain multiple second read request information sets in the instruction information, arbitrate the multiple second read request information sets respectively, and store each read request information in the multiple second read request information sets into a storage queue in sequence according to the arbitration results.

[0042] The selector may determine a first buffer storing the target data and a corresponding target buffer according to read request information of the target data to be read in the current clock cycle, and after reading the target data from the first buffer, store the target data in the target buffer.

[0043] In the above embodiment, the data reading circuit includes a request sending module, a memory and a data collector, the memory includes a plurality of storage queues, the data collector includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond to the plurality of storage queues one by one, and each selector corresponds to a group of second buffers; the request sending module is used to obtain the instruction information of the data reading instruction, and send the read request information of each data to be read in the instruction information to the corresponding storage queue respectively; the storage queue is used to read the data according to the received read request information, and transmit the read target data to the corresponding first buffer; the selector is used to select a target data from the plurality of first buffers in a single clock cycle and store it in a target buffer in a corresponding group of second buffers, and the target buffer corresponds to the read request information of the target data. In this way, since each selector can correspond to a group of second buffers, and selects the target data from the plurality of first buffers in a single clock cycle and stores it in the target buffer in the group of second buffers, compared with the solution in the related art that each selector corresponds to a second buffer respectively, the number of selectors can be reduced, thereby improving the problem of data collector wiring congestion, and reducing the circuit area consumption of the data reading circuit.

[0044] The embodiments of the present disclosure provide a data reading method, which can be applied to the above-mentioned data reading circuit. Figure 2 A schematic diagram of an implementation flow of a data reading method provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the method may include the following steps S101 to S103:

[0045] Step S101: a request sending module obtains instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the first read request information set includes read request information of a plurality of data to be read.

[0046] Here, the data read instruction may be a command for controlling computer hardware to perform a data read operation, and the read request information may be information indicating a storage location of data.

[0047] In some implementations, when data is stored in a storage unit in a storage queue, the data read request information may include a storage queue number and storage unit information.

[0048] In some implementations, the request sending module may receive instruction information of a data read instruction sent by the instruction information cache module.

[0049] Step S102: The request sending module sends the read request information of each of the to-be-read data to the corresponding storage queue.

[0050] In some implementations, each data to be read is stored in a storage queue, and the request sending module, in the process of sending the read request information of the data to be read, sends the read request information of the data to be read to the storage queue storing the data to be read.

[0051] By way of example, the multiple data to be read include data S0 to be read, data S1 to be read, data S2 to be read and data S3 to be read, respectively, wherein data S0 to be read and data S3 to be read are stored in storage queue B0, data S1 to be read is stored in storage queue B1, and data S2 to be read is stored in storage queue B2. In the process of sending read request information of each data to be read, the request sending module needs to send the read request information of data S0 to be read to storage queue B0, send the read request information of data S3 to be read to storage queue B0, send the read request information of data S1 to be read to storage queue B1, and send the read request information of data S2 to be read to storage queue B2.

[0052] In some implementations, the corresponding storage queue may be determined by the storage queue number in the read request information in the data to be read.

[0053] Step S103: the storage queue reads data according to the received read request information, and transmits the read target data to the corresponding first buffer.

[0054] Here, the storage queue can store the data to be read, and after receiving the read request information of the data to be read, the data to be read is taken out from the storage queue and sent to the data collector. The first buffer can be a buffer for storing the data to be read located in the same storage queue. The target data can be determined from a plurality of data to be read.

[0055] In some implementations, the storage queue storing the data to be read and the storage unit storing the data to be read in the storage queue can be determined by the storage location information in the read request information, and the target data can be read from the storage unit. It is understandable that the target data to be read is the data to be read.

[0056] In some embodiments, the number of first buffers is consistent with the number of storage queues, each storage queue has its corresponding first buffer, and during the process of transmitting target data, the storage queue sends the target data to the first buffer corresponding to the storage queue where the target data is located.

[0057] Step S104: The selector selects a target data from the plurality of first buffers within a single clock cycle, and stores the target data in a target buffer in a corresponding group of second buffers, wherein the target buffer corresponds to the read request information of the target data.

[0058] Here, the selector can send the data stored in the first buffer to the second buffer according to the read request information. The clock cycle is the minimum time unit for the processor to perform an action. In each clock cycle, the processor only completes a most basic action. The second buffer can be a buffer in any suitable memory for storing the read data to be read (i.e., target data). The target buffer can be determined from a group of second buffers.

[0059] In some embodiments, the number of second buffers is consistent with the number of data to be read, and each data to be read has its corresponding second buffer. During the target data transmission process, the selector sends the target data determined in the first buffer to the second buffer corresponding to the target data.

[0060] In some embodiments, when storing data in a storage queue, when the bit width of the data is greater than the storage bit width of a storage unit of the storage queue, the data needs to be split according to the storage bit width, and then the split sub-data is stored in the storage queue. In this case, when reading the data, the multiple sub-data obtained after the data is split can be used as a to-be-read data, and the second buffers corresponding to the multiple sub-data of the same data can be determined as a group of second buffers.

[0061] In some embodiments, in the process of storing data in the storage queue, when the bit width of the data is less than or equal to the storage bit width of the storage unit of the storage queue, the data can be directly stored in the storage queue. In this case, the second buffer corresponding to the data is determined as a group of second buffers. The data can correspond to the data to be read in the above embodiment.

[0062] In the disclosed embodiment, the read request information of each data to be read is sent to the corresponding storage queue through the request sending module, and then the storage queue transmits the target data to the first buffer according to the obtained read request information, and finally the selector selects a target data from the first buffer in a single clock cycle, and sends it to the target buffer in the corresponding group of second buffers, thereby completing the reading of the target data. In this way, since each selector can correspond to a group of second buffers, and selects target data from multiple first buffers in a single clock cycle and stores it in the target buffer in the group of second buffers, compared with the solution in the related art that each selector corresponds to a second buffer, the number of selectors can be reduced, thereby improving the problem of data collector wiring congestion and reducing the circuit area consumption of the data reading circuit.

[0063] In some embodiments, Figure 3 As shown, the request sending module 1 includes an instruction processing module 11, multiple arbitrators (for example, arbitrator 121, arbitrator 122..., arbitrator 12N) and multiple third buffers (for example, third buffer 131, third buffer 132,... third buffer 13N), the multiple arbitrators correspond one-to-one to the multiple third buffers, and the multiple third buffers correspond one-to-one to the multiple storage queues.

[0064] The above step S102 may include steps S111 to S114:

[0065] Step S111: the instruction processing module determines a second read request information set corresponding to each storage queue based on the read request information of each data to be read; the data to be read corresponding to each read request information in the second read request information set is stored in the storage queue corresponding to the second read request information set;

[0066] Here, the instruction processing module may be a module that classifies instruction information of data read instructions according to storage queues. The first read request information set of multiple data to be read obtained by the instruction processing module may include read request information of data to be read stored in different storage queues.

[0067] In some implementations, the read request information of all to-be-read data with the same storage queue number may be determined as a second read request information set according to the storage queue number in the read request information.

[0068] Step S112: The instruction processing module transmits the second read request information set corresponding to each storage queue to the corresponding arbitrator.

[0069] Here, the arbitrator is used to determine the order of read requests for the plurality of data to be read, that is, the order of sending the plurality of read request information for the plurality of data to be read.

[0070] In some embodiments, the number of arbitrators is consistent with the number of storage queues, and each storage queue has its corresponding arbitrator. During the process of transmitting read request information of the data to be read, the instruction processing module shall send the read request information of the data to be read to the arbitrator corresponding to the storage queue where the data to be read is located.

[0071] Step S113: The arbitrator arbitrates the second read request information set, and sends the read request information in the second read request information set to the corresponding third buffer according to the arbitration result.

[0072] Here, the arbitration result refers to the read request order of multiple data to be read in the same arbitrator. The third buffer may be a buffer for storing read request information of the data to be read in the same storage queue. The target data may be determined from the multiple data to be read.

[0073] In some embodiments, the number of third buffers is consistent with the number of arbitrators, and each arbitrator has its corresponding third buffer. When the arbitrator transmits read request information of the data to be read, the arbitrator must send the read request information of the data to be read to the third buffer corresponding to the arbitrator where the data to be read is located.

[0074] In some implementations, when the read request information in the arbitrator is single, the read request information of the data to be read may be directly sent to the corresponding third buffer.

[0075] In some embodiments, when there are multiple read request information in the arbitrator, the multiple read request information must first be arbitrated and sorted according to the arbitration rules pre-built into the arbitrator, and the result of the arbitration and sorting of the multiple read request information is determined as the arbitration result, and then the read request information is sent to the third cache in sequence according to the arbitration result.

[0076] Step S114: The third buffer sends the read request information of each of the to-be-read data to the corresponding storage queue.

[0077] In some embodiments, the number of third buffers is consistent with the number of storage queues, and each third buffer has its corresponding storage queue. When the third buffer is transmitting read request information of the data to be read, the read request information of the data to be read must be sent to the storage queue corresponding to the third buffer where the data to be read is located.

[0078] In the disclosed embodiment, the first read request information set is classified and processed by the instruction processing module, and then the read request information of the data to be read of the same storage queue is arbitrated by the arbitrator, and then the read request information of the data to be read is sent to the third buffer according to the arbitration result, and finally sent to the corresponding storage queue. In this way, the storage queue can send the data to be read to the first buffer according to the arbitration result.

[0079] In some embodiments, the above step S113 may include steps S121 to S123:

[0080] Step S121 : The arbitrator determines a target arbitration rule from among a plurality of arbitration rules; wherein the target arbitration rule is used to ensure that the number of clock cycles used by each selector to read the plurality of data to be read does not exceed a target number.

[0081] Here, the multiple arbitration rules refer to rules for determining the order of read requests for the to-be-read data in the arbitrator, wherein the multiple arbitration rules refer to more than one arbitration rule, for example, two arbitration rules, three arbitration rules, four arbitration rules, etc. The target arbitration rule may be determined from the multiple arbitration rules in the arbitrator. The target number may be determined according to the performance requirements of the data reading circuit, and the number of clock cycles used by the selector to read all the to-be-read data from the first buffer to the second buffer does not exceed the target number.

[0082] In some implementations, the number of clock cycles corresponding to each arbitration rule in the arbitrator may be determined respectively, and the arbitration rule corresponding to the number of clock cycles less than the target number may be determined. The number of clock cycles corresponding to the arbitration rule refers to the number of clock cycles used by the selector to read all the data to be read based on the arbitration rule. The number of arbitration rules corresponding to the number of clock cycles less than the target number may be single or multiple.

[0083] In some implementations, when the number of arbitration rules corresponding to the number of clock cycles less than the target number is only one, the corresponding arbitration rule may be directly determined as the target arbitration rule.

[0084] In some embodiments, when there are multiple arbitration rules corresponding to the number of clock cycles less than the target number, the arbitration rule corresponding to the minimum value of the number of clock cycles less than the target number can be determined as the target arbitration rule, or the arbitration rule corresponding to the maximum value of the number of clock cycles less than the target number can be determined as the target arbitration rule.

[0085] In some embodiments, first, the arbitrator arbitrates multiple read request information corresponding to multiple data to be read stored in the same storage queue, and obtains the arbitration result of the multiple data to be read in the storage queue, that is, the read request order of the multiple data to be read; then, the arbitrator sends the multiple read request information corresponding to the multiple data to be read to the third buffer corresponding to the arbitrator according to the read request order, and the third buffer sends the received multiple read request information to the corresponding storage queue, and the storage queue reads data according to the received read request information, and transfers the read target data to the first buffer; finally, the selector selects one target data from the first buffer in a single clock cycle. However, since the selector can only select one target data in one clock cycle, if there are multiple data to be read in the first buffer, the selector needs at least the same number of clock cycles as the data to be read in the first buffer to complete the reading of the data in the first buffer. For example, when there are 5 data to be read in the first buffer, the selector can complete the data reading within 5 clock cycles, or can complete the data reading within 6 clock cycles, or can complete the data reading within 7 clock cycles, wherein the number of clock cycles required for the selector to read the data is related to the arbitration result determined by the arbitrator, and the arbitration result corresponds to the arbitration rule, that is, by determining the target arbitration rule from multiple arbitration rules in the arbitrator, the number of clock cycles required for the selector to complete data reading can be less than or equal to the target number.

[0086] Step S122: The arbitrator determines the arbitration result of the plurality of to-be-read data corresponding to the second read request information set according to the arbitration order corresponding to the target arbitration rule based on the received second read request information set.

[0087] Here, the arbitration order refers to a rule for determining the order of read requests for multiple data to be read.

[0088] For example, if the data to be read include S0_L, S0_H, S1_L, S1_H, S2_L and S2_H, the arbitration order is S0_L>S0_H>S1_L>S1_H>S2_L>S2_H, and when the data to be read input into a certain arbitrator includes S0_L and S0_H, the arbitration result is determined to be: S0_H->S2_H, that is, the read request information of the data to be read S0_H is first sent to the corresponding third buffer, and then the read request information of the data to be read S2_H is sent to the corresponding third buffer, so that the third buffer can first send the read request information of the data to be read S0_H to the corresponding storage queue, and then send the read request information of the data to be read S2_H to the corresponding storage queue.

[0089] Step S123: The arbitrator sends the plurality of to-be-read data to the corresponding third buffer in sequence based on the arbitration result.

[0090] In some implementations, after the arbitrator determines arbitration results of a plurality of data to be read, the arbitrator may send read request information of corresponding data to be read to the third buffer according to the arbitration results.

[0091] For example, if the arbitration result of the plurality of to-be-read data in the arbitrator is S0_H->S2_H, the arbitrator first sends the read request information corresponding to S0_H to the third buffer, and then sends the read request information corresponding to S2_H to the third buffer.

[0092] In the disclosed embodiment, a target arbitration rule is determined from among multiple arbitration rules, thereby determining a read request order for multiple data to be read based on the target arbitration rule. By determining the read request order for multiple data to be read, the utilization rate of the selector in the data collector can be improved.

[0093] In some embodiments, the above method may further include the following steps S131 and S132:

[0094] Step S131: The instruction processing module determines the maximum value of the quantity of the to-be-read data respectively stored in a plurality of storage queues.

[0095] In some embodiments, the number of read request information with the same storage queue number can be determined based on the storage queue number in the read request information. Different storage queue numbers correspond to different storage queues, thereby obtaining the number of data to be read in each storage queue, and finally calculating the maximum value of the number of data to be read in all storage queues.

[0096] Step S132: The instruction processing module transmits the maximum number value to each of the arbitrators.

[0097] The above step S121 may include step S133:

[0098] Step S133: The arbitrator determines a target arbitration rule from among multiple arbitration rules based on the maximum number value.

[0099] Here, each arbitration rule in the arbitrator corresponds to a different quantity value of data to be read. For example, the arbitrator includes a first arbitration rule and a second arbitration rule, which correspond to: S0_L>S1_L>S1_H>S2_L>S2_H>S0_H, S0_L>S1_L>S2_L>S2_H>S1_H>S0_H, wherein the quantity value of data to be read corresponding to the first arbitration rule is 3, and the quantity value of data to be read corresponding to the second arbitration rule is 2. Therefore, when the maximum quantity value is 2, the second arbitration rule is determined as the target arbitration rule, and when the maximum quantity value is 3, the first arbitration rule is determined as the target arbitration rule.

[0100] In the embodiment of the present disclosure, the target arbitration rule is determined according to the maximum value of the quantity of the to-be-read data respectively stored in the multiple storage queues. The target arbitration rule determined by this method can improve the utilization rate of the selector in the data collector.

[0101] In some embodiments, the data read instruction is a read instruction of an operand of a computing unit, the operand includes at least two sub-operands, and the instruction information of the read instruction includes read request information of each of the sub-operands;

[0102] The number of the selectors is the same as the number of the operands, and each group of the second buffers includes at least two second buffers corresponding to at least two sub-operands of the same operand.

[0103] Here, the number of operands of the operation unit can be determined according to the operation task of the operation unit, and the embodiment of the present disclosure is not limited to this.

[0104] In some embodiments, the number of operands of the operation unit may be 3, and the sub-operands of each operand may be 2. For example, the operands may be S0, S1, and S2, and the operand S0 may be split into sub-operands S0_L and S0_H, the operand S1 may be split into sub-operands S1_L and S1_H, and the operand S2 may be split into sub-operands S2_L and S2_H.

[0105] For example, the arithmetic operation unit requires three operands with a bit width of 64 bits, which are S0, S1 and S2, and all of these operands are stored in the memory. There are four storage queues in the memory, namely storage queue B0, storage queue B1, storage queue B2 and storage queue B3. There are many storage units in each storage queue, but each storage unit can only store data with a bit width of 32 bits. Therefore, a 64-bit operand requires two storage units to store. In order to read a complete 64-bit operand from the memory at one time, taking S0 as an example, the computer will split S0 into two sub-data with a bit width of 32 bits in advance, respectively recorded as S0_L and S0_H. By analogy, S1 can be split into S1_L and S1_H, and S2 can be split into S2_L and S2_H.

[0106] In some embodiments, the operands include a first operand, a second operand, and a third operand, each of the operands includes a first sub-operand and a second sub-operand, and the maximum number value is 3;

[0107] The arbitration order corresponding to the target arbitration rule is: the sending priority of the read request information corresponding to the first sub-operand of the first operand, the first sub-operand of the second operand, the second sub-operand of the second operand, the first sub-operand of the third operand, the second sub-operand of the third operand and the second sub-operand of the first operand respectively decreases in sequence.

[0108] In some embodiments, the number of operands may be 3, and the number of sub-operands of each operand may be 2. For example, the operands may be S0 (first operand), S1 (second operand), and S2 (third operand), then the sub-operands of S0 may be S0_L (first sub-operand of the first operand) and S0_H (second sub-operand of the first operand), the sub-operands of S1 may be S1_L (first sub-operand of the second operand) and S1_H (second sub-operand of the second operand), and the sub-operands of S2 may be S2_L (first sub-operand of the third operand) and S2_H (third sub-operand of the second operand), then when the maximum number value is 3, the arbitration order corresponding to the target arbitration rule may be S0_L>S1_L>S1_H>S2_L>S2_H>S0_H.

[0109] In some embodiments, the operands include a first operand, a second operand, and a third operand, each of the operands includes a first sub-operand and a second sub-operand, and the maximum number value is 2;

[0110] The arbitration order corresponding to the target arbitration rule is: the sending priority of the read request information corresponding to the first sub-operand of the first operand, the first sub-operand of the second operand, the first sub-operand of the third operand, the second sub-operand of the third operand, the second sub-operand of the second operand and the second sub-operand of the first operand respectively decreases in sequence.

[0111] In some embodiments, the number of operands may be 3, and the number of sub-operands of each operand may be 2. For example, the operands may be S0 (first operand), S1 (second operand), and S2 (third operand), then the sub-operands of S0 may be S0_L (first sub-operand of the first operand) and S0_H (second sub-operand of the first operand), the sub-operands of S1 may be S1_L (first sub-operand of the second operand) and S1_H (second sub-operand of the second operand), and the sub-operands of S2 may be S2_L (first sub-operand of the third operand) and S2_H (third sub-operand of the second operand), then when the maximum number value is 2, the arbitration order corresponding to the target arbitration rule may be S0_L>S1_L>S2_L>S2_H>S1_H>S0_H.

[0112] In some embodiments, Figure 4 As shown, the data collector 3 also includes a fourth buffer 34; the above step S104 may include steps S115 to S118:

[0113] Step S115, the arbitrator sends the arbitration result to the fourth buffer.

[0114] Here, the fourth buffer may be a buffer for storing the arbitration results of the arbitrators, and the number of the fourth buffer may be one, for storing the arbitration results of all the arbitrators.

[0115] Step S116: The fourth buffer stores the arbitration results of each arbitrator, and sends the arbitration results of each arbitrator to each selector.

[0116] Here, the fourth buffer sends the received arbitration results of each arbitrator to each selector.

[0117] Step S117 : The selector selects a target data from the plurality of first buffers in sequence according to the arbitration results of the arbitrators within a single clock cycle, and determines the target buffer corresponding to the target data.

[0118] It should be noted that when the bit width of the data is larger than the storage bit width of the storage unit of the storage queue, the data can be split according to the storage bit width, and the sub-data obtained after the split is the data to be read in the above embodiment, wherein each data corresponds to each selector, and thus the selector selects the sub-data of the data corresponding to the selector in different first buffers.

[0119] In some implementations, the selector determines the currently selectable sub-data in each first buffer according to the arbitration result received from the arbitrator, and transports the sub-data to the buffer corresponding to the sub-data through the selector of the data corresponding to the sub-data.

[0120] Step S118: The selector stores the target data in the target buffer.

[0121] In an embodiment of the present disclosure, a method for selecting data of a selector is provided, by which data reading on a data reading circuit corresponding to a group of second buffers of a single selector is completed.

[0122] In some embodiments, Figure 5 As shown, the data reading circuit further includes an instruction information cache module 4, and the method further includes step S141:

[0123] Step S141: The instruction information cache module stores instruction information of a data read instruction, and transmits the instruction information to the request sending module; the instruction information includes a first read request information set.

[0124] Here, the instruction information cache module may be a module for storing data reading instructions.

[0125] In the disclosed embodiment, the data reading instructions stored in the instruction information cache module can provide the request sending module with the data reading instructions, so that the request sending module can determine the read request order of multiple data to be read according to the data reading instructions.

[0126] The present disclosure provides a data reading circuit. Figure 1 A schematic diagram of a data reading circuit provided in an embodiment of the present disclosure Figure 1 ,like Figure 1 As shown, the data reading circuit includes: a request sending module 1, a memory 2 and a data collector 3, the memory 2 includes a plurality of storage queues, the data collector 3 includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond one-to-one to the plurality of storage queues, and each selector corresponds to a group of the second buffers; wherein:

[0127] The request sending module 1 is used to: obtain instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the first read request information set includes read request information of a plurality of data to be read; and send the read request information of each data to be read to a corresponding storage queue respectively;

[0128] A storage queue, used for reading data according to the received read request information, and transmitting the read target data to the corresponding first buffer;

[0129] The selector is used to: select a target data from multiple first buffers in a single clock cycle, and store the target data in a target buffer in a corresponding group of second buffers, where the target buffer corresponds to the read request information of the target data.

[0130] In the above embodiment, since each selector can correspond to a group of second buffers, and selects target data from multiple first buffers within a single clock cycle and stores them in the target buffer in the group of second buffers, compared with the solution in the related technology that each selector corresponds to one second buffer, the number of selectors can be reduced, thereby improving the problem of data collector wiring congestion and reducing the circuit area consumption of the data reading circuit.

[0131] In some embodiments, Figure 3 As shown, the request sending module 1 includes: an instruction processing module 11, a plurality of arbitrators (for example, arbitrator 121, arbitrator 122 ..., arbitrator 12N) and a plurality of third buffers (for example, third buffer 131, third buffer 132, ... third buffer 13N), the plurality of arbitrators correspond one-to-one to the plurality of third buffers, and the plurality of third buffers correspond one-to-one to the storage queues; wherein,

[0132] The instruction processing module 11 is used to: determine the second read request information set corresponding to each storage queue based on the read request information of each data to be read; transmit the second read request information set corresponding to each storage queue to the corresponding arbitrator; store the data to be read corresponding to each read request information in the second read request information set in the storage queue corresponding to the second read request information set;

[0133] an arbitrator, configured to arbitrate the second read request information set, and send the read request information in the second read request information set to a corresponding third buffer according to an arbitration result;

[0134] The third buffer is used to send the read request information of each data to be read to the corresponding storage queue respectively.

[0135] Here, if Figure 3As shown, the request sending module 1 includes an instruction processing module 11, an arbitration module 12 and N third buffers 131 to 13N, wherein N is an integer greater than 1, and the arbitration module 12 includes N arbitrators 121 to 12N, and the N arbitrators 121 to 12N correspond one-to-one to the N third buffers 131 to 13N. Taking the arbitrator 121 as an example, the arbitrator 121 corresponds to the third buffer 131, and the third buffer 131 is used to receive the read request information sent by the arbitrator 121.

[0136] It should be noted that the value of N is related to the instruction information of the data reading instruction obtained in the request sending module 1. The number of storage queues corresponding to multiple data to be read is determined by the storage queue number in the instruction information of the data reading instruction. For example, if the number of storage queues is 3, then the value of N is 3.

[0137] In some embodiments, the arbitrator is further used to: determine a target arbitration rule among multiple arbitration rules; wherein the target arbitration rule is used to ensure that the number of clock cycles used by each selector to read the multiple data to be read does not exceed the target number; determine the arbitration result of the multiple data to be read corresponding to the second read request information set according to the arbitration order corresponding to the target arbitration rule; and send the multiple data to be read to the corresponding third buffer in sequence based on the arbitration result.

[0138] In some embodiments, the instruction processing module 11 is further used to: determine the maximum number value among the quantity values ​​of the to-be-read data stored in multiple storage queues respectively; transmit the maximum number value to each arbitrator; the arbitrator is further used to: determine the target arbitration rule among multiple arbitration rules based on the maximum number value.

[0139] In some embodiments, the data read instruction is a read instruction of an operand of the operation unit, the operand includes at least two sub-operands, and the instruction information of the read instruction includes read request information of each sub-operand;

[0140] The number of selectors is the same as the number of operands, and each group of second buffers includes at least two second buffers corresponding to at least two sub-operands of the same operand.

[0141] In some embodiments, the operands include a first operand, a second operand, and a third operand, each operand includes a first sub-operand and a second sub-operand, and the maximum number value is 3;

[0142] The arbitration order corresponding to the target arbitration rule is: the sending priority of the read request information corresponding to the first suboperand of the first operand, the first suboperand of the second operand, the second suboperand of the second operand, the first suboperand of the third operand, the second suboperand of the third operand and the second suboperand of the first operand respectively decreases in sequence.

[0143] In some embodiments, the operands include a first operand, a second operand, and a third operand, each operand includes a first sub-operand and a second sub-operand, and the maximum number value is 2;

[0144] The arbitration order corresponding to the target arbitration rule is: the sending priority of the read request information corresponding to the first suboperand of the first operand, the first suboperand of the second operand, the first suboperand of the third operand, the second suboperand of the third operand, the second suboperand of the second operand and the second suboperand of the first operand respectively decreases in sequence.

[0145] In some embodiments, Figure 4 As shown, the data collector 3 also includes a fourth buffer 34; wherein:

[0146] The arbitrator is further used to send the arbitration result to the fourth buffer 34;

[0147] A fourth buffer 34, used for storing the arbitration results of each arbitrator and sending the arbitration results of each arbitrator to each selector;

[0148] The selector is used to select a target data from multiple first buffers in sequence according to the arbitration results of each arbitrator in a single clock cycle, and determine the target buffer corresponding to the target data; and store the target data in the target buffer.

[0149] In some embodiments, Figure 5 As shown, the data reading circuit also includes an instruction information cache module 4; wherein:

[0150] The instruction information cache module 4 is used to store instruction information of data read instructions and transmit the instruction information to the request sending module 1; the instruction information includes a first read request information set.

[0151] The following describes the application of the data reading circuit provided by the embodiments of the present disclosure and the data reading method applied to the data reading circuit in actual scenarios, with a data reading instruction as a reading instruction of the operand of the operation unit, where three operands, each operand including two sub-operands, are used as an example for the following description.

[0152] The arithmetic operation unit requires three operands with a bit width of 64 bits, namely: S0, S1 and S2, which are stored in the memory. The memory includes four storage queues, namely storage queue B0, storage queue B1, storage queue B2 and storage queue B3. Each storage queue includes multiple storage units, and each storage unit can only store data with a bit width of 32 bits. Therefore, a 64-bit operand requires two storage units to store.

[0153] Since each storage queue has only one read port, it can only be accessed once in each clock cycle, and one data can be read each time it is accessed. In order to read a complete 64-bit operand from the memory at one time, taking S0 as an example, the computer will split S0 into two 32-bit sub-data (i.e., sub-operands) in advance, respectively recorded as S0_L and S0_H, and store S0_L and S0_H in two adjacent storage queues, and the storage queue number stored in S0_H is larger than the storage queue number stored in S0_L. For example, if S0_L is stored in storage queue B0, then S0_H is stored in storage queue B1. It should be noted that if S0_L is stored in storage queue B3, then S0_H is stored in storage queue B0. By analogy, S1 can be split into S1_L and S1_H, and S2 can be split into S2_L and S2_H. Therefore, S0, S1 and S2 are divided into 6 sub-data (S0_L, S0_H, S1_L, S1_H, S2_L and S2_H) in total. Since the memory has 4 storage queues in total, and two sub-data of the same 64-bit operand cannot be stored in the same storage queue, there must be 2 or 3 sub-data stored in the same storage queue among the 6 sub-data. For example, S0_L and S0_H are stored in storage queue B0 and storage queue B1 respectively, S1_L and S1_H are stored in storage queue B2 and storage queue B3 respectively, then S2_L and S2_H may be stored in storage queue B0 and storage queue B1 respectively, or in storage queue B1 and storage queue B2, or in storage queue B2 and storage queue B3, or in storage queue B3 and storage queue B0. Regardless of the storage combination of S2_L and S2_H, there will be a situation where two sub-data are stored in the same storage queue. Furthermore, S0_L, S1_L and S2_L are stored in the storage queue B0, and S0_H, S1_H and S2_H are stored in the storage queue B1. This is the aforementioned situation where the three sub-data are stored in the same storage queue.

[0154] Since a storage queue can only be accessed once in one clock cycle, if a storage queue stores 2 or 3 sub-data, it takes 2 or 3 clock cycles to read the data respectively. From the above analysis, it can be seen that if there are 2 sub-data stored in the same storage queue, it takes 2 clock cycles to read 6 sub-data; if there are 3 sub-data stored in the same storage queue, it takes 3 clock cycles to read 6 sub-data.

[0155] After these sub-data are read out from the storage queue, they will be cached in the cache corresponding to each cache queue. It should be noted that the caches used in the embodiments of the present disclosure are all first-in-first-out caches, that is, the data stored in the cache first will be read first, and the data stored in the cache later can only be read after the data stored first is read.

[0156] In related technologies, such as Fig. 6A As shown, the operand reading circuit includes: an instruction information cache module 4, a request sending module 1, a memory 2 and a data collector 3. The main function of the instruction information cache module 4 is to save the storage address information of the operation unit (ALU, Arithmetic And Logic Unit) executing the operands S0, S1 and S2, wherein the storage address information includes the storage queue number and the storage unit information; the main function of the request sending module 1 is to arbitrate the operand read request and store the operand read request in the first-level cache in sequence. The main function of the memory 2 is to store the sub-data of all operands used by the ALU, and when receiving the read request from the request sending module 1, the data of the storage unit is taken out and returned to the data collector 3 according to the read request information (storage queue number and storage unit information); the main function of the data collector 3 is to receive the data returned by the memory 2, and cache the returned data in the second-level cache in sequence, and the selector of each sub-data takes out the sub-data cached in the second-level cache according to the operand read request information, and sends the sub-data to the corresponding third-level cache.

[0157] In related technologies, such as Figure 6BAs shown, the instruction information cache module 4 transmits the instruction information (the instruction information mainly includes the read request information of 6 sub-data: storage queue number and storage unit information) to the request sending module 1. The request sending module 1 mainly includes an arbitration module 12 and four level 1 buffers (level 1 buffer D0, level 1 buffer D1, level 1 buffer D2 and level 1 buffer D3). Each level 1 buffer has a corresponding single-priority arbitrator located in the arbitration module 12. The request sending module 1 will classify the read requests of the 6 sub-data according to the storage queue number they are going to access. If there are two or three operand sub-data that need to be accessed in a storage queue, the read requests of the two or three operand sub-data will be arbitrated by the single-priority arbitrator, and finally all operand read requests to access this storage sequence number will be stored in the level 1 buffer in sequence. The arbitration priority of the single-priority arbitrator is: S0_L>S0_H>S1_L>S1_H>S2_L>S2_H.

[0158] For example, S0_L and S0_H need to access storage queue B0 and storage queue B1 respectively, S1_L and S1_H need to access storage queue B2 and storage queue B3 respectively, and S2_L and S2_H need to access storage queue B0 and storage queue B1 respectively. S0_L and S2_L need to be arbitrated by the single-priority arbitrator G0, and the single-priority arbitrator G0 will send S0_L and S2_L to the first-level cache D0 in the order of S0_L->S2_L according to the arbitration priority; S0_H and S2_H need to be arbitrated by the single-priority arbitrator G1, and the single-priority arbitrator G1 will send S0_H and S2_H to the first-level cache D1 in the order of S0_H->S2_H according to the arbitration priority; the single-priority arbitrator G2 and the single-priority arbitrator G3 have only one read request, S1_L and S1_H, respectively, so the single-priority arbitrator G2 and the single-priority arbitrator G3 will directly choose to send S1_L and S1_H to the first-level cache D2 and the first-level cache D3 respectively. It should be noted that when the single-priority arbitrator sends the sub-data read request information of the operand to the first-level cache, the arbitration module 12 will also send the operand read request information and its arbitration information to the data collector 3.

[0159] After the operand sub-data read request enters the first-level cache, the first-level cache will send the operand sub-data read request information (storage unit information) to the storage queue corresponding to the sub-data read request information. For example, the first-level cache D0 will send the read request information to the storage queue B0 of the memory 2. The corresponding storage queue will transfer the data of the storage unit to the data collector 3 according to the storage unit information in the read request information.

[0160] The data collector 3 has two types of L2 buffers. One type is the L2 buffer auxiliary register pointer buffer (ARB, Assistant Register Buffer), which is used to receive the read request arbitration information transmitted by the request sending module 1. The other type of L2 buffer has four, namely, L2 buffer E0, L2 buffer E1, L2 buffer E2 and L2 buffer E3, which are respectively used to receive data returned from storage queue B0, storage queue B1, storage queue B2 and storage queue B3. The data collector 3 has six L3 buffers, namely, L3 buffer S0_L2, L3 buffer S0_H2, L3 buffer S1_L2, L3 buffer S1_H2, L3 buffer S2_L2 and L3 buffer S2_H2, which are respectively used to cache S0_L, S0_H, 1_L, S1_H, S2_L and S2_H sub-data. Each three-level cache has a corresponding selector, namely selector S0_L1, selector S0_H1, selector S1_L1, selector S1_H1, selector S2_L1 and selector S2_H1, which are used to select S0_L, S0_H, S1_L, S1_H, S2_L and S2_H sub-data respectively, and send these sub-data to the corresponding three-level cache.

[0161] Each sub-data may be cached in any one of the L2 cache E0, L2 cache E1, L2 cache E2 and L2 cache E3, so each selector will select the data of a certain L2 cache to retrieve the corresponding sub-data according to the operand read request information in the L2 cache ARB. For example, S0_L and S0_H need to access the storage queue B0 and storage queue B1 respectively, S1_L and S1_H need to access the storage queue B2 and storage queue B3 respectively, and S2_L and S2_H need the storage queue B0 and storage queue B1 respectively. Due to the order of operand read requests, the storage queue B0, storage queue B1, storage queue B2 and storage queue B3 will first return S0_L, S0_H, S1_L and S1_H to the data collector 3, and cache them in the L2 cache E0, L2 cache E1, L2 cache E2 and L2 cache E3 respectively. Then the storage queue B0 and the storage queue B1 return S2_L and S2_H to the data collector 3 respectively, and cache them into the secondary cache E0 and the secondary cache E1 respectively.

[0162] According to the operand read request information in the L2 cache ARB: in the first data collection clock cycle: selector S0_L1 will select S0_L cached in the L2 cache E0 and send it to the L3 cache S0_L2; selector S0_H1 will select S0_H cached in the L2 cache E1 and send it to the L3 cache S0_H2; selector S1_L1 will select S1_L cached in the L2 cache E2 and send it to the L3 cache S1_L2; selector S_H1 will select S0_H cached in the L2 cache E3 and send it to the L3 cache S0_H2; since S2_L is cached in the L2 cache E0 and is cached after S0_L, and S2_H is cached in the L2 cache E1 and is cached after S0_H, in the first collection clock cycle, selectors S2_L1 and S2_H1 are idle.

[0163] In the second data collection clock cycle: selector S2_L1 will select S2_L cached in the second-level cache E0 and send it to the third-level cache S2_L2; selector S2_H1 will select S2_H cached in the second-level cache E1 and send it to the third-level cache S2_H2; the four selectors, selector S0_L1, selector S0_H1, selector S1_L1 and selector S1_H1, are idle.

[0164] From the above analysis, it can be found that in the first collection clock cycle, only four selectors, selector S0_L1, selector S0_H1, selector S1_L1 and selector S1_H1, are used, while selector S2_L1 and selector S2_H1 are idle; in the second collection clock cycle, only selector S2_L1 and selector S2_H1 are used, while selector S0_L1, selector S0_H1, selector S1_L1 and selector S1_H1 are idle; therefore, some selectors are idle in each collection clock cycle, and the selector utilization rate is not high.

[0165] In the related art, the data collection part requires 6 selectors, each of which is a 32-bit selector, which will lead to congestion in the back-end logic integrated wiring, and there is also the problem of low selector utilization, resulting in area waste.

[0166] If there is a routing congestion problem in the code design, it is usually not discovered until the back-end logic synthesis layout and routing stage. However, the means to alleviate routing congestion in the layout and routing stage are very limited. Therefore, it is particularly important to solve the routing congestion problem in the early code design.

[0167] The overall structural diagram of the operand reading circuit of the embodiment of the present disclosure and the overall structural diagram of the operand reading circuit of the related art Figure 1 To, here we still Fig. 6A To explain, Fig. 6A As shown, the overall structure of the operand reading circuit includes: an instruction information cache module 4, a request sending module 1, a memory 2 and a data collector 3. The functions of each module are similar to those of the relevant technology, and the differences from the relevant technology are as follows: the embodiment of the present disclosure uses a dual-priority arbitrator to arbitrate the sub-data read request of the operand; the embodiment of the present disclosure uses three selectors to select all sub-data. The three selectors are selector S00, selector S01 and selector S03, which are responsible for selecting S0_L / S0_H, S1_L / S2_H and S2_L / S2_H respectively. Each selector selects to collect one sub-data in one collection clock cycle.

[0168] Since the number of sub-data is 6, if 3 selectors are used reasonably, when 2 or 3 sub-data are stored in a storage queue, 6 operand sub-data can be collected in 2 or 3 clock cycles. Through the above analysis, it can be known that the order in which the operand read request is sent determines the order in which the data collector collects the sub-data. If the single-priority arbiter of the relevant technical solution is still used to arbitrate the operand sub-data read request, in some cases when 2 sub-data are stored in a storage queue, it cannot meet the collection of 6 operand sub-data within two clock cycles. For example: S0_L and S0_H need to access storage queue B0 and storage queue B1 respectively, S1_L and S1_H need to access storage queue B2 and storage queue B3 respectively, and S2_L and S2_H need storage queue B0 and storage queue B1 respectively. According to the order of the sub-data read requests of the sent operands, the L2 cache E0, L2 cache E1, L2 cache E2 and L2 cache E3 will cache S0_L, S0_H, S1_L and S1_H respectively. Then the L2 cache E0 and L2 cache E1 will cache S2_L and S2_H respectively. Therefore, according to the operand read request information and arbitration information in the second-level buffer ARB, in the first data collection clock cycle: selector S00 will select S0_L cached in the second-level buffer E0 to send to the third-level buffer S0_L2; selector S01 will select S1_L cached in the second-level buffer E2 to send to the third-level buffer S1_L2; since S2_L and S0_L are both cached in the second-level buffer E0, and S2_L is cached after S0_L, S2_L will not be read before S0_L is read; similarly, S2_H and S0_H are both cached in the second-level buffer E1, and S2_H is cached after S0_H, so S2_H will not be read before S0_H is read; therefore, in the first data collection clock cycle, S2_L and S2_H cannot be read, and selector S02 is idle in this clock cycle. In the second data collection clock cycle: selector S00 will select S0_H cached in the secondary cache E1 and send it to the third-level cache S0_H2; selector S01 will select S1_H cached in the secondary memory E3 and send it to the third-level cache S1_H2; at this time, because S0_L cached in the secondary cache E0 has been read out in the first data collection clock cycle, S2_L can be read in the second data collection clock cycle, and selector S02 will select S2_L cached in the secondary cache E0 and send it to the third-level cache S2_L2; therefore, all three selectors are used. At this time, it will be found that there is still an operand sub-data S2_H that has not been collected. Therefore, the third clock cycle is required to fetch data S2_H. Therefore, this scheme of using a single priority arbiter and three selectors will reduce the efficiency of the data collector in collecting data and reduce the performance of the entire circuit system, which is not allowed.

[0169] The disclosed embodiment improves the utilization rate of the selector in the data collector by changing the order of sending operand read requests, thereby reducing the number of selectors used and solving the problem of wiring congestion without reducing the performance of the original technical solution of the project.

[0170] The dual-priority arbiter in the disclosed embodiment will choose to follow one of the two arbitration priorities according to the situation of the operand accessing the storage queue. The two arbitration priorities are:

[0171] The first arbitration priority: S0_L>S1_L>S1_H>S2_L>S2_H>S0_H;

[0172] The second arbitration priority: S0_L>S1_L>S2_L>S2_H>S1_H>S0_H;

[0173] When there are three operand sub-data stored in the same storage queue (whether stored in storage queue B0, storage queue B1, storage queue B2 or storage queue B3), the dual-priority arbitrator follows the first arbitration priority. When there are only two operand sub-data stored in the same storage queue, the dual-priority arbitrator will follow the second arbitration priority. The order of sending operand sub-data read requests is determined according to these two sets of arbitration priorities to improve the utilization rate of the selector in the data collector. By recording the operand arbitration information and sending it to the data collector, each selector of the data collector decides to collect certain sub-data within a certain collection clock cycle according to the operand arbitration information.

[0174] As shown in Table 1, taking the case where 3T or 2T is stored in storage queue B0 as an example, 3T indicates the case where three operand sub-data are stored in the same storage queue B0, and 2T indicates the case where two operand sub-data are stored in the same storage queue B0. Case0 to Case7 in the table indicate the sub-data combination types of operands in the case of 3T or 2T. Storage queue B0 lists the case where the operand sub-data is stored in storage queue B0; storage queue B1 lists the case where the sub-data of some operands is stored in storage queue B0, and the sub-data of other operands is stored in storage queue B1; storage queue B2 lists the case where the sub-data of some operands is stored in storage queue B0, and the sub-data of other operands is stored in storage queue B2; storage queue B3 lists the case where the sub-data of some operands is stored in storage queue B0, and the sub-data of other operands is stored in storage queue B3. The arbitration priority lists two arbitration priorities, and the first arbitration priority is followed in 3T, and the second arbitration priority is followed in 2T. Selector S00, selector S01 and selector S02 represent three selectors in the data collector. C1, C2 and C3 represent the first collection clock cycle, the second collection clock cycle and the third collection clock cycle respectively.

[0175] As shown in Table 1, in the case of 3T, three collection clock cycles are required to collect all six operand sub-data. Taking Case 0 of 3T as an example, S0_L, S1_L and S2_L are stored in storage queue B0, and S0_H, S1_H and S2_H are stored in storage queue B1. According to the arbitration priority S0_L>S1_L>S1_H>S2_L>S2_H>S0_H, the order of operand read requests sent to storage queue B0 is S0_L->S1_L->S2_L, and the order of operand read requests sent to storage queue B1 is S1_H->S2_H->S0_H. The storage queue will return the data to the data collector in the order in which the read requests are sent. The data collector will cache the data in the corresponding secondary cache in the order in which the storage queue returns the data. Therefore, the order in which the operand sub-data read requests are sent determines the order in which the selector in the data collector collects the operand sub-data:

[0176] In the first collection clock cycle: according to the above operand arbitration information, selector S00 can select S0_L cached in the secondary cache E0; selector S01 can select S1_H cached in the secondary cache E1; since S2_L is stored after S0_L and S1_L at this time, it can only be read after S0_L and S1_L are read, and S2_H is stored after S0_H and S1_H, it can only be read after S0_H and S1_H are read, so selector S02 is idle in the first collection clock cycle.

[0177] In the second collection clock cycle: S0_L and S1_H have been read. Since S0_H is stored after S2_H at this time, selector S00 is idle in the second collection clock cycle. Selector S01 can select S1_L cached in the second-level cache E0; selector S02 can select S2_H cached in the second-level cache E1.

[0178] In the third collection clock cycle: S0_L and S1_H, S1_L and S2_H have been read, and selector S00 can select S0_H cached in the secondary cache E1; since S1_L and S1_H have been read at this time, selector S01 is idle in the first collection clock cycle. Selector S02 can select S2_L cached in the secondary cache E0.

[0179] Taking 2T Case 0 as an example, S0_L and S1_L are stored in storage queue B0, S0_H and S1_H are stored in storage queue B1, and S2_L and S2_H are stored in storage queue B2 and storage queue B3 respectively. According to the arbitration priority S0_L>S1_L>S2_L>S2_H>S1_H>S0_H, the order of operand read requests sent to storage queue B0 is S0_L->S1_L, the order of operand read requests sent to storage queue B1 is S1_H->S0_H, the order of operand read requests sent to storage queue B2 is S2_L, and the order of operand read requests sent to storage queue B3 is S2_H. The order of sending operand read requests determines the order in which the selector in the data collector collects operand sub-data:

[0180] In the first collection clock cycle: according to the above operand arbitration information, selector S00 can select S0_L cached in the L2 cache E0; selector S01 can select S1_H cached in the L2 cache E1; selector S02 can select S2_L cached in the L2 cache E2.

[0181] In the second collection clock cycle: S0_L, S1_H and S2_L have been read. Selector S00 can select S0_H cached in L2 buffer B01; selector S01 can select S1_L cached in L2 buffer E0; selector S02 can select S2_H cached in L2 buffer E3.

[0182] As can be seen from Table 1, three collection clock cycles are required at 3T and two collection clock cycles are required at 2T. The performance of the data collector has not changed, but the selectors of the data collector are reduced to 3, which solves the routing congestion problem during back-end logic synthesis and also reduces area overhead.

[0183] Table 1 Sub-operand storage combination

[0184]

[0185]

[0186]

[0187]

[0188] like Figure 6C As shown in the figure, taking Case 0 of 3T as an example, the specific implementation process is explained:

[0189] The request sending module 1 receives the operand storage address information sent by the instruction information cache module 4, and the arbitration module 12 sends S0_L, S1_L and S2_L to the dual-priority arbiter F0 according to the operand storage address information, and sends S0_H, S1_H and S2_H to the dual-priority arbiter F1. According to the arbitration priority S0_L>S1_L>S1_H>S2_L>S2_H>S0_H, the dual-priority arbiter F0 sends the read request information of S0_H, the read request information of S1_H and the read request information of S2_H to the first-level cache D0 in the order of S0_L->S1_L->S2_L, and the first-level cache D0 sends the operand read request to the storage queue B0 in the memory 2 in the order of S0_L->S1_L->S2_L; the dual-priority arbiter F1 sends the read request information of S0_H, S1_H and S2_H to the storage queue B0 in the memory 2 in the order of S1_H- >The read request information of S1_H, the read request information of S2_H and the read request information of S0_H are sent to the first-level cache D1 in the order of S2_H->S0_H, and the first-level cache D1 sends the operand read request to the storage queue B1 in the memory 2 in the order of S1_H->S2_H->S0_H; in addition, the dual-priority arbitrator sends the operand read request to the first-level cache, and also sends the operand read request information and arbitration information to the second-level cache ARB of the data collector 3 for caching.

[0190] Storage queues B0 and B1 will return data to L2 cache E0 and L2 cache E1 in data collector 3 in the order of sending read requests. Selectors S00, S01 and S02 will request information and arbitration information according to the operands in L2 cache ARB and select the correct sub-data in different data collection clock cycles.

[0191] In the first collection clock cycle: according to the above operand arbitration information, selector S00 can select S0_L cached in the second-level cache E0, and cache S0_L to the third-level cache S0_L2; selector S01 can select S1_H cached in the second-level cache E1, and cache S1_H to the third-level cache S1_H2; since S2_L is stored in the position after S0_L and S1_L at this time, S2_L can only be read after S0_L and S1_L are read, and S2_H is stored in the position after S1_H, and S2_H can only be read after S0_H and S1_H are read, so selector S02 is idle in the first collection clock cycle.

[0192] In the second collection clock cycle: S0_L and S1_H have been read. Since S0_H is stored after S2_H at this time, selector S00 is idle in the second collection clock cycle. Selector S01 can select S1_L cached in the second-level cache E0, and cache S1_L to the third-level cache S1_L2; selector S02 can select S2_H cached in the second-level cache E1, and cache S2_H to the third-level cache S2_H2.

[0193] In the third collection clock cycle: S0_L and S1_H, S1_L and S2_H have been read, selector S00 can select S0_H cached in the second-level cache E1, and cache S0_H to the third-level cache S0_H2; because S1_L and S1_H have been read at this time, selector S01 is idle in the third collection clock cycle. Selector S02 can select S2_L cached in the second-level cache E0, and cache S2_L to the third-level cache S2_L2.

[0194] like Figure 6C As shown in the figure, taking Case 0 of 2T as an example, the specific implementation process is explained:

[0195] The request sending module 1 receives the operand storage address information sent by the instruction information cache module 4, and the arbitration module 12 sends S0_L and S1_L to the dual-priority arbiter F0, sends S0_H and S1_H to the dual-priority arbiter F1, sends S2_L to the dual-priority arbiter F2, and sends S2_H to the dual-priority arbiter F3 according to the operand storage address information. According to the arbitration priority S0_L>S1_L>S2_L>S2_H>S1_H>S0_H, the dual-priority arbiter F0 sends the read request information of S0_L and the read request information of S1_L to the first-level cache D0 in the order of S0_L->S1_L, and the first-level cache D0 sends the operand read request to the storage queue B0 in the memory 2 in the order of S0_L->S1_L; the dual-priority arbiter F1 sends the read request information of S1_H and the read request information of S0_H to the first-level cache D1 in the order of S1_H->S0_H, and the first-level cache D1 sends the operand read request to the storage queue B0 in the memory 2 in the order of S1_H->S0_H. >The operand read request is sent to the storage queue B1 in the memory 2 in the order of S0_H; the dual-priority arbitrator F2 sends S2_L to the first-level cache D2, and the first-level cache D2 sends the S2_L read request to the storage queue B2 in the memory 2; the dual-priority arbitrator F3 sends S2_H to the first-level cache D3, and the first-level cache D3 sends the S2_H read request to the storage queue B3 in the memory 2; while sending the operand read request to the first-level cache, the dual-priority arbitrator will also send the operand read request information and arbitration information to the second-level cache ARB of the data collector 3 for caching.

[0196] Storage queues B0, B1, B2 and B3 will return data to the L2 cache E0, E1, E2 and E3 in the data collector in the order of sending read requests. Selectors S00, S01 and S02 will request information and arbitration information based on the operands in the L2 cache ARB, and select the correct sub-data in different data collection clock cycles:

[0197] During the first collection clock cycle: according to the above operand arbitration information, selector S00 can select S0_L cached in the second-level cache E0, and cache S0_L to the third-level cache S0_L2; selector S01 can select S1_H cached in the second-level cache E1, and cache S1_H to the third-level cache S1_H2; selector S02 can select S2_L cached in the second-level cache E2, and cache S2_L to the third-level cache S2_L2.

[0198] In the second collection clock cycle: S0_L, S1_H and S2_L have been read. Selector S00 can select S0_H cached in the L2 cache E1 and cache S0_H to the L3 cache S0_H2; selector S01 can select S1_L cached in the L2 cache E0 and cache S1_L to the L3 cache S1_L2; selector S02 can select S2_H cached in the L2 cache E3 and cache S2_H to the L3 cache S2_H2.

[0199] It should be noted that the first cache, the second cache and the third cache in the aforementioned embodiment can be implemented as the aforementioned second-level cache E0~E3, the third-level cache and the first-level cache D0~D3 respectively; the fourth cache can be implemented as the aforementioned second-level cache ARB.

[0200] In the disclosed embodiment, a dual-priority arbitration strategy is adopted to reduce the number of selectors of the data collector by half without reducing the performance of the relevant technical solution, thereby improving the wiring congestion problem during the back-end logic synthesis and reducing the area overhead of the selector by half.

[0201] Based on the foregoing embodiments, an embodiment of the present disclosure provides a chip, wherein the chip includes the data reading circuit in the foregoing embodiments.

[0202] Based on the foregoing embodiments, an embodiment of the present disclosure provides a graphics card, which includes the chip in the foregoing embodiments.

[0203] Based on the foregoing embodiments, an embodiment of the present disclosure provides an electronic device, wherein the electronic device includes the chip in the foregoing embodiments.

[0204] It should be noted here that the description of each embodiment above tends to emphasize the differences between the embodiments, and the same or similar aspects can be referenced to each other. The description of the above chip embodiment is similar to the description of the above circuit embodiment, and has similar beneficial effects as the circuit embodiment. For technical details not disclosed in the chip embodiment of the present disclosure, please refer to the description of the circuit embodiment of the present disclosure for understanding.

[0205] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution. The execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0206] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0207] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0208] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0209] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0210] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, etc., various media that can store program codes.

[0211] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0212] The above description is only an implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A data reading circuit, characterized in that: include: A request sending module, a memory and a data collector, wherein the memory includes a plurality of storage queues, the data collector includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond one-to-one to the plurality of storage queues, and each of the selectors corresponds to a group of the second buffers; wherein, The request sending module is used to: obtain instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the first read request information set includes read request information of a plurality of data to be read; and send the read request information of each of the data to be read to a corresponding storage queue respectively; The storage queue is used to read data according to the received read request information, and transmit the read target data to the corresponding first buffer; The selector is used to: select a target data from multiple first buffers within a single clock cycle, and store the target data in a target buffer in a corresponding group of second buffers, and the target buffer corresponds to the read request information of the target data.

2. The data reading circuit according to claim 1, characterized in that: The request sending module includes: an instruction processing module, a plurality of arbitrators and a plurality of third buffers, wherein the plurality of arbitrators correspond to the plurality of third buffers one-to-one, and the plurality of third buffers correspond to the plurality of storage queues one-to-one; wherein, The instruction processing module is used to: determine the second read request information set corresponding to each storage queue based on the read request information of each data to be read; transmit the second read request information set corresponding to each storage queue to the corresponding arbitrator; store the data to be read corresponding to each read request information in the second read request information set in the storage queue corresponding to the second read request information set; The arbitrator is used to arbitrate the second read request information set, and send the read request information in the second read request information set to the corresponding third buffer according to the arbitration result; The third buffer is used to send the read request information of each of the to-be-read data to the corresponding storage queue respectively.

3. The data reading circuit according to claim 2, characterized in that: The arbitrator is further used to: determine a target arbitration rule among multiple arbitration rules; wherein the target arbitration rule is used to ensure that the number of clock cycles used by each selector to read the multiple data to be read does not exceed a target number; determine an arbitration result of the multiple data to be read corresponding to the second read request information set according to the arbitration order corresponding to the target arbitration rule for the received second read request information set; and send the multiple data to be read to the corresponding third buffer in sequence based on the arbitration result.

4. The data reading circuit according to claim 3, characterized in that: The instruction processing module is further used to: determine the maximum value of the quantity of the to-be-read data respectively stored in the plurality of storage queues; and transmit the maximum value to each of the arbitrators; The arbitrator is further configured to determine a target arbitration rule from among a plurality of arbitration rules based on the maximum number value.

5. The data reading circuit according to claim 4, characterized in that: The data read instruction is a read instruction of an operand of a computing unit, the operand includes at least two sub-operands, and the instruction information of the read instruction includes read request information of each of the sub-operands; The number of the selectors is the same as the number of the operands, and each group of the second buffers includes at least two second buffers corresponding to at least two sub-operands of the same operand.

6. The data reading circuit according to claim 5, characterized in that: The operands include a first operand, a second operand and a third operand, each of the operands includes a first sub-operand and a second sub-operand, and the maximum number value is 3; The arbitration order corresponding to the target arbitration rule is: the sending priority of the read request information corresponding to the first sub-operand of the first operand, the first sub-operand of the second operand, the second sub-operand of the second operand, the first sub-operand of the third operand, the second sub-operand of the third operand and the second sub-operand of the first operand respectively decreases in sequence.

7. The data reading circuit according to claim 5, characterized in that: The operands include a first operand, a second operand and a third operand, each of the operands includes a first sub-operand and a second sub-operand, and the maximum number value is 2; The arbitration order corresponding to the target arbitration rule is: the sending priority of the read request information corresponding to the first sub-operand of the first operand, the first sub-operand of the second operand, the first sub-operand of the third operand, the second sub-operand of the third operand, the second sub-operand of the second operand and the second sub-operand of the first operand respectively decreases in sequence.

8. The data reading circuit according to claim 3, characterized in that: The data collector also includes a fourth buffer; wherein, The arbitrator is further used to send the arbitration result to the fourth buffer; The fourth buffer is used to store the arbitration results of each of the arbitrators and send the arbitration results of each of the arbitrators to each selector; The selector is used to select a target data from multiple first buffers in turn according to the arbitration results of each arbitrator within a single clock cycle, and determine the target buffer corresponding to the target data; and store the target data in the target buffer.

9. The data reading circuit according to any one of claims 1 to 8, characterized in that: The data reading circuit also includes an instruction information cache module; wherein, The instruction information cache module is used to store instruction information of data read instructions and transmit the instruction information to the request sending module; the instruction information includes a first read request information set.

10. A data reading method, characterized in that: Applied to a data reading circuit, the data reading circuit includes a request sending module, a memory and a data collector, the memory includes a plurality of storage queues, the data collector includes a plurality of first buffers, a plurality of selectors and a plurality of groups of second buffers, the plurality of first buffers correspond to the plurality of storage queues one by one, each of the selectors corresponds to a group of the second buffers, the method includes: The request sending module obtains instruction information of a data read instruction, wherein the instruction information includes a first read request information set; the first read request information set includes read request information of a plurality of data to be read; The request sending module sends the read request information of each of the to-be-read data to the corresponding storage queue respectively; The storage queue reads data according to the received read request information, and transmits the read target data to the corresponding first buffer; The selector selects a target data from the plurality of the first buffers within a single clock cycle, and stores the target data in a target buffer in a corresponding group of second buffers, wherein the target buffer corresponds to the read request information of the target data.

11. A chip, characterized in that: The chip includes the data reading circuit according to any one of claims 1 to 9.

12. A graphics card, characterized in that: The graphics card comprises the chip as claimed in claim 11.

13. An electronic device, characterized in that: The electronic device comprises the chip according to claim 11.

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