Four-node flip self-recovery latch

Abstract

The invention provides a four-node flip self-recovery latch. The four-node flip self-recovery latch comprises an output soft error interception module, a node soft error interception module and a transmission gate module, the output soft error interception module comprises eight input ends and one output end, the eight input ends are N1, N2, N3, N4, N5, N6, N7 and N8 respectively, and the output end is Q; the output soft error interception module is used for ensuring that an output value is kept unchanged when multi-node overturning is caused by a soft error; the node soft error interception module comprises eight node soft error interception circuits with the same structure, and each node soft error interception circuit comprises eight input ends and one output end; the input of the eight-node soft error interception circuit is Q and seven bits of N1, N2, N3, N4, N5, N6, N7 and N8, and the output of the eight-node soft error interception circuit is the other bit of N1, N2, N3, N4, N5, N6, N7 and N8; the node soft error interception module is used for ensuring that respective output values remain unchanged when multiple nodes are flipped due to soft errors; the transmission gate module comprises nine input ends and nine output ends, the nine input ends are used for inputting data, and the output ends are Q, N1, N2, N3, N4, N5, N6, N7 and N8 respectively; and the transmission gate module is used for transmitting data to N1, N2, N3, N4, N5, N6, N7 and N8 in a data transmission mode.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a four-node flip self-recovery latch. Background Art

[0002] With the continuous development of semiconductor manufacturing technology, the feature size of transistors has been scaled down, which is conducive to higher integration, shorter delay and lower overhead. However, the increasing sensitivity of nanometer-scale CMOS technology to radiation-induced soft errors has brought great challenges. When high-energy particles hit sensitive nodes in memory circuits, they cause single-event upsets (SEUs). In the past micron-scale integrated circuits (ICs), SEUs usually cause single-node upsets (SNUs) in latches. Since the total collected charge required to disturb sensitive nodes is significantly reduced in nanometer technology, due to the charge sharing effect, one particle impact may affect more than one adjacent node, resulting in multiple node upsets (MNUs), including double node upsets (DNUs), triple node upsets (TNUs) and quadruple node upsets (QNUs). Charge sharing is the result of carrier diffusion in the substrate or wells, leading to the complexity of SEUs and pulse quenching effects. As the proportion of TNU and QNU continues to rise, hardening technologies for MNU are needed to enhance the reliability of advanced integrated circuit systems.

[0003] In order to mitigate the impact of soft errors, radiation hardened design (RHBD) latches have received extensive attention. These existing hardened latch designs can be divided into three types: MNU-partial tolerance, MNU-full tolerance, and MNU-self-recovery latches, with protection capabilities increasing in sequence. In safety-critical storage systems, ensuring that data is correctly stored for a long time, especially in hold mode, is crucial for latches to prevent error accumulation. Therefore, MNU-self-recovery latches have received increasing attention. Existing designs basically use dual interlocked storage cells (DICE) and C elements (CE) to achieve soft error propagation blocking and data self-recovery. However, these hardened elements consume a lot of area and power. Among the existing hardened latches, there are very few latches that can achieve full QNU self-recovery, and these only designs are very expensive in terms of area and power consumption. Obviously, how to achieve the design of RHBD latches with QNU full self-recovery at a lower cost is still a difficult problem.

[0004] In view of this, it is necessary to provide a low-overhead four-node flip self-recovery latch to solve the above-mentioned problems in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a four-node flip self-recovery latch, which can solve the problems of high overhead and low reliability of the latch in the prior art.

[0006] In order to achieve the above object, the present invention provides a four-node flip self-recovery latch, comprising:

[0007] Output soft error interception module, node soft error interception module and transmission gate module;

[0008] The output soft error interception module includes 8 input terminals and 1 output terminal, the 8 input terminals are N1, N2, N3, N4, N5, N6, N7, and N8, and the output terminal is Q; the output soft error interception module is used to ensure that the output value remains unchanged when a soft error causes a multi-node flip;

[0009] The node soft error interception module comprises 8 node soft error interception circuits of the same structure, each of which comprises 8 input terminals and 1 output terminal; the inputs of the 8 node soft error interception circuits are Q and seven bits of N1, N2, N3, N4, N5, N6, N7, and N8, and the outputs are another bit of N1, N2, N3, N4, N5, N6, N7, and N8; the node soft error interception module is used to ensure that the respective output values ​​remain unchanged when a soft error causes multiple nodes to flip;

[0010] The transmission gate module includes 9 input terminals and 9 output terminals, the 9 input terminals are all used to input data, and the output terminals are Q and N1, N2, N3, N4, N5, N6, N7, and N8 respectively; the transmission gate module is used to transmit data to N1, N2, N3, N4, N5, N6, N7, and N8 in data transmission mode.

[0011] In an optional solution, the output soft error interception module includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first Schmitt inverter;

[0012] The gates of the first PMOS tube, the first NMOS tube, the second PMOS tube, the second NMOS tube, the third PMOS tube, the third NMOS tube, the fourth PMOS tube, and the fourth NMOS tube are connected to the N1, N2, N3, N4, N5, N6, N7, and N8 terminals respectively;

[0013] The source terminals of the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are connected to the ground, and the drain terminals are commonly connected to a point, denoted as tq, and the point is connected to the drain terminals of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube; the source terminals of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are connected to the power supply voltage; tq is connected to the input terminal of the first Schmitt inverter, and the output terminal of the first Schmitt inverter serves as the output terminal of the output soft error interception module.

[0014] In an optional solution, the node soft error interception circuit includes: a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and an inverter;

[0015] The gates of the fifth PMOS tube, the fifth NMOS tube, the sixth PMOS tube, the sixth NMOS tube, the seventh PMOS tube, the seventh NMOS tube, the eighth PMOS tube, and the eighth NMOS tube of different node soft error interception circuits are respectively connected to Q and seven of N1, N2, N3, N4, N5, N6, N7, and N8;

[0016] The source terminals of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are connected to the ground, and the drain terminals are commonly connected to a point, denoted as tn (n=1, 2, 3, 4, 5, 6, 7, 8), and the point is connected to the drain terminals of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube; the source terminals of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube are connected to the power supply voltage; tn is connected to the input terminal of the inverter, and the output terminals of the inverters of different node soft error interception circuits are connected to another one of N1, N2, N3, N4, N5, N6, N7, and N8.

[0017] In an optional scheme, the transmission gate module includes a first transmission gate, a second transmission gate, a third transmission gate, a fourth soft transmission gate, a fifth transmission gate, a sixth transmission gate, a seventh transmission gate, an eighth transmission gate, and a ninth transmission gate; the input ends of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate, the sixth transmission gate, the seventh transmission gate, the eighth transmission gate, and the ninth transmission gate are used for inputting data, and the outputs are Q, N1, N2, N3, N4, N5, N6, N7, and N8 respectively.

[0018] In an optional solution, the first Schmitt inverter and the inverter each include a control terminal for inputting a signal clock CLK;

[0019] The first transmission gate, the second transmission gate, the third transmission gate, the fourth soft transmission gate, the fifth transmission gate, the sixth transmission gate, the seventh transmission gate, the eighth transmission gate, and the ninth transmission gate each include a control terminal for inputting a signal NCK;

[0020] In data transmission mode, CLK is 0, NCK is 1, the transmission gate is turned on, and data is transmitted to N1, N2, N3, N4, N5, N6, N7, N8, and Q;

[0021] In data hold mode, CLK is 0, NCK is 1, and the transmission gate is off.

[0022] In an optional solution, the inverter is a Schmitt inverter.

[0023] The beneficial effects of the present invention are:

[0024] The present invention realizes that the latch result can remain unchanged or quickly recover to the correct value under the error flip of any four nodes of the circuit.

[0025] Furthermore, the latch achieves high radiation protection capability with four-node recoverability, achieves low area consumption, achieves low power consumption using clock gating technology, and has low data latency by introducing a high-speed path from D to Q. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0027] Figure 1 4 is a circuit diagram of a four-node flip self-recovery latch in one embodiment of the present invention.

[0028] Figure 2 FIG. 4 is a circuit structure diagram of an output soft error interception module in an embodiment of the present invention.

[0029] Figure 3 It is a structural diagram of a first node soft error interception circuit in a node soft error interception module in one embodiment of the present invention.

[0030] Figure 4 FIG. 4 is an input-output curve (DC analysis curve) of a Schmitt trigger in an embodiment of the present invention.

[0031] Figure 5 FIG. 4 is an input-output curve (transient analysis curve) of a Schmitt trigger in an embodiment of the present invention.

[0032] Figure 6Schematic diagram of transient simulation results of a key four-node particle injection latch circuit in one embodiment of the present invention.

[0033] Description of reference numerals:

[0034] 10-latch; 100-output soft error interception module; 200-node soft error interception module; 201-first node soft error interception circuit; 202-second node soft error interception circuit; 203-third node soft error interception circuit; 204-fourth node soft error interception circuit; 205-fifth node soft error interception circuit; 206-sixth node soft error interception circuit; 207-seventh node soft error interception circuit; 208-eighth node soft error interception circuit; 300-transmission gate module; 301-first transmission gate; 302-second transmission gate; 303-third transmission gate; 304-fourth transmission gate; 305-fifth transmission gate; 306-sixth transmission gate; 307-seventh transmission gate; 308-eighth transmission gate; 309-ninth transmission gate. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0037] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Example 1

[0040] Reference Figures 1 to 6 This embodiment provides a four-node flip self-recovery latch 10, including:

[0041] Output soft error interception module 100, node soft error interception module 200 and transmission gate module 300;

[0042] The output soft error interception module 100 includes 8 input terminals and 1 output terminal, the 8 input terminals are N1, N2, N3, N4, N5, N6, N7, N8, and the output terminal is Q; the output soft error interception module 100 is used to ensure that the output value remains unchanged when a soft error occurs and causes multiple nodes to flip;

[0043] The node soft error interception module 100 includes 8 node soft error interception circuits with the same structure, each of which includes 8 input terminals and 1 output terminal; the inputs of the 8 node soft error interception circuits are Q and seven bits of N1, N2, N3, N4, N5, N6, N7, and N8, and the outputs are another bit of N1, N2, N3, N4, N5, N6, N7, and N8; the node soft error interception module is used to ensure that the respective output values ​​remain unchanged when a soft error occurs and causes multiple nodes to flip;

[0044] The transmission gate module includes 9 input terminals and 9 output terminals, the 9 input terminals are all used to input data, and the output terminals are Q and N1, N2, N3, N4, N5, N6, N7, and N8 respectively; the transmission gate module is used to transmit data to N1, N2, N3, N4, N5, N6, N7, and N8 in data transmission mode.

[0045] Specifically, in this embodiment, the output soft error interception module includes: a first NMOS transistor M N1 , the second NMOS tube M N2 , the third NMOS tube M N3 , the fourth NMOS tube M N4 , the first PMOS tube M P1 , the second PMOS tube M P2 , the third PMOS tube M P3 , the fourth PMOS tube M P4 and a first Schmitt inverter; wherein the first PMOS tube M P1 , the first NMOS tube M N1 , the second PMOS tube M P2 , the second NMOS tube M N2 , the third PMOS tube M P3 , the third NMOS tube M N3 , the fourth PMOS tube M P4 , the fourth NMOS tube M N4 The gates of the first NMOS tube M are connected to the N1, N2, N3, N4, N5, N6, N7, and N8 terminals respectively; N1 , the second NMOS tube M N2 , the third NMOS tube M N3 , the fourth NMOS tube M N4 The source terminal is connected to the ground, and the drain terminal is connected to a point, which is denoted as tq, and the point is connected to the first PMOS tube M P1 , the second PMOS tube M P2 , the third PMOS tube M P3 , the fourth PMOS tube M P4 The drain terminal of the first PMOS tube M P1, the second PMOS tube M P2 , the third PMOS tube M P3 , the fourth PMOS tube M P4 The source terminal of is connected to the power supply voltage; tq is connected to the input terminal of the first Schmitt inverter, and the output terminal of the first Schmitt inverter serves as the output terminal of the output soft error interception module.

[0046] The output soft error interception module 100 uses a Schmitt inverter to generate a high / low threshold voltage with hysteresis; when the input voltage exceeds the high threshold voltage, the output voltage changes to a low level. At the same time, when the input voltage is lower than the low threshold voltage, the output voltage changes to logic "1". It is ensured that the output Q is not affected when any four nodes among N1, N2, N3, N4, N5, N6, N7, N8, t1, t2, t3, t4, t5, t6, t7, and t8 are flipped.

[0047] The node soft error interception module 200 includes 8 node soft error interception circuits with the same structure, namely: a first node soft error interception circuit 201, a second node soft error interception circuit 202, a third node soft error interception circuit 203, a fourth node soft error interception circuit 204, a fifth node soft error interception circuit 205, a sixth node soft error interception circuit 206, a seventh node soft error interception circuit 207, and an eighth node soft error interception circuit 208; each node soft error interception circuit includes four NMOS transistors, four PMOS transistors and an inverter; including eight input terminals and one output terminal; the input and output terminals of the 8 node soft error interception circuits are connected to different nodes, which is used to ensure that the modules can ensure that their respective output values ​​remain unchanged when a soft error causes multiple node flips. The node soft error interception circuit can use a Schmitt inverter or a common inverter to achieve data retention or self-recovery after the output is flipped for multiple internal nodes.

[0048] The first node soft error interception circuit 201 includes: a fifth NMOS transistor M N5 , the sixth NMOS tube M N6 , the seventh NMOS tube M N7 , the eighth NMOS tube M N8 , the fifth PMOS tube M P5 , the sixth PMOS tube M P6 , the seventh PMOS tube M P7 , the eighth PMOS tube M P8 and an inverter; wherein the fifth PMOS tube M P5 , the fifth NMOS tube M N5 , the sixth PMOS tube M P6 , the sixth NMOS tube M N6 , the seventh PMOS tube MP7 , the seventh NMOS tube M N7 , the eighth PMOS tube M P8 , the eighth NMOS tube M N8 The gates of the fifth NMOS tube M are connected to Q and N2, N3, N4, N5, N6, and N7 respectively; N5 , the sixth NMOS tube M N6 , the seventh NMOS tube M N7 , the eighth NMOS tube M N8 The source terminal is connected to the ground, and the drain terminal is connected to a point, which is denoted as t1, and the point is connected to the fifth PMOS tube M P5 , the sixth PMOS tube M P6 , the seventh PMOS tube M P7 , the eighth PMOS tube M P8 The drain terminal of the fifth PMOS tube M P5 , the sixth PMOS tube M P6 , the seventh PMOS tube M P7 , the eighth PMOS tube M P8 The source terminal of is connected to the power supply voltage; t1 is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to N1. Figure 1 , the input terminal Q of the second node soft error interception circuit 202 and N1, N3, N4, N5, N6, N7, N8; the input terminal of the inverter is t2, and the output terminal of the inverter is connected to N2; the input terminal Q of the third node soft error interception circuit 203 and N1, N2, N4, N5, N6, N7, N8; the input terminal of the inverter is t3, and the output terminal of the inverter is connected to N3; the input terminal Q of the fourth node soft error interception circuit 204 and N1, N2, N3, N5, N6, N7, N8; the input terminal of the inverter is t4, and the output terminal of the inverter is connected to N4; the input terminal Q of the fifth node soft error interception circuit 205 and N1, N2, N3, N4 , N6, N7, N8; the input end of the inverter is t5, and the output end of the inverter is connected to N5; the input end Q of the sixth node soft error interception circuit 206 and N1, N2, N3, N4, N5, N7, N8; the input end of the inverter is t6, and the output end of the inverter is connected to N6; the input end Q of the seventh node soft error interception circuit 207 and N1, N2, N3, N4, N5, N6, N8; the input end of the inverter is t7, and the output end of the inverter is connected to N7; the input end Q of the eighth node soft error interception circuit 208 and N1, N2, N3, N4, N5, N6, N7; the input end of the inverter is t8, and the output end of the inverter is connected to N8.

[0049] In this embodiment, the transmission gate module 300 includes a first transmission gate 301, a second transmission gate 302, a third transmission gate 303, a fourth soft transmission gate 304, a fifth transmission gate 305, a sixth transmission gate 306, a seventh transmission gate 307, an eighth transmission gate 308, and a ninth transmission gate 309; and is used to transmit data D to N1, N2, N3, N4, N5, N6, N7, N8, and Q in the data transmission mode. The transmission gate module 300 introduces a high-speed path from D to Q, and realizes a very small data delay.

[0050] In this embodiment, the first Schmidt inverter and the inverter each include a control terminal for inputting a signal clock CLK; the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate, the sixth transmission gate, the seventh transmission gate, the eighth transmission gate, and the ninth transmission gate each include a control terminal for inputting a signal NCK; in data transmission mode, CLK is 0, NCK is 1, the transmission gate is turned on, and data is transmitted to N1, N2, N3, N4, N5, N6, N7, N8, and Q; in data retention mode, CLK is 0, NCK is 1, and the transmission gate is turned off. The output soft error interception module 100 and the node soft error interception module 200 introduce CLK clock gating technology, and the circuit power consumption is effectively reduced. The CLK signal in the output soft error interception module 100 and the node soft error interception module 200 and the NCK signal in the transmission gate module are inverted signals; in the data transmission mode, CLK is 0, NCK is 1, all transmission gates are turned on, and data D is transmitted to N1, N2, N3, N4, N5, N6, N7, N8 and Q; all internal nodes N1, N2, N3, N4, N5, N6, N7, N8, t1, t2, t3, t4, t5, t6, t7, t8, Q, tq in the output soft error interception module 100 and the node soft error interception module 200 are initialized; in the data retention mode, CLK is 0, NCK is 1, and the transmission gate is turned off; the 9 feedback loops formed by the output soft error interception module 100 and the node soft error interception module 200 are used for self-recovery when a latch flip occurs within four nodes.

[0051] The following is a detailed description of the method for implementing four-node flip recovery in the four-node flip self-recovery latch 10 of this embodiment.

[0052] The internal nodes of the latch circuit are divided into two types, where the first type includes N1-N8 and Q, and the second type includes t1-t8 and tq. To provide a clear overview, the possible four-node upsets (QNU) are divided into five categories, as described below.

[0053] Case 1: All four failures occur on the first type of nodes, i.e.<N1,N2,N3,N4> ,<N1,N3,N5,N7> ,<N2,N4,N6,N8> ,<N1,N2,N3,Q> We first start with<N1,N2,N3,N4> For example, among the nine soft error interception circuits, the output soft error interception circuit 100 receives four fault inputs, and Q will remain in the previous state because the value of tq is lower than the high threshold voltage of the Schmitt trigger. The node soft error interception circuits 1 to 4 receive three fault inputs. Since these circuits can tolerate three fault inputs, the values ​​of t1 to t4 are not affected, thereby quickly refreshing the node group.<N1,N2,N3,N4> The soft error interception circuits 5 to 8 of other nodes will enter a temporary unstable state at the beginning, but all input and output nodes will soon recover to the correct state.<N1,N3,N5,N7> or<N2,N4,N6,N8> The QNU fault occurs at all inputs of the NMOS or PMOS transistors of the output soft error interception circuit. Since Q remains unchanged, all nodes will be automatically repaired. Although the power consumption temporarily increases during the QNU event, the overall power consumption is still within the acceptable range due to the rapid recovery of the error node.<N1,N2,N3,Q> In the case of , the faulty nodes are the outputs of the soft error interception circuit and the outputs of the node soft error interception circuits 1 to 3. Since the above circuit receives three faulty inputs, these nodes will self-heal.

[0054] Case 2: Three faults occur at the first type of nodes and one fault occurs at the second type of node, i.e.<N1,N2,N3,t4> ,<N1,N2,Q,t1> ,<N1,N2,N3,t1> ,<N1,N2,Q,tq> We first consider<N1,N2,N3,t4> QNU situation. t4 is disturbed and node soft error interception circuit 4 receives three fault inputs, so t4 can self-heal. Node soft error interception circuits 1 to 3 receive two fault inputs. The internal nodes from t1 to t3 in the circuit maintain the correct value. Therefore, N1, N2 and N3 are refreshed through node soft error interception circuits 1 to 3, and the inputs of other circuits become fault-free states, ensuring that all latch nodes are in the correct state.<N1,N2,Q,t1> In the case of QNU, N2 and Q are restored due to the correct values ​​of t2 and tq. t1 and N1 are also restored by the correct input of the node soft error interception circuit 1.<N1,N2,N3,t1> In the case of , N2 and N3 can self-repair through the node soft error interception circuit 2 and the output soft error interception circuit. t1 and N1 will also be refreshed through the non-faulty input of the node soft error interception circuit 1. Similarly,<N1,N2,Q,tq> The QNU will also have recovery capabilities.

[0055] Case 3: Two faults occur at the first type of nodes, and the other two faults occur at the second type of nodes, i.e.<N1,N2,t3,t4> ,<N1,Q,t3,t1> ,<N1,N2,t1,t3> ,<N1,Q,t3,tq> We first consider<N1,N2,t3,t4> QNU situation. Since the node values ​​of t1 and t2 remain correct, N1 and N2 can achieve self-repair. Node soft error interception circuits 3 and 4 (up to two input faults) drive t3 and t4 to automatically recover.<N1,Q,t3,t1> In the case of QNU, t3 is disturbed, but it and Q can self-repair under the correct input of the output soft error interception circuit. t1 and N1 are also recovered by the correct input of the node soft error interception circuit 1. Similarly,<N1,N2,t1,t3> and<N1,Q,t3,tq> It will also have the ability to recover.

[0056] Case 4: One fault occurs in the first type of node, and the other three faults occur in the second type of nodes, that is,<N1,t2,t3,t4> ,<Q,t2,t3,t4> ,<N1,t1,t2,t3> ,<Q,t1,t2,tq> We first consider<N1,t2,t3,t4> QNU case. Since node soft error interception circuits 2, 3, and 4 receive two fault inputs, the disturbances at t2, t3, and t4 will be automatically repaired. t1 is not affected because node soft error interception circuit 1 receives three fault inputs, and N1 is able to self-repair. Therefore, all nodes in the latch are corrected. Similarly, for<Q,t2,t3,t4> In the case of QNU, tq is not affected and the state of Q will be corrected. Then t2, t3, t4 and the associated N2, N3 and N4 will be repaired.<N1,t1,t2,t3> In the QNU case, t1 and N1 are temporarily disturbed but are repaired by the node soft error interception circuit 1. t2, t3 and correspondingly N2 and N3 are able to self-repair with less than three faults. Similarly,<Q,t1,t2,tq> The QNU will also have recovery capabilities.

[0057] Case 5: All four failures occur on the second type of nodes, i.e.<t1,t2,t3,t4> ,<t1,t2,t3,tq> We first consider<t1,t2,t3,t4> Although t1, t2, t3, and t4 are temporarily flipped, the number of input failures of node soft error interception circuits 1 to 4 does not exceed four. Therefore, t1, t2, t3, and t4 can automatically self-repair and correct QNU. Similarly, for<t1,t2,t3,tq> In the event of a fault, the faulty node will also self-repair, and the output soft error interception circuit, the outputs of the node soft error interception circuits 1 to 3 and other nodes will remain in the correct state.

[0058] Therefore, the four-node flip self-recovery latch can realize the comprehensive self-recovery of QNU.

[0059] Reference Figure 4 and Figure 5 , the input-output curve of the used Schmitt trigger shows the typical hysteresis behavior. When the input voltage exceeds the high threshold voltage, the output voltage transitions to a low level. At the same time, when the input voltage drops below the low threshold voltage, the output voltage becomes a logic "1". Under DC conditions, the high and low threshold voltages produce a hysteresis voltage greater than 300mV. For transient conditions, the hysteresis increases further due to device delays.

[0060] Reference Figure 6 , the simulation conditions are temperature 25℃, supply voltage 1.1V, and the lightning symbol represents the injected error. When Q is in state 0, the node group<N1,N2,N3,N4> ,<N1,N3,N5,N7> ,<N2,N4,N6,N8> ,<N1,N2,N3,Q> ,<N1,N2,N3,t4> ,<N1,N2,Q,t1> ,<N1,N2,N3,t1> ,<N1,N2,Q,tq> ,<N1,N2,t3,t4> ,<N1,Q,t1,t3> ,<N1,N2,t1,t3> ,<N1,Q,t3,tq> ,<N1,t2,t3,t4> ,<Q,t2,t3,t4> ,<N1,t1,t2,t3> ,<Q,t1,t2,tq> ,<t1,t2,t3,t4> ,<t1,t2,t3,tq> The QNU cases are rejected at 0.1, 0.25, 0.4, 0.55, 4.1, 4.25, 4.4, 4.55, 8.1, 8.25, 8.4, 8.55, 12.1, 12.25, 12.4, 12.55, 16.1, and 16.25 ns. Similarly, when Q is in state 1, the above node groups are evaluated at 2.1, 2.25, 2.4, 2.55, 6.1, 6.25, 6.4, 6.55, 10.1, 10.25, 10.4, 10.55, 14.1, 14.25, 14.4, 14.55, 18.1, and 18.25 ns. The results show that the output node Q and other nodes in the latch can self-recover from no more than 4 node error upsets.

[0061] It can be seen that the low-overhead four-node flip self-recovery latch of this embodiment can achieve that the latch result can remain unchanged or quickly recover to the correct value under the erroneous flip of any four nodes in the circuit. Specifically, it has the following beneficial effects: 1) The latch realizes a high radiation protection capability with four nodes that can be recovered; 2) Low area consumption can be achieved. 3) Low power consumption is achieved by using clock gating technology. 4) By introducing a high-speed path from D to Q, data latency is low.

[0062] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A four-node flip self-recovery latch, characterized in that: include: Output soft error interception module, node soft error interception module and transmission gate module; The output soft error interception module includes 8 input terminals and 1 output terminal, the 8 input terminals are N1, N2, N3, N4, N5, N6, N7, and N8, and the output terminal is Q; the output soft error interception module is used to ensure that the output value remains unchanged when a soft error causes a multi-node flip; The node soft error interception module comprises 8 node soft error interception circuits of the same structure, each of which comprises 8 input terminals and 1 output terminal; the inputs of the 8 node soft error interception circuits are Q and seven bits of N1, N2, N3, N4, N5, N6, N7, and N8, and the outputs are another bit of N1, N2, N3, N4, N5, N6, N7, and N8; the node soft error interception module is used to ensure that the respective output values ​​remain unchanged when a soft error causes multiple nodes to flip; The transmission gate module includes 9 input terminals and 9 output terminals, the 9 input terminals are all used to input data, and the output terminals are Q and N1, N2, N3, N4, N5, N6, N7, and N8 respectively; the transmission gate module is used to transmit data to N1, N2, N3, N4, N5, N6, N7, and N8 in data transmission mode.

2. The four-node flip self-recovery latch according to claim 1, characterized in that: The output soft error interception module includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first Schmitt inverter; The gates of the first PMOS tube, the first NMOS tube, the second PMOS tube, the second NMOS tube, the third PMOS tube, the third NMOS tube, the fourth PMOS tube, and the fourth NMOS tube are connected to the N1, N2, N3, N4, N5, N6, N7, and N8 terminals respectively; The source terminals of the first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are connected to the ground, and the drain terminals are commonly connected to a point, denoted as tq, and the point is connected to the drain terminals of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube; the source terminals of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are connected to the power supply voltage; tq is connected to the input terminal of the first Schmitt inverter, and the output terminal of the first Schmitt inverter serves as the output terminal of the output soft error interception module.

3. The four-node flip self-recovery latch according to claim 2, characterized in that: The node soft error interception circuit comprises: a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube and an inverter; The gates of the fifth PMOS tube, the fifth NMOS tube, the sixth PMOS tube, the sixth NMOS tube, the seventh PMOS tube, the seventh NMOS tube, the eighth PMOS tube, and the eighth NMOS tube of different node soft error interception circuits are respectively connected to Q and seven of N1, N2, N3, N4, N5, N6, N7, and N8; The source terminals of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are connected to the ground, and the drain terminals are commonly connected to a point, denoted as tn (n=1, 2, 3, 4, 5, 6, 7, 8), and the point is connected to the drain terminals of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube; the source terminals of the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube are connected to the power supply voltage; tn is connected to the input terminal of the inverter, and the output terminals of the inverters of different node soft error interception circuits are connected to another one of N1, N2, N3, N4, N5, N6, N7, and N8.

4. The four-node flip self-recovery latch according to claim 3, characterized in that: The transmission gate module includes a first transmission gate, a second transmission gate, a third transmission gate, a fourth soft transmission gate, a fifth transmission gate, a sixth transmission gate, a seventh transmission gate, an eighth transmission gate, and a ninth transmission gate; The input ends of the first transmission gate, the second transmission gate, the third transmission gate, the fourth transmission gate, the fifth transmission gate, the sixth transmission gate, the seventh transmission gate, the eighth transmission gate and the ninth transmission gate are used for inputting data, and the outputs are Q, N1, N2, N3, N4, N5, N6, N7 and N8 respectively.

5. The four-node flip self-recovery latch according to claim 4, characterized in that: The first Schmitt inverter and the inverter each include a control terminal for inputting a signal clock CLK; The first transmission gate, the second transmission gate, the third transmission gate, the fourth soft transmission gate, the fifth transmission gate, the sixth transmission gate, the seventh transmission gate, the eighth transmission gate, and the ninth transmission gate each include a control terminal for inputting a signal NCK; In data transmission mode, CLK is 0, NCK is 1, the transmission gate is turned on, and data is transmitted to N1, N2, N3, N4, N5, N6, N7, N8, and Q; In data hold mode, CLK is 0, NCK is 1, and the transmission gate is off.

6. The four-node flip self-recovery latch according to claim 3, characterized in that: The inverter is a Schmitt inverter.

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