Inversion type LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure with double-channel P-type drift region with groove-type gate and plane gate and preparation method of inversion type LDMOS structure
By introducing a double channel P-type drift zone structure of slot-type gate and planar gate into the LDMOS device, forming a thinner electronic inversion layer and independent conduction path, the contradiction between the on-resistance and the shutdown characteristics of traditional LDMOS devices is solved. The problem is that the conduction loss is reduced and the voltage resistance is improved.
Patent Information
- Application Number
- CN202411277473.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2024-12-17
AI Technical Summary
While traditional LDMOS devices increase the breakdown voltage, the on-resistance increases, resulting in a decrease in the shutdown characteristic of the device, making it difficult to reduce the on-destruction loss.
Adopt an inverse LDMOS structure with a double channel P-type drift region of the groove-type gate and a planar gate. By introducing an accumulation layer structure and a side gate structure, a thinner electronic inverse layer and independent conduction path are formed to improve conduction time. electron density and shutdown characteristics.
The on-resistance of the device is significantly reduced and the shutdown characteristic is improved, achieving a reduction in on-loss and an improvement in voltage resistance.
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Figure CN119153521A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a lateral double diffused metal oxide field effect transistor LDMOS, which can be used as a high-power device in electronic equipment and systems. Background Art
[0002] In modern electronic devices and systems, power semiconductor devices play a vital role and are widely used in power management, automotive electronics, industrial control, consumer electronics, communication equipment and renewable energy. With the continuous improvement of the performance and efficiency requirements of electronic devices, the performance of power semiconductor devices also needs to be continuously optimized to meet higher power density, lower on-resistance and better switching characteristics. Among them, the lateral double diffused metal oxide field effect transistor LDMOS has become an important component of power semiconductor devices due to its high integration, high frequency and low on-resistance. Since the withstand voltage of traditional LDMOS devices is mainly borne by the lightly doped drift region, in order to achieve high withstand voltage, it is necessary to reduce the doping concentration of the drift region of the device or increase the length of the drift region. However, both methods will increase the on-resistance of the device. Therefore, there is a contradictory relationship between the breakdown voltage and on-resistance of the device.
[0003] In order to improve the contradictory relationship between the device breakdown voltage and on-resistance, some researchers have proposed an inversion LDMOS device, which can significantly reduce the on-resistance of the device while ensuring a higher device withstand voltage, thus achieving a good compromise between the device breakdown voltage and on-resistance. However, the large number of free carriers present when the inversion device is turned on will significantly reduce the turn-off characteristics of the device, thereby affecting the switching frequency of the device.
[0004] Patent document with application number CN202310234418.8 discloses a separation groove lateral double diffusion power device and its manufacturing, such as Figure 1 As shown. From bottom to top, there are semiconductor substrate 1 and active area 2; the active area includes semiconductor drain area 3, semiconductor drift area 4 and semiconductor well area 8, and the semiconductor well area includes semiconductor source area 7 and semiconductor body contact area 6; separation groove 51 and gate groove 52 are etched in the drift area and gate area active area; a first dielectric layer 9 of high dielectric constant dielectric material is deposited in the separation groove and gate groove. Although this structure can reduce the on-resistance of the device while ensuring that the withstand voltage remains unchanged, because its trench gate dielectric is made of high dielectric constant material, the MIS capacitance formed by the gate electrode, trench dielectric and semiconductor material substrate increases, which reduces the turn-off characteristics of the device.
[0005] The patent document with application number US20210351296A1 discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a drift region on a substrate, a well region on the drift region, a source-end doped region in the well region, a drain-end doped region on the drift region, a channel region in the well region, and a gate structure between the source region and the drain region. The source doped region includes a first doped region and a second doped region of opposite doping types, and the channel region connects the first doped region and the drift region; the first doped region and the second doped region at the source end are at the same distance from the gate structure, which reduces the distance between the second doped region and the PN junction surface formed by the drift region and the well region, reduces the distance between the second doped region and the PN junction surface, reduces the risk of the parasitic NPN transistor being turned on by mistake, and thus improves the self-protection capability of the device. However, the structure does not optimize the on-resistance of the device, which is not conducive to reducing the conduction loss of the device. Summary of the invention
[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose an LDMOS structure with a trench gate and a planar gate double-channel P-type drift region inversion type and a preparation method thereof, so as to improve the turn-off characteristics of the device and reduce the conduction loss of the device while achieving low on-resistance.
[0007] To achieve the above objectives, the technical idea of the present invention is: by introducing an accumulation layer structure, when a forward voltage is applied to the planar gate, the surface of the P-type drift region is inverted to form a thinner electron inversion layer that can connect the channel and the N+ drain, thereby increasing the electron density during conduction and reducing the on-resistance of the device; by introducing a side gate structure, the device can form independent conduction paths in the N-type drift region and the P-type drift region respectively, thereby generating an additional electron disappearance path and improving the turn-off characteristics of the device.
[0008] According to the above ideas, the technical solutions of the present invention include the following:
[0009] 1. An LDMOS structure with a trench gate and a planar gate double channel P-type drift region inversion type, comprising: a P-type substrate, an N-type drift region, a P+ source region, a right N+ source region, a left N+ source region, a P-type base region, an N+ drain, an accumulation dielectric, a top silicon, a source electrode, a drain electrode and a substrate electrode, characterized in that:
[0010] The N-type drift region has a P-type drift region disposed thereon, and an N-type buffer layer is disposed on one side of the P-type drift region;
[0011] The P-type base region is located on the other side of the P-type drift, and a trench gate dielectric layer is provided on one side of the P-type base region, a heavily doped polysilicon layer is deposited inside the trench gate dielectric layer, and a trench gate is provided on the top of the trench gate dielectric layer;
[0012] The top silicon layer has a first P-type region and a second P-type region on both sides thereof, a planar gate is arranged above the first P-type region, and an N+ region is arranged on one side of the second P-type region.
[0013] Furthermore, the P-type substrate is made of any one of silicon, germanium, gallium arsenide, and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 The substrate electrode is located on the back of the P-type substrate; the N-type drift region is located on the upper part of the P-type substrate, and its doping concentration is 1×10 13 cm -3 ~1×10 16 cm -3 .
[0014] Furthermore, the accumulation dielectric layer is located above the P-type drift layer, and its doping concentration is 1×10 13 cm -3 ~1×10 16 cm -3 The accumulation dielectric layer is made of silicon dioxide or high-K material, and has a thickness of 0.05 to 0.2 microns.
[0015] Furthermore, the thickness of the top layer is 0.5 to 3 microns, and the doping concentration is 1×10 13 cm -3 ~7×10 15 cm -3 The doping concentration of the first P-type region, the second P-type region and the N+ region is 1×10 18 cm -3 ~1×10 20 cm -3 .
[0016] Furthermore, the P+ source region is located above the P-type base region, and its doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 , the doping concentration of the P-type base region is 1×10 16 cm -3 ~2×10 17 cm -3 The source electrode is located on the surface of the P-type base region, which covers the area between the right N+ source region and the left N+ source region; the right N+ source region and the left N+ source region are located on both sides of the P+ source region, and their doping concentrations are both 1×10 19 cm -3 ~1×10 20 cm -3 .
[0017] Furthermore, the trench gate dielectric has a lower boundary located below the P-type base region and the P-type drift region, and is made of silicon dioxide or high-K material with a thickness of 0.05 to 0.2 microns.
[0018] Furthermore, the N-type buffer layer is located below the N+ drain region, its lower boundary does not exceed the lower boundary of the N-type drift, and its doping concentration is 1×10 15 cm -3 ~2×10 16 cm -3 ; The doping concentration of the N+ drain region is 1×10 19 cm -3 ~1×10 20 cm -3 , the drain is located on the surface of the N+ drain region and the second P region.
[0019] 2. A method for preparing the above device, characterized in that it comprises the following steps:
[0020] 1) Select a P-type substrate and deposit metal on its back to form a substrate electrode;
[0021] 2) Using homoepitaxial growth technology, an N-type epitaxial layer is grown on the front side of a P-type substrate and doped to form an N-type drift;
[0022] 3) etching a groove in the upper end region of the N-type drift region, growing a groove gate dielectric material therein, and then etching back to retain a thickness of 0.05 to 0.2 microns to form a groove gate dielectric layer;
[0023] 4) depositing a polysilicon layer in the groove formed by the trench gate dielectric layer, and using chemical mechanical planarization technology to planarize the surface of the device;
[0024] 5) forming a P-type drift region, a P-type base region, a P+ source, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the N-type drift region by an ion implantation process;
[0025] 6) Select a top layer of 0.5 to 3 microns, grow accumulated oxidation on its lower surface, and then bond it to the device surface through a bonding process;
[0026] 7) forming a first P region, a second P region and an N+ region on the upper surface of the top silicon layer by an ion implantation process;
[0027] 8) Deposit metal in the area between the left N+ source region and the right N+ source region to form a source electrode; deposit metal on the surface of the polysilicon to form a trench gate, and deposit metal on the surface of the first P-type region to form a planar gate short-circuited with the trench gate; deposit metal on the surface of the N+ drain and the second P-type region to form a drain electrode, and complete the device manufacturing.
[0028] Compared with the prior art, the present invention has the following advantages:
[0029] 1. The present invention introduces a groove-type gate, which can generate an additional electron disappearance path when the device is turned off, thereby improving the turn-off characteristics of the device.
[0030] 2. The present invention introduces a P-type drift region, which allows electrons to be transported and recombine in the P-type drift region, accelerates the disappearance process of electrons, and further improves the turn-off characteristics of the device.
[0031] 3. The present invention introduces a planar gate above the first P region. When a forward voltage is applied to it, the device can be inverted on the surface of the P-type drift region to form a high-concentration, thin electron accumulation layer that can connect the channel and the N+ drain, thereby significantly reducing the on-resistance of the device.
[0032] 4. The present invention introduces an N-type buffer layer under the N+ drain region, which can receive the current controlled by the trench gate to the drain on the one hand, and can modulate the lateral and longitudinal electric fields of the device on the other hand, thereby improving the voltage resistance of the device.
[0033] The introduction of the above structure alleviates the contradictory relationship between the device's turn-off characteristics and on-resistance, and achieves a good compromise between the two. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 It is a structural diagram of the existing separation groove lateral double diffusion power device;
[0035] Figure 2 The structure diagram of the LDMOS with a trench gate and a planar gate double channel P-type drift region inversion type of the present invention;
[0036] Figure 3 The invention is made Figure 2 Schematic diagram of the device process;
[0037] Figure 4 A schematic diagram comparing the transfer characteristics of the LDMOS device of the present invention and the traditional LDMOS device;
[0038] Figure 5 It is a current density diagram of two conduction paths of the LDMOS device of the present invention when it is in the turned-on state;
[0039] Figure 6 The figure is a schematic diagram comparing the turn-off characteristics of the LDMOS device of the present invention and the traditional LDMOS device. DETAILED DESCRIPTION
[0040] The embodiments and effects of the present invention are further described in detail below in conjunction with the accompanying drawings.
[0041] Reference Figure 2The present invention has a trench gate and a planar gate double channel P-type drift region inversion LDMOS structure, including: a P+ source region 1, a right N+ source region 2, a left N+ source region 3, a P-type base region 4, a P-type drift region 5, an N+ drain region 6, an N-type buffer layer 7, an N-type drift region 8, a P-type substrate 9, a first P-type region 10, a top silicon layer 11, an N+ region 12, a second P-type region 13, a trench gate dielectric layer 14, an accumulation dielectric layer 15, a polysilicon layer 16, a trench gate 17, a source 18, a planar gate 19, a drain 20, and a substrate electrode 21, wherein:
[0042] The P-type substrate 9 has a doping concentration of 1×10 14 cm -3 ~5×10 14 cm -3 ;
[0043] The substrate electrode 21 is located on the back side of the P-type substrate 9;
[0044] The N-type drift region 8 is located above the P-type substrate 9 and has a doping concentration of 1×10 13 cm -3 ~1×10 16 cm -3 ;
[0045] The P-type drift region 5 is located above the N-type drift region 8 and has a doping concentration of ×10 13 cm -3 ~1×10 16 cm -3 ;
[0046] The accumulation dielectric layer 15 is located above the P-type drift region 5 and has a thickness of 0.05 to 0.2 microns;
[0047] The top silicon layer 11 is located above the accumulation dielectric layer 15 and has a thickness of 0.5 to 3 microns and a doping concentration of 1×10 13 cm -3 ~1×10 16 cm -3 ;
[0048] The first P-type region 10 and the second P-type region 13 are located on both sides of the top silicon 11, and the doping concentrations thereof are both 1×10 18 cm -3 ~1×10 20 cm -3 ;
[0049] The N+ region 12 is located on one side of the second P-type region 13 and has a doping concentration of 1×10 18 cm -3 ~1×10 20 cm-3 ;
[0050] The N-type buffer layer 7 is located on one side of the P-type drift region 5 and has a doping concentration of 1×10 15 cm -3 ~2×10 16 cm -3 ;
[0051] The P-type base region 4 is located on the other side of the P-type drift region 5, and its doping concentration is 1×10 16 cm -3 ~2×10 17 cm -3 ;
[0052] The trench gate dielectric layer 14 is located on one side of the P-type base region 4 and has a thickness of 0.5 to 3 microns;
[0053] The polysilicon layer 16 is deposited inside the groove formed by the groove gate dielectric layer 14;
[0054] The P+ source region 1 is located on one side of the trench gate dielectric layer 14 and has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 ;
[0055] The right N+ source region 2 and the left N+ source region 3 are located on both sides of the P+ source region 1, and their doping concentrations are both 1×10 19 cm -3 ~1×10 20 cm -3 ;
[0056] The N+ drain region 6 is located above the N-type buffer layer 7 and has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 ;
[0057] The source electrode 18 is located on the surface of the area between the right N+ source region 2 and the left N+ source region 3;
[0058] The groove gate 17 and the planar gate 19 are respectively located on the surface of the polysilicon layer 16 and above the first P-type region 10.
[0059] The drain electrode 20 is located on the surface of the second P-type region 13 and the N+ drain region 6 .
[0060] Reference Figure 3 The present invention provides a preparation Figure 2 Three embodiments of the device:
[0061] Embodiment 1: A P-type substrate made of silicon is selected, and a trench gate dielectric layer and an accumulation dielectric layer made of silicon dioxide with a thickness of 0.1 micron are manufactured thereon, and a double-channel P-type drift region inversion LDMOS structure with a top silicon thickness of 1 micron is manufactured.
[0062] Step 1: Use silicon material as the P-type substrate of the device, and deposit metal Al on its back to form a substrate electrode, such as Figure 3 (a).
[0063] Step 2, an N-type epitaxial layer is grown on the front side of the P-type substrate to form an N-type drift region, such as Figure 3 (b).
[0064] It is set to introduce H2 carrying SiCl4, SiHCl3, SiH4 or SiH2Cl2 silicon source gas into the reaction chamber; the reaction chamber temperature is 1150°C, and an N-type drift region is epitaxially grown on the front side of the P-type substrate.
[0065] Step 3, a groove is formed by etching at one end of the upper portion of the N-type drift region, and a groove gate dielectric made of silicon dioxide is grown inside the groove gate dielectric layer, and then the groove gate dielectric layer is formed by etching back to retain a thickness of 0.1 microns. Figure 3 (c).
[0066] Step 4, depositing a polysilicon layer in the groove formed by the trench gate dielectric layer, and using chemical mechanical planarization technology to planarize the surface of the polysilicon, such as Figure 3 (d).
[0067] Step 5, forming a P-type drift region, a P-type base region, a P+ source region, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the N-type drift region by an ion implantation process, as shown in FIG. Figure 3 (e).
[0068] 5.1) Boron ions are implanted on the surface of the N-type drift region to form a concentration of 1×10 15 cm -3 P-type drift region 5;
[0069] 5.2) Boron ions are implanted on one side of the P-type drift region to form a concentration of 1×10 16 cm -3 P-type base region 4;
[0070] 5.3) Boron ions are implanted into the surface of the P-type base region to form a concentration of 2×10 19 cm -3 P+ source region 1;
[0071] 5.4) Boron ions are implanted on both sides of the P+ source region to form a concentration of 2×10 19 cm -3The right N+ source 2 and the left N+ source region 3;
[0072] 5.5) Phosphorus ions are implanted on the other side of the P-type drift region to form a concentration of 1×10 16 cm -3 N-type buffer layer 7;
[0073] 5.6) Phosphorus ions are implanted on the surface of the N-type buffer layer to form a concentration of 2×10 19 cm -3 N+ drain region 6.
[0074] Step 6: Select a top silicon layer with a thickness of 1 micron, grow an oxide layer on its lower surface, and then bond it to the device surface through a bonding process, such as Figure 3 (f).
[0075] Step 7, forming a first P region, a second P region and an N+ region on the upper surface of the top silicon by an ion implantation process, such as Figure 3 (g).
[0076] 7.1) Boron ions are implanted on one side of the top silicon layer to form a concentration of 1×10 19 cm -3 The first P region 10;
[0077] 7.2) Boron ions are implanted on the other side of the top silicon layer to form a concentration of 1×10 19 cm -3 The second P zone 13;
[0078] 7.3) Phosphorus ions are implanted into one side of the second P region to form a concentration of 5×10 18 cm -3 N+ region 12.
[0079] Step 8, make electrodes, such as Figure 3 (h).
[0080] 8.1) Deposit metal in the area between the left N+ source region and the right N+ source region to form a source electrode;
[0081] 8.2) depositing metal Al on the surface of polysilicon to form a trench gate, and depositing metal Al on the surface of the first P-type region to form a planar gate short-circuited with the trench gate;
[0082] 8.3) Metal Al is deposited on the surface of the N+ drain region and the second P-type region to form a drain electrode, completing the device fabrication.
[0083] Embodiment 2: A P-type substrate made of germanium is selected, and a double-channel P-type drift region inversion LDMOS structure with a thickness of 0.07 microns and a trench gate dielectric layer and an accumulation dielectric made of high-K dielectric and a top silicon layer with a thickness of 1.5 microns is manufactured thereon.
[0084] Step 1: Use germanium material as the P-type substrate of the device, and deposit metal Ti on its back to form a substrate electrode, such as Figure 3 (a).
[0085] Step 2: grow an N-type epitaxial layer on the front side of the P-type substrate to form an N-type drift region, such as Figure 3 (b).
[0086] H2 carrying GeH4 germanium source gas is introduced into the reaction chamber by epitaxial technology; under the process condition of the reaction chamber temperature being 450° C., an N-type drift region is epitaxially grown on the front side of the P-type substrate.
[0087] Step 3: A groove is formed by etching at one end of the upper portion of the N-type drift region, and a high-K dielectric material is grown inside the groove. The groove is then etched back to retain a thickness of 0.07 microns to form a high-K dielectric layer. Figure 3 (c).
[0088] Step 4: deposit a polysilicon layer in the groove formed by the high-K dielectric layer, and use chemical mechanical planarization technology to planarize the surface of the polysilicon. Figure 3 (d).
[0089] Step 5: Form a P-type drift region, a P-type base region, a P+ source region, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the N-type drift region by an ion implantation process, as shown in FIG. Figure 3 (e).
[0090] Gallium ions are implanted into the surface of the N-type drift region to form a concentration of 2×10 15 cm -3 P-type drift region 5.
[0091] Gallium ions are injected into one side of the P-type drift region to form a concentration of 3×10 16 cm -3 P-type base region 4.
[0092] Gallium ions are implanted on the surface of the P-type base region to form a concentration of 5×10 19 cm -3 P+ source region 1.
[0093] Gallium ions are injected on both sides of the P+ source region to form a concentration of 5×10 19 cm -3 right N+ source 2 and left N+ source region 3.
[0094] Antimony ions are implanted on the other side of the P-type drift region to form a concentration of 8×10 15 cm -3 N-type buffer layer 7.
[0095] Antimony ions are implanted on the surface of the N-type buffer layer to form a concentration of 5×10 19 cm -3 N+ drain region 6.
[0096] Step 6: grow a 0.07 micron thick high-K dielectric accumulation dielectric layer on the lower surface of the 1.5 micron thick top silicon layer, and then bond it to the device surface through a bonding process, such as Figure 3 (f).
[0097] Step 7: Form a first P region, a second P region and an N+ region on the upper surface of the top silicon by ion implantation process, such as Figure 3 (g).
[0098] Gallium ions are implanted on one side of the top silicon layer to form a concentration of 2×10 19 cm -3 The first P region 10.
[0099] Gallium ions are implanted on the other side of the top silicon to form a concentration of 2×10 19 cm -3 The second P region 13.
[0100] Antimony ions are implanted into one side of the second P region to form a concentration of 7×10 18 cm -3 N+ region 12.
[0101] Step 8: Make electrodes, such as Figure 3 (h).
[0102] Metal Ti is deposited in the area between the left N+ source region and the right N+ source region to form a source electrode;
[0103] Depositing metal Ti on the surface of polysilicon to form a trench gate, and depositing metal Ti on the surface of the first P-type region to form a planar gate short-circuited with the trench gate;
[0104] Metal Ti is deposited on the surface of the N+ drain region and the second P-type region to form a drain electrode, completing the device manufacturing.
[0105] Embodiment 3: A P-type substrate made of silicon carbide is selected, and a trench gate dielectric layer and an accumulation dielectric layer made of silicon dioxide with a thickness of 0.05 microns are manufactured thereon, and a double-channel P-type drift region inversion LDMOS structure with a top silicon thickness of 1 micron is manufactured.
[0106] Step A, using silicon carbide material as the P-type substrate of the device, and depositing metal Al on its back to form a substrate electrode, such as Figure 3 (a).
[0107] Step B, epitaxially growing an N-type drift region. Figure 3 (b).
[0108] An N-type epitaxial layer is grown on the front side of a P-type substrate by epitaxial growth technology to form an N-type drift region. The epitaxial growth process conditions are as follows:
[0109] A mixed gas consisting of silicon source gas of H2 and SiH4 and carbon source gas of CH4 is introduced into the reaction chamber;
[0110] Set the reaction chamber temperature to 1600 °C.
[0111] Step C: forming a trench gate dielectric layer on the N-type drift region.
[0112] C1) etching a groove in an upper end region of the N-type drift region;
[0113] C2) growing a trench gate dielectric made of silicon dioxide inside the groove;
[0114] C3) etching back a trench gate dielectric layer with a thickness of 0.06 microns on the trench gate dielectric.
[0115] Step D, depositing a polysilicon layer on the surface of the trench gate dielectric layer, and using chemical mechanical planarization technology to planarize the surface of the polysilicon layer, such as Figure 3 (d).
[0116] Step E, forming a P-type drift region, a P-type base region, a P+ source region, a right N+ source region, a left N+ source region, an N-type buffer layer and an N+ drain region in the N-type drift region by an ion implantation process, such as Figure 3 (e).
[0117] E1) Aluminum ions are implanted on the surface of the N-type drift region to form a P-type drift region 5. The concentration of the aluminum ions is 9×10 14 cm -3 ;
[0118] E2) Aluminum ions are injected into one side of the P-type drift region to form a P-type base region 4. The concentration of the P-type base region is 5×10 16 cm -3 ;
[0119] E3) Aluminum ions are implanted on the surface of the P-type base region to form a P+ source region 1. The concentration of the P+ source region is 2×10 19 cm -3 ;
[0120] E4) Arsenic ions are implanted on both sides of the P+ source region to form a right N+ source 2 and a left N+ source region 3. The concentration of the right N+ source and the left N+ source region is 3×10 19 cm -3 ;
[0121] E5) Arsenic ions are implanted on the other side of the P-type drift region to form an N-type buffer layer 7, the concentration of which is 8×10 15 cm -3 ;
[0122] E6) Arsenic ions are implanted on the surface of the N-type buffer layer to form an N+ drain region 6, the concentration of which is 3×10 19 cm -3 .
[0123] Step F, select a top silicon layer with a thickness of 1 micron, grow a 0.06 micron thick accumulated oxide layer of silicon dioxide on its lower surface, and then bond it to the device surface through a bonding process, such as Figure 3 (f).
[0124] Step G, forming a first P region, a second P region and an N+ region on the upper surface of the top silicon by an ion implantation process, such as Figure 3 (g).
[0125] G1) Gallium ions are implanted on one side of the top silicon layer to form a first P region 10, the concentration of which is 4×10 19 cm -3 ;
[0126] G2) Gallium ions are implanted on the other side of the top silicon to form a second P region 13, and the concentration of the second P region is 4×10 19 cm -3 ;
[0127] G3) Antimony ions are implanted into one side of the second P region to form an N+ region 12, the concentration of which is 6×10 18 cm -3 .
[0128] Step H, making electrodes, such as Figure 3 (h).
[0129] Metal Al is deposited in the area between the left N+ source region and the right N+ source region to form a source electrode;
[0130] Depositing metal on the surface of polysilicon to form a trench gate, and depositing metal Al on the surface of the first P-type region to form a planar gate short-circuited with the trench gate;
[0131] Metal Al is deposited on the surface of the N+ drain region and the second P-type region to form a drain electrode, completing the device manufacturing.
[0132] The effect of the present invention can be further illustrated by the following simulation results:
[0133] 1. Simulation conditions
[0134] The software used for simulation is Sentaurus TCAD.
[0135] Set the device's withstand voltage level to 200V.
[0136] 2. Simulation content
[0137] Simulation 1: Under the above simulation conditions, the output characteristics of the device of Embodiment 1 of the present invention and the device of the traditional LDMOS are simulated respectively. The results are as follows: Figure 4 As shown. Figure 4 It can be seen that the specific on-resistance of the traditional LDMOS is 37.3mΩ·cm 2 , while the specific on-resistance of the present invention is 3.9mΩ·cm 2 , compared with the traditional LDMOS device, the present invention reduces 89.4%.
[0138] Simulation 2, under the above simulation conditions, simulates the current density of the two conduction paths of the device in the embodiment 1 of the present invention when it is in the conduction state. The results are as follows: Figure 5 As shown. Figure 5 It can be seen that the current density of the conduction path formed by the planar gate in the P-type drift region is 2×10 5 A / cm 2 , the current density of the conduction path controlled by the slot gate is 3×10 3 A / cm 2 , the current density difference between the two is within two orders of magnitude, indicating that the groove gate can serve as a good disappearing path for electrons, thereby improving the turn-off characteristics of the device.
[0139] Simulation 3: Under the above simulation conditions, the turn-off characteristics of the device in Embodiment 1 of the present invention and the traditional LDMOS are simulated respectively. The results are as follows: Figure 6 As shown. Figure 6 It can be seen that the turn-off time of the conventional LDMOS is 0.112 microseconds, while the turn-off time of the device of the present invention is 0.099 microseconds, and the turn-off characteristic of the device of the present invention is improved by 11.6%.
[0140] The above are only several preferred embodiments of the present invention. It should be pointed out that, after understanding the content and principle of the present invention, ordinary technicians in this technical field may make various modifications and changes in form and details without departing from the principle and structure of the present invention. For example, the LDMOS device in the present invention may be a P-type channel in addition to an N-type channel. However, these modifications and changes based on the concept of the present invention are still within the protection scope of the present invention.
Claims
1. An LDMOS structure with a trench gate and a planar gate double channel P-type drift region inversion type, comprising: P-type substrate (9), N-type drift region (8), P+ source region (1), right N+ source region (2), left N+ source region (3), P-type base region (4), N+ drain region (6), accumulation dielectric layer (15), top silicon (11), source (18), drain (20) and substrate electrode (21), characterized in that: The N-type drift region (8) has a P-type drift region (5) disposed thereon, forming a drift region structure in which N-type and P-type drift regions are vertically alternated, and an N-type buffer layer (7) is disposed on one side of the P-type drift region; The P-type base region (4) is located on the other side of the P-type drift region (5), and a trench gate dielectric layer (14) is provided on one side of the P-type base region, a heavily doped polysilicon layer (16) is deposited inside the trench gate dielectric layer (14), and a trench gate (17) is provided above the trench gate dielectric layer (14); The top silicon (11) has a first P-type region (10) and a second P-type region (13) on both sides thereof, a planar gate (19) is provided above the first P-type region, and an N+ region (12) is provided on one side of the second P-type region.
2. The LDMOS structure according to claim 1, characterized in that: The P-type substrate (9) is made of any one of silicon, germanium, gallium arsenide and silicon carbide, and its doping concentration is 1×10 14 cm -3 ~5×10 14 cm -3 , a substrate electrode (21) is located on the back side of the P-type substrate; The N-type drift region (8) is located on the upper part of the P-type substrate (9) and has a doping concentration of 1×10 13 cm -3 ~1×10 16 cm -3 .
3. The LDMOS structure according to claim 1, characterized in that: Above the P-type drift region (5) is an accumulation dielectric layer (15) having a doping concentration of 1×10 13 cm -3 ~1×10 16 cm -3 The accumulation dielectric layer is made of silicon dioxide or high-K material, and has a thickness of 0.05 to 0.2 microns.
4. The LDMOS structure according to claim 1, characterized in that: The thickness of the top silicon layer (11) is 0.5 to 3 micrometers, and the doping concentration is 1×10 13 cm -3 ~7×10 15 cm -3 . The doping concentrations of the first P-type region (10), the second P-type region (13) and the N+ region (12) are all 1×10 18 cm -3 ~1×10 20 cm -3 .
5. The LDMOS structure according to claim 1, characterized in that: The P+ source region (1) is located above the P-type base region (4) and has a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 , the doping concentration of the P-type base region (4) is 1×10 16 cm -3 ~2×10 17 cm -3 The source electrode (18) is located on the surface of the P-type base region (4), and covers the area between the right N+ source region (2) and the left N+ source region (3). The right N+ source region (2) and the left N+ source region (3) are located on both sides of the P+ source region (1), and their doping concentrations are both 1×10 19 cm -3 ~1×10 20 cm -3 .
6. The LDMOS structure according to claim 1, characterized in that: The groove gate dielectric layer (14) has a lower boundary located below the P-type base region (4) and the P-type drift region (5), is made of silicon dioxide or high-K material, and has a thickness of 0.05 to 0.2 micrometers.
7. The LDMOS structure according to claim 1, characterized in that: The N-type buffer layer (7) is located below the N+ drain region (6), its lower boundary does not exceed the lower boundary of the N-type drift region (8), and its doping concentration is 1×10 15 cm -3 ~2×10 16 cm -3 ; The doping concentration of the N+ drain region (6) is 1×10 19 cm -3 ~1×10 20 cm -3 The drain (20) is located on the surface of the N+ drain region and the second P region.
8. A method for preparing the device according to claim 1, characterized in that: The following steps are involved: 1) Selecting a P-type substrate (9) and depositing metal on the back side thereof to form a substrate electrode (21); 2) epitaxially growing an N-type epitaxial layer on the front side of the P-type substrate by homoepitaxial growth technology to form an N-type drift region (8); 3) etching a groove in an upper end region of the N-type drift region (8), growing a groove gate dielectric material therein, and then etching back to retain a thickness of 0.05 to 0.2 microns to form a groove gate dielectric layer (14); 4) depositing a polysilicon layer (16) in the groove formed by the groove gate dielectric layer (14), and flattening the surface of the device using a chemical mechanical flattening technique; 5) forming a P-type drift region (5), a P-type base region (4), a P+ source region (1), a right N+ source region (2), a left N+ source region (3), an N-type buffer layer (7) and an N+ drain region (6) in the N-type drift region (8) by an ion implantation process; 6) Selecting a top silicon layer (11) of 0.5 to 3 microns, growing an accumulated oxide layer (15) on its lower surface, and then bonding it to the device surface through a bonding process; 7) forming a first P region (10), a second P region (13) and an N+ region (12) on the upper surface of the top silicon layer (11) by an ion implantation process; 8) Depositing metal in the area between the left N+ source region (3) and the right N+ source region (2) to form a source electrode (18); depositing metal on the surface of the polysilicon (16) to form a trench gate (17); depositing metal on the surface of the first P-type region (10) to form a planar gate (19) short-circuited with the trench gate; depositing metal on the surface of the N+ drain region (6) and the second P-type region (13) to form a drain electrode (20), thereby completing device manufacturing.
9. The method according to claim 8, characterized in that: The homoepitaxial growth technology in step (2) has the following process conditions: Introduce H2 into the reaction chamber, which carries SiCl4, SiHCl3, SiH4 or SiH2Cl2 silicon source gas; The N-type drift region is epitaxially grown in a temperature range of 1150°C to 1200°C.
10. The method according to claim 8, characterized in that: The materials and concentrations of the ion implantations in the N-type region and the P-type region in the steps (5) and (7) are as follows: The implanted N-type ions are any one of phosphorus, arsenic and antimony; The implanted P-type ions are any one of boron, aluminum, and gallium; The right N+ source region (2), the left N+ source region (3) and the N+ drain region (6) are formed by injecting N-type ions, and the concentration of each of the N+ source regions is 1×10 19 cm -3 ~1×10 20 cm -3 ; The N-type buffer layer (7) formed by injecting N-type ions has a concentration of 1×10 15 cm -3 ~2×10 16 cm -3 ; The N+ region (12) formed by injecting N-type ions has a concentration of 1×10 18 cm -3 ~1×10 20 cm -3 ; The P-type drift region (5) formed by injecting P-type ions has a concentration of 1×10 13 cm -3 ~1×10 16 cm -3 ; The P-type base region (4) formed by injecting P-type ions has a concentration of 1×10 16 cm -3 ~2×10 17 cm -3 ; The first P region (10) and the second P region (13) are formed by injecting P-type ions, and the concentration of each of the P-type ions is 1×10 18 cm -3 ~1×10 20 cm -3 .