Lateral double diffused field effect transistor, manufacturing method, chip and circuit

Abstract

The present invention provides a lateral double diffused field effect transistor, a manufacturing method, a chip and a circuit, and relates to the field of semiconductors. The transistor includes: a substrate, a body region, a drift region, a source, a drain, and a substrate groove, wherein the substrate groove is a bowl-shaped configuration with a smooth bottom; a field plate oxide layer, formed in the substrate groove, and the thickness of the field plate oxide layer is less than the depth of the substrate groove; a gate oxide layer, formed on the upper surface of the substrate where the substrate groove is not formed between the source and the field plate oxide layer, and the groove wall surface where the substrate groove is close to the source and is not covered by the field plate oxide layer; a polysilicon layer, formed on the upper surface of the gate oxide layer, and covering part of the field plate oxide layer, the gate oxide layer and the polysilicon layer formed on the upper surface of the gate oxide layer are used together as a gate, and the field plate oxide layer and the polysilicon layer covering part of the field plate oxide layer are used together as a field plate. The present invention can improve the control ability of the gate over the channel, reduce the on-resistance, increase the breakdown voltage, and reduce the size of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a lateral double diffused field effect transistor, a lateral double diffused field effect transistor, a chip and a circuit. Background Art

[0002] Lateral Double-Diffused MOSFET (LDMOS) is a lateral power device with electrodes located on the device surface. It is easy to achieve monolithic integration with low-voltage signal circuits and other devices through internal connections. It also has the advantages of high voltage resistance, high gain, good linearity, high efficiency, and good broadband matching performance. It has been widely used in power integrated circuits, especially low-power and high-frequency circuits.

[0003] In the prior art, the gate of the lateral double diffused field effect transistor has a weak control capability over the channel, a high on-resistance, a slow switching speed and a low breakdown voltage. Summary of the invention

[0004] Aiming at the technical problems in the prior art that the gate of a lateral double diffused field effect transistor has weak control capability over a channel, high on-resistance, slow switching speed and low breakdown voltage, the present invention provides a lateral double diffused field effect transistor, a method for manufacturing the lateral double diffused field effect transistor, a chip and a circuit. The lateral double diffused field effect transistor can improve the control capability of the gate over the channel, reduce on-resistance, increase switching speed, reduce switching loss, increase breakdown voltage, reduce noise, and improve the reliability and life of the device.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a lateral double diffused field effect transistor, comprising: a substrate, a body region, a drift region, a source and a drain, the lateral double diffused field effect transistor also comprising: a substrate groove, the substrate groove is a bowl-shaped configuration with a smooth bottom; a field plate oxide layer, formed in the substrate groove, and the thickness of the field plate oxide layer is less than the depth of the substrate groove; a gate oxide layer, formed on the upper surface of the substrate where the substrate groove is not formed between the source and the field plate oxide layer, and on the groove wall surface of the substrate groove close to the source and not covered by the field plate oxide layer; wherein the body region extends from the gate oxide layer to an end of the substrate away from the field plate oxide layer; a polysilicon layer, formed on the upper surface of the gate oxide layer and covering a portion of the field plate oxide layer, the gate oxide layer and the polysilicon layer formed on the upper surface of the gate oxide layer together serve as a gate, and the field plate oxide layer and the polysilicon layer covering a portion of the field plate oxide layer together serve as a field plate.

[0006] Furthermore, the substrate groove is formed by sequentially utilizing a LOCOS process and a wet etching process.

[0007] Furthermore, the ratio of the depth of the substrate groove to the width of the substrate groove is between 1:10 and 1:5.

[0008] Furthermore, the lateral double diffused field effect transistor further includes: a substrate interface formed in the body region and arranged adjacent to the source, wherein the substrate interface and the source have different conductivity types.

[0009] Furthermore, the body region is arranged adjacent to the drift region.

[0010] Furthermore, the body region is arranged adjacent to the field plate oxide layer.

[0011] The second aspect of the present invention provides a method for manufacturing a lateral double diffused field effect transistor, which comprises: providing a substrate and forming a substrate groove on the substrate; wherein the substrate groove is a bowl-shaped configuration with a smooth bottom; forming a field plate oxide layer in the substrate groove; wherein the thickness of the field plate oxide layer is less than the depth of the substrate groove; forming a drift region, a gate oxide layer, a polysilicon layer and a body region; wherein the gate oxide layer is formed on the upper surface of the substrate where the substrate groove is not formed between a defined source and the field plate oxide layer, and on the surface of the groove wall of the substrate groove close to the defined source and not covered by the field plate oxide layer; the body region extends from the gate oxide layer to one end of the substrate away from the field plate oxide layer; the polysilicon layer is formed on the upper surface of the gate oxide layer and covers a portion of the field plate oxide layer, the polysilicon layer formed on the upper surface of the gate oxide layer and the gate oxide layer serve as a gate, and the polysilicon layer and the field plate oxide layer covering a portion of the field plate oxide layer serve as a field plate; and forming a source and a drain.

[0012] Furthermore, the forming of the substrate groove in the substrate includes: forming a LOCOS oxide layer in the substrate by using a LOCOS process; and removing the LOCOS oxide layer by using a wet etching solution to form the substrate groove.

[0013] Furthermore, the ratio of the depth of the substrate groove to the width of the substrate groove is between 1:10 and 1:5.

[0014] Further, forming a field plate oxide layer in the substrate groove comprises: depositing silicon dioxide in the substrate groove using a vapor deposition process to form the field plate oxide layer; wherein the thickness of the deposited silicon dioxide is less than the depth of the substrate groove.

[0015] Furthermore, the formation of the drift region, the gate oxide layer, the polysilicon layer and the body region includes: forming the drift region by ion implantation; forming a thermal oxide layer on the surface of the substrate by a thermal oxidation process, and using the thermal oxide layer between the defined source and the field plate oxide layer as the gate oxide layer; forming an initial polysilicon layer on the surface of the substrate by a vapor deposition process; removing part of the initial polysilicon layer by an etching process, and retaining only the initial polysilicon layer on the upper surface of the gate oxide layer and part of the upper surface of the field plate oxide layer as the polysilicon layer; and forming the body region by an ion implantation process using the polysilicon layer as a mask.

[0016] Furthermore, the method for manufacturing the lateral double diffused field effect transistor further includes: forming a substrate interface in the body region; wherein the substrate interface and the source have different conductivity types.

[0017] A third aspect of the present invention provides a chip, which includes the lateral double diffused field effect transistor described above.

[0018] A fourth aspect of the present invention provides a circuit comprising the lateral double diffused field effect transistor described above.

[0019] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0020] The lateral double diffused field effect transistor of the present invention comprises a substrate, a body region, a drift region, a source and a drain. A substrate groove is formed on the substrate, and the substrate groove is a bowl-shaped configuration with a smooth bottom. A field plate oxide layer is formed in the substrate groove, and the thickness of the field plate oxide layer is less than the depth of the substrate groove. The gate oxide layer is formed on the upper surface of the substrate where the substrate groove is not formed between the source and the field plate oxide layer, and on the groove wall surface where the substrate groove is close to the source and not covered by the field plate oxide layer. The body region extends from the gate oxide layer to one end of the substrate away from the field plate oxide layer. The polysilicon layer is formed on the upper surface of the gate oxide layer and covers part of the field plate oxide layer. The gate oxide layer and the polysilicon layer formed on the upper surface of the gate oxide layer serve as a gate together, and the field plate oxide layer and the polysilicon layer covering part of the field plate oxide layer serve as a field plate together. The gate is increased by the control area of ​​the upper surface of the substrate where the substrate groove is not formed between the original source and the field plate oxide layer, and the control area of ​​the groove wall surface where the substrate groove is close to the source and not covered by the field plate oxide layer. The groove wall of the substrate groove is downward and has a certain curvature. It can increase the control area of ​​the gate over the channel without increasing the width of the transistor, improve the control ability of the gate over the channel, reduce the on-resistance, increase the switching speed, reduce the switching loss, increase the breakdown voltage, reduce noise, reduce breakdown, improve the reliability and life of the device, reduce the device size, and reduce production costs.

[0021] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0023] Figure 1 A schematic structural diagram of a substrate formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of a structure of a window formed by a LOCOS oxide layer in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the structure of a LOCOS oxide layer formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0026] Figure 4 A schematic structural diagram of a substrate groove formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of the structure of a silicon dioxide layer formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of the structure of a field plate oxide layer formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0029] Figure 7 A schematic diagram of the structure of a drift region formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0030] Figure 8 A schematic diagram of the structure of a gate oxide layer and a polysilicon layer formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0031] Fig. 9 A schematic structural diagram of a body region formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0032] Fig.10 A schematic diagram of the structure of a lateral double diffused field effect transistor formed in the method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0033] Fig.11 The present invention provides a flowchart of a method for manufacturing a lateral double diffused field effect transistor according to an embodiment of the present invention.

[0034] Description of Reference Numerals

[0035] 1-substrate; 2-LOCOS oxide layer; 3-substrate groove; 4-field plate oxide layer; 5-drift region; 6-gate oxide layer; 7-polysilicon layer; 8-body region; 9-source; 10-drain; 11-substrate interface. DETAILED DESCRIPTION

[0036] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0037] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0038] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0039] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0040] Please refer to Fig.10 In a first aspect, an embodiment of the present invention provides a lateral double diffused field effect transistor, the lateral double diffused field effect transistor comprising: a substrate 1, a body region 8, a drift region 5, a source 9 and a drain 10, the lateral double diffused field effect transistor further comprising: a substrate groove 3, the substrate groove 3 being a bowl-shaped configuration with a smooth bottom; a field plate oxide layer 4 formed in the substrate groove 3, and the thickness of the field plate oxide layer 4 is less than the depth of the substrate groove 3; a gate oxide layer 6 formed between the source 9 and the field plate oxide layer 4 without forming the substrate The upper surface of the substrate 1 of the groove 3, and the groove wall surface of the substrate groove 3 close to the source 9 and not covered by the field plate oxide layer 4; wherein the body region 8 extends from the gate oxide layer 6 to an end of the substrate 1 away from the field plate oxide layer 4; the polysilicon layer 7 is formed on the upper surface of the gate oxide layer 6 and covers a portion of the field plate oxide layer 4, the gate oxide layer 6 and the polysilicon layer 7 formed on the upper surface of the gate oxide layer 6 are used together as a gate, and the field plate oxide layer 4 and the polysilicon layer 7 covering a portion of the field plate oxide layer 4 are used together as a field plate.

[0041] Specifically, in an embodiment of the present invention, a lateral double diffused field effect transistor includes a substrate 1, a body region 8 and a drift region 5 are formed in the substrate 1, a source 9 is formed in the body region 8, a drain 10 is formed in the drift region 5, and a substrate groove 3 is formed on the surface of the substrate 1, and the substrate groove 3 is a bowl-shaped configuration with a smooth bottom. The smooth bottom configuration can reduce the formation of sharp corners at the bottom of the field plate oxide layer 4 and reduce breakdown. A field plate oxide layer 4 is formed in the substrate groove 3, and the thickness of the field plate oxide layer 4 is less than the depth of the substrate groove 3. A gate oxide layer 6 is formed on the upper surface of the substrate 1 where the substrate groove 3 is not formed between the source 9 and the field plate oxide layer 4, and on the groove wall surface of the substrate groove 3 close to the source 9 and not covered by the field plate oxide layer 4. The body region 8 extends from the gate oxide layer 6 to an end of the substrate 1 away from the field plate oxide layer 4. A polysilicon layer 7 is formed on the upper surface of the gate oxide layer 6 and covers part of the field plate oxide layer 4. The gate oxide layer 6 and the polysilicon layer 7 formed on the upper surface of the gate oxide layer 6 serve as the gate together, and the field plate oxide layer 4 and the polysilicon layer 7 covering a portion of the field plate oxide layer 4 serve as the field plate together. The gate is formed by the control area (such as the control area) on the upper surface of the substrate 1 where the substrate groove 3 is not formed between the original source 9 and the field plate oxide layer 4. Fig.10 As shown by the dotted double arrows, a control area of ​​the groove wall surface of the substrate groove 3 close to the source 9 and not covered by the field plate oxide layer 4 is added (as shown in FIG. Fig.10 The groove wall of the substrate groove is downward and has a certain curvature, which can increase the control area of ​​the gate to the channel without increasing the lateral width of the transistor, improve the control ability of the gate to the channel, and achieve a higher drain current at a lower gate voltage, thereby reducing the on-resistance, increasing the switching speed, reducing the switching loss, and increasing the breakdown voltage. The improved gate control ability can reduce the noise of the transistor during the switching process and reduce the stress of the transistor during the switching process, thereby improving its reliability and life. Under the requirement of the same on-resistance, the device area is reduced, which is convenient for integration with other devices and reduces the production cost.

[0042] The lateral double diffused field effect transistor provided by the present invention can increase the control area of ​​the gate to the channel, improve the control ability of the gate to the channel, reduce the on-resistance, increase the switching speed, reduce the switching loss, reduce the breakdown, increase the breakdown voltage, reduce the noise, improve the reliability and life of the device, reduce the device size, and reduce the production cost.

[0043] Furthermore, the substrate groove 3 is formed by sequentially utilizing a LOCOS process and a wet etching process.

[0044] Specifically, in the embodiment of the present invention, the substrate groove 3 first uses the LOCOS process to form a LOCOS oxide layer, and then uses the wet etching process to remove the LOCOS oxide layer to form the substrate groove 3. In this way, the bottom of the substrate groove 3 formed by the LOCOS process is a smooth configuration, which can reduce the sharp corners at the bottom of the field plate, reduce the electric field concentration at the sharp corners, and reduce breakdown. In addition, the field plate oxide layer 4 formed by the vapor deposition process after the LOCOS oxide layer is removed by wet etching will not protrude from the surface of the substrate 1, so the parasitic capacitance on the surface of the substrate 1 can be reduced, the response speed and switching performance of the device can be improved, the stress concentration on the substrate 1 can be reduced, and the risk of increasing cracks and fractures can be reduced. In addition, the vapor deposition process can accurately control the thickness of the field plate oxide layer 4.

[0045] Furthermore, the ratio of the depth of the substrate groove 3 to the width of the substrate groove 3 is between 1:10 and 1:5.

[0046] Specifically, in the embodiment of the present invention, the ratio of the longitudinal depth of the substrate groove 3 to the lateral width of the substrate groove 3 is between 1:10 and 1:5. The larger the depth-to-width ratio of the substrate groove 3, the more vertical the angle of the sidewall of the substrate groove 3 will be. Under the same area, the distance of the gate oxide layer 6 in the vertical direction can be further increased, thereby improving the control capability of the gate oxide layer 6 over the channel. If the depth-to-width ratio of the substrate groove 3 is greater than 1:5, the difficulty of wet etching will increase. If the depth-to-width ratio of the substrate groove 3 is less than 1:10, the breakdown voltage will decrease.

[0047] Furthermore, the lateral double diffused field effect transistor further includes: a substrate interface 11 formed in the body region 8 and disposed adjacent to the source 9 , wherein the substrate interface 11 and the source 9 have different conductivity types.

[0048] Specifically, in the embodiment of the present invention, a substrate interface 11 is formed in the body region 8, and the substrate interface 11 has a different conductivity type from the source 9. The substrate interface 11 can absorb carriers flowing from the drift region 5 into the body region 8 when the transistor is turned on, reduce the carrier aggregation in the body region 8, reduce the parasitic triode conduction in the lateral double diffused field effect transistor, and improve the breakdown voltage of the lateral double diffused field effect transistor. Further, the substrate interface 11 is arranged adjacent to the source 9. The substrate interface 11 can improve the adsorption efficiency of carriers in the body region 8, and further improve the breakdown voltage of the lateral double diffused field effect transistor.

[0049] Furthermore, the body region 8 is disposed adjacent to the drift region 5 .

[0050] Specifically, in the embodiment of the present invention, the body region 8 is disposed adjacent to the drift region 5 , so that the on-resistance can be reduced while the breakdown voltage is guaranteed, the fabrication of the gate oxide layer 6 and the body region 8 is facilitated, and the lateral size of the device can be reduced.

[0051] Furthermore, the body region 8 is disposed adjacent to the field plate oxide layer 4 .

[0052] Specifically, in the embodiment of the present invention, the body region 8 is arranged adjacent to the field plate oxide layer 4, so that the gate oxide layer 6 can extend from the source 9 to the field plate oxide layer 4, increasing the length of the gate oxide layer 6 and further improving the gate's control over the channel.

[0053] Please refer to Fig.11 The second aspect of the present invention provides a method for manufacturing a lateral double diffused field effect transistor, the method comprising: S101: providing a substrate 1, and forming a substrate groove 3 on the substrate 1; wherein the substrate groove 3 is a bowl-shaped configuration with a smooth bottom; S102: forming a field plate oxide layer 4 in the substrate groove 3; wherein the thickness of the field plate oxide layer 4 is less than the depth of the substrate groove 3; S103: forming a drift region 5, a gate oxide layer 6, a polysilicon layer 7 and a body region 8; wherein the gate oxide layer 6 is formed between a defined source 9 and the field plate oxide layer; The upper surface of the substrate 1 where the substrate groove 3 is not formed between the layers 4, and the groove wall surface of the substrate groove 3 close to the defined source 9 and not covered by the field plate oxide layer 4; the body region 8 extends from the gate oxide layer 6 to an end of the substrate 1 away from the field plate oxide layer 4; the polysilicon layer 7 is formed on the upper surface of the gate oxide layer 6 and covers a portion of the field plate oxide layer 4, the polysilicon layer 7 formed on the upper surface of the gate oxide layer 6 and the gate oxide layer 6 serve as a gate, and the polysilicon layer 7 covering a portion of the field plate oxide layer 4 and the field plate oxide layer 4 serve as a field plate; S104: forming a source 9 and a drain 10.

[0054] Specifically, step S101 is first performed: providing a substrate 1 and forming a substrate groove 3 on the substrate 1; wherein the substrate groove 3 is a bowl-shaped configuration with a smooth bottom.

[0055] Furthermore, the forming of the substrate groove 3 on the substrate 1 includes: forming a LOCOS oxide layer 2 on the substrate 1 by using a LOCOS process; and removing the LOCOS oxide layer 2 by using a wet etching solution to form the substrate groove 3 .

[0056] Furthermore, the ratio of the depth of the substrate groove to the width of the substrate groove is between 1:10 and 1:5.

[0057] Specifically, in the embodiment of the present invention, first provide Figure 1The substrate 1 shown is one of a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, and a germanium-on-insulator substrate. The provided lateral double diffused field effect transistor can be an N-type lateral double diffused field effect transistor or a P-type lateral double diffused field effect transistor. When the lateral double diffused field effect transistor is an N-type lateral double diffused field effect transistor, the first doping type is P-type and the second doping type is N-type; when the lateral double diffused field effect transistor is a P-type lateral double diffused field effect transistor, the first doping type is N-type and the second doping type is P-type. The present invention does not limit this. The following text embodiment only takes the N-type lateral double diffused field effect transistor as an example for explanation.

[0058] A thin silicon dioxide layer is first deposited on a first doping type (P-type) substrate 1, and then a silicon nitride layer is deposited. A photoresist is formed on the silicon nitride layer, the photoresist is exposed and developed, an etching window is formed in the photoresist, and the silicon nitride layer and the silicon dioxide layer are etched in sequence using the etching window. Figure 2 The etching window shown in the figure exposes part of the substrate 1. The substrate 1 is placed in a high-temperature furnace and heated to a certain temperature (usually between 900°C and 1100°C) in an oxygen or oxygen-containing atmosphere, so that the exposed part of the substrate 1 reacts with oxygen to form a Figure 3 The LOCOS oxide layer 2 is removed by an acid etching solution to form a Figure 4 The substrate groove 3 is shown. The depth of the substrate groove 3 is greater than the designed thickness of the field plate oxide layer 4.

[0059] The aspect ratio of the substrate groove 3 is between 1:10 and 1:5, so that the sidewall angle of the substrate groove 3 is more vertical, and the distance of the gate oxide layer 6 in the vertical direction can be further increased under the same area, thereby improving the control ability of the gate oxide layer 6 over the channel. If the aspect ratio of the substrate groove 3 is greater than 1:5, the difficulty of wet etching will increase, and if the aspect ratio of the substrate groove 3 is less than 1:10, the breakdown voltage will decrease.

[0060] Then, step S102 is performed: forming a field plate oxide layer 4 in the substrate groove 3 ; wherein the thickness of the field plate oxide layer 4 is smaller than the depth of the substrate groove 3 .

[0061] Further, forming the field plate oxide layer 4 in the substrate groove 3 includes: depositing silicon dioxide in the substrate groove 3 using a vapor deposition process to form the field plate oxide layer 4; wherein the thickness of the deposited silicon dioxide is less than the depth of the substrate groove 3.

[0062] Specifically, in the embodiment of the present invention, Figure 5As shown, a silicon dioxide layer is deposited on the surface of the substrate 1 by a vapor deposition process. The thickness of the deposited silicon dioxide is less than the depth of the substrate groove 3, and the silicon oxide fills the bottom of the substrate groove 3. Then, chemical mechanical polishing is performed to remove the silicon dioxide on the surface of the silicon nitride, and the silicon nitride layer and the thin silicon dioxide layer are removed to form a Figure 6 The field plate oxide layer 4 is shown.

[0063] Then, step S103 is performed: a drift region 5, a gate oxide layer 6, a polysilicon layer 7 and a body region 8 are formed; wherein the gate oxide layer 6 is formed on the upper surface of the substrate 1 between the defined source 9 and the field plate oxide layer 4 where the substrate groove 3 is not formed, and on the groove wall surface of the substrate groove 3 close to the defined source 9 and not covered by the field plate oxide layer 4; the body region 8 extends from the gate oxide layer 6 to an end of the substrate 1 away from the field plate oxide layer 4; the polysilicon layer 7 is formed on the upper surface of the gate oxide layer 6 and covers a portion of the field plate oxide layer 4, the polysilicon layer 7 formed on the upper surface of the gate oxide layer 6 and the gate oxide layer 6 serve as a gate, and the polysilicon layer 7 and the field plate oxide layer 4 covering a portion of the field plate oxide layer 4 serve as a field plate.

[0064] Furthermore, the formation of the drift region 5, the gate oxide layer 6, the polysilicon layer 7 and the body region 8 includes: forming the drift region 5 by ion implantation; forming a thermal oxide layer on the surface of the substrate 1 by a thermal oxidation process, and using the thermal oxide layer between the defined source 9 and the field plate oxide layer 4 as the gate oxide layer 6; forming an initial polysilicon layer 7 on the surface of the substrate 1 by a vapor deposition process; removing part of the initial polysilicon layer 7 by an etching process, and retaining only the initial polysilicon layer 7 on the upper surface of the gate oxide layer 6 and part of the upper surface of the field plate oxide layer 4 as the polysilicon layer 7; using the polysilicon layer 7 as a mask, forming the body region 8 by an ion implantation process.

[0065] Specifically, in the embodiment of the present invention, a second doping type (N-type) ion implantation process is performed on the substrate 1 to form Figure 7 In the drift region 5 shown, the field plate oxide layer 4 is formed in the drift region 5, and the drift region 5 extends from the junction of the field plate oxide layer 4 and the defined gate oxide layer 6 to a position away from the defined gate oxide layer 6. Figure 8 As shown, a thermal oxidation process is then used to form a thermal oxide layer on the surface of the substrate 1, and the thermal oxide layer between the defined source 9 and the field plate oxide layer 4 is used as the gate oxide layer 6. An initial polysilicon layer is formed on the surface of the substrate 1 by a vapor deposition process, and a portion of the initial polysilicon layer is removed by an etching process, leaving only the initial polysilicon layer on the upper surface of the gate oxide layer 6 and a portion of the upper surface of the field plate oxide layer 4 as the polysilicon layer 7. The polysilicon layer 7 is used as a mask, and a P-type ion implantation is performed to form a Fig. 9 Body region 8 is shown.

[0066] Finally, step S104 is performed: forming the source electrode 9 and the drain electrode 10 .

[0067] Furthermore, the lateral double diffused field effect transistor manufacturing method further includes: forming a substrate interface 11 in the body region 8; wherein the substrate interface 11 and the source 9 have different conductivity types.

[0068] Specifically, in the embodiment of the present invention, a photoresist is formed on the surface of the substrate 1, and the photoresist is exposed and developed to form an ion implantation window. N-type ions are implanted into the body region 8 and the drift region 5 through the ion implantation window, and the photoresist is removed. A photoresist is formed again, and the photoresist is exposed and developed to form an ion implantation window. P-type ions are implanted into the body region 8 adjacent to the defined source 9 through the ion implantation window. The photoresist is removed, and annealing is performed to form a structure as shown in FIG. Fig.10 The source 9, drain 10 and substrate interface 11 are shown.

[0069] A third aspect of the present invention provides a chip, which includes the lateral double diffused field effect transistor described above.

[0070] A fourth aspect of the present invention provides a circuit comprising the lateral double diffused field effect transistor described above.

[0071] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0072] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0073] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A lateral double diffused field effect transistor, comprising: A substrate, a body region, a drift region, a source and a drain, wherein the lateral double diffused field effect transistor further comprises: A substrate groove, wherein the substrate groove is a bowl-shaped configuration with a smooth bottom; A field plate oxide layer is formed in the substrate groove, and the thickness of the field plate oxide layer is less than the depth of the substrate groove; A gate oxide layer is formed on the upper surface of the substrate where the substrate groove is not formed between the source and the field plate oxide layer, and on the groove wall surface of the substrate groove close to the source and not covered by the field plate oxide layer; wherein the body region extends from the gate oxide layer to an end of the substrate away from the field plate oxide layer; A polysilicon layer is formed on the upper surface of the gate oxide layer and covers a portion of the field plate oxide layer. The gate oxide layer and the polysilicon layer formed on the upper surface of the gate oxide layer serve together as a gate, and the field plate oxide layer and the polysilicon layer covering a portion of the field plate oxide layer serve together as a field plate.

2. The lateral double diffused field effect transistor according to claim 1, characterized in that: The substrate groove is formed by sequentially utilizing a LOCOS process and a wet etching process.

3. The lateral double diffused field effect transistor according to claim 1, characterized in that: The ratio of the depth of the substrate groove to the width of the substrate groove is between 1:10 and 1:

5.

4. The lateral double diffused field effect transistor according to claim 1, characterized in that: The lateral double diffused field effect transistor further includes: a substrate interface formed in the body region and disposed adjacent to the source, wherein the substrate interface and the source have different conductivity types.

5. The lateral double diffused field effect transistor according to claim 1, characterized in that: The body region is disposed adjacent to the drift region.

6. The lateral double diffused field effect transistor according to claim 1, characterized in that: The body region is disposed adjacent to the field plate oxide layer.

7. A method for manufacturing a lateral double diffused field effect transistor, characterized in that: The method for manufacturing a lateral double diffused field effect transistor comprises: Providing a substrate, and forming a substrate groove on the substrate; wherein the substrate groove is a bowl-shaped configuration with a smooth bottom; Forming a field plate oxide layer in the substrate groove; wherein the thickness of the field plate oxide layer is less than the depth of the substrate groove; A drift region, a gate oxide layer, a polysilicon layer and a body region are formed; wherein the gate oxide layer is formed on the upper surface of the substrate where the substrate groove is not formed between the delineated source and the field plate oxide layer, and on the groove wall surface of the substrate groove close to the delineated source and not covered by the field plate oxide layer; the body region extends from the gate oxide layer to an end of the substrate away from the field plate oxide layer; the polysilicon layer is formed on the upper surface of the gate oxide layer and covers a portion of the field plate oxide layer, the polysilicon layer formed on the upper surface of the gate oxide layer and the gate oxide layer serve as a gate, and the polysilicon layer and the field plate oxide layer covering a portion of the field plate oxide layer serve as a field plate; A source and a drain are formed.

8. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The forming of a substrate groove in the substrate comprises: A LOCOS oxide layer is formed on the substrate using a LOCOS process; The LOCOS oxide layer is removed by using a wet etching solution to form the substrate groove.

9. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The ratio of the depth of the substrate groove to the width of the substrate groove is between 1:10 and 1:

5.

10. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The forming of a field plate oxide layer in the substrate groove comprises: The field plate oxide layer is formed by depositing silicon dioxide in the substrate groove using a vapor deposition process; wherein the thickness of the deposited silicon dioxide is less than the depth of the substrate groove.

11. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The forming of the drift region, the gate oxide layer, the polysilicon layer and the body region comprises: forming the drift region by ion implantation; Forming a thermal oxide layer on the surface of the substrate by a thermal oxidation process, and using the thermal oxide layer between the defined source electrode and the field plate oxide layer as the gate oxide layer; forming an initial polysilicon layer on the surface of the substrate by a vapor deposition process; Removing part of the initial polysilicon layer by etching process, and retaining only the initial polysilicon layer on the upper surface of the gate oxide layer and part of the upper surface of the field plate oxide layer as the polysilicon layer; The body region is formed by an ion implantation process using the polysilicon layer as a mask.

12. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The method for manufacturing the lateral double diffused field effect transistor also includes: A substrate interface is formed in the body region; wherein the substrate interface and the source electrode have different conductivity types.

13. A chip, characterized in that: The chip comprises the lateral double diffused field effect transistor according to any one of claims 1 to 6.

14. A circuit, characterized in that: The circuit comprises the lateral double diffused field effect transistor according to any one of claims 1-6.

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