Printed circuit board

Abstract

The invention provides a printed circuit board. A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on an upper surface of the insulating layer; a second pad disposed on a lower surface of the insulating layer; a first device mounted on the first pad; a second device mounted on the second pad; a first molding layer disposed on the insulating layer and molding the first device; and a second molding layer disposed on a lower surface of the insulating layer and molding a second device. The lower surface of the second molding layer is positioned on the same plane as the lower surface of the second device.

Description

[0001] This application is a divisional application of a patent application with application number 202080067239.4 (PCT / KR2020 / 011292) filed on March 25, 2022, application date on August 25, 2020, and titled “Printed Circuit Board”. Technical Field

[0002] Embodiments relate to a printed circuit board and a package substrate including the printed circuit board. Background Art

[0003] Generally, a package substrate has a structure in which a first substrate to which a memory chip is attached and a second substrate to which a processor chip is attached are connected as one body.

[0004] The package substrate has advantages in that the mounting area of ​​the chips can be reduced by manufacturing a processor chip and a memory chip in one package, and high-speed signal transmission can be achieved through short circuiting.

[0005] Due to these advantages, the package substrate as described above is widely used in mobile devices and the like.

[0006] Figure 1 is a cross-sectional view showing a package substrate according to the related art.

[0007] refer to Figure 1 The package substrate includes a first substrate 20 and a second substrate 30 attached to the first substrate 20 .

[0008] In addition, the first substrate 20 includes: a first insulating layer 1; a circuit pattern 2, which is formed on at least one surface of the first insulating layer 1; a second insulating layer 2, which is formed on the first insulating layer 1; a third insulating layer 3, which is formed below the first insulating layer 1; a circuit pattern 4, which is formed on at least one surface of the first insulating layer 1; a conductive via 5, which is formed in at least one of the first insulating layer 1, the second insulating layer 2 and the second insulating layer 3; a pad 6, which is formed on the upper surface of the second insulating layer 2; a plurality of adhesives 7 on the pad 6; a memory chip 8, which is formed on at least one of the plurality of adhesives 7; a first protective layer 10, which is formed on the second insulating layer 2 and exposes a portion of the upper surface of the pad 6; and a second protective layer 9, which is formed on the protective layer 10 to cover the memory chip 8.

[0009] In addition, the second substrate 30 includes: a fourth insulating layer 11; a circuit pattern 12, which is formed on at least one surface of the fourth insulating layer 11; a pad 13, which is formed on at least one surface of the fourth insulating layer 11; a conductive via 14, which is formed in the fourth insulating layer 11; a processor chip 15, which is formed on the fourth insulating layer 11; and a connecting member (S), which connects the processor chip 15 and the pad 13.

[0010] like Figure 1 The package substrate according to the prior art shown is a schematic diagram of a package on package (PoP) to which TMV (Through Mold Via) technology (with laser technology applied) is applied.

[0011] In the TMV technology, as described above, a conductive via connected to a pad is formed by a laser process after molding the first substrate 20 , and thus a solder ball (adhesive) is printed in the conductive via.

[0012] Then, the second substrate 30 is attached to the first substrate 20 through the printed solder balls 7 .

[0013] However, the prior art as described above is a method of connecting the first substrate and the second substrate using the solder balls 7, and thus there is a problem in that there is a limitation in responding to a fine pitch.

[0014] Furthermore, because the related art uses the solder ball 7 as described above, there is a high possibility that problems such as solder cracks, bridges, and solder collapse may occur. Summary of the invention

[0015] Technical issues

[0016] The embodiment provides a printed circuit board having a novel structure and a package substrate including the printed circuit board.

[0017] Furthermore, the embodiment provides a printed circuit board capable of easily responding to a fine pitch and a package substrate including the printed circuit board.

[0018] In addition, the embodiment provides a printed circuit board capable of minimizing the occurrence of warpage by maintaining the balance of an upper portion and a lower portion, and a package substrate including the same.

[0019] Furthermore, the embodiment provides a printed circuit board capable of improving reliability of a post bump and a package substrate including the printed circuit board.

[0020] The technical problems to be achieved in the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned in the following description will be clearly understood by a person skilled in the art in the embodiments proposed from the following description.

[0021] Technical Solution

[0022] According to an embodiment, a printed circuit board includes: an insulating layer; a plurality of first pads, which are arranged on an upper surface of the insulating layer; a plurality of second pads, which are arranged on a lower surface of the insulating layer; a first device, which is mounted on any one of the plurality of first pads; a second device, which is mounted on any one of the plurality of second pads; a first molding layer, which is arranged on the insulating layer and molds the first device; a second molding layer, which is arranged on a lower surface of the insulating layer and molds the second device; a first columnar bump, which is arranged on any one of the plurality of second pads; and a second columnar bump, which is arranged on any one of the plurality of first pads.

[0023] In addition, the first pillar bump and the second pillar bump are symmetrical with respect to the insulating layer.

[0024] In addition, a lower surface of the second mold layer is positioned on the same plane as a lower surface of the second device, and an upper surface of the first mold layer is positioned higher than an upper surface of the first device.

[0025] In addition, the printed circuit board further includes: a first protection layer disposed between an upper surface of the insulating layer and the first molding layer; and a second protection layer disposed between a lower surface of the insulating layer and the second molding layer.

[0026] Furthermore, a lower surface of the first pillar bump is positioned higher than a lower surface of the second mold layer, and an upper surface of the second pillar bump is positioned lower than an upper surface of the first mold layer.

[0027] Furthermore, an upper surface of the first pillar bump is in direct contact with a lower surface of the second pad, and a lower surface of the second pillar bump is in direct contact with an upper surface of the first pad.

[0028] In addition, the entire area of ​​the side surface of the first columnar bump includes a first portion directly contacting the second protective layer and a second portion directly contacting the second mold layer, and the entire area of ​​the side surface includes a third portion directly contacting the first protective layer and a fourth portion directly contacting the first mold layer.

[0029] Furthermore, the entire area of ​​the side surface of the first pillar bump is in direct contact with the second mold layer, and the entire area of ​​the side surface of the second pillar bump is in direct contact with the first mold layer.

[0030] In addition, the printed circuit board further includes: a first seed layer, which is arranged between the lower surface of the insulating layer and the second pad; and a second seed layer, which is arranged between the upper surface of the insulating layer and the first pad, wherein the first columnar bump is an electroplating layer formed using the first seed layer, and the second columnar bump is an electroplating layer formed using the second seed layer.

[0031] In addition, the first seed layer includes a first region arranged between the lower surface of the insulating layer and the second pad, and a second region extending from the first region and arranged between the lower surface of the insulating layer and the second protective layer, wherein the second seed layer includes a third region arranged between the upper surface of the insulating layer and the first pad, and a fourth region extending from the third region and arranged between the upper surface of the insulating layer and the first protective layer.

[0032] In addition, the first seed layer includes a first region arranged between the lower surface of the insulating layer and the second pad, and a second region spaced apart from the first region and arranged between the lower surface of the insulating layer and the second protective layer, wherein the second seed layer includes a third region arranged between the upper surface of the insulating layer and the first pad, and a fourth region spaced apart from the third region and arranged between the upper surface of the insulating layer and the first protective layer.

[0033] In addition, the first seed layer includes a fifth region connecting the first region and the second region and disposed between a lower surface of the insulating layer and the second mold layer, and the second seed layer includes a sixth region connecting the third region and the fourth region and disposed between an upper surface of the insulating layer and the first mold layer.

[0034] Furthermore, a vertical width or height of each of the first and second column bumps has a range of 0.4 to 0.7 times a horizontal width of each of the first and second column bumps.

[0035] Meanwhile, the package substrate according to the embodiment includes a printed circuit board, which includes: an insulating layer; a plurality of first pads, which are arranged on the upper surface of the insulating layer; a plurality of second pads, which are arranged on the lower surface of the insulating layer; a first device, which is mounted on any one of the plurality of first pads; a second device, which is mounted on any one of the plurality of second pads; a first molding layer, which is arranged on the upper surface of the insulating layer and molds the first device; a second molding layer, which is arranged on the lower surface of the insulating layer and molds the second device; a first columnar bump, which is arranged in the plurality of second pads any one of the plurality of first solder pads; and a second columnar bump, which is arranged on any one of the plurality of first solder pads; a first solder ball, which is arranged on a lower surface of the first columnar bump; a second solder ball, which is arranged on an upper surface of the second columnar bump; a mainboard, which is attached to the first columnar bump of the printed circuit board through the first solder ball; and an upper package, which is attached to the second columnar bump of the printed circuit board through the second solder ball, wherein the lower surface of the second molding layer of the printed circuit board is positioned on the same plane as the lower surface of the second device, and the lower surface of the second device is arranged to directly face the upper surface of the mainboard.

[0036] In addition, the upper surface of the first columnar bump is in direct contact with the lower surface of the second pad, the lower surface of the second columnar bump is in direct contact with the upper surface of the first pad, and the entire area of ​​the side surface of the first columnar bump is in direct contact with at least one of the second protective layer and the second mold layer, and the entire area of ​​the side surface of the second columnar bump is in direct contact with at least one of the first protective layer and the first mold layer.

[0037] In addition, the printed circuit board further includes a first seed layer, which is arranged between the lower surface of the insulating layer and the second pad; and a second seed layer, which is arranged between the upper surface of the insulating layer and the first pad, wherein the first columnar bump is an electroplating layer formed using the first seed layer, and the second columnar bump is an electroplating layer formed using the second seed layer.

[0038] According to an embodiment, a printed circuit board includes: an insulating layer; a first solder pad, which is arranged on the upper surface of the insulating layer; a second solder pad, which is arranged on the lower surface of the insulating layer; a first device, which is mounted on the first solder pad; a second device, which is mounted on the second solder pad; a first molding layer, which is arranged on the insulating layer and molds the first device; a second molding layer, which is arranged on the lower surface of the insulating layer and molds the second device, wherein the lower surface of the second molding layer is arranged on the same plane as the lower surface of the second device.

[0039] In addition, an upper surface of the first mold layer is positioned higher than an upper surface of the first device.

[0040] In addition, the printed circuit board further includes a first protective layer disposed between an upper surface of the insulating layer and the first mold layer; and a second protective layer disposed between a lower surface of the insulating layer and the second mold layer.

[0041] In addition, the printed circuit board further includes a pillar bump disposed below a lower surface of the second pad exposed through the opening of the second protective layer.

[0042] Furthermore, a lower surface of the stud bump is positioned higher than a lower surface of the second mold layer.

[0043] Furthermore, the upper surface of the pillar bump is in direct contact with the lower surface of the second pad.

[0044] Furthermore, the entire area of ​​the side surface of the pillar bump includes a first portion in direct contact with the second protective layer and a second portion in direct contact with the second mold layer.

[0045] Furthermore, the entire area of ​​the side surface of the pillar bump is in direct contact with the second mold layer.

[0046] In addition, the printed circuit board further includes a seed layer disposed between the lower surface of the insulating layer and the second pad, wherein the pillar bump is an electroplating layer formed using the seed layer.

[0047] Furthermore, the seed layer includes a first region disposed between a lower surface of the insulating layer and the second pad, and a second region extending from the first region and disposed between the lower surface of the insulating layer and the second protection layer.

[0048] In addition, the seed layer includes a first region disposed between a lower surface of the insulating layer and the second pad, and a second region spaced apart from the first region and disposed between the lower surface of the insulating layer and the second protection layer.

[0049] In addition, the seed layer includes a third region connected between the first region and the second region and disposed between the insulating layer and the second mold layer.

[0050] Furthermore, the vertical width or height of the stud bump has a range of 0.4 to 0.7 times the horizontal width of the stud bump.

[0051] Meanwhile, the packaging substrate according to the embodiment includes a printed circuit board, which includes: an insulating layer; a first solder pad, which is arranged on the upper surface of the insulating layer; a second solder pad, which is arranged on the lower surface of the insulating layer; a first device, which is mounted on the first solder pad; a second device, which is mounted on the second solder pad; a first molding layer, which is arranged on the insulating layer and molds the first device; a second molding layer, which is arranged on the lower surface of the insulating layer and molds the second device; a first protective layer, which is arranged between the upper surface of the insulating layer and the first molding layer; a second protective layer, which is arranged between the lower surface of the insulating layer and the second molding layer; and a columnar bump, which is arranged below the lower surface of the second solder pad exposed by the opening of the second protective layer; a solder ball, which is arranged on the lower surface of the columnar bump; and a main board, which is attached to the columnar bump of the printed circuit board through the solder ball, wherein the lower surface of the second molding layer of the printed circuit board is positioned on the same plane as the lower surface of the second device, and the lower surface of the second device is arranged to directly face the upper surface of the main board.

[0052] Furthermore, an upper surface of the pillar bump is in direct contact with a lower surface of the second pad, and an entire area of ​​a side surface of the pillar bump is in direct contact with at least one of the second protective layer and the second mold layer.

[0053] Furthermore, the printed circuit board includes a seed layer disposed between a lower surface of the insulating layer and the second pad, and the stud bump is a plating layer formed using the seed layer.

[0054] A printed circuit board according to an embodiment includes: an insulating layer; a pad disposed on an upper surface of the insulating layer; a seed layer disposed between the upper surface of the insulating layer and the pad; a protective layer disposed on the upper surface of the insulating layer and having an opening exposing the upper surface of the pad; and a columnar bump disposed on the upper surface of the pad exposed by the opening of the protective layer, wherein a lower surface of the columnar bump is in direct contact with the upper surface of the pad.

[0055] Furthermore, at least a portion of the side surface of the stud bump is in direct contact with the protection layer.

[0056] Furthermore, the stud bump is a plated layer formed using a seed layer.

[0057] Furthermore, the seed layer includes a first region disposed between an upper surface of the insulating layer and the pad, and a second region extending from the first region and disposed between a lower surface of the insulating layer and the second protective layer.

[0058] In addition, the seed layer includes a first region disposed between an upper surface of the insulating layer and the pad, and a second region spaced apart from the first region and disposed between an upper surface of the insulating layer and the protective layer.

[0059] In addition, the seed layer includes a third region disposed on the insulating layer exposed through the opening of the protective layer and connected between the first region and the second region.

[0060] Furthermore, the vertical width or height of the stud bump is in the range of 0.4 to 0.7 times the horizontal width of the stud bump.

[0061] In addition, the printed circuit board further includes: a device mounted on the upper surface of the insulating layer; and a molding layer which is disposed on the upper surface of the protection layer and molds the device.

[0062] Furthermore, the upper surface of the molding layer is positioned on the same plane as the upper surface of the device.

[0063] Furthermore, an upper surface of the stud bump is positioned lower than an upper surface of the molding layer.

[0064] Furthermore, the entire area of ​​the side surface of the pillar bump includes: a first portion directly contacting the protection layer; and a second portion directly contacting the mold layer.

[0065] Furthermore, the entire area of ​​the side surface of the stud bump is in direct contact with the mold layer.

[0066] On the other hand, a method for manufacturing a printed circuit board according to an embodiment includes: preparing an insulating layer; forming a seed layer on the upper surface of the insulating layer; forming a pad on the upper surface of the seed layer by performing electroplating using the seed layer of the insulating layer; forming a protective layer having an opening exposing the upper surface of the pad on the upper surface of the insulating layer; performing electroplating using the seed layer of the insulating layer, forming a columnar bump on the upper surface of the pad exposed by the opening of the protective layer; and removing at least a portion of the seed layer; wherein the seed layer for electroplating the pad is the same as the seed layer for electroplating the columnar bump, and the lower surface of the columnar bump is in direct contact with the upper surface of the pad.

[0067] Furthermore, at least a portion of the side surface of the stud bump is in direct contact with the protection layer.

[0068] Furthermore, the seed layer after removal includes a first region disposed between an upper surface of the insulating layer and the pad, and a second region extending from the first region and disposed between a lower surface of the insulating layer and the second protective layer.

[0069] Furthermore, the seed layer after removal includes a first region disposed between an upper surface of the insulating layer and the pad, and a second region spaced apart from the first region and disposed between an upper surface of the insulating layer and the protective layer.

[0070] In addition, the seed layer after removal includes a third region disposed on the insulating layer exposed through the opening of the protective layer and connecting the first region and the second region.

[0071] Furthermore, the vertical width or height of the stud bump has a range of 0.4 to 0.7 times the horizontal width of the stud bump.

[0072] Beneficial Effects

[0073] According to this embodiment, a package substrate is manufactured by forming stud bumps on a printed circuit board and attaching a package or a main board using the stud bumps, and thus, fine pitches can be responded to and productivity of manufacturers can be maximized.

[0074] In addition, according to the present embodiment, each device is mounted on both surfaces of the printed circuit board, and a molding layer for molding the mounted devices is provided. Therefore, compared with the existing single-sided molding structure, the balance of the upper and lower parts of the printed circuit board can be maintained. Therefore, the occurrence of warping of the printed circuit board can be minimized.

[0075] In addition, according to the embodiment, each device is mounted on both sides of the printed circuit board. Therefore, all active or passive devices mounted on the existing upper package can be mounted on the printed circuit board, and thus the overall thickness of the package substrate can be reduced.

[0076] In addition, according to this embodiment, the lower surface of the mold layer attached to the main board is positioned on the same plane as the lower surface of the device mounted on the lower portion of the printed circuit board. Therefore, the reliability of the connection between the main board and the printed circuit board can be improved.

[0077] Furthermore, according to the present embodiment, the stud bumps are respectively provided on both sides of the printed circuit board, and therefore, compared with the existing one-sided stud bump arrangement structure, the package balance can be improved, and therefore, the occurrence of warpage can be minimized.

[0078] Furthermore, according to the present embodiment, the pillar bumps are respectively provided on both surfaces of the printed circuit board, so that heat can be dissipated to both sides of the printed circuit board through the pillar bumps, and thus, heat dissipation characteristics can be improved.

[0079] In addition, according to the present embodiment, the height of the pillar bump can be adjusted as much as the height of the device, and thus the design of the package is easy.

[0080] In addition, according to the embodiment, a columnar bump can be formed on a pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Therefore, it is not necessary to form a separate seed layer for forming the columnar bump, and thus the manufacturing process can be simplified, and the problem of cracks between the seed layers of the columnar bump can be solved, and thus the reliability and durability of the product can be improved. In addition, according to the embodiment, it is not necessary to perform a desmear process on the solder resist separately, and thus the whitening phenomenon of the solder resist caused by the desmear solution can be prevented.

[0081] Furthermore, in the embodiment, the aspect ratio of the pillar bump is included in the range of 0.4 to 0.7, and thus, the durability of the pillar bump can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 is a cross-sectional view of a package substrate according to the prior art.

[0083] Figure 2 is a view showing a printed circuit board according to the first embodiment.

[0084] Figure 3 2 is a view illustrating a structure of a second material included in an insulating layer of a circuit board according to an embodiment.

[0085] Figure 4 is a view illustrating an arrangement structure of a first material and a second material included in an insulating layer of a printed circuit board according to an embodiment.

[0086] Figure 5 is a view for explaining the structure of a stud bump in a comparative example.

[0087] Figure 6 2 is a view for explaining the structure of the stud bump according to the first embodiment.

[0088] Figure 7 2 is a view for explaining the structure of a stud bump according to a second embodiment.

[0089] Figure 8 : is a view for explaining the structure of a stud bump according to a third embodiment.

[0090] Figures 9 to 15 It shows the order of the process according to Figure 2 FIG. 2 is a diagram of a method for manufacturing a printed circuit board according to a first embodiment shown in FIG.

[0091] Fig.16 is a view showing a package substrate of the first embodiment.

[0092] Fig.17is a view showing a printed circuit board of the second embodiment.

[0093] Fig.18 is a view showing a package substrate according to a second embodiment. Specific embodiments

[0094] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the spirit and scope of the present invention are not limited to a part of the described embodiments and can be implemented in various other forms, and within the spirit and scope of the present invention, one or more elements of the embodiments can be selectively combined and used in place of each other.

[0095] In addition, unless otherwise explicitly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs, and terms such as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.

[0096] In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not used to limit the present invention. In this specification, unless otherwise specified in a phrase, a singular form may also include a plural form, and may include at least one of all combinations that may be included in A, B, and C when "at least one (or more)" is described in A (and), B, and C.

[0097] In addition, when describing the elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish elements from other elements and are not limited to the nature, order, or sequence of the elements.

[0098] In addition, when an element is described as being “connected,” “coupled” or “connected” to another element, it may include not only when the element is directly “connected,” “coupled” or “connected” to other elements, but also when the element is “connected,” “coupled” or “connected” by another element between the element and the other elements.

[0099] In addition, when described as being formed or disposed “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only when the two elements are directly connected to each other but also when one or more other elements are formed or disposed between the two elements.

[0100] Furthermore, when expressed as “upper (above)” or “lower (lower)”, it may include not only an upper direction but also a lower direction based on one element.

[0101] Figure 2is a view showing a printed circuit board according to the first embodiment.

[0102] refer to Figure 2 The printed circuit board 100 includes a first insulating layer 101, a circuit pattern 102, a via 103, a second insulating layer 103, a third insulating layer 104, a first pad 106, a second pad 107, a protective layer 108, a first molding layer 109, a second molding layer 110, a first connecting portion 111, a first device 112, a second connecting portion 113, a second device 114, a third connecting portion 115, a third device 116 and a columnar bump 117.

[0103] The first insulating layer 101 may be a core substrate.

[0104] The first insulating layer 101 may be a supporting substrate of a printed circuit board on which a single circuit pattern is formed, but may also mean a region on which any one circuit pattern is formed among substrates having a plurality of stacked structures.

[0105] The second insulating layer 104 is formed on the first insulating layer 101 , and the third insulating layer 105 is formed under the first insulating layer 101 .

[0106] The first to third insulating layers 101, 104 and 105 form an insulating board and may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or a glass fiber impregnated substrate, and in the case of including a polymer resin, it may include an epoxy-based insulating resin such as FR-4, BT (bismaleimide triazine) and ABF (Ajinomoto Build up Film), and alternatively, it may include a polyimide-based resin, but is not particularly limited thereto.

[0107] The first to third insulating layers 101, 104, and 105 may be formed of different materials. For example, the first insulating layer 101 is an impregnated substrate including glass fiber, and the second insulating layer 104 and the third insulating layer 105 may be insulating sheets made of only resin.

[0108] The first insulating layer 101 is a central insulating layer and may be thicker than the second and third insulating layers 104 and 105 .

[0109] The inner circuit pattern 102 is formed on at least one of the upper and lower portions of the first insulating layer 101 .

[0110] The circuit pattern 102 may be formed by a conventional manufacturing process of a printed circuit board, such as an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), a SAP (Semi Additive Process) method, etc., and a detailed description thereof is omitted herein.

[0111] In addition, via holes 103 are formed in the first insulating layer 101 to connect internal circuit patterns 102 formed in different layers.

[0112] An external circuit pattern (not shown) is also formed on the second insulating layer 104 formed on the first insulating layer 101 and the third insulating layer 105 formed below the first insulating layer.

[0113] External circuit patterns (not shown) are also formed on exposed surfaces of the second insulating layer 104 formed on the first insulating layer 101 and the third insulating layer 105 formed below the first insulating layer.

[0114] The external circuit pattern may mean the pads 106 and 107 shown in the drawing. That is, the external circuit pattern is formed by the same process as the pads 106 and 107, and is divided into a pattern and a pad according to their functions.

[0115] That is, circuit patterns are formed on the surfaces of the second insulating layer 104 and the third insulating layer 105, and according to the function of the circuit patterns, a portion may be an external circuit pattern and another portion may be pads 106 and 107 connected to a chip or other substrates.

[0116] Furthermore, via holes are formed in the second insulating layer 104 and the third insulating layer 105 .

[0117] The via hole 103 as described above forms a via hole for opening at least one of the first, second, and third insulating layers 101 , 104 , and 105 by a laser process, and thus, it may be formed by filling the inside of the formed via hole with a metal paste.

[0118] In this case, the metal material forming the via hole 103 may be any one selected from Cu, Ag, Sn, Au, Ni and Pd, and the metal material may be filled using any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing.

[0119] Meanwhile, the via hole may be formed by any one of machining methods including mechanical machining, laser machining and chemical machining.

[0120] When the via hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used, and when the via hole is formed by laser processing, UV or CO2 laser methods can be used, and when the via hole is formed by chemical processing, drugs containing aminosilane, ketones, etc. can be used, so that the first, second and third insulating layers 101, 104 and 105 can be opened.

[0121] On the other hand, laser processing is a cutting method that melts and evaporates a part of a material into a desired shape by focusing light energy on a surface. It can easily process complex forms through computer programs and can process composite materials that are difficult to cut by other methods.

[0122] In addition, processing by laser enables a cutting diameter of at least 0.005 mm and has a wide range of advantages in the possible thickness range.

[0123] As the laser processing drill, it is preferable to use a YAG (yttrium aluminum garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, and the CO2 laser is a laser that can only process the insulating layer.

[0124] The protective layer 108 is formed on the surfaces of the second insulating layer 104 and the third insulating layer 105 (the surfaces exposed to the outside, the surfaces on which the pads are formed).

[0125] The protection layer 108 has an opening exposing the upper surface of the first pad 106 .

[0126] That is, the protective layer 108 is used to protect the surfaces of the second insulating layer 104 and the third insulating layer 105 and the front surfaces of the second insulating layer 104 and the third insulating layer 105. It has an opening for opening the surface of the stacked structure of the first pad 106 and the second pad 107 to expose.

[0127] The protective layer 108 may be formed of at least one layer using any one or more of a solder resist (SR), an oxide, and Au. Preferably, the protective layer 108 may be a solder resist. In addition, the protective layer 108 may include an upper protective layer or a first protective layer disposed on the upper surface of the second insulating layer 104. In addition, the protective layer 108 may include a lower protective layer or a second protective layer disposed below the lower surface of the third insulating layer 105.

[0128] The first pads 106 exposed through the openings of the protection layer 108 are classified according to their functions.

[0129] That is, the first pads 106 may include pads connected to the first device 112 and pads connected to the second device 114 .

[0130] To this end, the connection portions 111 and 113 may be disposed on the first pads 106. That is, the first connection portion 111 may be disposed on a pad on which the first device 112 is mounted among the first pads 106. In addition, the second connection portion 113 may be disposed on a pad on which the second device 114 is mounted among the first pads 106.

[0131] The first connection portion 111 and the second connection portion 113 may have a hexahedral shape. For example, the cross-section of the first connection portion 111 and the second connection portion 113 may include a rectangular shape. In more detail, the cross-section of the first connection portion 111 and the second connection portion 113 may include a rectangular or square shape. The first connection portion 111 and the second connection portion 113 may include gold (Au). For example, the first connection portion 111 and the second connection portion 113 may be gold bumps.

[0132] The first device 112 may be attached on the first connection portion 111 . In addition, the second device 114 may be attached on the second connection portion 113 .

[0133] The first device 112 and the second device 114 may be active devices and passive devices constituting a memory package. However, the embodiment is not limited thereto, and the first device 112 and the second device 114 may include devices other than the memory package. For example, the first device 112 and the second device 114 may include at least one of a driver IC chip, a diode chip, a power IC chip, a touch sensor IC chip, a multilayer ceramic capacitor (MLCC) chip, a BGA (ball grid array) chip, and a chip capacitor.

[0134] The first mold layer 109 is disposed on the upper protective layer or the first protective layer among the protective layers 108. The first mold layer 109 may be disposed on the upper protective layer or the first protective layer to cover the first device 112 and the second device 114. The first mold layer 109 may be formed of a resin. The first mold layer 109 can protect the first device 112 and the second device 114 from the external environment by molding the first device 112 and the second device 114 therein. The upper surface of the first mold layer 109 may be positioned higher than the upper surface of the first device 112 and the second device 114. For example, the upper surface of the first device 112 and the upper surface of the second device 114 may be arranged to cover the upper surface of the first mold layer 109.

[0135] Meanwhile, the second pads 107 are disposed on the lower surface of the third insulating layer 105. In addition, the second pads 107 may include a mounting pad on which the third device 116 is mounted, and a bump pad on which a stud bump 117 for connecting to an external main board is disposed.

[0136] The third connection portion 115 may be disposed on the mounting pad of the second pad 107. In this case, the third connection portion 115 may have a shape different from the shapes of the first connection portion 111 and the second connection portion 113. For example, the third connection portion 115 may have a spherical shape. Alternatively, the cross-section of the third connection portion 115 may include a circle. Alternatively, the third connection portion 115 may have a circular shape in whole or in part. For example, the cross-sectional shape of the third connection portion 115 may include a flat surface on one side and a curved surface on the other side opposite to the one side.

[0137] The third connection portion 115 may have a size different from that of the first connection portion 111 and the second connection portion 113. For example, the third connection portion 115 may be formed to have a smaller size than the first connection portion 111 and the third connection portion 113. The third connection portion 115 may include at least one of copper (Cu), tin (Sn), aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (Sb), bismuth (Bi), silver (Ag), and nickel (Ni). The third connection portion 115 may be a solder bump. The third connection portion 115 may be a solder ball and thus may be melted at the temperature of the reflow process.

[0138] The pillar bump 117 may be disposed under the lower protective layer or the second pad 107 exposed through the lower surface of the second protective layer or the bump pad.

[0139] The columnar bump 117 may protrude from the lower surface of the lower protective layer or the second protective layer. The columnar bump 117 may have an upper width and a lower width that are equal to each other. In addition, the columnar bump 117 may have an upper width and a different lower width. The columnar bump 117 may have a column shape.

[0140] The columnar bump 117 may be composed of at least two or more. For example, the columnar bump 117 may include: a first columnar bump 117, which is disposed on any one of the second pads formed on the left side relative to the center among the plurality of second pads 107; and a second columnar bump, which is disposed on any one of the second pads formed on the right side.

[0141] In this case, the lower surface of the pillar bump 117 may be positioned higher than the lower surface of the third device 116. The pillar bump 117 may include a first portion disposed in the opening of the lower protective layer or the second protective layer and a second portion protruding below the lower surface of the lower protective layer or the second protective layer.

[0142] In this case, the upper width and the lower width of the first portion may be equal to each other. In addition, the upper width and the lower width of the second portion may be equal to each other. In addition, the width of the first portion and the width of the second portion may be equal to each other. Alternatively, the width of the first portion and the width of the second portion may be different from each other. For example, the width of the second portion may be greater than the width of the first portion. Therefore, the second portion of the columnar bump 117 may be formed to extend to the lower surface of the lower protective layer or the second protective layer.

[0143] A surface treatment layer (not shown) may be provided on the lower surface of the columnar bump 117. For example, a surface treatment layer for protecting the surface of the columnar bump 117 may be provided on the lower surface of the columnar bump 117. The surface treatment layer may be formed by any one of an organic solderability preservative (OSP), ENEPIG, and thin nickel electroless palladium immersion gold (EPIG). In addition, the surface treatment layer may be formed of soft gold composed of Ni / Au and may have a thickness of 5 to 10 μm.

[0144] The second mold layer 110 is disposed under the lower protective layer or the second protective layer among the protective layers 108. The second mold layer 110 may be disposed on the lower protective layer or the second protective layer to cover the third device 116. The second mold layer 110 may be formed of a resin. In this case, the second mold layer 110 may be disposed to cover the side of the third device 116. In addition, the second mold layer 110 may be disposed to expose the lower surface of the third device 116. In other words, the lower surface of the second mold layer 110 may be positioned on the same plane as the lower surface of the third device 116. In this case, the lower surface of the second mold layer 110 is the same as the lower surface of the third device 116. In this case, in a state where the second mold layer 110 is formed to cover the lower surface of the third device 116, it may be formed by grinding the second mold layer 110 so that the lower surface of the second mold layer 110 is positioned on the same plane as the lower surface of the third device 116.

[0145] As described above, the printed circuit board 100 according to the first embodiment includes the first mold layer 109 for molding the devices mounted on the insulating layers 101, 104, and 105. In addition, the printed circuit board 100 according to the first embodiment includes the second mold layer 110 for molding the devices mounted below the insulating layers 101, 104, and 105. Therefore, in the printed circuit board 100, the mold layer is not provided only on one side of the insulating layer, but the mold layer is provided on both sides, so that the balance of both sides of the printed circuit board can be maintained, and therefore, the occurrence of warpage can be minimized.

[0146] Meanwhile, the insulating layers 101 , 104 , and 105 in the embodiment may have a low dielectric constant.

[0147] That is, the first insulating layer 101 includes glass fibers. Typically, the thickness of the glass fibers is about 12 μm. Therefore, the thickness of the first insulating layer 101 may have a thickness of 21 μm±2 μm, including the thickness of the glass fibers. Specifically, the thickness of the first insulating layer 101 may be in the range of 19 μm to 23 μm.

[0148] Alternatively, glass fiber is not included in the second insulating layer 104 and the third insulating layer 105. Preferably, the second insulating layer 104 and the third insulating layer 105 may be made of RCC. Therefore, each of the second insulating layer 104 and the third insulating layer 105 may have a thickness of 12 μm±2 μm. That is, the thickness of each of the second insulating layer 104 and the third insulating layer 105 may be in the range of 10 μm to 14 μm.

[0149] In this embodiment, an insulating layer is formed using RCC having a low dielectric constant, thereby reducing the thickness of the circuit board and providing a high reliability circuit board with minimized signal loss even in a high frequency band. This can be achieved by the properties of the materials included in the second insulating layer 104 and the third insulating layer 105, which will be described in more detail below.

[0150] To this end, the second insulating layer 104 and the third insulating layer 105 may include a material capable of ensuring mechanical / chemical reliability with a low dielectric constant.

[0151] In detail, the second insulating layer 104 and the third insulating layer 105 may have a dielectric constant Dk of 3.0 or less. In more detail, the second insulating layer 104 and the third insulating layer 105 may have a dielectric constant of 2.03 to 2.7. Therefore, the second insulating layer 104 and the third insulating layer 105 may have a low dielectric constant, and when the insulating layer is applied to a circuit board used at a high frequency, the transmission loss according to the dielectric constant of the insulating layer can be reduced.

[0152] In addition, the second insulating layer 104 and the third insulating layer 105 may have a thermal expansion coefficient of 50 ppm / ° C. or less. In detail, the second insulating layer 104 and the third insulating layer 105 may have a thermal expansion coefficient of 15 ppm / ° C. to 50 ppm / ° C.

[0153] Therefore, the second insulating layer 104 and the third insulating layer 105 may have a low thermal expansion coefficient, thereby minimizing cracks in the insulating layers due to temperature changes.

[0154] To this end, the second insulating layer 104 and the third insulating layer 105 may be formed of two materials. In detail, the second insulating layer 104 and the third insulating layer 105 may include a material in which two compounds are mixed. In detail, the second insulating layer 104 and the third insulating layer 105 may include a first compound and a second compound.

[0155] The first material and the second material may be included in a specific ratio range. In detail, the first material and the second material may be included in a ratio of 4:6 to 6:4.

[0156] In addition, the second insulating layer 104 and the third insulating layer 105 may further include inorganic particles. In detail, the second insulating layer 104 and the third insulating layer 105 may further include inorganic particles, such as silicon dioxide (SiO2). Based on the total amount of the second insulating layer 104 and the third insulating layer 105, the inorganic particles can be included in an amount of about 55wt% to about 70wt%.

[0157] When the ratio of the inorganic particles exceeds the above range, the magnitude of the thermal expansion coefficient or the dielectric constant may be increased by the inorganic particles, and thus the performance of the insulating layer may be deteriorated.

[0158] In addition, the first material and the second material may be chemically non-bonded to each other in the second insulating layer 104 and the third insulating layer 105. However, the embodiment is not limited thereto, and the first material including the first compound and the second material including the second compound may be chemically bonded directly or through a separate linking group.

[0159] The first material may include a material having insulating properties. In addition, the first material may have improved mechanical properties due to high impact strength. In detail, the first material may include a resin material. For example, the first material may include a first compound containing polyphenylene ether (PPE).

[0160] The first material may include a plurality of first compounds, and may form the first compounds by chemically bonding with each other. In detail, the first compounds may be linearly connected to each other by covalent bonds, that is, π-π bonds (ππ).

[0161] That is, the first compounds may be formed by chemically bonding to each other such that the first material has a molecular weight of about 300 to 500.

[0162] In addition, the second material may include a second compound. In detail, the second material may be formed by chemically bonding a plurality of second compounds to each other.

[0163] The second compound may include a material having a low dielectric constant and a thermal expansion coefficient. In addition, the second compound may include a material having improved mechanical strength.

[0164] The second compound may include tricyclodecane and a terminal group connected to the tricyclodecane. The terminal group connected to the tricyclodecane may include various materials, wherein the second compounds may be connected to each other through a carbon double bond (C=C bond). In detail, the terminal group connected to the tricyclodecane may include an acrylate group, an epoxy group, a carboxyl group, a hydroxyl group, and an isocyanate group.

[0165] The second compound may be linked to each other between the terminal groups connected to the tricyclodecane. Specifically, the second compound is cross-linked between the terminal groups through carbon double bonds (C=C bonds) to form a network structure.

[0166] Figure 3 2 is a view illustrating a structure of a second material included in an insulating layer of a circuit board according to an embodiment.

[0167] Specifically, refer to Figure 3 , the second compound may be cross-linked to form a network structure. That is, the second compound may be an aggregate having bonds of a plurality of network structures.

[0168] Therefore, the second material formed of the second compound may have a low dielectric constant and a thermal expansion coefficient according to material properties, and may have improved mechanical strength due to a network structure.

[0169] Figure 4 104 and 105. FIG. 105 is a view for explaining the arrangement of the first material and the second material constituting the second insulating layer 104 and the third insulating layer 105. FIG.

[0170] The first material and the second material may be formed into a single phase in the insulating layer. Figure 8 , the first material connected by the covalent bond of the first compound can be arranged inside the second material which is cross-linked with each other by the second compound to form a network structure.

[0171] In detail, the first compound may be disposed inside a network structure of the second material formed by chemically bonding the second compound to prevent the first material from being separated from the second material.

[0172] That is, the second insulating layer 104 and the third insulating layer 105 can be formed into a single-phase structure without the first material and the second material being phase-separated in the insulating layer. Therefore, since the first material and the second material have a low dielectric constant and a low thermal expansion coefficient due to the material properties of the first material and the second material, they can be formed into a single phase and thus have high mechanical strength.

[0173] Meanwhile, in an embodiment, a plating seed layer (described later) for forming the second pad 107 may be used to form the columnar bump 117. Therefore, in the printed circuit board 100 of the embodiment, a separate seed layer for forming the columnar bump 117 may be omitted. In addition, the columnar bump 117 may be arranged to be in direct contact with the second pad 107. In addition, the columnar bump 117 may be arranged to be in direct contact with the lower protective layer or the second protective layer. That is, the upper surface of the columnar bump 117 may directly contact the lower surface of the second pad 107. In addition, the side surface of the columnar bump 117 may directly contact the lower protective layer or the second protective layer. That is, in the printed circuit board of the comparative example, a separate seed layer for plating the columnar bump is formed between the pad and the columnar bump. Therefore, the printed circuit board of the comparative example has a structure in which the columnar bump and the pad are not directly in contact with each other.

[0174] That is, in the present embodiment, a columnar bump can be formed on the pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Accordingly, there is no need to form a separate seed layer for forming the columnar bump, so the manufacturing process can be simplified. Moreover, the problem of cracks between the seed layers of the columnar bump can be solved, and thus the reliability and durability of the product can be improved. In addition, according to the present embodiment, there is no need to perform a decontamination process on the solder resist separately, and therefore, the whitening phenomenon of the solder resist caused by the decontamination solution can be prevented.

[0175] Hereinafter, the structure of the pillar bump 117 will be described in more detail.

[0176] Figure 5 is a view for explaining the structure of a pillar bump in a comparative example, Figure 6 is a view for explaining the structure of a pillar bump according to a first embodiment, Figure 7 is a view for explaining the structure of a pillar bump according to a second embodiment, and Figure 8 : is a view for explaining the structure of a stud bump according to a third embodiment.

[0177] refer to Figure 5 , the printed circuit board of the comparative example includes an insulating layer 41 .

[0178] And, the pad 42 is provided on the insulating layer 41. In this case, the first seed layer 43 for plating the pad 42 is provided between the insulating layer 41 and the pad 42.

[0179] In addition, a protective layer 44 having an opening exposing at least a portion of the upper surface of the pad 42 is disposed on the insulating layer 41. In addition, a columnar bump 46 may be disposed on the upper surface of the pad 42 exposed through the opening of the protective layer 44. That is, the columnar bump 46 has a predetermined height and is disposed on the pad 42 having a protruding structure, and therefore, the columnar bump 46 cannot be formed by chemical plating. Therefore, the columnar bump 46 is formed by electroplating, and therefore, the second seed layer 45 is disposed on the pad 107. The second seed layer 45 may be disposed on the upper surface of the pad 42, on the upper surface of the protective layer 44, and on the inner wall of the opening of the protective layer 44, respectively.

[0180] That is, in the PCB of the comparative example, the second seed layer 45 is disposed on the pad 42 to form the pillar bump 46. Therefore, in the PCB of the comparative example, a process of forming the second seed layer 45 needs to be additionally performed, and thus the manufacturing process becomes complicated or the manufacturing time increases.

[0181] In addition, in the printed circuit board of the comparative example, the protective layer 44 whitening phenomenon occurs due to the solution during the decontamination process of the second seed layer 45 formed by chemical plating. In addition, in the printed circuit board of the comparative example, the second seed layer 45 is provided between the pad and the columnar bump, and thus the bump layer has a porous microstructure. And, this porous structure has a low metal density, and therefore, cracks are generated in the porous second seed layer 45 due to external impact or other physical forces, and therefore, there is a problem that the columnar bump is destroyed and the reliability or durability of the product is rapidly reduced.

[0182] The lateral width of the pillar bump of the comparative example is a, and the longitudinal width is b. In this case, the aspect ratio (b / a) of the pillar bump of the comparative example is included in the range of 0.8 to 2.0, and thus the durability of the pillar bump is low.

[0183] refer to Figure 6 The pillar bump of the first embodiment has a structure in which the second seed layer of the comparative example is omitted. In other words, the pillar bump of the first embodiment can be formed by plating on the pad 107 using the seed layer 107A for plating the pad. Figure 6 Includes solder mask definition (SMD) type protective layer.

[0184] In the SMD type, a portion of the upper surface of the pad 107 is exposed through the opening of the protective layer 108A, and the columnar bump 117A can be disposed on the exposed upper surface. In addition, the width of the opening of the protective layer 108A in the SMD type is smaller than the width of the upper surface of the columnar bump 117A. Therefore, at least a portion of the upper surface of the columnar bump 117A is covered by the protective layer 108A.

[0185] In this case, the lower surface of the columnar bump 117A in the first embodiment is in direct contact with the upper surface of the pad 107. In addition, the side surface of the columnar bump 117A is in direct contact with the protective layer 108A. Specifically, the side surface of the columnar bump 117A can be set to be in direct contact with the inner wall of the opening of the protective layer 108A.

[0186] Here, the seed layer 107A is disposed between the insulating layer 105 and the pad 107. In this case, the seed layer 107A is not removed immediately after the pad 107 is formed, but remains until the pillar bump 117A is formed. That is, after the pad is formed, all regions of the first seed layer in the comparative example except for the region disposed under the pad are removed.

[0187] Unlike this, the seed layer 107A according to the embodiment is not removed from the region except the lower portion of the pad 107 until all the pillar bumps 117A are formed. In addition, since the seed layer 107A is removed after the pillar bumps 117A are formed as described above, it may have a different structure from the first seed layer of the comparative example.

[0188] That is, the first seed layer of the comparative example is disposed only in the region where the pad is disposed. That is, the first seed layer of the comparative example is disposed only under the pad.

[0189] Alternatively, in the first embodiment, the seed layer 107A may be provided not only in the region where the pad 107 is provided but also may extend from the region and be provided under the protective layer 108A.

[0190] That is, the seed layer 107A includes a first region disposed between the pad 107 and the insulating layer 105 , and a second region extending from the first region and disposed between the protective layer 108A and the insulating layer 105 .

[0191] Therefore, a columnar bump can be formed on a pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Accordingly, there is no need to form a separate seed layer for forming the columnar bump, so the manufacturing process can be simplified. Furthermore, the problem of cracks between the seed layers of the columnar bump can be solved, and therefore, the reliability and durability of the product can be improved. In addition, according to an embodiment, it is not necessary to perform a decontamination process on the solder resist separately, and therefore the whitening phenomenon of the solder resist caused by the decontamination solution can be prevented.

[0192] In addition, the columnar bump according to the first embodiment may have a horizontal width A and a vertical width B. In addition, the aspect ratio (B / A) of the columnar bump 117A in the first embodiment is included in the range of 0.4 to 0.7, thereby improving the durability of the columnar bump 117A. In other words, the vertical width or height of the columnar bump is set to have a range of 0.4 to 0.7 times the horizontal width of the columnar bump. At this time, when the aspect ratio (B / A) of the columnar bump 117A is less than 0.4, the height of the columnar bump 117A cannot be guaranteed, so that the columnar bump 117A cannot work properly. In addition, when the aspect ratio (B / A) of the columnar bump 117A is greater than 0.7, because the vertical width of the columnar bump 117A is too large compared to the horizontal width, there is a durability problem that the columnar bump 117A is easily collapsed.

[0193] In addition, the side surface of the columnar bump 117A having such a structure may include a first portion directly in contact with the protective layer 108 and a second portion directly in contact with the second mold layer 110. That is, the columnar bump in the comparative example has a structure not including the first portion of the columnar bump because the seed layer is additionally provided between the protective layer and the columnar bump, but in an embodiment, a columnar bump including the first portion directly in contact with the protective layer may be provided.

[0194] refer to Figure 7 The pillar bump of the second embodiment has a structure in which the second seed layer of the comparative example is omitted. In other words, the pillar bump of the second embodiment can be formed by electroplating on the pad 107 using the seed layer 107B for electroplating the pad. Figure 7 Includes non-solder mask defined (NSMD) type protective layer.

[0195] In the NSMD type, the entire area of ​​the upper surface of the pad 107 is exposed through the opening of the protective layer 108B, and the columnar bump 117B can be disposed on the exposed upper surface. In addition, the width of the opening of the protective layer 108B of the NSMD type is greater than the width of the upper surface of the columnar bump 117B. Therefore, the protective layer 108B can be disposed at a position separated by a predetermined distance from the columnar bump 117B and the pad 107.

[0196] In this case, the lower surface of the columnar bump 117B in the second embodiment is disposed in direct contact with the upper surface of the pad 107. In addition, the side surface of the columnar bump 117B may be exposed. More specifically, the side surface of the columnar bump 117B may be disposed in direct contact with the second mold layer 110.

[0197] Here, the seed layer 107B is disposed between the insulating layer 105 and the pad 107. In this case, the seed layer 107B is not removed immediately after the pad 107 is formed, but remains until the pillar bump 117B is formed. That is, in the first seed layer of the comparative example, after the pad is formed, all regions except the region disposed under the pad are removed.

[0198] In contrast, in the seed layer 107B according to the second embodiment, a portion provided in an area other than the lower portion of the pad 107 is not removed until all the columnar bumps 117B are formed. In addition, since the seed layer 107B is removed after the columnar bumps 117B are formed as described above, it may have a structure different from that of the first seed layer of the comparative example.

[0199] That is, the first seed layer of the comparative example is disposed only in the region where the pad is disposed. That is, the first seed layer of the comparative example is disposed only under the pad.

[0200] Alternatively, the seed layer 107B according to the second embodiment may be provided not only in the region where the pad 107 is provided but also may extend from the region and be provided under the protective layer 108B.

[0201] That is, the seed layer 107B includes a first region disposed between the pad 107 and the insulating layer 105 , and a second region spaced apart from the first region and disposed between the protective layer 108B and the insulating layer 105 .

[0202] Therefore, it is possible to form a columnar bump on a pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Accordingly, it is not necessary to form a separate seed layer for forming the columnar bump, and thus, the manufacturing process can be simplified. Furthermore, the problem of cracks between the seed layers of the columnar bump can be solved, and thus, the reliability and durability of the product can be improved. In addition, according to the present embodiment, it is not necessary to perform a decontamination process on the solder resist separately, and thus, the whitening phenomenon of the solder resist caused by the decontamination solution can be prevented.

[0203] In addition, the columnar bump according to the second embodiment may have a horizontal width of A' and a vertical width of B'. In addition, the aspect ratio (B' / A') of the columnar bump 117B in the second embodiment is included in the range of 0.4 to 0.7, thereby improving the durability of the columnar bump 117B. When the aspect ratio (B' / A') of the columnar bump 117B is less than 0.4, the height of the columnar bump 117B cannot be guaranteed, so that the columnar bump 117B cannot operate normally. In addition, when the aspect ratio (B' / A') of the columnar bump 117B is greater than 0.7, because the vertical width of the columnar bump 117B is too large compared to the horizontal width, there is a durability problem that the columnar bump 117B is easily collapsed.

[0204] Furthermore, the entire area of ​​the side surface of the pillar bump 117 in the second embodiment may have a structure in direct contact with the second mold layer 110 .

[0205] refer to Figure 8 , the pillar bump of the third embodiment has a structure in which the second seed layer of the comparative example is omitted. In other words, the pillar bump of the third embodiment can be formed by plating the pad 107 using the seed layer 107C for plating the pad. Figure 8 Includes non-solder mask defined (NSMD) type protective layer.

[0206] In the NSMD type, the entire area of ​​the upper surface of the pad 107 is exposed through the opening of the protective layer 108C, and the columnar bump 117C can be disposed on the exposed upper surface. In addition, the width of the opening of the protective layer 108C of the NSMD type is greater than the width of the upper surface of the columnar bump 117C. Therefore, the protective layer 108C can be disposed at a position separated by a predetermined distance from the columnar bump 117C and the pad 107.

[0207] In this case, the lower surface of the columnar bump 117C in the third embodiment is disposed in direct contact with the upper surface of the pad 107. In addition, the side surface of the columnar bump 117C may be exposed. More specifically, the side surface of the columnar bump 117C may be disposed in direct contact with the second mold layer 110.

[0208] Here, the seed layer 107C is disposed between the insulating layer 105 and the pad 107. In this case, the seed layer 107C is not removed immediately after the pad 107 is formed, but is maintained until the pillar bump 117C is formed. That is, in the first seed layer of the comparative example, after the pad is formed, all regions except the region disposed under the pad are removed.

[0209] Unlike this, in the third embodiment, the seed layer 107C provided in the region other than the lower portion of the pad 107 is not removed until all the pillar bumps 117C are formed. In addition, since the seed layer 107C is removed after the pillar bumps 117C are formed as described above, it may have a different structure from the first seed layer of the comparative example.

[0210] That is, the first seed layer of the comparative example is disposed only in the region where the pad is disposed. That is, the first seed layer of the comparative example is disposed only under the pad.

[0211] Alternatively, in the third exemplary embodiment, the seed layer 107C may be provided not only in the region where the pad 107 is provided but also extend from the region and be provided under the protective layer 108C.

[0212] That is, the seed layer 107C includes a first region disposed between the pad 107 and the insulating layer 105 , a second region separated from the first region and disposed between the protective layer 108C and the insulating layer 105 , and a third region disposed between the second mold layer 110 and the insulating layer 105 between the first and second regions.

[0213] Therefore, it is possible to form a columnar bump on a pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Accordingly, it is not necessary to form a separate seed layer for forming the columnar bump, so the manufacturing process can be simplified. In addition, the problem of cracks between the seed layers of the columnar bump can be solved, and therefore, the reliability and durability of the product can be improved. In addition, according to an embodiment, it is not necessary to perform a decontamination process on the solder resist separately, and therefore, the whitening phenomenon of the solder resist caused by the decontamination solution can be prevented.

[0214] In the following, the following will be described in detail Figure 2 A method for manufacturing a printed circuit board according to a first embodiment is shown in FIG.

[0215] Figures 9 to 15 The order of the process is shown in Figure 2 FIG. 2 is a diagram of a method for manufacturing a printed circuit board according to a first embodiment shown in FIG.

[0216] First, refer to Fig. 9 , a first insulating layer 101 as a basis for manufacturing the printed circuit board 100 is prepared.

[0217] The first insulating layer 101 is a base material for forming a circuit pattern present in the printed circuit board 100 .

[0218] The first insulating layer 101 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate, or a glass fiber impregnated substrate, and it may include a polymer resin such as an epoxy-based insulating resin, and alternatively, it may include a polyimide-based resin.

[0219] A metal layer (not shown) is formed on at least one surface of the first insulating layer 101 . The metal layer (not shown) is used to form the internal circuit pattern 102 .

[0220] The metal layer may be formed on the first insulating layer 101 through chemical plating, and alternatively, a copper clad laminate (CCL) may be used.

[0221] In this case, when the metal layer is formed by chemical plating, roughness is provided to the upper surface of the first insulating layer 101 so that plating can be smoothly performed.

[0222] The metal layer may be formed of a conductive metal material such as copper (Cu), iron (Fe), and alloys thereof.

[0223] Afterwards, refer to Fig.10 , a circuit pattern 102 is formed by etching the metal layer on the upper and lower surfaces of the prepared first insulating layer 101, and a via hole (not shown) is formed in the first insulating layer 101, and thus, a conductive via 103 for electrically connecting the circuit patterns 102 respectively formed on the upper and lower surfaces of the first insulating layer 101 to each other is formed.

[0224] The circuit pattern 102 may be formed by coating a photoresist on the upper and lower surfaces of the metal layer, patterning it, and then exposing and developing to form a photoresist pattern.

[0225] That is, the circuit pattern 102 may be formed by a conventional manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP) process, etc., and a detailed description thereof will be omitted here.

[0226] The conductive via 103 is formed to conduct at least one or more regions in the single-layer circuit pattern and the two-layer circuit pattern. The via hole for forming the conductive via 103 can be formed by a process such as laser processing, and it can be formed by a process of filling the inside of the formed via hole with a metal material.

[0227] In this case, the metal material may be any one material selected from Cu, Ag, Sn, Au, Ni, and Pd, and the metal material may be filled using any one or a combination of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet, and dispensing.

[0228] In this case, the order of forming the circuit pattern 102 and the conductive via 103 is not very important. However, in order to more efficiently process the via hole, the conductive via 103 is processed first to form the conductive via 103, and then the circuit pattern 102 is formed.

[0229] Afterwards, refer to Fig.11 , a second insulating layer 104 covering the circuit pattern 102 formed on the upper surface of the first insulating layer 101 is formed.

[0230] In this case, the second insulating layer 104 may be formed as a single layer, but may have a structure in which each of the plurality of layers is formed and stacked in a plurality of layers. In this case, the second insulating layer 104 may be formed of a plurality of layers made of the same material by applying epoxy resin, phenolic resin, prepreg, polyimide film, ABF film, etc. Preferably, the second insulating layer 104 may be formed of RCC as described above.

[0231] Therefore, a metal layer (not shown) may be formed on one surface of the second insulating layer 104 .

[0232] A metal layer may be present to later form the first pad 106 or an external circuit pattern (not shown).

[0233] The metal layer serves to facilitate the flow and diffusion of the resin by heat and pressure during the resin pressing process.

[0234] The third insulating layer 105 covering the circuit pattern 102 formed on the lower surface of the first insulating layer 101 is formed.

[0235] In this case, the third insulating layer 105 may be formed as a single layer, but may have a structure in which each is formed into a plurality of layers and stacked in a plurality of layers. In this case, the third insulating layer 105 may be formed of a plurality of layers made of the same material by applying epoxy resin, phenolic resin, prepreg, polyimide film, ABF film, etc. Preferably, the third insulating layer 105 may be formed of RCC.

[0236] Therefore, a metal layer (not shown) may be formed on one surface of the third insulating layer 105 .

[0237] The metal layer may be present to later form the second pad 107 or an external circuit pattern (not shown). The metal layer serves to facilitate the flow and diffusion of the resin by heat and pressure during the press process.

[0238] Next, the first pad 106 is formed by etching the metal layer on the upper surface of the second insulating layer 104 prepared, and a via hole (not shown) is formed in the second insulating layer 104, and thus, a conductive via for electrically connecting the circuit pattern 102 formed on the upper surface of the first insulating layer 101 and the first pad 106 to each other is formed.

[0239] That is, the first pad 106 may be formed by a conventional manufacturing process of a printed circuit board such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP) process, etc., and a detailed description thereof will be omitted here.

[0240] In addition, the second pad 107 is formed by etching the metal layer on the lower surface of the third insulating layer 105 prepared, thereby forming a via hole (not shown) in the third insulating layer 105, and a conductive via for electrically connecting the circuit pattern 102 formed on the lower surface of the first insulating layer 101 and the second pad 107 to each other is formed.

[0241] Next, refer to Fig.12 , the first connection portion 111 and the second connection portion 113 are disposed on the first pad 106. Then, the first device 112 is mounted on the first pad 106 using the first connection portion 111.

[0242] Furthermore, a second device 114 is mounted on the first pad 106 using the second connection portion 113 .

[0243] In addition, the third connection portion 115 is formed on the second pad 108. Then, the third device 116 is mounted on the second pad 108 using the third connection portion 115.

[0244] Next, refer to Fig.13 A protection layer 108 is formed on the upper surface of the second insulating layer 104 and the lower surface of the third insulating layer 105, respectively.

[0245] The protective layer 108 is used to protect the surface of the second insulating layer 104, the surface of the first pad 106, the surface of the third insulating layer 105 and the surface of the second pad 107, respectively, and it can be formed of at least one layer or multiple layers using at least one of solder resist, oxide and Au.

[0246] Thereafter, the protective layer 108 is processed to expose the surface of the second pad 107 to the outside.

[0247] That is, the protection layer 108 is formed to include an opening (not shown) exposing a portion of the upper surface of the second pad 107 , and the opening may have a smaller diameter than that of the second pad 107 (SMD type).

[0248] Therefore, edge regions of the first pad 106 and the second pad 107 are protected by the protection layer 108 .

[0249] Thereafter, the pillar bump 117 is formed on the second pad 108 exposed through the opening of the protective layer 108. In this case, as described above, the pillar bump 117 may be formed by performing electroplating using a seed layer formed for electroplating the second pad 108.

[0250] Next, refer to Fig.14 The first mold layer 109 is formed by molding the first device 112 and the second device 114 on the upper protective layer or the first protective layer of the protective layer 108 .

[0251] In addition, a second mold layer for molding the third device 116 is formed on the lower protective layer or the second protective layer of the protective layer 108. In this case, a lower surface of the second mold layer 110 may be positioned lower than a lower surface of the third device 116. In addition, an upper surface of the first mold layer 109 may be positioned higher than upper surfaces of the first device 112 and the second device 114.

[0252] Next, refer to Fig.15 , the lower region of the second mold layer 110 is ground to expose the lower surface of the third device 116. That is, the lower region of the second mold layer 110 may be ground so that the lower surface of the second mold layer 110 is positioned on the same plane as the lower surface of the third device 116.

[0253] According to this embodiment, a package substrate is manufactured by forming stud bumps on a printed circuit board and attaching a package or a main board using the stud bumps, and thus, fine pitches can be responded to and productivity of manufacturers can be maximized.

[0254] In addition, according to this embodiment, each device is mounted on both surfaces of the printed circuit board, and a molding layer for molding the mounted devices is provided. Therefore, compared with the existing single-sided molding structure, the balance of the upper and lower parts of the printed circuit board can be maintained. Therefore, the occurrence of warping of the printed circuit board can be minimized.

[0255] In addition, according to the embodiment, each device is mounted on both sides of the printed circuit board. Therefore, all active or passive devices mounted on the existing upper package can be mounted on the printed circuit board, and thus, the overall thickness of the package substrate can be reduced.

[0256] In addition, according to this embodiment, the lower surface of the mold layer of the attached main board is positioned on the same plane as the lower surface of the device mounted on the lower portion of the printed circuit board. Therefore, the reliability of the connection between the main board and the printed circuit board can be improved.

[0257] In addition, according to the present embodiment, the pillar bumps are respectively provided on both surfaces of the printed circuit board, so that heat can be dissipated to both sides of the printed circuit board through the pillar bumps, and thus, heat dissipation characteristics can be improved.

[0258] In addition, according to the present embodiment, the height of the pillar bump can be adjusted as much as the height of the device, and thus the design of the package is easy.

[0259] In addition, according to the embodiment, a columnar bump can be formed on a pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Therefore, it is not necessary to form a separate seed layer for forming the columnar bump, and therefore, the manufacturing process can be simplified, and the problem of cracks between the seed layers of the columnar bump can be solved, and therefore, the reliability and durability of the product can be improved. In addition, according to the embodiment, it is not necessary to perform a decontamination process on the solder resist separately, and therefore, the whitening phenomenon of the solder resist caused by the decontamination solution can be prevented.

[0260] Furthermore, in the embodiment, the aspect ratio of the stud bump is included in the range of 0.4 to 0.7, and therefore, the durability of the stud bump can be improved.

[0261] Fig.16 is a view showing a package substrate according to the first embodiment.

[0262] refer to Fig.16 The package substrate according to the first embodiment includes a reference Figure 2 A printed circuit board 100 is described.

[0263] Furthermore, the solder balls 210 may be disposed on the lower surfaces of the stud bumps 117 of the printed circuit board 100 .

[0264] In addition, the main board 200 may be attached below the pillar bump 117 through the solder ball 210. That is, a pad (not shown) contacting the solder ball 210 may be provided on the upper surface of the main board 200 while being aligned with the pillar bump 117. Therefore, the upper surface of the main board 200 may be provided to directly face the lower surface of the third device 116.

[0265] As described above, the package substrate in the first embodiment forms the columnar bumps 117 connected to the main board 200 under the printed circuit board, and the main board and the printed circuit board can be electrically connected to each other by using the columnar bumps 117. In addition, the lower surface of the second mold layer 110 disposed under the printed circuit board is positioned on the same plane as the lower surface of the third device 116, and the non-contact problem between the printed circuit board and the main board can be solved.

[0266] Fig.17is a view showing a printed circuit board according to a second embodiment.

[0267] Fig.17 The printed circuit board 300 is different from Figure 2 printed circuit board because the pillar-shaped bump has a vertically symmetrical structure.

[0268] That is, in the printed circuit board according to the first embodiment, the stud bumps 117 are provided only on the lower portion of the printed circuit board.

[0269] Alternatively, in the printed circuit board according to the second embodiment, the stud bumps may be respectively provided on both surfaces of the printed circuit board.

[0270] refer to Fig.17 The printed circuit board 300 includes a first insulating layer 301, a circuit pattern 302, a via 303, a second insulating layer 303, a third insulating layer 304, a first pad 306, a second pad 307, a protective layer 308, a first molding layer 309, a second molding layer 310, a first connecting portion 311, a first device 312, a second connecting portion 313, a second device 314, a third connecting portion 315, a third device 316 and columnar bumps 317 and 318.

[0271] The first insulating layer 301 may be a core substrate.

[0272] The first insulating layer 301 may be a supporting substrate of a printed circuit board on which a single circuit pattern is formed, but may also mean a region on which any one circuit pattern is formed among substrates having a plurality of stacked structures.

[0273] The second insulating layer 304 is formed on the first insulating layer 301 , and the third insulating layer 305 is formed under the first insulating layer 301 .

[0274] The first to third insulating layers 301, 304 and 305 form an insulating board and may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, an organic-inorganic composite material substrate or a glass fiber impregnated substrate, and in the case of including a polymer resin, it may include an epoxy-based insulating resin such as FR-4, BT (bismaleimide triazine) and ABF (Ajinomoto reinforcement film), and alternatively, it may include a polyimide-based resin, but is not particularly limited thereto.

[0275] The first to third insulating layers 301, 304, and 305 may be formed of different materials. For example, the first insulating layer 301 is an impregnated substrate including glass fiber, and the second insulating layer 304 and the third insulating layer 305 may be insulating sheets made of only resin.

[0276] The internal circuit pattern 302 is formed on at least one of the upper and lower portions of the first insulating layer 301 .

[0277] Furthermore, via holes 303 are formed in the first insulating layer 301 to connect internal circuit patterns 302 formed in different layers.

[0278] An external circuit pattern (not shown) is also formed on the second insulating layer 304 formed on the first insulating layer 301 and the third insulating layer 305 formed below the first insulating layer.

[0279] An external circuit pattern (not shown) is also formed on the exposed surfaces of the second insulating layer 304 formed on the first insulating layer 301 and the third insulating layer 305 formed below the first insulating layer.

[0280] The external circuit pattern may mean the pads 306 and 307 shown in the drawing. That is, the external circuit pattern is formed by the same process as the pads 306 and 307, and is divided into a pattern and a pad according to its function.

[0281] That is, circuit patterns are formed on the surfaces of the second insulating layer 304 and the third insulating layer 305, and according to the function of the circuit patterns, a portion may be an external circuit pattern and another portion may be pads 306 and 307 connected to a chip or other substrates.

[0282] Furthermore, via holes are formed in the second insulating layer 304 and the third insulating layer 305 .

[0283] The via hole 303 as described above forms a via hole for opening at least one of the first, second, and third insulating layers 301 , 304 , and 305 by a laser process, and thus, it may be formed by filling the inside of the formed via hole with a metal paste.

[0284] In this case, the metal material forming the via hole 303 may be any one material selected from Cu, Ag, Sn, Au, Ni and Pd, and the metal material may be filled using any one or a combination of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing.

[0285] The protective layer 108 is formed on the surfaces of the second insulating layer 304 and the third insulating layer 305 (the surfaces exposed to the outside, the surfaces on which the pads are formed).

[0286] The protection layer 308 has openings that expose the upper surfaces of the first pad 306 and the second pad 307 .

[0287] That is, the protective layer 308 is used to protect the surfaces of the second insulating layer 304 and the third insulating layer 305 and the front surfaces of the second insulating layer 304 and the third insulating layer 305. It has an opening for opening the surface of the stack structure of the first pad 306 and the second pad 307 to expose.

[0288] The protection layer 308 may be formed of at least one layer using any one or more of a solder resist (SR), an oxide, and Au. Preferably, the protection layer 308 may be a solder resist.

[0289] The first pads 306 exposed through the openings of the protection layer 308 are classified according to their functions.

[0290] That is, the first pads 306 may include a pad connected to the first device 312 , a pad connected to the second device 314 , and a pad connected to the second pillar bump 318 .

[0291] To this end, the connection portions 311 and 313 may be disposed on the first pad 306. That is, the first connection portion 311 may be disposed on a pad on which the first device 312 is mounted among the first pads 306. In addition, the second connection portion 313 may be disposed on a pad on which the second device 314 is mounted among the first pads 306.

[0292] The first device 312 may be attached on the first connection portion 311. In addition, the second device 314 may be attached to the second connection portion 313.

[0293] Furthermore, a second pillar bump 318 may be disposed on the first pad 306 .

[0294] The first mold layer 309 is disposed on the upper protective layer or the first protective layer among the protective layers 308. The first mold layer 309 may be disposed on the upper protective layer or the first protective layer to cover the first device 312 and the second device 314. The first mold layer 309 may be formed of a resin. The first mold layer 309 can protect the first device 312 and the second device 314 from the external environment by molding the first device 312 and the second device 314 therein. The upper surface of the first mold layer 309 may be positioned higher than the upper surface of the first device 312 and the second device 314. For example, the upper surface of the first device 312 and the upper surface of the second device 314 may be arranged to cover the upper surface of the first mold layer 309.

[0295] The lower surface of the second pillar bump 318 may directly contact the upper surface of the first pad 306. In addition, the side surface of the second pillar bump 318 may include a first portion directly contacting the first protective layer or the upper protective layer, and a second portion directly contacting the first mold layer 309.

[0296] Meanwhile, the second pads 307 are disposed on the lower surface of the third insulating layer 305. In addition, the second pads 307 may include a mounting pad on which the third device 316 is mounted, and a bump pad on which the first pillar bump 317 for connecting to an external mainboard is disposed.

[0297] The third connection portion 315 may be disposed on a mounting pad of the second pad 307 .

[0298] The first pillar bump 317 may be disposed under the lower protection layer or the second pad 307 exposed through the lower surface of the second protection layer or the bump pad.

[0299] The first columnar bump 317 may protrude from the lower surface of the lower protective layer or the second protective layer. The first columnar bump 317 may have the same upper width and the same lower width. In addition, the first columnar bump 317 may have an upper width and different lower widths. The first columnar bump 317 may have a column shape.

[0300] In this case, a lower surface of the first pillar bump 317 may be positioned higher than a lower surface of the third device 316 .

[0301] The second mold layer 310 is disposed under the lower protective layer or the second protective layer among the protective layers 308. The second mold layer 310 may be disposed on the lower protective layer or the second protective layer to cover the third device 316. The second mold layer 310 may be formed of a resin. In this case, the second mold layer 310 may be disposed to cover the side of the third device 316. In addition, the second mold layer 310 may be disposed to expose the lower surface of the third device 316. In other words, the lower surface of the second mold layer 310 may be positioned on the same plane as the lower surface of the third device 316. In this case, the lower surface of the second mold layer 310 is the same as the lower surface of the third device 316. In this case, in a state where the second mold layer 310 is formed to cover the lower surface of the third device 316, it may be formed by grinding the second mold layer 310 so that the lower surface of the second mold layer 310 is positioned on the same plane as the lower surface of the third device 116.

[0302] As described above, the printed circuit board 300 according to the second embodiment includes the first mold layer 309 for molding the devices mounted on the insulating layers 301, 304, and 305. In addition, the printed circuit board 300 according to the second embodiment includes the second mold layer 310 for molding the devices mounted under the insulating layers 301, 304, and 305. Therefore, in the printed circuit board 300, the mold layer is provided not only on one side of the insulating layer but also on both sides, so that the balance of both sides of the printed circuit board can be maintained, and therefore, the occurrence of warpage can be minimized.

[0303] In addition, the printed circuit board 300 according to the second embodiment forms the columnar bumps 318 and 317 provided on the first pad 306 and the second pad 307 to have a symmetrical structure with each other. In this way, the columnar bumps are not arranged only on one side of the printed circuit board 300 with respect to the insulating layer, but the columnar bumps are arranged on both sides, and the balance of both sides of the printed circuit board can be maintained, and therefore, the occurrence of warpage can be minimized.

[0304] In addition, the first columnar bump 317 and the second columnar bump 318 may have a reference Figures 5 to 7 The described structure, and therefore, can improve the resistance to fracture due to external physical and internal lamination pressures.

[0305] Fig.18 is a view showing a package substrate according to a second embodiment.

[0306] refer to Fig.18 The package substrate according to the second embodiment includes a reference Fig.17 A printed circuit board 300 is described.

[0307] In addition, the first solder balls 410 may be disposed on the lower surface of the first pillar bumps 317 of the printed circuit board 300 .

[0308] Furthermore, the second solder balls 510 may be disposed on the upper surfaces of the second pillar bumps 318 of the printed circuit board 300 .

[0309] In addition, the main board 400 may be attached under the first pillar bump 317 through the first solder ball 410. That is, a pad (not shown) contacting the first solder ball 210 may be provided on the upper surface of the main board 400 while being aligned with the first pillar bump 317.

[0310] In this way, the package substrate in the second embodiment forms the first columnar bump 317 connected to the main board 400 under the printed circuit board, and the main board and the printed circuit board can be electrically connected to each other using the first columnar bump 317. In addition, the lower surface of the second mold layer 310 provided under the printed circuit board is positioned on the same plane as the lower surface of the third device 316, and the non-contact problem between the printed circuit board and the main board can be solved.

[0311] Furthermore, the upper package 500 may be attached on the second pillar bumps 318 through the second solder balls 510 .

[0312] According to this embodiment, a package substrate is manufactured by forming stud bumps on a printed circuit board and attaching a package or a main board using the stud bumps, and thus, fine pitches can be responded to and productivity of manufacturers can be maximized.

[0313] In addition, according to this embodiment, each device is mounted on both surfaces of the printed circuit board, and a molding layer for molding the mounted devices is provided. Therefore, compared with the existing single-sided molding structure, the balance of the upper and lower parts of the printed circuit board can be maintained. Therefore, the occurrence of warping of the printed circuit board can be minimized.

[0314] In addition, according to the embodiment, each device is mounted on both sides of the printed circuit board. Therefore, all active or passive devices mounted on the existing upper package can be mounted on the printed circuit board, and thus, the overall thickness of the package substrate can be reduced.

[0315] In addition, according to this embodiment, the lower surface of the mold layer of the attached main board is positioned on the same plane as the lower surface of the device mounted on the lower portion of the printed circuit board. Therefore, the reliability of the connection between the main board and the printed circuit board can be improved.

[0316] In addition, according to the present embodiment, the stud bumps are respectively provided on both sides of the printed circuit board, and therefore, compared with the existing one-sided stud bump arrangement structure, the package balance can be improved, and therefore, the occurrence of warpage can be minimized.

[0317] In addition, according to the present embodiment, the pillar bumps are respectively provided on both surfaces of the printed circuit board, so that heat can be dissipated to both sides of the printed circuit board through the pillar bumps, and thus, heat dissipation characteristics can be improved.

[0318] Furthermore, according to the present embodiment, the height of the pillar bump can be adjusted as much as the height of the device, and thus the design of the package is easy.

[0319] In addition, according to the embodiment, a columnar bump can be formed on a pad by using a seed layer provided under the pad, without separately forming a seed layer for electroplating under the columnar bump. Therefore, it is not necessary to form a separate seed layer for forming the columnar bump, and therefore, the manufacturing process can be simplified, and the problem of cracks between the seed layers of the columnar bump can be solved, and therefore, the reliability and durability of the product can be improved. In addition, according to the embodiment, it is not necessary to perform a decontamination process on the solder resist separately, and therefore, the whitening phenomenon of the solder resist caused by the decontamination solution can be prevented.

[0320] Furthermore, in the embodiment, the aspect ratio of the stud bump is included in the range of 0.4 to 0.7, and therefore, the durability of the stud bump can be improved.

[0321] The characteristics, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the characteristics, structures, effects, etc. illustrated in each embodiment relative to other embodiments. Therefore, it should be interpreted that the contents related to such combinations and such modifications are also included in the scope of the embodiments.

[0322] The above mainly describes the embodiments, but they are only examples and do not limit the embodiments. It can be understood by those skilled in the art to which the embodiments belong that several changes and applications not presented above can be made without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be changed. In addition, it should be interpreted that the differences associated with such deformations and such applications are included in the scope of the embodiments defined in the following claims.

Claims

1. A circuit board, comprising: Insulation layer; a metal layer, the metal layer being disposed on the insulating layer; a protective layer, the protective layer being disposed on the metal layer; as well as a bump, wherein the bump is disposed on the protective layer, Wherein, the protective layer includes through holes, wherein the metal layer includes a first portion disposed in the through hole of the protective layer and a second portion spaced apart from the first portion and vertically overlapping the protective layer, wherein a thickness of the first portion in a vertical direction is greater than a thickness of the second portion in the vertical direction, and The second portion of the metal layer is electrically separated from the first portion of the metal layer and the bump, and the second portion of the metal layer directly contacts the protective layer.

Images