B-code time synchronization accuracy compensation method and device used in nuclear power plants

Abstract

The embodiment of the application discloses a B-code time synchronization precision compensation method, device, equipment, product and storage medium for a nuclear power plant, which is applied to a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen and a single-board digital signal processor (DSP); an external interrupt IO port is arranged on the single-board DSP; the B-code time synchronization module is connected with the time synchronization device and the display screen respectively; the display screen is connected with the single-board DSP; the single-board DSP is connected with the time synchronization device through the external interrupt IO port; the method comprises the following steps: determining a first time error of a synchronization time sent by the time synchronization device to the display screen; determining a second time error of time setting information sent by the display screen to the single-board DSP for completing time setting; determining a third time error of the time synchronization device based on the first time error and the second time error; and compensating the time set in the time synchronization device by using the third time error.

Description

Technical Field

[0001] This application relates to the field of signal transmission technology, and in particular to a B-code time synchronization accuracy compensation method, device, equipment, product and storage medium for use in nuclear power plants. Background Technology

[0002] For nuclear power plant projects, all equipment is equipped with B-code time synchronization modules, which can be used for board-level time settings. However, due to the increased transmission medium, the time setting process introduces significant delays during data transmission, resulting in large time errors in the board-level settings. Summary of the Invention

[0003] In view of this, embodiments of this application aim to provide a B-code time synchronization accuracy compensation method, apparatus, equipment, product, and storage medium for nuclear power plants.

[0004] The technical embodiments of this application are implemented as follows:

[0005] This application provides a B-code time synchronization accuracy compensation method for nuclear power plants, applied to a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen, and a single-board digital signal processor (DSP); the single-board DSP is provided with an external interrupt I / O port; the B-code time synchronization module is connected to the time synchronization device and the display screen respectively; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt I / O port; the method includes:

[0006] Determine the first time error between the synchronization time sent by the time synchronization device and the display screen;

[0007] Determine the second time error between the time setting information sent by the display screen and the time setting completed by the single-board DSP;

[0008] The third time error of the time synchronization device is determined based on the first time error and the second time error;

[0009] The third time error is used to compensate for the time set in the time synchronization device.

[0010] In the above scheme, determining the first time error between the synchronization time sent by the time synchronization device and the display screen includes:

[0011] The system obtains the first time when the external interrupt I / O port is activated by the synchronization time sent by the time synchronization device recorded by the single-board DSP, and the second time when the display screen receives the synchronization time.

[0012] The first time error is determined based on the first time and the second time.

[0013] In the above scheme, determining the first time error based on the first time and the second time includes:

[0014] Determine the first difference between the second time and the first time;

[0015] The first difference is taken as the first time error.

[0016] In the above scheme, determining the second time error between the time setting information sent by the display screen and the completion of the time setting by the single-board DSP includes:

[0017] Record the third time when the display screen sends the time setting information;

[0018] Record the fourth time when the single-board DSP receives the time setting information;

[0019] Record the fifth time when the single-board DSP completes the time setting based on the time setting information;

[0020] Record the sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting;

[0021] The second time error is determined based on the third time, the fourth time, the fifth time, and the sixth time.

[0022] In the above scheme, determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time includes:

[0023] Determine the second difference between the sixth time and the third time;

[0024] Determine the third difference between the fifth time and the fourth time;

[0025] The second time error is determined based on the second difference and the third difference.

[0026] In the above scheme, determining the second time error based on the second difference and the third difference includes:

[0027] The fourth difference is obtained by subtracting the second difference from the third difference.

[0028] The fourth difference is taken as the second time error.

[0029] In the above scheme, when the transmission path between the display screen and the single-board DSP is symmetrical, the method further includes:

[0030] The delay time between the display screen and the single-board DSP is determined based on the second time error;

[0031] The delay time is used to compensate for the setting time of the single-board DSP.

[0032] In the above scheme, when the transmission path between the display screen and the single-board DSP is asymmetrical, the method further includes:

[0033] Re-determine the second time error between the time setting information sent by the display screen and the time setting completed by the single-board DSP;

[0034] Calculate the average of the second time error and the recalculated second time error;

[0035] The average value is used to compensate for the setup time of the single-board DSP.

[0036] In the above scheme, determining the third time error of the time synchronization device based on the first time error and the second time error includes:

[0037] The third time error is obtained by summing the first time error and the second time error.

[0038] This application provides a B-code time synchronization accuracy compensation device for nuclear power plants, which is installed in a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen, and a single-board digital signal processor (DSP). The single-board DSP is provided with an external interrupt I / O port. The B-code time synchronization module is connected to the time synchronization device and the display screen respectively. The display screen is connected to the single-board DSP. The single-board DSP is connected to the time synchronization device through the external interrupt I / O port. The device includes:

[0039] The first determining unit is used to determine the first time error between the synchronization time sent by the time synchronization device and the display screen;

[0040] The second determining unit is used to determine the second time error between the time setting information sent by the display screen and the completion of the time setting by the single-board DSP.

[0041] The third determining unit is used to determine the third time error of the time synchronization device based on the first time error and the second time error.

[0042] The compensation unit is used to compensate for the time set in the time synchronization device using the third time error.

[0043] This application provides a B-code time synchronization accuracy compensation device for nuclear power plants, comprising:

[0044] Memory, used to store executable instructions;

[0045] A processor, when executing executable instructions stored in the memory, implements any step of the method described above.

[0046] This application provides a computer program product, including a computer program that, when executed by a processor, implements any step of the method described above.

[0047] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any step of the method described above.

[0048] This application provides a B-code time synchronization accuracy compensation method, apparatus, equipment, product, and storage medium for nuclear power plants. It is applied to a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen, and a single-board digital signal processor (DSP). The single-board DSP is equipped with an external interrupt I / O port. The B-code time synchronization module is connected to both the time synchronization device and the display screen. The display screen is connected to the single-board DSP. The single-board DSP is connected to the time synchronization device via the external interrupt I / O port. The method includes: determining a first time error from the synchronization time sent by the time synchronization device to the display screen; determining a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP; determining a third time error of the time synchronization device based on the first and second time errors; and compensating for the time set in the time synchronization device using the third time error. By using the technical solution of this application, the time error from the synchronization time sent by the time synchronization device to the display screen and the time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP are determined, and then added together to obtain a total time error. This total time error is then used to compensate for the set time, eliminating the time error caused by communication. Attached Figure Description

[0049] Figure 1 This is a schematic diagram illustrating the implementation process of a B-code time synchronization accuracy compensation method for nuclear power plants according to an embodiment of this application.

[0050] Figure 2 This is a schematic diagram of the time synchronization device in the embodiments of this application;

[0051] Figure 3 This is a schematic diagram of information transmission in the time synchronization device of this application;

[0052] Figure 4 This is a schematic diagram illustrating the calculation of the time information transmission error between the display screen and the DSP in an embodiment of this application;

[0053] Figure 5 This is a schematic diagram illustrating an application scenario of errors in the transmission of time information from the time synchronization device to the display screen in this application embodiment;

[0054] Figure 6 This is a flowchart illustrating the process of calculating the time information transmission error from the time synchronization device to the display screen in an embodiment of this application.

[0055] Figure 7 This is a schematic diagram illustrating the elimination of delay error in the time synchronization device in the embodiments of this application;

[0056] Figure 8 This is a schematic diagram of the structure of a B-code time synchronization accuracy compensation device for a nuclear power plant according to an embodiment of this application;

[0057] Figure 9 This is a schematic diagram of the structure of the B-code time synchronization accuracy compensation device used in nuclear power plants according to an embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0059] For nuclear power plant projects, all equipment is equipped with B-code time synchronization modules, which can be used for board-level time settings. However, due to the increased transmission medium, the time setting process introduces significant delays during data transmission, resulting in large time errors in the board-level settings.

[0060] Based on this, this embodiment proposes a B-code time synchronization accuracy compensation method for nuclear power plants. This method can be applied to B-code time synchronization accuracy compensation equipment for nuclear power plants. The function implemented by this method can be achieved by the processor in the B-code time synchronization accuracy compensation equipment for nuclear power plants calling program code. Of course, the program code can be stored in the memory of the processing device. It can be seen that the processing device includes at least a processor and a memory.

[0061] Figure 1This is a schematic diagram illustrating the implementation process of a B-code time synchronization accuracy compensation method for nuclear power plants according to an embodiment of this application. This application provides a B-code time synchronization accuracy compensation method for nuclear power plants, applied to a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen, and a single-board digital signal processor (DSP). The single-board DSP is equipped with an external interrupt I / O port. The B-code time synchronization module is connected to the time synchronization device and the display screen respectively. The display screen is connected to the single-board DSP. The single-board DSP is connected to the time synchronization device through the external interrupt I / O port. Figure 1 As shown, the method includes:

[0062] Step S101: Determine the first time error between the synchronization time sent by the time synchronization device and the display screen.

[0063] Step S102: Determine the second time error between the time setting information sent by the display screen and the time setting completed by the single-board DSP.

[0064] Step S103: Determine the third time error of the time synchronization device based on the first time error and the second time error.

[0065] Step S104: Use the third time error to compensate for the time set in the time synchronization device.

[0066] It should be noted that the compensation used in the nuclear power plant based on the delay error of the B-code time synchronization signal can be understood as compensating for the delay error caused by the transmission of the B-code time synchronization signal.

[0067] The time synchronization device can be determined according to the actual situation and is not limited here. As an example, the time synchronization device may include a time synchronization instrument.

[0068] The B-code time synchronization module can be determined according to the actual situation, and is not limited here. As an example, the B-code time synchronization module may include a B-code decoding module, etc.

[0069] The time synchronization device can be determined according to the actual situation and is not limited here. For ease of understanding, it can be combined with... Figure 2 To understand, Figure 2 This is a schematic diagram of a time synchronization device in an embodiment of this application.

[0070] The display screen is connected to the single-board DSP. This connection can be determined according to the actual situation and is not limited here. As an example, the connection can be a wired connection or a wireless connection; wherein, the wired connection can be a wire connection capable of transmitting data; the wireless connection can use short-range communication technology, such as Bluetooth, Zigbee, etc.; or it can use long-range communication technology, such as WiFi (Wireless Fidelity) connection.

[0071] The connection between the single-board DSP and the time synchronization device via the external interrupt I / O port can be understood as the single-board DSP having an I / O port, and the time synchronization device being connected to the I / O port.

[0072] In step S101, the specific process for determining the first time error between the synchronization time sent by the time synchronization device and the display screen can be determined according to actual conditions and is not limited here. As an example, determining the first time error between the synchronization time sent by the time synchronization device and the display screen may include obtaining the first time when the external interrupt I / O port is activated by the synchronization time sent by the time synchronization device recorded by the single-board DSP and the second time when the display screen receives the synchronization time; and determining the first time error based on the first time and the second time. The first time error can be determined according to actual conditions and is not limited here. As an example, the first time error can be denoted as Tdly1.

[0073] In step S102, the specific process for determining the second time error between the time setting information sent by the display screen and the completion of time setting by the single-board DSP can be determined according to actual conditions and is not limited here. As an example, determining the second time error between the time setting information sent by the display screen and the completion of time setting by the single-board DSP may include recording a third time when the display screen sends the time setting information; recording a fourth time when the single-board DSP receives the time setting information; recording a fifth time when the single-board DSP completes time setting based on the time setting information; recording a sixth time when the display screen receives the flag information sent by the single-board DSP after completing time setting; and determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time. The second time error can be determined according to actual conditions and is not limited here. As an example, the second time error can be denoted as Tdly2.

[0074] In step S103, the specific determination process for determining the third time error of the time synchronization device based on the first time error and the second time error can be determined according to actual circumstances and is not limited here. As an example, determining the third time error of the time synchronization device based on the first time error and the second time error may include summing the first time error and the second time error to obtain the third time error. The third time error can be determined according to actual circumstances and is not limited here. As an example, the third time error can be denoted as Tdly.

[0075] In step S104, the specific process of compensating the time set in the time synchronization device using the third time error can be determined according to the actual situation and is not limited here. As an example, compensating the time set in the time synchronization device using the third time error can be understood as calibrating the time set in the time synchronization device using the third time error and the set time. The set time can be determined according to the actual situation and is not limited here. As an example, the set time can be denoted as... Tset .

[0076] In this embodiment, the time error between the synchronization time sent by the time synchronization device and the display screen and the time error between the time setting information sent by the display screen and the time setting completed by the single-board DSP are determined and then added together to obtain the total time error. The total time error is then used to compensate for the set time, thereby eliminating the time error caused by communication.

[0077] In one optional embodiment of this application, determining the first time error between the synchronization time sent by the time synchronization device and the display screen includes:

[0078] The system obtains the first time when the external interrupt I / O port is activated by the synchronization time sent by the time synchronization device recorded by the single-board DSP, and the second time when the display screen receives the synchronization time.

[0079] The first time error is determined based on the first time and the second time.

[0080] In this embodiment, the first time and the second time can be determined according to the actual situation, and are not limited here. As an example, the first time can be recorded as T1'; the first time can be recorded as T2'.

[0081] The specific determination process for determining the first time error based on the first time and the second time can be determined according to the actual situation and is not limited here. As an example, determining the first time error based on the first time and the second time may include determining a first difference between the second time and the first time; and using the first difference as the first time error.

[0082] In one optional embodiment of this application, determining the first time error based on the first time and the second time includes:

[0083] Determine the first difference between the second time and the first time;

[0084] The first difference is taken as the first time error.

[0085] In this embodiment, as an example, the first time can be denoted as T1'; the second time can be denoted as T2'. Determining the first difference between the second time and the first time can be understood as determining T2'-T1' as the first difference.

[0086] As an example, the first time error can be denoted as Tdly1. Using the first difference as the first time error can be understood as Tdly1 = T2' - T1'.

[0087] In practical applications, the information transmission from the time synchronization device to the display screen is unidirectional, making it impossible to use bidirectional timestamps to account for transmission errors. However, the delay time can be calculated using unidirectional timestamp recording. An external interrupt function is used to sample the transmission time of the synchronization device. The display screen records the time of receiving the received time information. Using this time difference, the data transmission delay time during this process can be calculated. Specifically, this includes: the time synchronization device sending the synchronization time, the display screen receiving the synchronization time (recorded as T2'), and simultaneously, the external interrupt I / O port activating. The DSP records the interrupt trigger time T1' and the time of receiving the display screen's transmission T2', calculating the delay time Tdly1 = T2' - T1'.

[0088] In one optional embodiment of this application, determining the second time error between the time setting information sent by the display screen and the completion of the time setting by the single-board DSP includes:

[0089] Record the third time when the display screen sends the time setting information;

[0090] Record the fourth time when the single-board DSP receives the time setting information;

[0091] Record the fifth time when the single-board DSP completes the time setting based on the time setting information;

[0092] Record the sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting;

[0093] The second time error is determined based on the third time, the fourth time, the fifth time, and the sixth time.

[0094] In this embodiment, the third time, the fourth time, the fifth time, and the sixth time can all be determined according to the actual situation, and are not limited here. As an example, the third time can be denoted as T1; the fourth time can be denoted as T2; the fifth time can be denoted as T3; and the sixth time can be denoted as T4.

[0095] The specific determination process for determining the second time error based on the third, fourth, fifth, and sixth times can be determined according to the actual situation and is not limited here. As an example, determining the second time error based on the third, fourth, fifth, and sixth times may include determining a second difference between the sixth time and the third time; determining a third difference between the fifth time and the fourth time; and determining the second time error based on the second difference and the third difference.

[0096] In one optional embodiment of this application, determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time includes:

[0097] Determine the second difference between the sixth time and the third time;

[0098] Determine the third difference between the fifth time and the fourth time;

[0099] The second time error is determined based on the second difference and the third difference.

[0100] In this embodiment, as an example, the third time can be denoted as T1; the sixth time can be denoted as T4; determining the second difference between the sixth time and the third time can be understood as determining T4-T1 as the second difference.

[0101] As an example, the fourth time can be denoted as T2; the fifth time can be denoted as T3; determining the third difference between the fifth time and the fourth time can be understood as determining T3-T2 as the third difference.

[0102] The specific determination process for determining the second time error based on the second difference and the third difference can be determined according to the actual situation and is not limited here. As an example, determining the second time error based on the second difference and the third difference may include subtracting the second difference from the third difference to obtain a fourth difference; and using the fourth difference as the second time error.

[0103] In one optional embodiment of this application, determining the second time error based on the second difference and the third difference includes:

[0104] The fourth difference is obtained by subtracting the second difference from the third difference.

[0105] The fourth difference is taken as the second time error.

[0106] In this embodiment, the step of subtracting the second difference from the third difference to obtain the fourth difference can be understood as the fourth difference being equal to (T4-T1)-(T3-T2).

[0107] As an example, the second time error is denoted as Tdly2, and the fourth difference can be understood as the second time error as Tdly2 = (T4 - T1) - (T3 - T2).

[0108] In practical applications, data transmission between the display screen and the board is bidirectional. Due to time delays in data transmission and processing, there is an error between the set time and the actual time. To minimize or compensate for this error, the delay time can be calculated by recording the time points generated in each step of the setting process. Specifically, this can include: the display screen records the current timestamp T1 while sending the time setting command; the board records the current timestamp T2 after receiving the command; the board records the current timestamp T3 after setting the time; and the display screen records the current timestamp T4 after receiving the time setting completion flag from the board. The delay time can be calculated as: Tdly2 = (T4 - T1) - (T3 - T2). For ease of understanding, here is an example: assume T1 is 2 o'clock; T2 is 2 o'clock one second later; T3 is 2 o'clock two seconds later; T4 is 2 o'clock three seconds later; the command is sent once per second, and the setting is performed once per minute.

[0109] In an optional embodiment of this application, when the transmission path between the display screen and the single-board DSP is symmetrical, the method further includes:

[0110] The delay time between the display screen and the single-board DSP is determined based on the second time error;

[0111] The delay time is used to compensate for the setting time of the single-board DSP.

[0112] In this embodiment, the symmetrical transmission route between the display screen and the single-board DSP can be understood as the transmission routes being the same, and the delay times being symmetrical and basically the same.

[0113] The specific process for determining the delay time between the display screen and the single-board DSP based on the second time error can be determined according to the actual situation and is not limited here. As an example, the second time error is denoted as Tdly2, and the delay time can be denoted as Td; determining the delay time between the display screen and the single-board DSP based on the second time error can be understood as Tb = Tdly2 / 2. If Tdly2 = (T4-T1)-(T3-T2), then Tb = [(T4-T1)-(T3-T2)] / 2.

[0114] Compensating for the setting time of the single-board DSP using the aforementioned delay time can be understood as calibrating the setting time of the single-board DSP using the delay time and the setting time; wherein, the setting time can be determined according to the actual situation and is not limited here. As an example, the setting time can be denoted as Tset. Calibrating the setting time of the single-board DSP using the aforementioned delay time and setting time can be understood as the calibrated time being T = Tb + Tset.

[0115] In practical applications, since the transmission lines are the same and the delay times are symmetrical and basically the same, the required compensation delay time Tb = Tdly / 2; the time after calibration is T = Tb + Tset.

[0116] In an optional embodiment of this application, when the transmission path between the display screen and the single-board DSP is asymmetrical, the method further includes:

[0117] Re-determine the second time error between the time setting information sent by the display screen and the time setting completed by the single-board DSP;

[0118] Calculate the average of the second time error and the recalculated second time error;

[0119] The average value is used to compensate for the setup time of the single-board DSP.

[0120] In this embodiment, it is mainly considered that when the transmission path between the display screen and the single-board DSP is asymmetrical, it can be understood that when the asymmetry of the transmission path needs to be considered, that is, the delays of sending and receiving are different, the error can be reduced by multiple measurements and averaging.

[0121] The second time error in re-determining the time setting information sent by the display screen to the single-board DSP to complete the time setting can be understood as multiple measurements of the second time error.

[0122] The specific compensation process for compensating the setup time of the single-board DSP using the average value can be determined according to the actual situation and is not limited here. As an example, compensating the setup time of the single-board DSP using the average value may include compensating the setup time of the single-board DSP after weighting the average value.

[0123] In practical applications, when it's necessary to consider transmission path asymmetry—that is, the sending and receiving delays are different—errors can be reduced through multiple measurements and averaging. Compensation can include multiple measurements: performing multiple measurements and calculating the average to reduce error. It can also involve adjusting the model: if the delay in a certain direction is known to be longer, the delay in that direction can be weighted in the calculation.

[0124] In one optional embodiment of this application, determining the third time error of the time synchronization device based on the first time error and the second time error includes:

[0125] The third time error is obtained by summing the first time error and the second time error.

[0126] In this embodiment, as an example, the first time error can be denoted as Tdly1; the second time error can be denoted as Tdly2; and the third time error can be denoted as Tdly. Summing the first time error and the second time error, the third time error can be understood as Tdly = Tdly1 + Tdly2.

[0127] In practical applications, the elimination of delay errors in the entire system is mainly divided into error elimination from the synchronization device to the display screen and error elimination from the display screen to the DSP. The method involves recording timestamps, but due to transmission differences, it is necessary to separately sample the one-way timestamps to calculate the error Tdly1 and the two-way timestamps to calculate Tdly2. Time compensation is then applied to the set time using the calculated time difference to eliminate time errors caused by communication. Specifically, this includes calculating the time error Tdly1 from the synchronization device to the display screen; calculating the time error Tdly2 from the display screen to the DSP; calculating the total time error Tdly = Tdly1 + Tdly2; and performing time compensation T = Tdly + Tset.

[0128] To facilitate understanding of this application, the B-code time synchronization accuracy compensation method used in nuclear power plants is specifically a method for compensating for delay errors caused by the transmission of B-code time synchronization signals. This method is applied to a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen, and a single-board digital signal processor (DSP). Assume the time synchronization device is specifically a time synchronization instrument, and the B-code time synchronization module is specifically a B-code decoding module. The time synchronization instrument sends the synchronization time to the B-code decoding module; the B-code decoding module decodes the time and sends it to the display screen; the display screen sends a time setting frame to the single-board DSP; the single-board DSP provides feedback on whether the time setting is complete to the display screen. This content can be combined with... Figure 3 To understand, Figure 3 This is a schematic diagram of information transmission in the time synchronization device of this application.

[0129] The specific implementation steps are as follows:

[0130] First, calculate the time information transmission error between the display screen and the DSP.

[0131] For data transmission between the display screen and the board, this segment is bidirectional. Due to time delays during data transmission and processing, there is an error between the set time and the actual time. To minimize or compensate for this error, the time points generated in each step of the setup process can be recorded, and the delay time can be calculated for compensation.

[0132] step:

[0133] 1. The display screen records the current timestamp T1 while sending the time setting command;

[0134] 2. After receiving the instruction, the board records the current timestamp T2;

[0135] 3. After setting the time on the board, record the current timestamp T3;

[0136] 4. After receiving the board setting time completion flag, the display screen records the current timestamp T4;

[0137] 5. The delay time can be calculated as follows: Tdly = (T4 - T1) - (T3 - T2);

[0138] 6. Since the transmission lines are the same and the delay times are symmetrical and basically the same, the required compensation delay time Tb = Tdly / 2;

[0139] 7. The time after calibration is T = Tb + Tset.

[0140] To make it easier to understand, this can be combined with... Figure 4 To understand, Figure 4 This is a schematic diagram illustrating the calculation of the time information transmission error between the display screen and the DSP in an embodiment of this application.

[0141] When it is necessary to consider the asymmetry of the transmission route, that is, the delays of sending and receiving are different, the error can be reduced by multiple measurements and averaging.

[0142] Compensation methods may include:

[0143] 1. Multiple measurements: Perform multiple measurements and calculate the average value to reduce errors. Adjust the model;

[0144] 2. If the delay time in a certain direction is known to be longer, the delay in that direction can be weighted in the calculation.

[0145] Second, calculate the error in the transmission of time information from the time synchronization device to the display screen.

[0146] The information transmission from the time synchronization device to the display screen is unidirectional, making it impossible to use bidirectional timestamps to account for transmission errors. However, the delay time can be calculated using unidirectional timestamp recording. An external interrupt function is used to sample the transmission time of the synchronization device. The display screen records the received time information; this time difference can be used to calculate the data transmission delay during this process.

[0147] To make it easier to understand, this can be combined with... Figure 5 , Figure 6 To understand, Figure 5 This is a schematic diagram illustrating an application scenario of errors in the transmission of time information from the time synchronization device to the display screen in this application embodiment; Figure 6 This is a flowchart illustrating the process of calculating the time information transmission error from the time synchronization device to the display screen in an embodiment of this application.

[0148] Third, the elimination of delay errors in the entire system is mainly divided into error elimination from the synchronization device to the display screen and error elimination from the display screen to the DSP. The method used is to record timestamps, but due to transmission differences, it is necessary to sample the one-way timestamps to calculate the error Tdly1 and the two-way timestamps to calculate Tdly2. The calculated time difference is then used to compensate for the set time, which can eliminate the time error caused by communication.

[0149] To make it easier to understand, this can be combined with... Figure 7 To understand, Figure 7 This is a schematic diagram illustrating the elimination of delay errors in the time synchronization device in the embodiments of this application.

[0150] In this embodiment, the fault recording-based visualization early warning system can detect potential faults in advance and present them visually, allowing maintenance personnel to intuitively understand the system's health status and potential risks, and quickly take corresponding measures, effectively reducing the time and economic losses caused by faults. Furthermore, when a fault occurs repeatedly, the system will proactively allocate resources for continuous querying. When conditions in the fault early warning model are triggered, a corresponding alarm will be generated for the entire system, enabling staff to perceive the alarm in advance and implement appropriate preventative strategies.

[0151] This application embodiment also provides a B-code time synchronization accuracy compensation device for nuclear power plants, which is installed in a time synchronization device including a time synchronization device, a B-code time synchronization module, a display screen, and a single-board digital signal processor (DSP); the single-board DSP is provided with an external interrupt I / O port; the B-code time synchronization module is connected to the time synchronization device and the display screen respectively; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt I / O port; as shown... Figure 8 As shown, Figure 8 This is a schematic diagram of a B-code time synchronization accuracy compensation device for a nuclear power plant according to an embodiment of this application. The device 800 includes:

[0152] The first determining unit 801 is used to determine the first time error between the synchronization time sent by the time synchronization device and the display screen;

[0153] The second determining unit 802 is used to determine the second time error between the time setting information sent by the display screen and the completion of the time setting by the single-board DSP.

[0154] The third determining unit 803 is used to determine the third time error of the time synchronization device based on the first time error and the second time error.

[0155] The compensation unit 804 is used to compensate for the time set in the time synchronization device using the third time error.

[0156] In one embodiment, the first determining unit 801 is further configured to acquire the first time when the external interrupt I / O port is activated by the synchronization time sent by the time synchronization device recorded by the single-board DSP, and the second time when the display screen receives the synchronization time; and determine the first time error based on the first time and the second time.

[0157] In one embodiment, the first determining unit 801 is further configured to determine a first difference between the second time and the first time; and to use the first difference as the first time error.

[0158] In one embodiment, the second determining unit 802 is further configured to record a third time when the display screen sends the time setting information; record a fourth time when the single-board DSP receives the time setting information; record a fifth time when the single-board DSP completes the time setting based on the time setting information; record a sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting; and determine the second time error based on the third time, the fourth time, the fifth time, and the sixth time.

[0159] In one embodiment, the second determining unit 802 is further configured to determine a second difference between the sixth time and the third time; determine a third difference between the fifth time and the fourth time; and determine the second time error based on the second difference and the third difference.

[0160] In one embodiment, the second determining unit 802 is further configured to subtract the second difference from the third difference to obtain a fourth difference; and to use the fourth difference as the second time error.

[0161] In one embodiment, when the transmission path between the display screen and the single-board DSP is symmetrical, the third determining unit 803 is further configured to determine the delay time between the display screen and the single-board DSP based on the second time error;

[0162] The compensation unit 804 is also used to compensate for the setting time of the single-board DSP using the delay time.

[0163] In one embodiment, when the transmission path between the display screen and the single-board DSP is asymmetrical, the second determining unit 802 is further configured to redetermine the second time error between the time setting information sent by the display screen and the completion of the time setting by the single-board DSP.

[0164] The compensation unit 804 is also used to compensate for the setting time of the single-board DSP using the average value.

[0165] In one embodiment, the third determining unit 803 is further configured to sum the first time error and the second time error to obtain the third time error.

[0166] It should be noted that, in the embodiments of this application, if the above-mentioned B-code time synchronization accuracy compensation method for nuclear power plants is implemented in the form of software functional modules and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical embodiments of this application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a B-code time synchronization accuracy compensation system for nuclear power plants (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0167] Based on the hardware implementation of the above program modules, this application embodiment also provides a B-code time synchronization accuracy compensation device for nuclear power plants, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements the steps in the B-code time synchronization accuracy compensation method for nuclear power plants provided in the above embodiment.

[0168] Correspondingly, this application provides a computer program product, which, when executed by a processor, implements the steps in the B-code time synchronization accuracy compensation method for nuclear power plants provided in the above embodiments.

[0169] Correspondingly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps in the B-code time synchronization accuracy compensation method for nuclear power plants provided in the above embodiments.

[0170] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0171] Based on the hardware implementation of the above program modules, this application embodiment also provides a B-code time synchronization accuracy compensation device for nuclear power plants, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the method described above.

[0172] Correspondingly, embodiments of this application provide a computer program product, including a computer program on which the computer program is stored, and which, when executed by a processor, implements the steps of the method described above.

[0173] Correspondingly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method described above.

[0174] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0175] It should be noted that, Figure 9 This is a schematic diagram of the structure of the B-code time synchronization accuracy compensation device used in a nuclear power plant according to an embodiment of this application, as shown below. Figure 9 As shown, the device 900 includes a processor 901 and a memory 903. Optionally, the device 900 may also include a communication interface 902.

[0176] It is understood that memory 903 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 903 described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0177] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 901. The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 901 or by instructions in the form of software. The processor 901 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 901 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in the memory 903. The processor 901 reads the information in the memory 903 and combines it with its hardware to complete the steps of the aforementioned method.

[0178] In an exemplary embodiment, the device may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned method.

[0179] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0180] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0181] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0182] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0183] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0184] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for compensating for B-code time synchronization accuracy for a nuclear power plant, characterized by, The application is applied to a time synchronization device including a time synchronization device, a B code time synchronization module, a display screen and a single-board digital signal processor (DSP); an external interrupt IO port is arranged on the single-board DSP; the B code time synchronization module is connected with the time synchronization device and the display screen respectively; the display screen is connected with the single-board DSP; the single-board DSP is connected with the time synchronization device through the external interrupt IO port; the method comprises the following steps: determining a first time error of synchronization time sent by the time synchronization device to the display screen; determining a second time error of time setting information sent by the display screen to the single-board DSP for completing time setting; determining a third time error of the time synchronization device based on the first time error and the second time error; compensating the time set in the time synchronization device by using the third time error; wherein, the first time error of synchronization time sent by the time synchronization device to the display screen is determined by acquiring a first time recorded by the single-board DSP that the synchronization time sent by the time synchronization device makes the external interrupt IO port act and a second time recorded by the display screen that the synchronization time is received; the first time error is determined based on the first time and the second time; wherein, the first time error is determined based on the first time and the second time, which comprises the following steps:

2. The method of claim 1, wherein, determining a first difference value between the second time and the first time; and taking the first difference value as the first time error. the second time error of time setting information sent by the display screen to the single-board DSP for completing time setting is determined by the following steps: recording a third time when the display screen sends the time setting information; recording a fourth time when the single-board DSP receives the time setting information; recording a fifth time when the single-board DSP completes time setting based on the time setting information; recording a sixth time when the display screen receives the flag information sent by the single-board DSP for completing the time setting; 3. The method of claim 2, wherein, determining the second time error based on the third time, the fourth time, the fifth time and the sixth time. the second time error is determined based on the third time, the fourth time, the fifth time and the sixth time, which comprises the following steps: determining a second difference value between the sixth time and the third time; determining a third difference value between the fifth time and the fourth time; 4. The method of claim 3, wherein, determining the second time error based on the second difference value and the third difference value. the second time error is determined based on the second difference value and the third difference value, which comprises the following steps: subtracting the second difference value from the third difference value to obtain a fourth difference value; 5. The method of claim 4, wherein, taking the fourth difference value as the second time error. when the transmission route between the display screen and the single-board DSP is symmetrical, the method further comprises the following steps: determining a delay time between the display screen and the single-board DSP based on the second time error; 6. The method of claim 5, wherein, compensating the set time of the single-board DSP by using the delay time. when the transmission route between the display screen and the single-board DSP is asymmetrical, the method further comprises the following steps: The second time error of time setting information sent by the display screen to the single-board DSP completing time setting is determined again; An average of the second time error and the determined second time error is calculated; The average is used to compensate for the time setting of the single-board DSP.

7. The method according to any one of claims 1 to 4, characterized in that, The third time error of the time synchronization device is determined based on the first time error and the second time error, including: The first time error and the second time error are summed to obtain the third time error.

8. A B-code time synchronization accuracy compensation device for a nuclear power plant, characterized by comprising: The time synchronization device includes a time synchronization device, a B code time module, a display screen, and a single-board digital signal processor (DSP). An external interrupt IO port is arranged on the single-board DSP. The B code time module is connected with the time synchronization device and the display screen respectively. The display screen is connected with the single-board DSP. The single-board DSP is connected with the time synchronization device through the external interrupt IO port. The device includes: A first determination unit is configured to determine a first time error of synchronization time sent by the time synchronization device to the display screen. A second determination unit is configured to determine a second time error of time setting information sent by the display screen to the single-board DSP completing time setting. A third determination unit is configured to determine a third time error of the time synchronization device based on the first time error and the second time error. A compensation unit is configured to compensate for the time set in the time synchronization device by using the third time error. The first determination unit is further configured to acquire a first time at which the single-board DSP records the synchronization time sent by the time synchronization device to make the external interrupt IO port act, and a second time at which the display screen receives the synchronization time; and determine the first time error based on the first time and the second time. The first determination unit is further configured to determine a first difference between the second time and the first time; and take the first difference as the first time error.

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