Method for improving storage performance

Abstract

The invention relates to a method for improving storage performance. It belongs to the field of data storage. It identifies whether an access request accessing a storage falls into the category of a single logical cluster, and performs the operation on the storage according to the original access request if the access request does not cross different logical clusters. Otherwise, if the access request crosses different logical clusters, it combines the different logical clusters involved in the access request into a logically position-variable elastic logical cluster, and reorganizes the repeated contents in the access request that are directed to different logical clusters into a single content of the same kind, and performs the operation on the storage according to the reorganized access request. The typical advantage is to compress the data stream generated by the storage operation action, saving bandwidth and significantly improving the data storage operation performance of the storage during the construction and transmission and parsing of the storage operation request.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and in particular, to a method for improving storage performance in a storage system such as a mechanical hard disk or a solid state disk. BACKGROUND

[0002] With the development of storage systems, hardware interface technology and communication protocols are also updated. In the early days, mechanical hard disks and solid state disks were limited by the intrinsic characteristics of the internal physical storage medium, such as small capacity and small data width used for single read / write, so low-level bandwidth interfaces did not show any problems. Currently, with the update iteration of storage media, the input / output (IO) bandwidth of hard disks has increased by several to hundreds of times. The low-level bandwidth storage operations currently used (such as fragmentation of instructions, repetition of partial abstract content, etc.) will severely constrain the improvement of storage performance in the face of high-level bandwidth scenarios.

[0003] In a popular understanding, even if optimization is implemented for storage operations, traditional optimization such as priority cannot highlight the superiority of such optimization or provide a matching adaptive solution channel. Typically, limited bandwidth will still put read / write data and corresponding optimization operations and other channel information in a situation of competing for resources, and performance improvement is out of the question. For example, a single queue mode is used for data interaction between a host and a mechanical hard disk or a solid state disk, and although high concurrency is allowed to read data from multiple different locations of the storage medium at the same time, the single queue becomes a bottleneck for concurrency.

[0004] In a storage system, in the communication process between a host and a hard disk, under the premise of accurately writing data to be stored into a storage and accurately reading data from the storage, how to compress unnecessary communication data and streamline various interactive data to reduce the pressure on the interface, reduce communication delay, and ensure the smoothness of software execution is a concern that needs to be improved in the storage system. The solution to these problems will greatly improve the performance of the storage system. The development of communication protocols provides room for improvement in storage operation optimization. For example, the speed improvement in IO bandwidth of communication protocols such as PCIe / NVMe is unprecedented, and there is great room for improvement in storage operations between a host and a hard disk. SUMMARY

[0005] The application relates to a method for improving storage performance, which mainly comprises the following steps: identifying whether an access request for accessing a memory falls within the scope of a single logical cluster, performing an operation on the memory according to the original access request if the access request does not cross different logical clusters, or combining different logical clusters involved in the access request into a flexible logical cluster with variable logical positions and reorganizing repeated contents in the access request into a single same request if the access request crosses different logical clusters, and performing an operation on the memory according to the reorganized access request.

[0006] The method has the following characteristics: the operation category of the access request on the memory at least includes a data read operation, a data write operation or a data erase operation.

[0007] The method has the following characteristics: the memory is a flash-based solid state disk, and the memory maps logical addresses (address information) carried by the original access request or the reorganized access request to physical addresses in the memory.

[0008] The method has the following characteristics: the flexible logical cluster contains a total number of logical clusters which is a positive integer multiple of a single logical cluster, and the change of the logical positions of the flexible logical cluster is implemented in a way of covering one or a plurality of logical clusters at a time.

[0009] The method has the following characteristics: for a logical cluster covered by the flexible logical cluster but not involved in the current access request, information corresponding to the logical address of the logical cluster is subjected to the same operation as the current access request, and the execution time of the same operation is kept synchronous with the execution time of the current access request.

[0010] The method has the following characteristics: if the access request crosses different logical clusters, the same request at least includes a read request, a write request or an erase request (for example, the same request is embodied in the reorganizing step).

[0011] The method has the following characteristics: in the flexible logical cluster, the addresses of the different logical clusters involved in the access request are continuous or the addresses of the different logical clusters involved in the access request are separated by logical clusters not involved in the access request.

[0012] The method has the following characteristics: when the memory receives a plurality of continuous access requests, it first determines whether the target minimum command execution units of the plurality of access requests are consistent, and then determines the operation categories of the plurality of access requests.

[0013] The series of access requests with the same minimum command execution unit and the same operation category are synchronously executed once with corresponding operations according to the physical addresses mapped by the respective logical addresses and according to the operation categories, so as to replace the sequential execution of the memory on the access requests.

[0014] The method comprises:

[0015] The series of access requests with the same minimum command execution unit and different operation categories are sequentially executed according to the physical addresses mapped by the respective logical addresses and according to the operation categories; or

[0016] The series of access requests with different minimum command execution units and the same or different operation categories are synchronously executed according to the physical addresses mapped by the respective logical addresses and according to the operation categories.

[0017] The application relates to a method for improving storage performance, characterized by comprising:

[0018] The application relates to a method for improving storage performance, characterized by comprising:

[0019] The series of access requests with the same minimum command execution unit and the same operation category are synchronously executed once with corresponding operations according to the physical addresses mapped by the respective logical addresses and according to the operation categories, so as to replace the sequential execution of the memory on the access requests.

[0020] The application relates to a method for improving storage performance, characterized by comprising:

[0021] The application relates to a method for improving storage performance, characterized by comprising:

[0022] The memory receives a plurality of the access requests in succession, and first determines whether the target minimum command execution units of the plurality of the access requests are consistent, and judges the operation categories of the plurality of the access requests respectively;

[0023] The series of the access requests with the same minimum command execution units and different operation categories are executed in sequence according to the physical addresses mapped by the respective logical addresses and according to the operation categories of the access requests; or

[0024] The series of the access requests with different minimum command execution units and the same or different operation categories are executed synchronously according to the physical addresses mapped by the respective logical addresses and according to the operation categories of the access requests.

[0025] The application relates to a method for improving storage performance, characterized by comprising:

[0026] Identifying whether the access request for accessing the memory falls within the category of a single logical cluster, wherein the operation of the memory is performed according to the original access request when the access request does not cross different logical clusters;

[0027] The memory receives a plurality of the access requests in succession, and first determines whether the target minimum command execution units of the plurality of the access requests are consistent, and judges the operation categories of the plurality of the access requests respectively;

[0028] The series of the access requests with the same minimum command execution units and the same operation categories are executed synchronously according to the physical addresses mapped by the respective logical addresses and according to the operation categories of the access requests, so as to replace the sequential execution of the plurality of the access requests by the memory.

[0029] The application relates to a method for improving storage performance, characterized by comprising:

[0030] Identifying whether the access request for accessing the memory falls within the category of a single logical cluster, wherein the operation of the memory is performed according to the original access request when the access request does not cross different logical clusters;

[0031] The memory receives a plurality of the access requests in succession, and first determines whether the target minimum command execution units of the plurality of the access requests are consistent, and judges the operation categories of the plurality of the access requests respectively;

[0032] The series of the access requests with the same minimum command execution units and different operation categories are executed in sequence according to the physical addresses mapped by the respective logical addresses and according to the operation categories of the access requests; or

[0033] The series of access requests with different minimum command execution units, same or different operation categories are synchronously executed according to the physical addresses mapped by the respective logical addresses and according to their operation categories.

[0034] In electronic products, the traditional mechanical hard disk (HDD) contains mechanical components, and the magnetic head needs to move to the target position on the rapidly rotating magnetic disk to write and read, and a large number of tasks are consumed on inefficient mechanical actions. The solid state disk (SSD) far exceeds the read speed of the mechanical hard disk, and no longer pays attention to mechanical action, and further, the solid state disk is more shockproof and drop-resistant in physical structure than the mechanical hard disk, because the solid state disk is made of a solid-state electronic storage chip array and uses an integrated circuit instead of a traditional rotating magnetic disk.

[0035] Although the solid state disk has many storage advantages, such as extremely high storage density, it also means that the storage particles or storage chips need to use more word lines and bit lines to manipulate the transistors that store bit data. Further, the high-density transistor array also brings complexity in storage management. Typically, there is a lot of repetitive content in the communication instructions between the host and the hard disk, but how to deal with repetitive content is one of the difficult problems. If unnecessary operation data and simplified storage interaction data can be compressed to reduce the pressure on the interface and reduce communication delay, the data access of the storage system will be much smoother and faster, and this is one of the goals that the context scheme of the present application can achieve. With the current mainstream high-speed communication protocol, the storage performance (such as storage operation performance) is greatly improved. Therefore, the method for improving the storage performance can be referred to as the method for improving the data storage operation performance of the storage in this paper.

[0036] The advantage of the example introduced in the context of the present application is that during information storage operation, even if part of the request exists in the case of repetition, even if the operation request of the storage exists in the case of overlap in construction and transmission and analysis, the unnecessary information of the storage operation can still be simplified and the bandwidth can be saved to the maximum extent under the premise of guaranteeing the safety and reliability of the data. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to make the above purposes and features and advantages more popular and easy to understand, the specific embodiments are described in detail in the following with reference to the drawings, and after reading the following description and referring to the following drawings, the features and advantages of the present application will be apparent.

[0038] Figure 1 is the data interaction between the host and the solid state disk with physical blocks, pages and sectors.

[0039] Figure 2 is to identify whether the access request for accessing the storage falls within the scope of a single logical cluster.

[0040] Figure 3 is that there are a lot of repetitive data segments in the interaction between the host and the hard disk and cause blocking.

[0041] Figure 4 is that the storage operation needs to process data construction and transmission and parsing and so on and produces redundant data.

[0042] Figure 5 is that the access request crosses different logical clusters and combines them into one elastic logical cluster.

[0043] Figure 6 is that the access request may or may not cross different logical clusters.

[0044] Figure 7 is that the storage operation does not produce or produces a small amount of redundant data and almost does not occupy the bandwidth. DETAILED DESCRIPTION

[0045] The technical solutions disclosed in the present application will be described in detail below in combination with specific embodiments. The described embodiments are only used for the description and illustration of the present application and are not all the embodiments. Based on the embodiments, those skilled in the art should realize that any solution obtained without creative labor falls within the protection scope of the present application.

[0046] Referring to Figure 1 , one parameter of the solid state disk (SSD) is the read speed. The traditional solid state disk is usually designed to communicate with the host (HOST Device) through the serial advanced technology attachment (SATA) interface. With the increasing access speed of the flash memory chip in the solid state disk, the improvement of the chip and the hardware, and the gradual development of the interface technology, it has gradually become an advantage to further improve the data transmission speed between the solid state disk and the host or similar devices. This advantage is extremely beneficial and crucial for the improvement of the data storage performance and storage involved in this paper.

[0047] Referring to Figure 1 , the relevant SATA interface is formulated by the "Serial ATA Working Group" group. The main function is used for data transmission between the motherboard and the data storage device (such as the hard disk and the optical disk drive). It is named because it uses a serial way to transmit data, has the advantages of simple structure and supports hot plug. It belongs to the computer bus. The SATA bus uses embedded clock frequency signals, has stronger error correction ability than traditional interfaces, can check the transmission instructions and the transmission data and automatically correct when errors are found, and the main purpose is to improve the reliability of data transmission.

[0048] Referring to Figure 1, the relevant PCIe interface belongs to the high-speed serial computer expansion bus standard interface, and PCIe is mainly based on replacing the traditional PCI bus. PCI-Express (Peripheral Component Interconnect express) is designed based on a point-to-point topology, and each device is connected to the root system / host through a separate serial link. Based on the shared bus topology, the PCI bus in a single direction can be arbitrated in the case of multiple hosts, and is limited to one host at a time. In terms of clock scheme, the traditional PCI bus limits the bus clock to the slowest peripheral on the bus. In contrast, the PCIe bus link supports full-duplex communication between any two endpoints, with concurrent access across multiple endpoints and no inherent limitations.

[0049] Referring to Figure 1 , the relevant NVMe interface specification can be named VM Express (NVMe) as Non Volatile Memory, which belongs to a bus transmission protocol specification based on a device logical interface, such as an application layer in a communication protocol, used to access non-volatile storage media such as flash memory attached through a PCI-Express (PCIe) bus. Theoretically, it is not necessarily required to use the PCIe bus protocol. The NVMe specification mainly provides a low-latency, internally concurrent native interface specification for flash-based storage devices, and provides native storage concurrency support for current mainstream processors and computer platforms and related applications, so that the host hardware and software can fully utilize the parallel storage capabilities of solid-state storage devices. Relying on the PCIe bus, the NVMe device can be carried on various physical slots or related hardware that support the PCIe bus.

[0050] Referring to Figure 1 , data is stored in the form of files in the memory of a computer or electronic device, and the form of target data is generally ASCII code or binary. For storage media such as flash memory chips, designing a driving function that matches the storage media can very conveniently read and write data on the memory. The target content can be converted into ASCII code, stored in an array, and the array content can be written to a specified address on the flash memory chip, and the data can be read from the address when needed and the read data can be interpreted in ASCII code format.

[0051] Referring to Figure 1 , with the development of interface technology from SATA to PCIe and NVMe, the data access has been improved by several times, even tens of times or even higher.

[0052] Referring to Figure 1 , the theoretical transmission speed of a typical SATA interface is several megabytes per second (MB / S).

[0053] Referring to Figure 1 The theoretical transmission speed of the PCIe / NVMe interface is several gigabytes per second (GB / S).

[0054] Referring to Figure 1 In optional embodiments, unnecessary communication data should be compressed and various types of interaction data should be simplified to reduce the pressure on the interface, reduce intermediate communication delay, and ensure the smoothness of software execution. Preferably, the implementation of such an improvement scheme should take into account the bandwidth of various high and low levels.

[0055] Referring to Figure 1 A solid state disk (SSD) usually contains one or more storage particles or storage chips (LUN), which are basically the smallest units of command execution, and different LUNs can execute different command sequences.

[0056] Referring to Figure 1 A single storage particle or storage chip of a solid state disk (SSD) has multiple planes (Plane), and each plane is provided with independent data registers and cache registers in order to optimize flash access speed.

[0057] Referring to Figure 1 A single plane (Plane) of a solid state disk (SSD) contains one or more blocks (Block), and a block usually contains a large number of pages. For example, some manufacturers stipulate that the number of blocks should be a multiple of 32.

[0058] Referring to Figure 1 Taking a block (Block_0) and another block (Block_63) as an example, the number of blocks in a single plane in actual applications is much larger than the number shown in the figure.

[0059] Referring to Figure 1 A page (page) of a solid state disk (SSD) contains a large number of bytes. The size of a page is usually a power of 2 but does not include the capacity of the spare area (spare). A single page includes several sectors (sector).

[0060] Referring to Figure 1 The spare area (spare) and the data area (user data) are common concepts of storage.

[0061] Referring to Figure 1, the detailed explanation of the SSD inside can be described as follows. The space occupied by a single memory block usually includes a data area (user data) and a spare area. Taking a single memory block containing 64 pages as an example, the data area of the single memory block can be divided into 64 parts, each of which is used to store the write data or information of each page. The spare area or redundant space of the memory block can also be divided into 64 parts, each of which is used to store the redundant data or spare data of each page. Therefore, the space occupied by a single page includes a data area and a spare area. For example, Block_0 includes pages P0-P63, etc.

[0062] Referring to Figure 1 Taking a single page containing 8 sectors as an example, the data area of the page can also be divided into 8 parts, each of which is used to store the data of each sector. The spare area of the page can also be divided into 8 parts, each of which is used to store the redundant data or spare data of each sector. In addition, the information storage mode of the page can also be adaptively modified, for example, a certain spare space or redundant space of a single page is opened to uniformly store the redundant data or spare data of all sectors in the page. Some single pages P3 or P4, etc. are shown in the figure, which are divided into 8 sectors Sec1, Sec2, Sec3, …, Sec8, etc. The SSD can maintain the mapping relationship between the logical block address and the physical memory block address through a mapping table.

[0063] Referring to Figure 1 In an optional embodiment, the SSD essentially integrates a control chip and a storage grain, and the control chip can also be called an SSD controller or a command & control logic, and the naming of different storage manufacturers can be slightly different. Regarding the logical control unit contained in the memory, it contains a mode register and a command decoder. The external host, for example, inputs a command to the logical control unit through a command bus and an address bus, and the command is decoded by the command decoder, and then the control parameters are saved to the mode register and the logical control unit to control the logic to run. The external host, for example, inputs address information through an address bus, and the address information plays an auxiliary role when the logical control unit is logically controlled. In addition, the multiplexed address bus and the internal devices such as the control logic, the row address multiplexer, the column address counter latch, and the column address decoder work together to accurately select the storage unit corresponding to the row and column addresses in the storage array, and then perform data access operations. The functions of the logical control unit of different storage manufacturers can also be different, and the above is only an example and does not constitute any limitation.

[0064] Referring to Figure 1Direct storage of storage media can bring great inconvenience, such as difficulty in recording the location of valid data and determining the remaining space of the storage medium, and how to interpret the data in a certain format. As a huge unmanaged storage space, various contents are stored in a disorganized manner, making it difficult to find the required document. Imagine when operating the computer and using the storage space, just write the content into the storage space without management, when operating the computer again and trying to read a document, you have to find it from various mounting spaces.

[0065] Referring to Figure 1 , it can be known by analysis that the aforementioned storage mode of directly storing data is still acceptable for small-capacity storage media such as EEPROM, but for large-capacity devices such as Flash memory chips or SD cards and SSD solid-state hard disks, an efficient way is needed to manage its storage content. Otherwise, a large amount of complex and easily changed address information with the amount of written data needs to be remembered to match the written data. If the storage system is considered from the perspective of enterprise-level commercial scenarios, large-capacity SSD solid-state hard disks designed as unified storage or distributed storage are supported as the main research object and storage medium, and mass storage demand, data credibility and security are preconditions that must be considered.

[0066] Referring to Figure 1 , the conventional management mode of managing the storage content of the storage medium is the file system, which is an organizational structure established on the storage medium for the purpose of storing and managing data, such as necessary modules including the operating system boot area and directory and file.

[0067] Referring to Figure 1 , for example, file system formats include FAT32, NTFS, exFAT, etc. Such formats are common file systems under the Windows operating system. Before using the file system, the storage medium can be formatted. Formatting erases the original content, such as creating a new file allocation table and directory on the storage medium.

[0068] Referring to Figure 1 , when using the file system, data is basically stored in the form of files.

[0069] Referring to Figure 1 , when writing a new file, a file index indicating the information of the physical address where the file is stored needs to be created in the directory, and then the data is stored in the address.

[0070] Referring to Figure 1When the data needs to be read, the index of the file can be found in the directory, and the data can be read in the corresponding address according to the index. In addition, it also relates to a series of auxiliary structures or processing procedures such as logical address, cluster size, and discontinuous storage.

[0071] Referring to Figure 2 Through the process of participating in the management of the storage content of the storage medium by the file system, it can be known that the existence of the file system makes the data not be directly read and written to the physical address of the storage medium when the data is accessed, but should follow the read and write format of the file system. For example, through logical conversion, a complete and integral file can be stored in multiple segments in discontinuous physical addresses, and the position of the next segment can be known by using the directory or the linked list. If the volume of the integral file is large and needs to occupy a large storage space, the participation of the file system is necessary.

[0072] Referring to Figure 2 In optional embodiments, the hard disk capacity is continuously expanded, and the early definition of 512 bytes per sector is no longer reasonable, and some manufacturers set the sector 512 bytes to the sector 4096 bytes. With NTFS and the like becoming the standard hard disk file system, the default allocation unit size (cluster) of their file system can be selected as 4096 bytes. Considering that the cluster corresponds to the sector, even if the physical hard disk partition is aligned with the logical partition used by the computer, and based on ensuring the hard disk reading and writing efficiency and reading and writing speed, it is necessary to design optimization measures for the interaction of the cluster and the hard disk.

[0073] Referring to Figure 2 In optional embodiments, if the access request crosses different logical clusters, the hard disk can need to write two physical storage space units when the file system operates a certain cluster. However, in essence, a single physical storage space unit is sufficient to meet the data operation and storage needs of the file system. If the logical cluster and the physical storage space such as the sector match, not only the writing speed of the hard disk is increased, but also the service life of the hard disk is lengthened. On the contrary, if the logical cluster operated by the computer and the physical storage space such as the sector mismatch, not only the operation speed of the hard disk is lowered, but also the service life of the hard disk is ended in advance due to the imbalance of the reading and writing areas of the hard disk, and some space is easily turned into a bad area.

[0074] Referring to Figure 2 In specific embodiments, the data of the logical cluster corresponds to 8 logical blocks, and the data volume of each logical block is defined as, for example, 512B bytes, and the 8 logical blocks are Log1, Log2, …, Log 8, and the like. It is noted that the data size and the number of logical blocks listed are only examples given for the convenience of explanation, and the real computer is not limited thereto.

[0075] Referring to Figure 2In a specific embodiment, the access request, such as a read request Real_D, spans different logical clusters, such as logical cluster CLU_1 and logical cluster CLU_2. In this embodiment, the logical cluster CLU_1 is partitioned with a start position at cluster logical block C0 and a stop position at cluster logical block C7, which amounts to 8 blocks. The logical cluster CLU_2 is partitioned with a start position at cluster logical block C8 and a stop position at cluster logical block C15, which amounts to 8 blocks. The access request then spans two physical storage space units, and the hard disk can write two physical storage space units when the file system writes a cluster, or the hard disk can read two physical storage space units when the file system reads a cluster.

[0076] Referring to Figure 2 In a specific embodiment, the access request, such as a read request Real_D, does not span different logical clusters, but the problem arises that in the interaction of this access request, a control node has to be assigned for each physical storage space unit, and in the control nodes belonging to the same instruction, a large amount of information or fields is highly repetitive. For example, the information usually carried by an access request: the access request operation type, the logical address information and the physical address information, which results in a large waste of computer resources.

[0077] Referring to Figure 2 In a specific embodiment, the first type of request content of the read request Real_D for the logical cluster CLU_1 and the second type of request content of the read request Real_D for the logical cluster CLU_2 have the same parts, of course, there are also different parts, and the two types or two instances of the read request Real_D have the same parts, and the information carried by the two instances of the access request has repetitive content, which is redundant. In general, the information of an access request is the operation object, i.e. the data itself and the access-related information, which coexist. The operation object is, for example, data to be read or data to be stored or data to be erased or any related data.

[0078] Referring to Figure 2In a specific embodiment, for example, a read request Real_D accesses different logical clusters, such as logical cluster CLU_1 and logical cluster CLU_2. There is repetition between the amount of information that the read request Real_D accesses the logical cluster CLU_1 and the amount of information that the same read request accesses the logical cluster CLU_1. As mentioned above, the amount of information generally includes various operation types, such as read operations or write operations or erasing, instruction information included in the amount of information, such as interactive master-slave mode or interactive one-way bidirectional communication mode or whether hardware control or software control is based, address information included in the amount of information, such as storage grain LUN address or other logical address or physical address, and the like, identification included in the amount of information, such as clock polarity or phase or frequency factor, and of course all the information included in the amount of information is not repeated here. In addition to the data itself, there is a large amount of access accompanying information accompanying the data. The repeated part of the amount of information that the read request Real_D accesses the logical cluster CLU_1 and the logical cluster CLU_2, for example, includes operation type, instruction information, address information, identification information, clock information, and some other necessary information such as MSB / LSB agreement, CRC check expression, data frame length, and the like. In addition to the data itself, the access accompanying information is also an important part of the access request.

[0079] Referring to Figure 2 In a specific embodiment, if analyzed from the perspective of the host HOST, the processor will cross different logical clusters CLU_1 and CLU_2 due to the read request Real_D, resulting in the processor needing to process repeated various access data and various access information. However, in essence, the processor's processing process for the logical cluster CLU_1 and the processor's processing process for the logical cluster CLU_2 are filled with the same content. In other words, the internal memory part of the computer, such as SRAM or DRAM, will be through the same content, which will greatly affect the computing performance and memory performance of the computer system and seriously occupy the interface bandwidth. In the case of low bandwidth of the interface SATA, it is easy to realize that repeated throughput content occupies a large amount of interface bandwidth. In the case of high bandwidth of the interface PCIe / NVMe, it is often difficult to intuitively find the relationship between repeated throughput content and interface bandwidth, but a large part of the bandwidth of PCIe / NVMe is used to transport the accompanying information of the access information.

[0080] Referring to Figure 2In a specific embodiment, if analyzed from the perspective of the memory MMRY, the controller or command & control logic involved also needs to handle the repetitive various memory operations and various amounts of access information. The memory MMRY and the host HOST are both different and similar.

[0081] Referring to Figure 3 The command & control logic of the memory MMRY typically needs to decode the first type of request content in the read request Real_D for the logical cluster CLU_1 and the second type of request content for the logical cluster CLU_2. The same part of the two types or two times of access requests in the read request Real_D is repeatedly decoded and translated at the memory MMRY end. Therefore, the same content is also involved in the processing procedure at the memory end, which restricts the performance of the memory. The memory end also needs to spend a large amount of hardware and software resources to handle the redundancy in the access request. It is worth noting that the redundancy here is based on the consideration and cognition from the human perspective. In fact, from the perspective of the host HOST and the memory MMRY, whether it is repetitive content or not, it needs to be executed in turn according to the instructions specified in advance.

[0082] Referring to Figure 3 In an ideal state, the read request Real_D should have a reasonable time consumption Real_T during the operation of the computer or the memory. The time axis TIME in the figure represents the time consumption of the execution event (such as a data read operation or a data write operation or a data erase operation or an access request). The logical cluster CLU_1 starts at the cluster logical block C0 and ends at the cluster logical block C7, which belongs to a partition block. The logical cluster CLU_2 starts at the cluster logical block C8 and ends at the cluster logical block C15, which belongs to a partition block. Due to the partition characteristics of the logical cluster CLU_1 and the logical cluster CLU_2, the read request Real_D consumes some time in the first request content of the first physical storage space unit, which is represented by WAIT_T1 in the figure. The read request Real_D consumes some time in the second request content of the second physical storage space unit, which is represented by WAIT_T2 in the figure. If the access request such as the read request Real_D crosses more physical storage space units, more time will be consumed.

[0083] Referring to Figure 4, the total time consumption of the ideal time consumption Real_T of the read request Real_D executed by the host HOST and the time execution event will be seriously lagging behind, because the main content of the information usually needs to complete the data construction and transmission and parsing processes in sequence when the execution event is executed. The processor and the memory will be equivalent to the blocked situation due to repeated processing of repeated content, although the computer or the memory is executing the task according to its own program. Therefore, from the task end, there is no blocking, and from the perspective of the computer or the memory executing the task, there is no blocking, and the program does not exist in the execution stage. The resistance or hardware factors that prevent the normal execution of the program, and it will not be suspended. Therefore, the difficult problem is that the blocking is hidden.

[0084] Referring to Figure 4 , the same content being swallowed inside the memory SRAM or DRAM can be represented as: wherein there is a data stream STREAM1 representing the data being swallowed when the first event is executed (assuming that the data stream STREAM1 is a request information that needs to be set for the first independent logical cluster to be executed for data operation); similarly, wherein there is a data stream STREAM2 representing the data being swallowed when the second event is executed (assuming that the STREAM2 is a request information that needs to be set for the second independent logical cluster to be executed for data operation); similarly, wherein there is a data stream STREAM3 representing the data being swallowed when the third event is executed (assuming that the STREAM3 is a request information that needs to be set for the third independent logical cluster to be executed for data operation). More data streams are not shown in the figure.

[0085] Referring to Figure 4 , the first independent logical cluster, the second independent logical cluster, the third independent logical cluster, or more independent logical clusters belong to different physical storage space units. Therefore, when the file system reads and writes a certain cluster, the hard disk may correspond to reading and writing three or more physical storage space units.

[0086] Referring to Figure 5 , the data in the data streams STREAM1-STREAM3 have normal data such as the objects of the operation, i.e. the data itself read or stored, and generate normal caches Buff0-Buff2. The data in the STREAM1-STREAM3 have a large amount of repeated content and generate redundant caches OV1 / OV2, etc. Assuming that OV1 is a large amount of repeated content between STREAM1 / STREAM2, such as the same read operation or write operation, etc. OV2 is a large amount of repeated content between STREAM2 / STREAM3, such as the same storage grain LUN address or the same instruction information, etc. It will be found that even a simple operation will generate a large memory overhead, which is unbearable in many storage occasions. The typical one is the field of artificial neural network involving a large amount of matrix operation, and the memory overhead directly drags the operation speed of the entire system.

[0087] Referring to Figure 5 In the illustrated example, the logical cluster CLU_1 is partitioned starting at cluster logical block C0 and ending at cluster logical block C7, for a total of 8 blocks. The logical cluster CLU_2 is partitioned starting at cluster logical block C8 and ending at cluster logical block C15, for a total of 8 blocks.

[0088] Referring to Figure 5 In the illustrated example, it is identified whether an access request, such as Real_D0, accessing the memory falls within the scope of a single logical cluster, such as Real_D0 falling within cluster logical blocks C4-C7 of logical cluster CLU_1, while also finding that Real_D0 falls within cluster logical blocks C8-C11 of logical cluster CLU_2. It is apparent that the access request spans different logical clusters, CLU_1 and CLU_2.

[0089] Referring to Figure 5 In an alternative embodiment, if an access request spans different logical clusters, the different logical clusters involved in the access request are combined into a single flexible logical cluster of variable size. Since Real_D0 spans different logical clusters, CLU_1 and CLU_2, the different logical clusters involved in the access request, such as Real_D0, are combined into a single flexible logical cluster of variable size, CLU_PR0. This includes logical cluster CLU_1 having a location at C4-C7 and logical cluster CLU_2 having a location at C8-C15. Note that cluster logical blocks C4-C7 and cluster logical blocks C8-C11 cannot be combined into flexible logical cluster CLU_PR0 individually, but rather the logical clusters (e.g., CLU_1 and CLU_2) represented by cluster logical blocks C4-C7 and cluster logical blocks C8-C11, respectively, are combined into flexible logical cluster CLU_PR0 as a whole.

[0090] Referring to Figure 5 In an alternative embodiment, the repeated content within an access request, such as Real_D0, directed to different logical clusters (e.g., different logical clusters CLU_1 and CLU_2) is reorganized into a single content, and the memory is operated upon according to the reorganized access request.

[0091] Referring to Figure 5In an optional embodiment, for the same content of the access request Real_D0, such as a read operation, the first read operation information based on CLU_1 and the second read operation information based on CLU_2 are combined into a single content read operation request. For the same content of the access request Real_D0, such as a write operation, the first write operation information based on CLU_1 and the second write operation information based on CLU_2 are combined into a single content write operation request. For the same content of the access request Real_D0, such as a LUN address, the first LUN information based on CLU_1 and the second LUN information based on CLU_2 are combined into a single content LUN address operation request.

[0092] Referring to Figure 6 , for the flexible logical cluster CLU_PR0 with variable logical location, if the request Real_D0 spans different logical clusters CLU_1 and CLU_2, such as the cluster logical blocks C0-C7 of the logical cluster CLU_1 and the cluster logical blocks C8-C11 of the logical cluster CLU_2, then the different logical clusters involved in the request Real_D0 are combined into a flexible logical cluster CLU_PR0 with variable logical location, which includes the logical cluster CLU_1 with the location adjusted to C0-C7 and the logical cluster CLU_2 with the previous location C8-C15. Note that the cluster logical blocks C0-C7 and the cluster logical blocks C8-C11 cannot be combined into the flexible logical cluster CLU_PR0 individually, but the logical clusters (such as CLU_1 and CLU_2) represented by the cluster logical blocks C0-C7 and the cluster logical blocks C8-C11 are combined into the flexible logical cluster CLU_PR0 as a whole.

[0093] Referring to Figure 6In the illustrated example, it is identified whether an access request, such as Real_Dl, accessing the memory falls into the category of a single logical cluster, and the access request Real_Dl falls into the cluster logical blocks C0-C7 of the logical cluster CLU_1, while it is also found that the access request Real_Dl does not fall into any cluster logical block of other logical clusters. It is obvious that the access request does not span different logical clusters at the same time. The access request, such as Real_Dl, does not span different logical clusters, and the operation on the memory is performed according to the original access request, such as Real_Dl. The operation on the memory by the original access request includes at least a data read operation or a data write operation or a data erase operation. Alternatively, the access request, such as Real_Dl, does not span different logical clusters, and the logical cluster involved in the access request is regarded as a fixed logical cluster CLU_PR1, or the current so-called fixed logical cluster CLU_PR1 is the logical cluster itself or itself involved in the access request Real_Dl.

[0094] Referring to Figure 6 In the illustrated example, the access request Real_Dl and the access request Real_D2 coexist, which means that there are multiple accesses between the computer and the memory, and the contents of the two requests Real_Dl and Real_D2 can be the same or different, such as the former is a read operation and the latter is a write operation, or vice versa.

[0095] Referring to Figure 6 In the illustrated example, the logical cluster CLU_2 is partitioned with a start position of the cluster logical block C8 and an end position of the cluster logical block C15, and a total of 8 blocks. The logical cluster CLU_3 is partitioned with a start position of the cluster logical block C16 and an end position of the cluster logical block C23, and a total of 8 blocks.

[0096] Referring to Figure 6 In the illustrated example, it is identified whether an access request, such as Real_Dl, accessing the memory falls into the category of a single logical cluster, and the access request Real_Dl falls into the cluster logical blocks C0-C7 of the logical cluster CLU_1, while it is also found that the access request Real_Dl does not fall into any cluster logical block of other logical clusters. It is obvious that the access request does not span different logical clusters at the same time. The access request, such as Real_Dl, does not span different logical clusters, and the operation on the memory is performed according to the original access request, such as Real_Dl. The operation on the memory by the original access request includes at least a data read operation or a data write operation or a data erase operation. Alternatively, the access request, such as Real_Dl, does not span different logical clusters, and the logical cluster involved in the access request is regarded as a fixed logical cluster CLU_PR1, or the current so-called fixed logical cluster CLU_PR1 is the logical cluster itself or itself involved in the access request Real_Dl.

[0097] Referring to Figure 6In an alternative embodiment, if the access request spans different logical clusters, the different logical clusters involved in the access request are combined into one logically position variable elastic logical cluster. The request of Real_D2 spans different logical clusters CLU_2 and CLU_3, the different logical clusters involved in the access request of Real_D2 need to be combined into one logically position variable elastic logical cluster CLU_PR2. It includes logical cluster CLU_2 with position at C8-C11 and logical cluster CLU_3 with position at C16-C23. The cluster logical blocks C8-C11 and the cluster logical blocks C16-C23 cannot be combined into elastic logical cluster CLU_PR2 individually, the logical clusters (e.g. CLU_2 and CLU_3) represented by the cluster logical blocks C8-C11 and the cluster logical blocks C16-C23 need to be combined into elastic logical cluster CLU_PR2 as a whole.

[0098] Referring to Figure 6 , regarding the logically position variable elastic logical cluster CLU_PR2: if the request of Real_D2 spans different logical clusters CLU_2 and CLU_3, for example, the cluster logical blocks C8-C11, the cluster logical blocks C12-C15 of the cluster CLU_2 are aware of the access request Real_D2, at the same time, the cluster logical blocks C16-C23 of the cluster CLU_3 are aware of the access request Real_D2, then the different logical clusters involved in the access request of Real_D2 need to be combined into one logically position variable elastic logical cluster CLU_PR2, which includes logical cluster CLU_2 with position at C8-C15 and logical cluster CLU_3 with previous position at C16-C23.

[0099] Referring to Figure 6 , in an alternative embodiment, the repeated contents in the access request Real_D2 for different logical clusters (e.g. different logical clusters CLU_2 and CLU_3) are reorganized into a single content of the same kind of request, so as to perform the operation on the memory according to the reorganized access request.

[0100] Referring to Figure 7In an optional embodiment, the access request Real_D2 contains repetitive content for different logical clusters (e.g., different logical clusters CLU_2 and CLU_3), such as mode instructions. If this instruction originally recorded a first master-slave mode based on CLU_2 and a second master-slave mode based on CLU_3 in the access request's data structure, then the first and second master-slave information are merged and reorganized into a single master-slave request. Similarly, the access request Real_D2 contains repetitive content for different logical clusters (e.g., different logical clusters CLU_2 and CLU_3), such as data frame length. If the data format originally recorded a first data frame length based on CLU_2 and a second data frame length based on CLU_3 in the access request's data structure, then the first and second data format operation information are merged and reorganized into a single data frame length request.

[0101] See Figure 4 The memory SRAM or DRAM will contain the same content, which can be represented as follows: it contains a data stream STREAM1 representing the throughput when the first event is executed (assuming that the data stream STREAM1 is the information of a request that needs to be set when the first independent logical cluster is performed data operation); similarly, it also contains a data stream STREAM2 representing the throughput when the second event is executed (assuming that STREAM2 is the information of a request that needs to be set when the second independent logical cluster is performed data operation).

[0102] See Figure 7 The data streams STREAM1-STREAM3 contain normal data, such as the objects being operated on (i.e., the data being read or stored), generating normal caches Buff0-Buff2. STREAM1-STREAM3 also contain a large amount of duplicate content, generating redundant caches OV1 / OV2, etc. For example, OV1 contains a large amount of duplicate content between STREAM1 and STREAM2, such as identical read or write operations; OV2 contains a large amount of duplicate content between STREAM2 and STREAM3, such as identical LUN addresses or identical instruction information. Figure 7 The redundant caches are merged and reorganized into single-content requests of the same type, so that OV1 / OV2 appear almost once in the data stream.

[0103] See Figure 6, will find that any storage operation will no longer generate a huge additional memory overhead, regardless of the storage occasion, which is extremely respected, saving memory open to the entire computer storage high-speed operation. The various hardware parts of the computer include interface modules and memory modules, etc., which originally swallow the same or repeated content according to the traditional scheme in this paper, which is greatly compressed and greatly reduced, which will greatly improve the computing performance and memory performance of the computer system and release the interface bandwidth occupied by the amount of redundant information. The interface SATA or PCIe / NVMe no longer needs to spend a lot of resources to transport the accompanying redundant information of the access request information. The memory MMRY involved controller or logic control unit (command & control logic) also does not need to process repeated storage operations and various repeated access information. Thus, the storage performance is significantly improved. The computer and memory-related data operations involved in this paper can be considered as a realizable way of in-memory computing.

[0104] Referring to Figure 1 , in optional embodiments, the operation category of the access request such as Real_D1, Real_D2 on the memory at least includes data read operation or data write operation or data erase operation. The memory is, for example, a solid state disk such as Figure 6 , especially a flash-based solid state disk. The memory MMRY maps the logical address carried by the original access request or the access request after reorganization to its internal physical address. The case of the original access request: under this condition, if the access request does not cross different logical clusters, the operation on the memory is performed according to the original access request. The case of the access request after reorganization: under this condition, if the access request crosses different logical clusters, the different logical clusters involved in the access request are combined into a logically variable elastic logical cluster, and the repeated content in the access request for different logical clusters can be reorganized into a single content of the same request (i.e. the access request after reorganization), so that the operation on the memory is performed according to the access request after reorganization.

[0105] Referring to Figure 5 , in optional embodiments, for the logical cluster covered by the elastic logical cluster but not involved in the current access request, the information corresponding to its logical address is executed with the same operation as the current access request, and the execution time of the same operation is synchronized with the execution time of the current access request.

[0106] Referring to Figure 5In a specific embodiment, for a logical cluster such as CLU_1 (in detail, cluster logical blocks of the logical cluster CLU_1 such as cluster logical blocks C0-C3) that is covered by a resilient logical cluster such as CLU_PR0 but is not involved by a current access request such as Real_D0, then the information corresponding to the logical addresses of the cluster logical blocks such as C0-C3 of the logical cluster CLU_1 is executed the same operation (e.g. read / write, etc.) as the current access request such as Real_D0, and the execution time of the same operation (e.g. read / write, etc.) is synchronized with the execution time of the current access request such as Real_D0.

[0107] Referring to Figure 5 In a more specific embodiment, for a cluster logical block such as C0-C3 of a logical cluster such as CLU_1 that is covered by a resilient logical cluster such as CLU_PR0 but is not involved by a current access request such as Real_D0 (in detail, a cluster logical block of the logical cluster CLU_1 that is covered by the resilient logical cluster but is not involved by the current access request), then the information corresponding to the logical addresses of the cluster logical blocks such as C0-C3 of the logical cluster CLU_1 is executed the same operation (e.g. read / write, etc.) as the current access request such as Real_D0, and the execution time of the same operation (e.g. read / write, etc.) is synchronized with the execution time of the current access request such as Real_D0. For example, the information corresponding to the cluster logical blocks C0-C3 is executed the same operation as the information corresponding to the cluster logical blocks C4-C7, C8-C11 that are covered by the resilient logical cluster such as CLU_PR0 and are involved by the current access request such as Real_D0, and the execution time of the same operation is synchronized with the execution time of the current access request such as Real_D0 (e.g. for C4-C7, C8-C11). The advantage is that the adaptation relationship of making the cluster corresponding to the sector can be followed, the physical space partition is aligned with the logical partition of the computer, the storage space is not wasted, and the high speed of data read / write operation is guaranteed. And the interface speed of the mainstream PICe / NVMe is balanced. The data operation is implemented on all cluster logical blocks of the logical cluster on average, rather than being biased to always perform data operation on a small number of cluster logical blocks and end the life of the entire logical cluster where the small number of cluster logical blocks are located in advance.

[0108] Referring to Figure 5 In an optional embodiment, the total number of logical clusters contained in the resilient logical cluster CLU_PR0 and the like is a positive integer multiple of a single logical cluster (e.g. Figure 6 2 times or Figure 5The change of the logical location of the elastic logical cluster is implemented in a way that covers the whole one or several logical clusters at one time (e.g. 1 to 2 times of the size of the elastic logical cluster). The change of the logical location of the elastic logical cluster does not allow covering only half of the logical cluster, or covering less than the total number of cluster logical blocks (e.g. 8) in a single logical cluster (e.g. 1-7 cluster logical blocks).

[0109] Referring to Figure 5 In an optional embodiment, the logical location of the elastic logical cluster CLU_PR0 is implemented in a way that covers the whole two logical clusters, e.g. CLU_1 and CLU_2. The change of the logical location of the elastic logical cluster does not allow covering less than the total number of cluster logical blocks (e.g. 8) in a single logical cluster CLU_1 (e.g. 4 cluster logical blocks C4-C7 in the logical cluster CLU_1). The change of the logical location of the elastic logical cluster does not allow covering less than the total number of cluster logical blocks (e.g. 8) in a single logical cluster CLU_2 (e.g. 4 cluster logical blocks C8-C11 in the logical cluster CLU_2).

[0110] Referring to Figure 5 In an optional example, if the access request spans different logical clusters, the different logical clusters involved by the access request are combined into one elastic logical cluster with variable logical location, and the contents of the access request that are different for different logical clusters but repetitive are reorganized into a single content of the same kind (the same kind of requests for different logical clusters at least include read requests or write requests or erase requests), and the operation is performed on the memory according to the reorganized access request.

[0111] Referring to Figure 5 In an optional embodiment, in the elastic logical cluster, the addresses of the different logical clusters involved by the access request are continuous, or they are separated by logical clusters not involved by the access request.

[0112] Referring to Figure 6 In an optional example, the addresses of the different logical clusters (e.g. CLU_1 and CLU_2) involved by the access request Real_D0 in the elastic logical cluster CLU_PR0 are continuous. In Figure 6 assuming that the request of Real_D2 does not include the logical cluster CLU_2 but only the logical cluster CLU_3, in Figure 5In the case where Real_Dl and D2 requests are assumed to belong to the same operation, the addresses of CLU 1 of Real_Dl request and CLU 3 of Real_D2 request are spaced apart by a logical cluster, CLU 2, which is not involved in the access request Real_Dl and D2. It is assumed that Real_Dl and D2 requests belong to the same operation: for example, Real_Dl and Real_D2 belong to the same read operation or write operation, etc. It is an optional scheme that both of them are combined into a single operation (the access request can be noted Real_Dl / D2), or it is also an optional scheme that both of them belong to two different operations (the access request can be noted Real_Dl and Real_D2).

[0113] Referring to Figure 6 In the optional embodiment, in the elastic logical cluster, the addresses of the cluster logical blocks of the different logical clusters involved in the access request are continuous, or, the addresses of the cluster logical blocks of the different logical clusters involved in the access request are spaced apart by the logical cluster blocks not involved in the access request. From the embodiment, it can be seen that the adaptability of the method for improving the storage performance is very good. The scheme for improving the storage performance is applicable to the case where the addresses of the logical clusters are continuous (or the addresses of the cluster logical blocks of the logical clusters are continuous) and also applicable to the case where the addresses of the logical clusters are discontinuous (or the addresses of the cluster logical blocks of the logical clusters are discontinuous). This consideration is mainly based on the fact that the data in the actual storage environment can be randomly in a continuous distribution state or in a discontinuous distribution state in the storage space.

[0114] Referring to Figure 6 In the optional embodiment, it is assumed that the Real_D2 request has included the logical cluster CLU 2 and included the logical cluster CLU 3, in Figure 6 In the case where Real_Dl and D2 requests are assumed to belong to the same operation, the addresses of the cluster logical blocks C0-C7, C8-C15, C16-C23 of the different logical clusters such as CLU 1 to CLU 3 involved in the access request are continuous rather than discontinuous, which is an optional embodiment. The access request at this time belongs to Real_Dl / D2.

[0115] Referring to Figure 6 In the optional embodiment, it is assumed that the Real_D2 request has not included the logical cluster CLU 2 but only included the logical cluster CLU 3, in Figure 6 In the case where Real_Dl and D2 requests are assumed to belong to the same operation, the addresses of the cluster logical blocks C0-C7, C16-C23 of the different logical clusters such as CLU 1 and CLU 3 involved in the access request are discontinuous and spaced apart by the logical clusters or logical cluster blocks not involved in the access request such as C8-C15. This is also an optional embodiment and the access request at this time belongs to Real_Dl / D2.

[0116] Referring to Figure 6 In optional embodiments, when the memory MMRY receives a series of access requests, the memory MMRY can first determine whether the minimum command execution units, e.g., LUNs, of the series of access requests, e.g., Real_D1 and Real_D2, are consistent and determine the operation categories of the series of access requests, e.g., Real_D1 and Real_D2. The series of access requests, e.g., Real_D1 and Real_D2, with the same minimum command execution units and the same operation categories are synchronously executed once with the corresponding operations according to the physical addresses mapped by the logical addresses of the series of access requests and according to the operation categories of the series of access requests, instead of sequentially executing the series of access requests, e.g., executing Real_D1 first and then executing Real_D2. Real_D1 and D2 in this example are assumed to access the same LUN and belong to the same category of access requests, e.g., both are read operations or both are write operations. Real_D1 and D2 are synchronously executed once with the corresponding operations, e.g., read operations, according to the physical addresses mapped by the logical addresses of Real_D1 and D2 and according to the operation categories of Real_D1 and D2, e.g., read operations. The requests of Real_D1 and D2 are synchronously executed in this example, instead of sequentially executed in the conventional scheme. The main advantages are to enhance the robustness of data operations, to reduce the latency of data operations, and to improve the balance of the overall storage space of the memory.

[0117] Referring to Figure 6 In optional embodiments, when the memory MMRY receives a series of access requests, the memory MMRY can first determine whether the minimum command execution units, e.g., LUNs, of the series of access requests, e.g., Real_D1 and Real_D2, are consistent and determine the operation categories of the series of access requests, e.g., Real_D1 and Real_D2. The series of access requests, e.g., Real_D1 and Real_D2, with the same minimum command execution units and different operation categories are sequentially executed according to the physical addresses mapped by the logical addresses of the series of access requests and according to the operation categories of the series of access requests. Real_D1 and D2 in this example are assumed to access the same LUN and belong to different categories of access requests, e.g., one is a read operation and the other is a write operation. Real_D1 and D2 are sequentially executed according to the physical addresses mapped by the logical addresses of Real_D1 and D2 and according to the operation categories of Real_D1 and D2, e.g., read operation and write operation, respectively. The requests of Real_D1 and D2 are sequentially executed in this example, e.g., executing Real_D1 first and then executing Real_D2. The main advantages are to enhance the robustness of data operations, to reduce the latency of data operations, and to improve the balance of the overall storage space of the memory.

[0118] Referring to Figure 6In an optional embodiment, when the memory MMRY receives a plurality of consecutive access requests, it can first determine whether the minimum command execution units of the plurality of access requests (e.g., Real_D1 and Real_D2) are consistent and determine the operation categories of the plurality of access requests (e.g., Real_D1 and Real_D2). The series of access requests (e.g., Real_D1 and Real_D2) having different minimum command execution units and the same or different operation categories are executed synchronously according to the physical addresses mapped by the respective logical addresses and according to their operation categories. Real_D1 and D2 in an example are assumed to access different LUN1 and LUN2 and belong to the same category of access requests, e.g., they are both read operations or they are both write operations. Real_D1 and D2 are executed synchronously according to the physical addresses mapped by the respective logical addresses and according to their operation categories (e.g., read), and the requests of Real_D1 and D2 are executed synchronously but not sequentially in the conventional scheme in this example. In contrast, Real_D1 and D2 in an example are assumed to access different LUN1 and LUN2 and belong to different categories of access requests, e.g., one of them is a write operation and the other is a read operation. Real_D1 and D2 are executed synchronously according to the physical addresses mapped by the respective logical addresses and according to their operation categories (e.g., write and read, respectively), and the requests of Real_D1 and D2 are executed synchronously but not sequentially in the conventional scheme in this example. The main advantages are to enhance the robustness of data operations and to reduce the latency of data operations, and to improve the balance of the overall storage space of the memory.

[0119] Referring to Figure 5 , the method for improving storage performance, in combination with Figure 5 , mainly includes, e.g., identifying at the computer end or the memory end whether an access request falls within a single logical cluster of the memory, combining different logical clusters involved in the access request into a flexible logical cluster with variable logical positions if the access request spans different logical clusters, and reorganizing repeated contents in the access request for different logical clusters into a single content, and performing operations on the memory according to the reorganized access request. As mentioned above, when the memory receives a plurality of consecutive access requests, the series of access requests having the same minimum command execution units and the same operation category are executed synchronously according to the physical addresses mapped by the respective logical addresses and according to their operation categories, thereby replacing the sequential execution of the plurality of access requests by the memory.

[0120] Referring to Figure 6In optional embodiments, if the access request spans different logical clusters, the different logical clusters involved in the access request are combined into a single logically variable elastic logical cluster, and the repeated contents in the access request that are directed to different logical clusters are reorganized into a single homogeneous request, and the memory is operated according to the reorganized access request. The address ordering of the cluster logical blocks of the different logical clusters in the elastic logical cluster is disordered, and the cluster logical blocks that need to perform the operation (i.e., operate the memory according to the reorganized access request) implement the operation in sequence according to the disordered addresses based on the address ordering disorder. If the preset verification between the data information of any cluster logical block and the operation does not match during the implementation of the operation, the operation in the elastic logical cluster is immediately canceled until all cluster logical blocks that need to perform the operation return to the original state. Here, the operation is canceled in the middle is essentially equivalent to the operation failing, and the file system needs to automatically cancel this operation, and the data is restored to the original state. In combination with Figure 5 .

[0121] Referring to Figure 5For example, if the access request Real_D0 spans the logical clusters CLU_1 and CLU_2, the logical clusters CLU_1 and CLU_2 involved in the access request are combined into a logically position variable elastic logical cluster CLU_PR0, and the contents of the access request which are different in the different logical clusters but repetitive are reorganized into a single content, and the operation is performed on the memory according to the reorganized access request. In an optional embodiment, for the elastic logical cluster CLU_PR0, the original addresses of the cluster logical blocks of the different logical clusters, for example, CLU_1 and CLU_2, are disordered, and a small number of cluster logical blocks, for example, C0-C9, are taken as examples, and the actual cluster logical blocks are not limited thereto. The cluster logical blocks which need to perform the operation, for example, C0-C9, are sequentially implemented according to the disordered addresses under the condition of address disordering. The disordered addresses of the address disordering are, for example, C0, C3, C6, C9, C1, C4, C7, C2, C5, and C8. In contrast, the original addresses of the address disordering are, for example, C0, C1, C2, C3, C4, C5, C6, C7, C8, and C9. It should be noted that the rule of the address disordering is not limited, but the same logical cluster, for example, CLU_1 or CLU_2, should avoid the situation that the operation is directly performed without data recovery. If the preset verification between the data information of any cluster logical block, for example, C9, and the operation does not match during the implementation of the operation (for example, a write operation or an erase operation or data covering), the operation is cancelled in the elastic logical cluster to all the cluster logical blocks, for example, C0, C3, C6, and C9, which need to perform the operation, and the cluster logical blocks which have already performed the operation still need to return to the original state, and the cluster logical blocks which have not performed the operation do not continue to perform the operation. The address disordering can effectively avoid the situation that the cluster logical blocks arranged in sequence in the same logical cluster perform the operation and lose all the original information. The preset verification is, for example, that a given operation (for example, a digital quantity A) and the data information (for example, a digital quantity B) as the operation object perform a preset verification operation (for example, an XOR check), and if the preset verification between the data information of any cluster logical block and the operation does not match, the operation of all the cluster logical blocks C0-C9 is cancelled. The verification operation using the XOR check as an example is only an optional solution and is not a limiting solution.

[0122] Referring to Figure 5, according to the foregoing, if the verification between the data and operation instructions of any cluster logical block during the execution of the operation does not match, the operation is immediately cancelled. Cancel the operation in the middle, equivalent to the operation fails, then set the file system to automatically cancel this operation, and restore the data to the original state. Similar data overlay, if the data overlay exits in the middle, allow active cancellation of data overlay and actively guide the automatic cancellation of this data overlay operation. The reason is: the current technical conditions cannot ensure that the storage operation action between the computer and the memory is always 100% accurate. The operation instructions themselves or the combination of operation instructions loaded on the data or any information (such as operation instructions and operation objects) in the middle process of construction, transmission, analysis between different devices, etc. Many scenarios can cause them to fail in storage operation action. The present application combines different logical clusters involved in the access request into a flexible logical cluster with variable logical position, and the data error of any cluster logical block of any logical cluster will cause the entire data of the flexible logical cluster to be wrong, such as Figure 2 The fine cluster logical block Log1 of the cluster logical block C7 will cause the entire data of the flexible logical cluster CLU_PR0 to be wrong due to a single access request operation failure (such as erasing or writing), not just limited to the logical cluster C7 itself. This situation usually causes irreversible data error operation consequences for the entire data in the memory MMRY. Combining different logical clusters involved in the access request into a flexible logical cluster with variable logical position, and reorganizing the repeated contents in the access request into single content, and then performing the operation on the memory according to the reorganized access request: Obviously, although this scheme can bring advantages, it will also bring disadvantages. The main reason for the disadvantage is that Figure 5 If the access request is not the reorganized access request, such disadvantages can be avoided, such as the first access request operating CLU_1 and then operating CLU_2 by the second access request after the operation of CLU_1 is completed. If CLU_1 and CLU_2 are not combined into a flexible logical cluster with variable logical position, there will be no data error consequences for the entire data in the memory. CLU_1 error is only its own error and will not affect CLU_2, and CLU_2 error will not affect CLU_1. On the contrary, according to the reorganized access request to perform the operation on the memory, CLU_1 error may affect CLU_1 to CLU_4096 or even more space of the flexible logical cluster CLU_PR0; CLU_2 error may affect CLU_1 to CLU_4096 or even more space of the flexible logical cluster CLU_PR0. Avoiding these disadvantages may lose the advantages mentioned above, obviously a difficult problem appears here and how to eliminate the disadvantages is a doubt to be solved. The foregoing scheme involving random addressing is a feasible scheme.

[0123] See Figure 5According to the foregoing, if the access request crosses different logical clusters and the different logical clusters involved in the access request are combined into a logically variable elastic logical cluster, some disadvantages will be brought. In the same request, the repeated contents in the access request are reorganized into single contents, and the operation on the memory is performed according to the reorganized access request, which also brings related disadvantages. The disadvantage event is that when any logical cluster in the elastic logical cluster occurs an error during the execution of the operation, the entire logical cluster in the elastic logical cluster will be induced to occur an error at the same time and cause irreversible data loss or error. Note that the combination of different single logical clusters as a whole and the synchronous execution of the reorganized access request of different single logical cluster wholes are the root causes of the disadvantage event. The main use of the foregoing solution is to avoid the occurrence of the above disadvantage event.

[0124] Referring to Figure 7 According to the foregoing, the measure is equivalent to: performing the operation every several cluster logical blocks and leaving a series of reserved cluster logical blocks without performing the operation, until the operation flows to the end cluster logical block and then performing the same operation on the reserved cluster logical block again. This is also a data operation verification method that disrupts the cluster logical block sorting rule, that is, the correctness of the data operation is not verified according to the original logical cluster sorting, but the address sorting of the cluster logical blocks of different logical clusters in the elastic logical cluster is disrupted, and the cluster logical blocks that need to perform the operation are verified according to the address disruption based on the address sorting. The advantage is that there is still an opportunity to cancel the misoperation during the discovery of the misoperation, and the solution provided in this paper provides multiple verifications for the operation, and further ensures the complete correctness of the operation. This is an advantage that the traditional storage operation solution does not have and is difficult to achieve. Here, multiple verifications are embodied in providing an opportunity for each cluster logical block to provide a verification and providing an opportunity for each logical cluster to provide at least one data recovery and regression. This is determined based on the specific solution of performing the operation on the memory.

[0125] Referring to ​ Regarding the method for improving storage performance, those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, which executes the steps including the above-mentioned method embodiments when executed. The storage medium includes: ROM, RAM, disk or optical drive, and various media that can store program codes.

[0126] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and practice described. Accordingly, all suitable modifications and equivalents should be considered as falling within the scope of the application as defined by the claims that follow.

Claims

1. A method of improving storage performance, characterized by, Comprising: identifying whether an access request accessing the memory falls into a single logical cluster, performing an operation on the memory according to the original access request if the access request does not cross different logical clusters; otherwise, if the access request crosses different logical clusters, combining the different logical clusters involved in the access request into a logically position-variable elastic logical cluster, and reorganizing the contents of the access request that are internal to the different logical clusters but repetitive into a single content of the same kind of request, and performing the operation on the memory according to the reorganized access request, wherein the address ordering of the cluster logical blocks of the different logical clusters in the elastic logical cluster is disordered, and the cluster logical blocks that need to perform the operation are sequentially implemented according to the disordering of the address ordering on the condition that the address ordering is disordered, and if the preset verification between the data information of any cluster logical block and the operation does not match during the implementation of the operation, the operation is cancelled in the elastic logical cluster until all the cluster logical blocks that need to perform the operation return to the original state.

2. The method of claim 1, wherein: the operation category of the access request on the memory includes at least a data read operation or a data write operation or a data erase operation.

3. The method of claim 1, wherein: the type of the memory includes a flash-based solid state disk, and the memory maps the logical addresses carried by the original access request or the reorganized access request to the physical addresses inside the memory.

4. The method of claim 1, wherein: the total number of logical clusters included in the elastic logical cluster is a positive integer multiple of a single logical cluster, and the change of the logical position is implemented in a manner of covering one or more complete logical clusters at a time.

5. The method of claim 1, wherein: for the logical clusters covered by the elastic logical cluster but not involved in the current access request, the same operation as the current access request is performed on the information corresponding to the logical addresses of the logical clusters, and the execution time of the same operation is synchronized with the execution time of the current access request.

6. The method of claim 1, wherein: the same kind of request for different logical clusters includes at least a read request or a write request or an erase request.

7. The method of claim 1, wherein: in the elastic logical cluster, the addresses of the different logical clusters involved in the access request are continuous, or the addresses of the different logical clusters involved in the access request are separated by the logical clusters not involved in the access request.

8. The method of claim 1, wherein: when the memory receives a plurality of the access requests in succession, it first determines whether the target minimum command execution units of the plurality of the access requests are consistent, and determines the operation categories of the plurality of the access requests respectively; a series of the access requests with the same minimum command execution units and the same operation categories are synchronously executed once with a corresponding operation according to the physical addresses mapped by the logical addresses and according to the operation categories, thereby replacing the sequential execution of the plurality of the access requests by the memory.

9. The method of claim 1, wherein: The memory receives a plurality of consecutive access requests, and determines whether the target minimum command execution units of the access requests are consistent and the operation categories of the access requests are different; a series of access requests with the same minimum command execution units and different operation categories are executed in sequence according to the physical addresses mapped by the logical addresses and the operation categories; or a series of access requests with different minimum command execution units and the same or different operation categories are executed synchronously according to the physical addresses mapped by the logical addresses and the operation categories.

10. A method of improving storage performance, characterized by, The method comprises: determining whether an access request falls within a single logical cluster of a memory, combining different logical clusters involved in the access request into a flexible logical cluster with variable logical positions if the access request spans different logical clusters, and reorganizing repeated contents in the access request for different logical clusters into a single content, so as to perform an operation on the memory according to the reorganized access request, wherein the addresses of cluster logical blocks of different logical clusters in the flexible logical cluster are disordered, and the cluster logical blocks that need to perform the operation are sequentially implemented according to the disordered addresses, and if the preset verification between the data information of any cluster logical block and the operation is inconsistent during the implementation of the operation, the operation is cancelled in the flexible logical cluster until all the cluster logical blocks that need to perform the operation return to the original state; when the memory receives a plurality of consecutive access requests, a series of access requests with the same minimum command execution units and the same operation category are synchronously executed once for a corresponding operation according to the physical addresses mapped by the logical addresses and the operation categories, instead of sequentially executing the access requests by the memory.

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