Memory device and driving method of sensing device included in the memory device

Abstract

A memory device includes: a memory cell array including a first memory cell connected to a bit line, and a second memory cell connected to a complementary bit line; a bit line sense amplifier including a sense bit line and a sense complementary bit line; a first charge transfer transistor between the bit line and the sense bit line; a second charge transfer transistor between the complementary bit line and the sensing complementary bit line; a first pre-charge transistor that pre-charges the bit line and the complementary bit line with a first pre-charge voltage; a second pre-charge transistor pre-charging the sensing bit line and the sensing complementary bit line with a second pre-charge voltage; a first transfer gate transistor supplying a first transfer gate voltage to the first charge transfer transistor; and a second transfer gate transistor supplying a second transfer gate voltage to the second charge transfer transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0078783 filed on June 20, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0143896 filed on October 25, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a memory device and a method for driving a sensing device included in the memory device. Background Art

[0004] Semiconductor memory devices are used for data storage. Random Access Memory (RAM) is a volatile memory device that is mainly used as the main memory in computers. Dynamic Random Access Memory (DRAM) is a subset of RAM, which is also volatile and consists of memory cells. In order to effectively sense the data stored in these cells, the bit line and the complementary bit line are precharged with a precharge voltage. Subsequently, a charge sharing operation is performed so that a voltage difference is generated between the bit line and the complementary bit line. This voltage difference (referred to as dVBL) is then amplified by a sense amplifier to sense the data stored in the memory cell.

[0005] On the other hand, when precharging the bit line and the complementary bit line, setting the precharge voltage to the ground voltage VSS or the power supply voltage VDD can increase the sensing margin compared to setting the amplitude of the precharge voltage to half the power supply voltage VDD. However, this method may cause an imbalance caused by data polarity. Summary of the invention

[0006] Embodiments of the present disclosure provide a memory device capable of enhancing the performance of sensing data stored in a memory cell.

[0007] Embodiments of the present disclosure also provide a method for driving a sensing device, which can improve the performance of sensing data stored in a memory cell.

[0008] According to an embodiment of the present disclosure, a memory device is provided, comprising: a memory cell array, comprising a first memory cell connected to a bit line, and a second memory cell connected to a complementary bit line; a bit line sense amplifier, comprising a sense bit line connected to the bit line, and a sense complementary bit line connected to the complementary bit line, wherein the bit line sense amplifier is configured to: output a signal of the sense bit line to the bit line and output a signal of the sense complementary bit line to the complementary bit line to sense data stored in the first memory cell and the second memory cell; a first charge transfer transistor, connected between the bit line and the sense bit line, wherein a gate of the first charge transfer transistor receives a first signal via a first node; a second charge transfer transistor, connected between the complementary bit line and the sense bit line, wherein a gate of the first charge transfer transistor receives a first signal via a first node; and a second charge transfer transistor, connected between the complementary bit line and the sense bit line. line and a sensing complementary bit line, wherein the gate of the second charge transfer transistor receives a second signal via a second node; a first precharge transistor is configured to precharge the bit line and the complementary bit line with a first precharge voltage; a second precharge transistor is configured to precharge the sensing bit line and the sensing complementary bit line with a second precharge voltage different from the first precharge voltage; a first transfer gate transistor is configured to provide a first transfer gate voltage to the gate of the first charge transfer transistor in response to a first control signal; and a second transfer gate transistor is configured to provide a second transfer gate voltage different from the first transfer gate voltage to the gate of the second charge transfer transistor in response to the first control signal.

[0009] According to an embodiment of the present disclosure, a memory device is provided, comprising: a memory cell array, comprising a first memory cell connected to a bit line, and a second memory cell connected to a complementary bit line; a bit line sense amplifier, comprising a sense bit line connected to the bit line, and a sense complementary bit line connected to the complementary bit line, wherein the bit line sense amplifier is configured to: output a signal of the sense bit line to the bit line and output a signal of the sense complementary bit line to the complementary bit line to sense data stored in the first memory cell and the second memory cell; a first charge transfer transistor, connected between the bit line and the sense bit line, and selected by a first signal provided to a first node; a second charge transfer transistor A transistor connected between a complementary bit line and a sensing complementary bit line and selected by a second signal connected to a second node; and a plurality of transfer gate transistors, configured to: in response to the bit line sensing amplifier sensing the data stored in the first storage unit, provide a first transfer gate voltage to the gate of the first charge transfer transistor, and provide a second transfer gate voltage lower than the first transfer gate voltage to the gate of the second charge transfer transistor; and configured to: in response to the bit line sensing amplifier sensing the data stored in the second storage unit, provide the second transfer gate voltage to the gate of the first charge transfer transistor, and provide the first transfer gate voltage to the gate of the second charge transfer transistor.

[0010] According to an embodiment of the present disclosure, a method for driving a sensing device is provided, wherein the sensing device is configured to sense data of a first storage unit connected to the bit line and a second storage unit connected to the complementary bit line by using a bit line sensing amplifier including a sensing bit line and a sensing complementary bit line, a first charge transfer transistor connected to the sensing bit line and the bit line, and a second charge transfer transistor connected to the sensing complementary bit line and the complementary bit line, the method comprising: precharging the sensing bit line and the sensing complementary bit line using a first precharge voltage; providing a first transfer gate voltage to a gate of the first charge transfer transistor, and providing a second transfer gate voltage different from the first transfer gate voltage to a gate of the second charge transfer transistor; and applying an isolation voltage greater than the amplitude of each of the first transfer gate voltage and the second transfer gate voltage to the gate of the first charge transfer transistor and the gate of the second charge transfer transistor, and sensing data stored in at least one of the first storage unit and the second storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram for illustrating a memory device according to some embodiments.

[0013] Figure 2 It is used to illustrate Figure 1 Diagram of a storage unit.

[0014] Figure 3 is a diagram for explaining a memory cell array to which a bit line sense amplifier according to some embodiments is applied.

[0015] Figure 4 is a diagram illustrating a memory device including a sensing device according to some embodiments.

[0016] Figure 5 It shows Figure 4 Circuit diagram of a sensing device and a charge transfer transistor driving circuit.

[0017] Figure 6 yes Figure 4 Circuit diagram of a voltage generator.

[0018] Figure 7 and Figure 8 It is used to illustrate Figure 6 Diagram of the operation of the voltage generator.

[0019] Fig. 9 is a circuit diagram of a voltage generator according to some other embodiments.

[0020] Fig.10 is a circuit diagram of a timing generator according to some embodiments.

[0021] Fig.11 and Fig.12 It is used to illustrate Fig.10 Diagram of the operation of the timing generator.

[0022] Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 is a diagram for explaining a method of driving a sensing device according to some embodiments.

[0023] Fig.23 is a circuit diagram illustrating a sensing device and a charge transfer transistor driving circuit according to some other embodiments.

[0024] Fig.24 and 25 It shows Fig.23 A timing diagram of the operation of the bit line sense amplifier.

[0025] Fig.26 is a diagram for explaining a stacked memory device according to some embodiments.

[0026] Fig. 27 is a diagram for explaining a semiconductor package according to some embodiments.

[0027] Fig.28 is a diagram for explaining a memory module and a memory controller including a memory device according to some embodiments.

[0028] Fig.29 is a diagram for illustrating a computer system including a memory device according to some embodiments. DETAILED DESCRIPTION

[0029] Hereinafter, a memory device and a method of driving a sensing device included in the memory device according to some embodiments will be described with reference to the accompanying drawings.

[0030] Figure 1 is a block diagram for illustrating a memory device according to some embodiments.

[0031] Reference Figure 1, the memory device 100 may be a memory device based on semiconductor elements. For example, the memory device 100 may be a dynamic random access memory (DRAM), such as a double data rate static DRAM (DDR SDRAM), a single data rate SDRAM (SDR SDRAM), a low power DDR SDRAM (LPDDR SDRAM), a low power SDR SDRAM (LPSDRSDRAM), and a direct Rambus DRAM (RDRAM), or may be any volatile memory device. Specifically, the memory device 100 may be a device to which a standard specification such as DDR4 or DDR5 is applied.

[0032] In an embodiment, the number of data pins to which the DDR4 or DDR5 standard specification is applied may be 4, 8, or 16, and the number of data pins of the memory device 100 according to the present disclosure may be 16. Hereinafter, the description of the number of data pins of the memory device 100 used in the description of this specification may be applied according to the standard specification of a dynamic random access memory, but is not necessarily limited thereto.

[0033] The memory device 100 may output data through a data line DQ in response to a command CMD, an address ADDR, and a control signal received from an external device (e.g., a memory controller). The memory device 100 may include a memory cell array 110, a command decoder 112, a control logic 114, an address buffer 120, a row decoder 130, a column decoder 140, a sense amplifier array 150, a data input / output circuit 160, a voltage generator 170, and a charge transfer transistor drive circuit 180.

[0034] The memory cell array 110 includes a plurality of memory cells provided in a matrix form arranged in rows and columns. The memory cell array 110 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0035] According to some embodiments, the memory cells may include normal memory cells storing data and redundant memory cells. The redundant memory cells are used to rescue defective normal memory cells.

[0036] The command decoder 112 decodes commands received from the memory controller, for example, a write enable signal ( / WE), a row address strobe signal ( / RAS), a column address strobe signal ( / CAS), a chip select signal ( / CS), etc. The command CMD may include an activate command, a read command, a write command, a precharge command, etc.

[0037] The control logic 114 may generate various control signals required for access operations (e.g., write operations, read operations, precharge operations, etc.) to the memory cell array 110 in response to the decoded commands. For example, the control logic 114 may generate a precharge equalization signal PEQ and a precharge equalization signal PEQi based on the decoded commands. The control logic 114 may generate a voltage control signal CTRL_Vol and transmit the voltage control signal CTRL_Vol to the voltage generator 170, and may generate control signals CS1, CS2, and CS3 and transmit the control signals CS1, CS2, and CS3 to the charge transfer transistor drive circuit 180. Figure 5 etc. describe the control signals CS1 , CS2 , and CS3 generated by the control logic 114 .

[0038] The address buffer 120 receives an address ADDR from a memory controller as an external device. The address ADDR includes a row address RA for addressing a row of the memory cell array 110 and a column address CA for addressing a column of the memory cell array 110. The address buffer 120 may transmit the row address RA to the row decoder 130, and may transmit the column address CA to the column decoder 140.

[0039] The row decoder 130 may select any one of a plurality of word lines WL connected to the memory cell array 110. The row decoder 130 may decode the row address RA received from the address buffer 120, select any one of the word lines corresponding to the row address RA, and activate the selected word line. At the time of word line activation, in other words, at the time of word line enable operation, a high power supply voltage VPP higher than the power supply voltage VDD may be applied to the gate of the access transistor of the memory cell.

[0040] The column decoder 140 may select a specific bit line from among the plurality of bit lines BL of the memory cell array 110. The column decoder 140 may decode the column address CA received from the address buffer 120 and select a specific bit line corresponding to the column address CA.

[0041] The sense amplifier array (S / A) 150 is connected to the bit line BL of the memory cell array 110. The sense amplifier array 150 senses a voltage change of a selected bit line among the plurality of bit lines BL, and amplifies and outputs the sensed voltage change. The data input / output circuit 160 can output data output from the sense amplifier array 150 based on the sensed and amplified voltage to the outside through the data line DQ.

[0042] Although the following will refer to Figure 31, but the sense amplifier array 150 may include a plurality of bit line sense amplifiers BLSA. The bit line sense amplifier BLSA may be connected to a bit line pair including a bit line BL and a complementary bit line BLB to sense and amplify a potential appearing on the bit line. Figure 3 and Figure 4 Describe the specific connections between the bit line sense amplifier and the bit line pair.

[0043] The sense amplifier array 150 may receive a precharge equalization signal PEQ and a precharge equalization signal PEQi from the control logic 114. The sense amplifier array 150 may precharge the bit line BL and the complementary bit line BLB according to the precharge equalization signal PEQ. The sense amplifier array 150 may precharge the sense bit line SBL and the sense complementary bit line SBLB according to the precharge equalization signal PEQi. Figure 5 etc. describe the precharge operation.

[0044] The voltage generator 170 may generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_Vol. For example, the voltage generator 170 may generate a transmission gate voltage VTG1, a transmission gate voltage VTG2, and an isolation voltage VISO required for a sensing operation of a bit line sense amplifier BLSA included in the sense amplifier array 150, and provide the voltages VTG1, VTG2, and VISO to the charge transfer transistor driving circuit 180.

[0045] Figure 2 It is used to illustrate Figure 1 Diagram of a storage unit.

[0046] Also refer to Figure 1 and Figure 2 , memory cells MC included in the memory cell array 110 are connected to word lines WL and bit lines BL.

[0047] The memory cell MC is composed of a cell transistor MTR and a cell capacitor C. The memory device 100 can perform a read operation or a refresh operation based on the amount of charge in the cell capacitor C included in the memory cell MC. For example, the bit line BL connected to the memory cell MC is precharged with a precharge voltage VBL. Thereafter, when the word line WL is activated, a charge sharing operation occurs between the charge of the bit line BL charged with the precharge voltage VBL and the charge of the cell capacitor C of the memory cell MC. Due to the charge sharing operation, the voltage of the bit line BL can be reduced or increased by a voltage change amount V from the precharge voltage VBL. Each of the bit line sense amplifiers BLSA in the sense amplifier array 150 can sense the voltage change amount V and amplify the voltage change amount V.

[0048] Figure 3is a diagram for explaining a memory cell array to which a bit line sense amplifier according to some embodiments is applied.

[0049] Reference Figure 3 , the memory device 100 includes a plurality of memory cell arrays 110_1 to 110 — n and a plurality of bit line sense amplifiers 150_1 to 150 — n.

[0050] Each of the plurality of bit line sense amplifiers 150_1 to 150_n may include a plurality of bit line sense amplifiers BLSA. Each of the plurality of bit line sense amplifiers BLSA may be implemented as Figure 1 and Figure 2 The sense amplifier array 150 described in .

[0051] The plurality of bit line pairs BL and BLB connected to the plurality of memory cell arrays 110_1 to 110_n may be connected to a plurality of bit line sense amplifiers BLSA, respectively. Figure 5 As described, each bit line sense amplifier BLSA may be a cross-coupled differential sense amplifier implemented by a P-type sense amplifier and an N-type sense amplifier.

[0052] Each of the bit line sense amplifiers BLSA is a circuit element that normally operates when the semiconductor memory device 100 operates. Each of the bit line sense amplifiers BLSA is different from the dummy bit line sense amplifiers 150_1 and 150_n implemented in a region other than a region where the bit line sense amplifiers 150_2 to 150_n-1 are implemented.

[0053] According to some embodiments, the odd-numbered bit lines of the memory cell array 110_1 may be connected to the bit lines BL, and the even-numbered bit lines of the memory cell array 110_1 may be connected to the complementary bit lines BLB. The bit line sense amplifier 150_2 may be connected to each of the bit line pairs BL and BLB in both directions. For example, the bit line sense amplifier 150_2 may be connected to the odd-numbered bit lines (e.g., BL1, BL3, BL5, etc.) of the left memory cell array 110_1, in other words, the bit lines BL; the bit line sense amplifier 150_2 may be connected to the even-numbered bit lines (e.g., BL0, BL2, BL4, etc.) of the right memory cell array 110_2, in other words, the complementary bit lines BLB. For example, the odd-numbered bit lines may constitute the bit lines BL, and the even-numbered bit lines may constitute the complementary bit lines BLB.

[0054] When the potential of the bit line BL is high in the sensing operation of the bit line sense amplifier BLSA, the potential of the complementary bit line BLB becomes low in the sensing operation of the bit line sense amplifier BLSA. On the other hand, when the potential of the bit line BL is low in the sensing operation of the bit line sense amplifier BLSA, the potential of the complementary bit line BLB becomes high in the sensing operation of the bit line sense amplifier BLSA. In other words, the bit line sense amplifier BLSA can smoothly perform the sensing operation only when there is a sufficient voltage difference between the bit line BL and the complementary bit line BLB.

[0055] Odd-numbered bit lines of the memory cell array 110_2 may extend in a direction opposite to the bit line sense amplifier 150_2 and may be connected to the bit line sense amplifier 150_3 .

[0056] Figure 4 is a diagram illustrating a memory device including a sensing device according to some embodiments. Figure 5 It shows Figure 4 The circuit diagram of the sensing device and the charge transfer transistor driving circuit of FIG. Figure 4 and Figure 5 A memory device including a sensing device according to some embodiments is described.

[0057] First refer to Figure 4 , the memory device 100 may include a sensing device 200, memory cell arrays 110A and 110B, a voltage generator 170, and a charge transfer transistor driving circuit 180. The sensing device 200 may include at least one bit line sense amplifier BLSA, at least one charge transfer transistor MN1, and at least one charge transfer transistor MN2. Each bit line sense amplifier BLSA may be connected to the charge transfer transistor driving circuit 180 through its charge transfer transistors MN1 and MN2. Word lines WLa to WLa+n may be connected to the memory cell array 110A, and word lines WLb to WLb+n may be connected to the memory cell array 110B.

[0058] The charge transfer transistor MN1 may be turned on by a signal S1. For example, if the charge transfer transistor MN1 is an N-type transistor, it may be turned on when the signal S1 is logic high. Depending on the voltage of the node N1, the signal S1 may be logic high or logic low. The charge transfer transistor MN2 may be turned on by a signal S2. For example, if the charge transfer transistor MN2 is an N-type transistor, it may be turned on when the signal S2 is logic high. Depending on the voltage of the node N2, the signal S2 may be logic high or logic low.

[0059] Hereinafter, one bit line sense amplifier BLSA included in the sensing device 200 and the charge transfer transistor MN1 and the charge transfer transistor MN2 connected to both ends of the bit line sense amplifier BLSA will be described as an example. However, the following description can be similarly applied to other bit line sense amplifiers BLSA included in the sensing device 200 and the charge transfer transistors MN1 and the charge transfer transistors MN2 connected to both ends of the other bit line sense amplifiers BLSA.

[0060] The memory cell arrays 110A and 110B illustrate some of the multiple memory cell arrays included in the memory device 100, and the memory device 100 may further include multiple memory cell arrays in addition to the memory cell arrays 110A and 110B. The memory cell arrays 110A and 110B may be two memory cell arrays closest to each other among the multiple memory cell arrays included in the memory device 100. For example, the memory cell array 110A may be an even-numbered memory cell block, and the memory cell array 110B may be an odd-numbered memory cell block. In another embodiment, the memory cell array 110A may be an odd-numbered memory cell block, and the memory cell array 110B may be an even-numbered memory cell block.

[0061] The charge transfer transistor driving circuit 180 may include transfer gate transistors MN7, MN8, MN11, and MN12 and isolation transistors MN9 and MN10. Figure 4 , the transfer gate transistors MN7, MN8, MN11, and MN12 and the isolation transistors MN9 and MN10 are all shown as N-type transistors. However, according to an embodiment, at least one transfer transistor among the transfer gate transistors MN7, MN8, MN11, and MN12 and the isolation transistors MN9 and MN10 included in the charge transfer transistor driving circuit 180 may be implemented as a P-type transistor.

[0062] One end of the transmission gate transistor MN7 may be connected to the transmission gate voltage line VTG2, and the other end of the transmission gate transistor MN7 may be connected to the node N1. One end of the transmission gate transistor MN8 may be connected to the transmission gate voltage line VTG1, and the other end of the transmission gate transistor MN8 may be connected to the node N1.

[0063] One end of the isolation transistor MN9 may be connected to the isolation voltage line VISO, and the other end of the isolation transistor MN9 may be connected to the node N1. In this way, the transfer gate transistors MN7 and MN8 and the isolation transistor MN9 may use the node N1 as a common node. Therefore, any voltage among the transfer gate voltage VTG1, the transfer gate voltage VTG2, and the isolation voltage VISO may be provided to the node N1, and the voltage provided to the node N1 may be provided to the gate of the charge transfer transistor MN1 as the signal S1.

[0064] One end of the transmission gate transistor MN11 may be connected to the transmission gate voltage line VTG1, and the other end of the transmission gate transistor MN11 may be connected to the node N2. One end of the transmission gate transistor MN12 may be connected to the transmission gate voltage line VTG2, and the other end of the transmission gate transistor MN12 may be connected to the node N2.

[0065] One end of the isolation transistor MN10 may be connected to the isolation voltage line VISO, and the other end of the isolation transistor MN10 may be connected to the node N2. In this way, the transfer gate transistors MN11 and MN12 and the isolation transistor MN10 may use the node N2 as a common node. Therefore, any voltage among the transfer gate voltage VTG1, the transfer gate voltage VTG2, and the isolation voltage VISO may be provided to the node N2, and the voltage provided to the node N2 may be provided to the gate of the charge transfer transistor MN2 as the signal S2.

[0066] The voltage generator 170 may generate a transmission gate voltage VTG1 and provide it to each of one end of the transmission gate transistor MN8 and one end of the transmission gate transistor MN11. In addition, the voltage generator 170 may generate a transmission gate voltage VTG2 and provide it to each of one end of the transmission gate transistor MN7 and one end of the transmission gate transistor MN12. Figure 6 An internal circuit configuration of the voltage generator 170 that generates the transmission gate voltage VTG1 and the transmission gate voltage VTG2 is described.

[0067] In some embodiments, the memory device 100 may further include a timing generator 190. For example, the timing generator 190 may be included in Figure 1 The control logic 114 can generate control signals CS1 and CS3 and provide them to the charge transfer transistor drive circuit 180. Figures 10 to 12 The timing generator 190 is described.

[0068] Next, refer to Figure 4 and Figure 5The bit line sense amplifier BLSA may be connected between the bit line BL and the complementary bit line BLB. The bit line sense amplifier BLSA may use a signal input from the bit line BL and a signal input from the complementary bit line BLB as a differential input signal pair. The bit line sense amplifier BLSA may include a sense bit line SBL and a sense complementary bit line SBLB.

[0069] The bit line sense amplifier BLSA may include P-type amplifying parts MP1 and MP2 and N-type amplifying parts MN5 and MN6, one end of the P-type amplifying parts MP1 and MP2 is connected to the control line LA, and one end of the N-type amplifying parts MN5 and MN6 is connected to the control line LAB. For example, the ends of the P-type amplifying parts MP1 and MP2 may be connected to each other, and the ends of the N-type amplifying parts MN5 and MN6 may be connected to each other. The other end of each of the P-type amplifying parts MP1 and MP2 and the N-type amplifying parts MN5 and MN6 may be electrically connected to a sensing bit line SBL connected to the bit line BL or a sensing complementary bit line SBLB connected to the complementary bit line BLB. The amplifying transistors MP1 and MP2, and the amplifying transistors MN5 and MN6 may be connected to each other in a cross-coupling structure.

[0070] For example, the amplifier transistor MP1 may be connected between the control line LA and the sensing bit line SBL, and the gate of the amplifier transistor MP1 may be connected to the sensing complementary bit line SBLB. The amplifier transistor MP2 may be connected between the control line LA and the sensing complementary bit line SBLB, and the gate of the amplifier transistor MP2 may be connected to the sensing bit line SBL. The amplifier transistor MN5 may be connected between the control line LAB and the sensing bit line SBL, and the gate of the amplifier transistor MN5 may be connected to the sensing complementary bit line SBLB. The amplifier transistor MN6 may be connected between the control line LAB and the sensing complementary bit line SBLB, and the gate of the amplifier transistor MN6 may be connected to the sensing bit line SBL.

[0071] In some embodiments, the bit line sense amplifier BLSA may include an equalization transistor MN3 and an equalization transistor MN4. The equalization transistor MN3 may be connected between the sensing bit line SBL and the node N3, and the equalization transistor MN4 may be connected between the sensing complementary bit line SBLB and the node N3. When the control signal CS4 is applied to the gates of the equalization transistor MN3 and the equalization transistor MN4, the sensing bit line SBL and the sensing complementary bit line SBLB may be electrically connected. In addition, when the control signal CS4 is applied to the gates of the equalization transistor MN3 and the equalization transistor MN4, the electrically connected sensing bit line SBL and the sensing complementary bit line SBLB may be precharged with a precharge voltage VBL, or may be precharged with a precharge voltage VPRE. The precharge voltages VBL and VPRE may be provided to the equalization transistors MN3 and MN4 via the node N3. According to some embodiments, the equalization transistors MN3 and MN4 may be, but are not limited to, N-type transistors. According to an embodiment, the equalization transistors MN3 and MN4 may be implemented as P-type transistors.

[0072] The bit line sense amplifier BLSA may include a precharge transistor MN13 and a precharge transistor MN14. The precharge transistor MN13 may be turned on / off in response to a precharge equalization signal PEQ provided to the gate of the precharge transistor MN13. For example, if the precharge transistor MN13 is implemented as an N-type transistor, it may be turned on when the precharge equalization signal PEQ is logic high. The precharge transistor MN13 may precharge the bit line BL and the complementary bit line BLB to any voltage level of the high voltage VH or the low voltage VL. At this time, the high voltage VH and the low voltage VL may each have a voltage level between the power supply voltage VDD and the ground voltage VSS, and the amplitude of the high voltage VH may be greater than the amplitude of the low voltage VL. In other words, the precharge voltage VBL may be a high voltage VH or a low voltage VL, and the bit line BL and the complementary bit line BLB may be equally precharged to any voltage level of the high voltage VH and the low voltage VL.

[0073] The precharge transistor MN14 can be turned on / off in response to a precharge equalization signal PEQi provided to the gate of the precharge transistor MN14. For example, if the precharge transistor MN14 is implemented as an N-type transistor, it can be turned on when the precharge equalization signal PEQi is logic high. The precharge transistor MN14 can precharge the sensing bit line SBL and the sensing complementary bit line SBLB to any voltage level of the high voltage VH or the low voltage VL. In other words, the precharge voltage VPRE can be any one of the high voltage VH or the low voltage VL, and the sensing bit line SBL and the sensing complementary bit line SBLB can be equally precharged to any one of the voltage levels of the high voltage VH and the low voltage VL.

[0074] In some embodiments, the bit line BL and the sensing bit line SBL may be precharged at different voltages, and the complementary bit line BLB and the sensing complementary bit line SBLB may be precharged at different voltages. For example, when the charge transfer transistor MN1 and the charge transfer transistor MN2 are both turned on by the isolation voltage VISO supplied to the node N1 and the node N2, and the precharge transistor MN13 is turned on in response to the precharge equalization signal PEQ supplied to the gate, all the bit lines BL, the sensing bit line SBL, the complementary bit line BLB, and the sensing complementary bit line SBLB may be precharged at the precharge voltage VBL.

[0075] Thereafter, the charge transfer transistors MN1 and MN2 are turned off, the precharge transistor MN14 is turned on in response to a precharge equalization signal PEQi supplied to a gate of the precharge transistor MN14, and the sensing bit line SBL and the sensing complementary bit line SBLB may be precharged with the precharge voltage VPRE.

[0076] At this time, the precharge voltage VBL and the precharge voltage VPRE may have different voltage levels from each other. In other words, by turning off both the charge transfer transistors MN1 and MN2, the bit line BL, the sensing bit line SBL, the complementary bit line BLB, and the sensing complementary bit line SBLB may be precharged at different voltages. For example, when the bit line BL and the complementary bit line BLB are precharged with a precharge voltage VBL corresponding to the low voltage VL, the sensing bit line SBL and the sensing complementary bit line SBLB may be precharged with a precharge voltage VPRE corresponding to the high voltage VH. On the contrary, when the bit line BL and the complementary bit line BLB are precharged with a precharge voltage VBL corresponding to the high voltage VH, the sensing bit line SBL and the sensing complementary bit line SBLB may be precharged with a precharge voltage VPRE corresponding to the low voltage VL.

[0077] In some embodiments, when the precharge voltage VBL is a low voltage VL and the precharge voltage VPRE is a high voltage VH, each of the charge transfer transistor MN1 and the charge transfer transistor MN2 may be implemented as an N-type transistor. As another embodiment, when the precharge voltage VBL is a high voltage VH and the precharge voltage VPRE is a low voltage VL, each of the charge transfer transistor MN1 and the charge transfer transistor MN2 may be implemented as a P-type transistor.

[0078] In some embodiments, one end of the charge transfer transistor MN1 may be connected to the bit line BL, and the other end of the charge transfer transistor MN1 may be connected to the sensing bit line SBL. The charge transfer transistor MN1 may connect the bit line BL and the sensing bit line SBL according to a signal applied to the gate of the charge transfer transistor MN1. For example, when the isolation voltage VISO is applied to the gate of the charge transfer transistor MN1, the charge transfer transistor MN1 is turned on, and the bit line BL and the sensing bit line SBL may be connected to each other. Alternatively, when the transmission gate voltage VTG1 or the transmission gate voltage VTG2 is applied to the gate of the charge transfer transistor MN1, the charge transfer transistor MN1 may amplify the charge transferred from the sensing bit line SBL to the bit line BL. When the local voltage VSS is applied to the gate of the charge transfer transistor MN1, the charge transfer transistor MN1 is turned off, and the bit line BL and the sensing bit line SBL may not be connected to each other.

[0079] One end of the charge transfer transistor MN2 may be connected to a complementary bit line BLB, and the other end of the charge transfer transistor MN2 may be connected to a sensing complementary bit line SBLB. The charge transfer transistor MN2 may connect the complementary bit line BLB and the sensing complementary bit line SBLB according to a signal applied to the gate of the charge transfer transistor MN2. For example, when the isolation voltage VISO is applied to the gate of the charge transfer transistor MN2, the charge transfer transistor MN2 is turned on, and the complementary bit line BLB and the sensing complementary bit line SBLB may be connected to each other. When the transmission gate voltage VTG1 or the transmission gate voltage VTG2 is applied to the gate of the charge transfer transistor MN2, the charge transfer transistor MN2 may amplify the charge transferred from the sensing complementary bit line SBLB to the complementary bit line BLB. When the local voltage VSS is applied to the gate of the charge transfer transistor MN2, the charge transfer transistor MN2 is turned off, and the complementary bit line BLB and the sensing complementary bit line SBLB may not be connected to each other.

[0080] like Figure 5 As shown, in the charge transfer transistor driving circuit 180, the transistors MN7, MN8, and MN9 that provide the signal S1 to the gate of the charge transfer transistor MN1, and the transistors MN10, MN11, and MN12 that provide the signal S2 to the gate of the charge transfer transistor MN2 may be implemented to be separated from each other. For example, the transfer gate transistors MN7 and MN8 and the isolation transistor MN9 may provide the signal S1 to the node N1 connected to the gate of the charge transfer transistor MN1, and the transfer gate transistors MN11 and MN12 and the isolation transistor MN10 may provide the signal S2 to the node N2 connected to the gate of the charge transfer transistor MN2.

[0081] The charge transfer transistor MN1 and the charge transfer transistor MN2 may be turned on at the same time. For example, the isolation transistors MN9 and MN10 may be gated and turned on by the same control signal CS2, and thus, the isolation voltage VISO may be provided to each gate of the charge transfer transistors MN1 and MN2 to turn them on.

[0082] Since the driving circuit that provides signal S1 to the gate of charge transfer transistor MN1 is separated from the driving circuit that provides signal S2 to the gate of charge transfer transistor MN2, when charge transfer transistor MN1 outputs the signal of sensing bit line SBL to bit line BL, and charge transfer transistor MN2 outputs the signal of sensing complementary bit line SBLB to complementary bit line BLB, voltages of different amplitudes can be applied to the gates of charge transfer transistor MN1 and charge transfer transistor MN2.

[0083] For example, the transfer gate transistor MN7 and the transfer gate transistor MN11 may be each gated by the control signal CS1, and the transfer gate voltage MN8 and the transfer gate voltage MN12 may be each gated by the control signal CS3. In addition, the amplitude of the transfer gate voltage VTG1 and the amplitude of the transfer gate voltage VTG2 may be set to be different from each other. Therefore, the transfer gate voltage VTG1 or the transfer gate voltage VTG2 of different amplitudes may be applied to the gates of the charge transfer transistor MN1 and the charge transfer transistor MN2.

[0084] In this way, when both the bit line BL and the bit line BLB are precharged with the same low voltage VL or the same high voltage VH, when the charge transfer operation of the bit line sense amplifier BLSA is performed, the amplitude of the transfer gate voltage applied to each gate of the charge transfer transistor MN1 and the charge transfer transistor MN2 is set to be different from each other, and the current driving capabilities of the charge transfer transistor MN1 and the charge transfer transistor MN2 can be set to be different from each other. Therefore, the ability of the bit line sense amplifier BLSA to sense data 0 or data 1 stored in the memory cell MC can be improved. Fig.14 etc. describe the operation of the bit line sense amplifier BLSA.

[0085] Figure 6 is a circuit diagram of a voltage generator according to some embodiments.

[0086] Figure 6 It shows that when Figure 4 and Figure 5 A diagram of a circuit of a bias voltage generator 170A that generates a transfer gate voltage VTG1 and / or a transfer gate voltage VTG2 when the charge transfer transistors MN1 and MN2 are implemented as N-type transistors.

[0087] Reference Figure 6, the drain of the transistor MN15 may be connected to the current source 171, and the source of the transistor MN15 may be grounded. The gate of the transistor MN15 may be connected to the drain of the transistor MN15. The current source 171 connected to the drain of the transistor MN15 may generate a variable current IB that varies according to temperature.

[0088] The voltage VBN provided by the node N4 connected to the gate of the transistor MN15 may be the transmission gate voltage VTG1 and / or the transmission gate voltage VTG2. Figure 4 The voltage generator 170A is used to generate the transmission gate voltage VTG1 and the transmission gate voltage VTG2 having different voltage levels. Alternatively, according to an embodiment, Figure 4 The voltage generator 170A generates the transmission gate voltage VTG1 or the transmission gate voltage VTG2, and can generate a voltage different from the generated transmission gate voltage by a predetermined voltage level and set it as the other of the transmission gate voltage VTG1 and the transmission gate voltage VTG2.

[0089] Figure 7 and Figure 8 It is used to illustrate Figure 6 Although the following description will be made by taking the charge transfer transistor MN1 as an example, the same description also applies to the charge transfer transistor MN2.

[0090] First refer to Figure 7 , Figure 7 The graph of shows the drain current Id of the charge transfer transistor MN1 with respect to the gate-source voltage Vgs on a logarithmic scale.

[0091] When the amplitude of the gate-source voltage Vgs of the charge transfer transistor MN1 is greater than the amplitude of the threshold voltage Vth of the charge transfer transistor MN1 and the charge transfer transistor MN1 is in a strong inversion state, the gain of the charge transfer transistor MN1 can be relatively small because the slope of the drain current Id relative to the gate-source voltage Vgs is relatively small compared to the case where the charge transfer transistor MN1 is in a weak inversion state.

[0092] Therefore, during the charge transfer operation of the bit line sensing amplifier BLSA, it is necessary to set the amplitude of the gate-source voltage Vgs of the charge transfer transistor MN1 to approximately the amplitude of the threshold voltage Vth of the charge transfer transistor MN1, and set the charge transfer transistor MN1 to operate in a weak inversion state, thereby ensuring that the charge transfer transistor MN1 has sufficient gain.

[0093] For example, according to an embodiment, when the transfer gate voltage VTG1 or the transfer gate voltage VTG2 is applied to the gate of the charge transfer transistor MN1 during the charge transfer operation of the bit line sense amplifier BLSA, it is necessary to set the magnitude of the transfer gate voltage VTG1 or VTG2 to be approximately equal to the magnitude of the threshold voltage Vth of the charge transfer transistor MN1. This ensures that the charge transfer transistor MN1 obtains sufficient gain.

[0094] However, when the charge transfer transistor MN1 is in a weak inversion state during the charge transfer operation of the bit line sense amplifier BLSA, the current of the charge transfer transistor MN1 may vary according to the temperature. Figure 8 , when the temperature is high, the amount of current flowing through the charge transfer transistor MN1 during the charge transfer operation of the bit line sense amplifier BLSA may be large, and when the temperature is low, the amount of current flowing through the charge transfer transistor MN1 during the charge transfer operation of the bit line sense amplifier BLSA may be small.

[0095] In this way, when the current flowing through the charge transfer transistor MN1 during the charge transfer operation of the bit line sense amplifier BLSA varies with temperature, the gain value of the charge transfer transistor MN1 also varies with temperature. Therefore, in addition to the amplitude of the transfer gate voltage applied to the gate of the charge transfer transistor MN1, the temperature condition can also become a factor affecting the current driving capability of the charge transfer transistor MN1. Therefore, when the transfer gate voltage VTG1 or the transfer gate voltage VTG2 applied to the gate of the charge transfer transistor MN1 is generated at the time of the charge transfer operation of the bit line sense amplifier BLSA, the amount of current flowing through the charge transfer transistor MN1 needs to be set to be independent of the temperature condition.

[0096] Reference Figure 8 ,Depend on Figure 6 The magnitude of the voltage VBN generated by the voltage generator 170A may have a value inversely proportional to the temperature. In other words, when using Figure 6 When the voltage generator 170A generates the transfer gate voltage VTG1 or the transfer gate voltage VTG2 applied to the gate of the charge transfer transistor MN1, when the temperature of the charge transfer transistor MN1 is high, the amplitude of the generated transfer gate voltage VTG1 or VTG2 may be reduced, and since the temperature of the charge transfer transistor MN1 may be low, the amplitude of the generated transfer gate voltage VTG1 or VTG2 may be large.

[0097] Thus, when a voltage VBN inversely proportional to temperature is applied to the gate of the charge transfer transistor MN1, the voltage VBN is offset by the current of the charge transfer transistor MN1 proportional to temperature. Therefore, the amount of current flowing through the charge transfer transistor MN1 can be constant regardless of temperature changes during the charge transfer operation of the bit line sense amplifier BLSA.

[0098] Therefore, when passing Figure 6 When the complementary to absolute temperature (CTAT) voltage generator shown generates a transfer gate voltage VTG1 and / or a transfer gate voltage VTG2 to be applied to each gate of the charge transfer transistor MN1 and the charge transfer transistor MN2, when the bit line sense amplifier BLSA performs a charge transfer operation, the current flowing through the charge transfer transistors MN1 and MN2 is set to be independent of temperature, and the gain value of the charge transfer transistors MN1 and MN2 can be set to be constant according to the temperature.

[0099] Fig. 9 is a circuit diagram of a voltage generator according to some other embodiments.

[0100] Fig. 9 It shows that when Figure 4 and Figure 5 FIG. 1 is a diagram of a circuit of a bias voltage generator 170B that generates a transfer gate voltage VTG1 and / or a transfer gate voltage VTG2 when the charge transfer transistors MN1 and MN2 are implemented as P-type transistors.

[0101] Reference Fig. 9 , the drain of transistor MN16 may be connected to current source 172, and the source of transistor MN16 may be grounded. The gate of transistor MN16 may be connected to the drain of transistor MN16. Current source 172 connected to the drain of transistor MN16 may generate current IB that varies according to temperature.

[0102] The gate of transistor MN16 may be connected to the gate of transistor MN17. The source of transistor MN17 may be grounded, and the drain of transistor MN17 may be connected to the drain of transistor MN18. The source of transistor MN18 may be connected to power supply voltage VDD, and the gate of transistor MN18 and the drain of transistor MN18 may be connected to each other. The voltage VBP provided by node N5 connected to the gate of transistor MN18 may be a transmission gate voltage VTG1 and / or a transmission gate voltage VTG2. In some embodiments, the transmission gate voltage VTG2 may be used. Fig. 9 The voltage generator 170B is used to generate the transmission gate voltage VTG1 and the transmission gate voltage VTG2 having different voltage levels. Alternatively, according to an embodiment, Fig. 9The voltage generator 170B generates the transmission gate voltage VTG1 or VTG2 and may generate a voltage different from the generated transmission gate voltage by a predetermined voltage level and set it as the other of the transmission gate voltages VTG1 and VTG2.

[0103] Fig.10 is a circuit diagram of a timing generator according to some embodiments.

[0104] Reference Fig.10 , the current source 191 and the inverter Inv1 may be connected to the node N6. The current source 191 may be connected to the switch SW1, and when the enable signal EN1 is applied to the switch SW1, the switch SW1 is turned on and the power supply voltage VDD may be provided to the node N6. According to this embodiment, the current source 191 is implemented as a variable current source and may generate a current IB that varies according to temperature. Alternatively, the current source 191 may generate a current IB that is constant according to temperature.

[0105] A first end of the reset capacitor CReset may be grounded, and a second end of the reset capacitor CReset may be connected to the node N6. The node N7 may be connected to the switch SW2, and when the reset signal RST is applied to the switch SW2, the switch SW2 is turned on and the reset voltage VR may be provided to the node N7.

[0106] Inverter Inv1 may be connected to switch SW3. When enable signal EN2 is applied to switch SW3, switch SW3 is turned on, and power supply voltage VDD may be provided to inverter Inv1, and inverter Inv1 may perform an inversion operation on input signal Vramp. An input terminal of inverter Inv1 may be connected to node N6, and an output terminal of inverter Inv1 may be connected to an input terminal of inverter Inv2. An output terminal of inverter Inv2 may be connected to an input terminal of inverter Inv3, and a signal output from inverter Inv3 may be input to NAND gate NAND. In addition, signal tCT_initial may be input to NAND gate NAND. NAND gate NAND may output signal tCT_control based on the signal input to NAND gate NAND.

[0107] The signal tCT_control finally generated by the timing generator 190 may correspond to Figure 4The signal tCT_control can adjust the time width during which the transfer gate voltage VTG1 or the transfer gate voltage VTG2 is applied to the charge transfer transistor MN1 during the charge transfer operation of the bit line sense amplifier BLSA. Similarly, the signal tCT_control can adjust the time width during which the transfer gate voltage VTG1 or the transfer gate voltage VTG2 is applied to the charge transfer transistor MN2 during the charge transfer operation of the bit line sense amplifier BLSA.

[0108] For example, when the charge transfer transistors MN1 and MN2 are implemented as N-type transistors and the signal tCT_control1 has a logic high state for a long time, the amount of charge transferred by each of the charge transfer transistors MN1 and MN2 during the charge transfer operation of the bit line sense amplifier BLSA may be large.

[0109] Fig.11 and 12 It is used to illustrate Fig.10 Diagram of the operation of the timing generator.

[0110] First, refer to Fig.10 and Fig.11 , when the enable signal EN1 is applied to the switch SW1, the switch SW1 is turned on, and the current IB flows through the node N6, and the charge can be stored in the reset capacitor CReset. At this time, when the reset signal RST is applied to the switch SW2 at time t1 and the switch SW2 is turned on, the reset voltage VR can be applied to the node N7. Therefore, the voltage Vramp of the node N6 gradually increases over time.

[0111] At this time, the current IB may be a current proportional to absolute temperature (PTAT). In other words, the magnitude of the voltage Vramp of the node N6 may increase as the temperature increases (temperature T1 > temperature T2 > temperature T3).

[0112] Similarly, as mentioned above Figure 7 As described above, when the charge transfer transistor MN1 is in a weak inversion state, the amount of current flowing through the charge transfer transistor MN1 during the charge transfer operation of the bit line sense amplifier BLSA may be large due to high temperature. Therefore, the gain value of the charge transfer transistor MN1 may vary according to temperature.

[0113] Thereafter, when the enable signal EN2 is applied to the switch SW3, the switch SW3 is turned on and the power supply voltage VDD may be supplied to the inverter Inv1. The inverter Inv1 may receive the voltage Vramp as an input to perform an inversion operation, and the output signal may be input to the inverter Inv2. In this way, when the signal finally output by the inverter Inv2 and the inverter Inv3 and the signal tCT_initial are input to the NAND gate NAND, the signal tCT_control may be finally generated.

[0114] Next, refer to Fig.12 The time that the signal tCT_control generated by the timing generator 190 has a logic high state may vary according to the temperature. In other words, when the temperature is high, the time that the signal tCT_control remains in the logic high state may be short, and when the temperature is low, the time that the signal tCT_control remains in the logic high state may be long.

[0115] For example, when the temperatures are T1, T2, and T3, use Fig.10 Each signal tCT_control generated by the timing generator 190 may transition from logic low L to logic high H at time t1. Thereafter, the signal tCT_control generated when the temperature is T1 may transition to logic low L at time t2, the signal tCT_control generated when the temperature is T2 lower than T1 may transition to logic low L at time t3 after time t2, and the signal tCT_control generated at t3 when the temperature is lower than T2 may transition to logic low L at time t4 after time t3.

[0116] Thus, in some embodiments, even if the driving current of the charge transfer transistors MN1 and MN2 varies with temperature during the charge transfer operation of the bit line sense amplifier BLSA, the time during which the transfer gate voltage is applied to each gate of the charge transfer transistors MN1 and MN2 is adjusted to be shorter at a high temperature, and the time during which the transfer gate voltage is applied to each gate of the charge transfer transistors MN1 and MN2 is adjusted to be longer at a lower temperature. Therefore, the gate values ​​of the charge transfer transistors MN1 and MN2 can be kept constant according to temperature.

[0117] Figures 13 to 22 is a diagram for explaining a method of driving a sensing device according to some embodiments. Figures 13 to 22 Hereinafter, a case where the bit line BL and the complementary bit line BLB are precharged with the low voltage VL and the charge transfer transistor MN1 and the charge transfer transistor MN2 are implemented as N-type transistors will be described as an example.

[0118] First, refer to Figures 13 to 20 describe Fig.13 The memory cell array 110A is activated and the sensing device 200 senses data 0 stored in the memory cells of the memory cell array 110A. Fig.14 is a timing diagram illustrating the operation of a bit line sense amplifier BLSA according to some embodiments. The bit line sense amplifier BLSA may sequentially perform a precharge operation, a charge sharing operation, a charge transfer operation, a sensing operation, and a recovery operation.

[0119] Reference Fig.14 and Fig.15 , the bit line sense amplifier BLSA may first perform a precharge operation during the interval (t0 to t1). The precharge equalization signal PEQ is applied to the gate of the precharge transistor MN13 at a logic high, and the precharge transistor MN13 may be turned on to provide a precharge voltage VBL through the node N3. At this time, the control signal CS4 is applied to each gate of the equalization transistors MN3 and MN4 at a logic high, and the equalization transistors MN3 and MN4 may be turned on to precharge the sensing bit line SBL and the sensing complementary bit line SBLB with the precharge voltage VBL corresponding to the low voltage VL through the nodes N8 and N9, respectively.

[0120] In addition, the control signal CS2 is applied to each gate of the isolation transistors MN9 and MN10 at a logic high, and the isolation transistors MN9 and MN10 can be turned on to provide the isolation voltage VISO to the nodes N1 and N2, respectively. The isolation voltage VISO of each of the nodes N1 and N2 can turn on the charge transfer transistors MN1 and the charge transfer transistors MN2 to connect the sensing bit line SBL and the bit line BL, and connect the sensing complementary bit line SBLB and the complementary bit line BLB. Therefore, the bit line BL, the sensing bit line SBL, the complementary bit line BLB, and the sensing complementary bit line SBLB can be constantly precharged with the precharge voltage VBL corresponding to the low voltage VL.

[0121] Thereafter, the bit line sense amplifier BLSA may perform a charge sharing operation during an interval (t1 to t3). Fig.13 , Fig.14 and Fig.16 , the memory cell array 110A can be activated. For example, when the address buffer 120 sends the row address RA to Figure 1 When the row decoder 130 in the address buffer 120 is activated, the row decoder 130 decodes the row address RA received from the address buffer 120, and can activate any one of the word lines WLa to WLa+n connected to the memory cell array 110A corresponding to the row address RA. Hereinafter, the case where the word line WLa is activated will be described as an example.

[0122] At time t1, the voltage supplied to the word line WLa may be changed from the low level L to the high level H. Therefore, the word line WLa is activated, and the memory cell MC connected to the word line WLa may be selected. However, at this time, charge sharing hardly occurs between the charge stored in the cell capacitor of the memory cell MC connected to the word line WLa and the charge stored in the bit line BL. For example, since the bit line BL is precharged with a low voltage VL (e.g., a ground voltage VSS) during the interval (t0 to t1), when data 0 is stored in the cell capacitor, there is no potential difference between the cell capacitor and the bit line BL, and therefore, a charge sharing operation hardly occurs.

[0123] On the other hand, at time t1, the precharge equalization signal PEQi changes from logic low L to logic high H, and may be applied to the gate of the precharge transistor MN14. Therefore, the precharge transistor MN14 may be turned on to provide a precharge voltage VPRE through the node N3. At this time, the precharge voltage VPRE may correspond to a high voltage VH (e.g., a power supply voltage VDD), in contrast to the precharge voltage VBL corresponding to the low voltage VL.

[0124] The precharge equalization signal PEQ changes from logic high H to logic low L during the interval (t0 to t1), and the precharge voltage VBL may not be provided to the node N3 at time t1. At this time, the control signal CS4 is still in a logic high state, and the equalization transistors MN3 and MN4 may remain in a turned-on state and precharge the sensing bit line SBL and the sensing complementary bit line SBLB with the precharge voltage VPRE corresponding to the high voltage VH through the nodes N8 and N9, respectively.

[0125] In addition, the control signal CS2 changes from logic high H to logic low L during the interval (t0 to t1), and the charge transfer transistor MN1 and the charge transfer transistor MN2 may be in a cut-off state at time t1. Therefore, during the interval (t1 to t2), the bit line BL and the complementary bit line BLB may maintain a precharge state with a low voltage VL, and the sensing bit line SBL and the sensing complementary bit line SBLB may be precharged with a high voltage VH.

[0126] Next, refer to Fig.14 and Fig.17 , the bit line sense amplifier BLSA may perform a charge transfer operation during the interval (t2 to t3). At time t2, the precharge equalization signal PEQi transitions from a logic high H to a logic low L, the precharge transistor MN14 may be turned off, and thus the precharge voltage VPRE may not be provided to the node N3. In addition, at time t2, the control signal CS1 transitions from a logic low L to a logic high H, and the transfer gate transistor MN7 and the transfer gate transistor MN11 may be turned on, respectively.

[0127] According to the connection of the transistors in the interval (t2 to t3), the transfer gate voltage VTG2 is provided to the node N1 through the transfer gate transistor MN7, the charge transfer transistor MN1 is weakly turned on according to the voltage level of the node N1, and the charge stored in the sensing bit line SBL can be output to the bit line BL through the charge transfer transistor MN1. In addition, the transfer gate voltage VTG1 is provided to the node N2 through the transfer gate transistor MN11, the charge transfer transistor MN2 is weakly turned on according to the voltage level of the node N2, and the charge stored on the sensing complementary bit line SBLB can be output to the complementary bit line BLB through the charge transfer transistor MN2.

[0128] At this time, since the control signal LA and the control signal LAB have a predetermined intermediate level M voltage, the P-type amplifier part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5, MN6) do not amplify the charge stored in the sensing bit line SBL and the sensing complementary bit line SBLB. On the contrary, the P-type amplification part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5, MN6) can directly output the amount of charge stored in the sensing bit line SBL and the sensing complementary bit line SBLB to the bit line BL and the complementary bit line BLB at time t2.

[0129] In some embodiments, the magnitudes of the transmission gate voltage VTG1 and the transmission gate voltage VTG2 may be smaller than the magnitude of the isolation voltage VISO.

[0130] In some embodiments, when the bit line BL and the complementary bit line BLB are precharged with a low voltage VL, the sensing bit line SBL and the sensing complementary bit line SBLB are precharged with a high voltage VH, and the charge transfer transistors MN1 and MN2 are implemented as N-type transistors, the magnitude of the charge transfer voltage VTG2 applied to the gate of the charge transfer transistor MN1 connected to the activated memory cell array 110A may be greater than the magnitude of the charge transfer voltage VTG1 applied to the gate of the transfer transistor MN2 connected to the inactivated memory cell array 110B. Therefore, when the charge transfer operation of the bit line sense amplifier BLSA is performed during the interval (t2 to t3), the potential reduction of the sensing bit line SBL may be greater than the potential reduction of the sensing complementary bit line SBLB.

[0131] In other words, as described above, when the bit line BL and the complementary bit line BLB are precharged with the low voltage VL, and the data 0 stored in the memory cell MC connected to the bit line BL is sensed, after the charge sharing operation, there is no sufficient potential difference between the bit line BL and the complementary bit line BLB, and therefore, the bit line sense amplifier BLSA can hardly sense the data 0.

[0132] Therefore, in some embodiments, by applying a higher voltage to the gate of the charge transfer transistor MN1 connected to the activated memory cell array 110A than the voltage applied to the gate of the charge transfer transistor MN2 connected to the inactivated memory cell array 110B during the charge transfer operation, the current driving capability of the charge transfer transistor MN1 can be set to be greater than the current driving capability of the charge transfer transistor MN2 during the charge transfer operation of the bit line sense amplifier BLSA. Therefore, even if the voltage levels of the bit line BL and the complementary bit line BLB are substantially the same after the charge sharing operation, the sense bit line SBL can perform the charge transfer operation faster than the complementary sense bit line SBLB, and therefore, at time t3, a sufficient potential difference can occur between the sense bit line SBL and the sense complementary bit line SBLB. Therefore, the bit line sense amplifier BLSA can sense the potential difference between the sense bit line SBL and the sense complementary bit line SBLB.

[0133] Next, refer to Fig.14 and Fig.18 , the bit line sense amplifier BLSA may perform a sensing operation during the interval (t3 to t4). At time t3, the control signal CS1 changes from logic high H to logic low L, each of the transfer gate transistor MN7 and the transfer gate transistor MN11 may be turned off, and the charge transfer transistor MN1 and the charge transfer transistor MN2 may be turned off. In addition, at time t3, the control signal LA and the control signal LAB change to logic high H and logic low L, respectively, and the P-type amplification part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5 and MN6 of the sensing bit line SBL may be activated to amplify the amount of charge stored in the sensing bit line SBL and the sensing complementary bit line SBLB, and a voltage corresponding to the amplified amount of charge may be output to the bit line BL and the complementary bit line BLB.

[0134] Next, refer to Fig.14 and Fig.19, the bit line sense amplifier BLSA may perform a recovery operation during the interval (t4 to t5). At time t4, when the control signal CS2 changes from logic low L to logic high H, the isolation transistors MN9 and MN10 may be turned on again, providing the isolation voltage VISO to each of the nodes N1 and N2, and the charge transfer transistors MN1 and MN2 may be turned on. The control signals LA and LAB are maintained similarly to the interval (t3 to t4), and the P-type amplification part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 Therefore, the complementary bit line BLB can be sensed by the charge transfer transistor MN2 to sense the complementary bit line SBLB and charged with the amplified charge, and the bit line BL can maintain the low voltage VL level.

[0135] Next, refer to Fig.14 and Fig. 20 ,exist Fig. 9 At time t5, the precharge equalization signal PEQ changes from logic low L to logic high H, the precharge transistor MN13 is turned on, and the precharge operation can be performed again during the interval (t5 to t6). Thereafter, the bit line sense amplifier BLSA can sequentially perform a charge sharing operation, a charge transfer operation, a sensing operation, and a recovery operation during the interval after t6.

[0136] Next, refer to Fig.21 and Fig. 22 , will describe Fig.21 The memory cell array 110B is activated and the sensing device 200 senses data 0 stored in the memory cells of the memory cell array 110B. Fig. 22 It shows that when Fig.21 1 is a timing diagram of the operation of the bit line sense amplifier BLSA when the memory cell array 110B is activated. Hereinafter, the differences from the aforementioned embodiment will be mainly described, and repeated description will not be provided.

[0137] Reference Fig. 22 ,and Fig.14 Differently, the voltage supplied to the word line WLb may transition from a low level L to a high level H at time t1. Therefore, the word line WLb is activated, and the memory cell MC connected to the word line WLb may be selected. In addition, at time t2, the control signal CS3 transitions from a logic low L to a logic high H, and each of the transfer gate transistor MN8 and the transfer gate transistor MN12 may be turned on.

[0138] According to the connection of the transistors in the interval (t2 to t3), the transfer gate voltage VTG1 is supplied to the node N1 through the transfer gate transistor MN8, the charge transfer transistor MN1 is weakly turned on according to the voltage level of the node N1, and the charge stored in the sensing bit line SBL can be output to the bit line BL through the charge transfer transistor MN1. In addition, the transfer gate voltage VTG2 is supplied to the node N2 through the transfer gate transistor MN12, the charge transfer transistor MN2 is weakly turned on according to the voltage level of the node N2, and the charge stored in the sensing complementary bit line SBLB can be output to the complementary bit line BLB through the charge transfer transistor MN2.

[0139] In this way, since the bit line BL and the complementary bit line BLB are precharged with the low voltage VL, the sensing bit line SBL and the sensing complementary bit line SBLB are precharged with the high voltage VH, and the memory cell array 110B is activated, the magnitude of the transfer gate voltage VTG2 applied to the gate of the charge transfer transistor MN2 connected to the activated memory cell array 110B can be greater than the magnitude of the transfer gate voltage VTG1 applied to the gate of the charge transfer transistor MN1 connected to the inactivated memory cell array 110A. Therefore, when the charge transfer operation of the bit line sense amplifier BLSA is performed during the interval (t2 to t3), the potential drop of the sensing complementary bit line SBLB can be greater than the potential drop of the sensing bit line SBL.

[0140] Therefore, the bit line sense amplifier BLSA may sense data 0 stored in the activated memory cell MC of the memory cell array 110B by sensing the potential difference between the sensing bit line SBL and the sensing complementary bit line SBLB.

[0141] Fig.23 is a circuit diagram showing a sensing device and a charge transfer transistor driving circuit according to some other embodiments. Hereinafter, descriptions repeated with the previous embodiments will be omitted, and the following description will focus on the differences.

[0142] Reference Fig.23 ,and Figure 5 Differently, the precharge transistor MP3 of the sensing device 200A can be implemented as a P-type transistor, and the charge transfer transistor MP4 and the charge transfer transistor MP5 can each be implemented as a P-type transistor. In addition, the isolation transistors MP6 and MP7 of the charge transfer transistor driving circuit 180A can be implemented as P-type transistors, respectively.

[0143] Fig.24 and Fig.25 It shows Fig.23 A timing diagram of the operation of the bit line sense amplifier.

[0144] First, refer to Fig.24 , Fig.24 Is used to illustrate when Fig.23 The charge transfer transistor MP4 is connected to the memory cell array (for example, Fig.13 1 1 0A) is activated, and the memory cell array (eg, Fig.13 110B) is not activated, the sensing device 200A senses data 1 stored in a memory cell of the memory cell array 110A.

[0145] The bit line sense amplifier BLSA may first perform a precharge operation during the interval (t0 to t1). The precharge equalization signal PEQ is applied to the gate of the precharge transistor MP3 at a logic low, and the precharge transistor MP3 may be turned on to provide a precharge voltage VBL through the node N3. Fig.14 In addition, the control signal CS4 is applied to each gate of the equalization transistors MN3 and MN4 at logic high, and the equalization transistors MN3 and MN4 can be turned on to precharge the sensing bit line SBL and the sensing complementary bit line SBLB with the precharge voltage VBL corresponding to the high voltage VH through the nodes N8 and N9, respectively.

[0146] In addition, the control signal CS2 is applied to each gate of the isolation transistors MP6 and MP7 at a logic low level, and each of the isolation transistors MP6 and MP7 can be turned on to provide the isolation voltage VISO to the nodes N1 and N2, respectively. At this time, the isolation voltage VISO can be a ground voltage VSS corresponding to a logic low. The isolation voltage VISO of each of the nodes N1 and N2 can turn on each of the charge transfer transistors MP4 and MP5, connect the sensing bit line SBL and the bit line BL to each other, and connect the sensing complementary bit line SBLB and the complementary bit line BLB to each other. Therefore, the bit line BL, the sensing bit line SBL, the complementary bit line BLB, and the sensing complementary bit line SBLB can be precharged with a precharge voltage VBL corresponding to the high voltage VH.

[0147] Thereafter, the bit line sense amplifier BLSA may perform a charge sharing operation during the interval (t1 to t3). Hereinafter, a memory cell array 110A ( Fig.13 1 and 2 ), in which the word line WLa is activated among the word lines (WLa to WLa+n) shown in FIG.

[0148] At time t1, the voltage supplied to the word line WLa may be changed from the low level L to the high level H. Therefore, the word line WLa is activated, and the memory cell MC connected to the word line WLa may be selected. However, at this time, charge sharing may hardly occur between the charge stored in the cell capacitor of the memory cell MC connected to the word line WLa and the charge stored in the bit line BL. For example, since the bit line BL is precharged with a high voltage VH (e.g., the power supply voltage VDD) during the interval (t0 to t1), when data 1 is stored in the cell capacitor, there is no potential difference between the cell capacitor and the bit line BL, and therefore, a charge sharing operation hardly occurs.

[0149] On the other hand, at time t1, the precharge equalization signal PEQi changes from logic low L to logic high H, and may be applied to the gate of the precharge transistor MN14. Therefore, the precharge transistor MN14 may be turned on to provide a precharge voltage VPRE through the node N3. At this time, the precharge voltage VPRE may correspond to a low voltage VL (e.g., a ground voltage VSS), in contrast to the precharge voltage VBL corresponding to the high voltage VH.

[0150] The precharge equalization signal PEQ changes from logic low L to logic high H during the interval (t0 to t1), and the precharge voltage VBL may not be provided to the node N3 at time t1. At this time, the control signal CS4 is still in a logic high state, and the equalization transistors MN3 and MN4 can remain in a turned-on state and precharge the sensing bit line SBL and the sensing complementary bit line SBLB with the precharge voltage VPRE corresponding to the low voltage VL through the nodes N8 and N9, respectively.

[0151] In addition, the control signal CS2 changes from logic low L to logic high H during the interval (t0 to t1), and the charge transfer transistor MP4 and the charge transfer transistor MP5 can be in a cut-off state at time t1. Therefore, during the interval (t1 to t2), the bit line BL and the complementary bit line BLB can maintain a precharge state with a high voltage VH, and the sense bit line SBL and the sense complementary bit line SBLB can be precharged with a low voltage VL.

[0152] Thereafter, the bit line sense amplifier BLSA may perform a charge transfer operation during the interval (t2 to t3). At time t2, the precharge equalization signal PEQi transitions from a logic high H to a logic low L, and the precharge transistor MN14 may be turned off, and thus the precharge voltage VPRE may not be provided to the node N3. In addition, at time t2, the control signal CS1 transitions from a logic low L to a logic high H, and the transfer gate transistor MN7 and the transfer gate transistor MN11 may be turned on, respectively.

[0153] According to the connection of the transistors in the interval (t2 to t3), the transfer gate voltage VTG2 is provided to the node N1 through the transfer gate transistor MN7, the charge transfer transistor MP4 is weakly turned on according to the voltage level of the node N1, and the charge stored in the sensing bit line SBL can be output to the bit line BL through the charge transfer transistor MP4. In addition, the transfer gate voltage VTG1 is provided to the node N2 through the transfer gate transistor MN11, the charge transfer transistor MP5 is weakly turned on according to the voltage level of the node N2, and the charge stored on the sensing complementary bit line SBLB can be output to the complementary bit line BLB through the charge transfer transistor MP5.

[0154] At this time, since the control signal LA and the control signal LAB have a predetermined intermediate level M voltage, the P-type amplifier part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5, MN6) do not amplify the charge stored in the sensing bit line SBL and the sensing complementary bit line SBLB. On the contrary, the P-type amplification part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5, MN6) can directly output the amount of charge stored in the sensing bit line SBL and the sensing complementary bit line SBLB to the bit line BL and the complementary bit line BLB at time t2.

[0155] In some embodiments, when the bit line BL and the complementary bit line BLB are precharged with a high voltage VH, the sensing bit line SBL and the sensing complementary bit line SBLB are precharged with a low voltage VL, and the charge transfer transistors MP4 and MP5 are implemented as P-type transistors, the charge transfer voltage VTG2 applied to the gate of the charge transfer transistor MP4 connected to the activated memory cell array 110A may be lower than the charge transfer voltage VTG1 applied to the gate of the charge transfer transistor MP5 connected to the inactivated memory cell array 110B. For example, the absolute value of the magnitude of the charge transfer voltage VTG2 may be greater than the absolute value of the magnitude of the charge transfer voltage VTG1. Therefore, when the charge transfer operation of the bit line sense amplifier BLSA is performed during the interval (t2 to t3), the potential increase of the sensing bit line SBL may be greater than the potential increase of the sensing complementary bit line SBLB.

[0156] In other words, as described above, when the bit line BL and the complementary bit line BLB are precharged with the high voltage VH and the data 1 stored in the memory cell MC connected to the bit line BL is sensed, since there is no sufficient potential difference between the bit line BL and the complementary bit line BLB after the charge sharing operation, the bit line sense amplifier BLSA can hardly sense the data 1.

[0157] Therefore, in some embodiments, during the charge transfer operation, by applying a voltage (e.g., a voltage with a larger absolute value) to the gate of the charge transfer transistor MP4 connected to the activated memory cell array 110A than the voltage applied to the gate of the charge transfer transistor MP5 connected to the inactivated memory cell array 110B, the current driving capability of the charge transfer transistor MP4 during the charge transfer operation of the bit line sense amplifier BLSA can be set to be greater than the current driving capability of the charge transfer transistor MP5. Therefore, even if the voltage levels of the bit line BL and the complementary bit line BLB are substantially the same after the charge sharing operation, the sense bit line SBL can perform the charge transfer operation faster than the complementary sense bit line SBLB, and at time t3, a sufficient potential difference can occur between the sense bit line SBL and the sense complementary bit line SBLB. Therefore, the bit line sense amplifier BLSA can sense the potential difference between the sense bit line SBL and the sense complementary bit line SBLB.

[0158] The bit line sense amplifier BLSA may perform a sensing operation during the interval (t3 to t4). At time t3, the control signal CS1 changes from a logic high H to a logic low L, each of the transfer gate transistor MN7 and the transfer gate transistor MN11 may be turned off, and each of the charge transfer transistor MP4 and the charge transfer transistor MP5 may be turned off. In addition, at time t3, the control signal LA and the control signal LAB each change to a logic high H and a logic low L, and the P-type amplification part ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5 and MN6 of the sensing bit line SBL may be activated to amplify the amount of charge stored in the sensing bit line SBL and the sensing complementary bit line SBLB, and a voltage according to the amplified amount of charge may be output to the bit line BL and the complementary bit line BLB.

[0159] Thereafter, the bit line sense amplifier BLSA may perform a recovery operation during the interval (t4 to t5). At time t4, when the control signal CS2 transitions from logic high H to logic low L, the isolation transistors MP6 and MP7 may be turned on again, and the isolation voltage VISO is provided to each of the nodes N1 and N2, and the charge transfer transistors MP4 and MP5 may be turned on. The control signals LA and LAB are maintained similarly to the interval (t3 to t4), and the P-type amplification portion ( Figure 5 MP1, MP2) and N-type amplifier part ( Figure 5 MN5, MN6) can perform an amplification operation. Therefore, the complementary bit line BLB can be sensed by the charge transfer transistor MP5, transferred to the sense complementary bit line SBLB, and then discharged as amplified charge. At the same time, the bit line BL can maintain a high voltage VH level.

[0160] Subsequently, in the bit line sense amplifier BLSA, the precharge equalization signal PEQ changes from logic high H to logic low L at time t5, the precharge transistor MP3 is turned on, the precharge operation can be performed again during the interval (t5 to t6), and the bit line sense amplifier BLSA can sequentially perform the charge sharing operation, charge transfer operation, sensing operation and recovery operation again during the interval after t6.

[0161] Next, refer to Fig.25 , Fig.25 Is used to illustrate when Fig.23 The charge transfer transistor MP5 is connected to the memory cell array (for example, Fig.21 110B) is activated, and the memory cell array (eg, Fig.21 When the sensing device 200A (such as 1 10A) is not activated, Fig.23 1 and 10B) are timing diagrams of operations of sensing data 1 stored in memory cells of a memory cell array 110B. Hereinafter, differences from the aforementioned embodiment will be mainly described, and repeated description will not be provided.

[0162] Reference Fig.25 ,and Fig.24 Differently, the voltage supplied to the word line WLb may be changed from a low level L to a high level H at time t1. Therefore, the word line WLb is activated, and the memory cell MC connected to the word line WLb may be selected. In addition, at time t2, the control signal CS3 is changed from a logic low L to a logic high H, and the transfer gate transistor MN8 and the transfer gate transistor MN12 may be turned on, respectively.

[0163] According to the connection of the transistors in the interval (t2 to t3), the transfer gate voltage VTG1 is provided to the node N1 through the transfer gate transistor MN8, the charge transfer transistor MP3 is weakly turned on according to the voltage level of the node N1, and the charge stored in the sensing bit line SBL can be output to the bit line BL through the charge transfer transistor MP4. In addition, the transfer gate voltage VTG2 is provided to the node N2 through the transfer gate transistor MN12, the charge transfer transistor MP5 is weakly turned on according to the voltage level of the node N2, and the charge stored on the sensing complementary bit line SBLB can be output to the complementary bit line BLB through the charge transfer transistor MP5.

[0164] In this way, since the bit line BL and the complementary bit line BLB are precharged with the high voltage VH, the sensing bit line SBL and the sensing complementary bit line SBLB are precharged with the low voltage VL, and the memory cell array 110B is activated, the transfer gate voltage VTG2 applied to the gate of the charge transfer transistor MP5 connected to the activated memory cell array 110B can be smaller than the transfer gate voltage VTG1 applied to the gate of the charge transfer transistor MP4 connected to the inactivated memory cell array 110A. In other words, the absolute value of the amplitude of the charge transfer voltage VTG2 can be greater than the absolute value of the amplitude of the charge transfer voltage VTG1. Therefore, when the charge transfer operation of the bit line sense amplifier BLSA is performed during the interval (t2 to t3), the potential reduction of the sensing complementary bit line SBLB can be greater than the potential reduction of the sensing bit line SBL.

[0165] Therefore, the bit line sense amplifier BLSA may sense data 1 stored in the activated memory cell MC of the memory cell array 110B by sensing the potential difference between the sensing bit line SBL and the sensing complementary bit line SBLB.

[0166] Fig.26 is a diagram for explaining a stacked memory device according to some embodiments.

[0167] Reference Fig.26 , the stacked memory device 300 may include a buffer die 310 and a plurality of core dies 320, 330, 340, and 350. The buffer die 310 may also be referred to as an interface die, a base die, a logic die, a master die, etc., and each of the core dies 320 to 350 may also be referred to as a storage die, a slave die, etc. Although Fig.26 The stacked memory device 300 is shown as including four core dies 320 to 350, but the number of core dies may vary. For example, the stacked memory device 300 may include eight, twelve, or sixteen core dies.

[0168] The buffer die 310 and the core dies 320 to 350 may be stacked and electrically connected through through silicon vias (TSVs). Therefore, the stacked memory device 300 may have a three-dimensional memory structure in which a plurality of dies 310 to 350 are stacked. For example, the stacked memory device 300 may be implemented based on the HBM or HMC standard.

[0169] The stacked memory device 300 may support multiple functionally independent channels (or libraries). For example, the stacked memory device 300 may support eight channels CH0, CH1, CH2, CH3, CH4, CH5, CH6, and CH7. If each of the channels CH0 to CH7 supports 128 data (DQ) transmission paths (I / O), the stacked memory device 300 may support 1024 data transmission paths. However, the embodiment is not limited thereto, and the stacked memory device 300 may support 1024 or more data transmission paths, and may support 8 or more channels (e.g., 16 channels). If the stacked memory device 300 supports 16 channels, each channel may support 64 data transmission paths.

[0170] Each of the core dies 320 to 350 may support at least one channel. Fig.26 As shown, each of the core dies 320 to 350 can support 2 channels (CH0 to CH2, CH1 to CH3, CH4 to CH6, and CH5 to CH7). In this case, the core dies 320 to 350 can support different channels from each other. However, the present disclosure is not limited thereto, and at least two of the core dies 320 to 350 can support the same channel. For example, each of the core dies 320 to 350 can support the first channel CH0.

[0171] Each channel may constitute an independent command and data interface. For example, each channel may be independently clocked based on independent timing requirements and may not be synchronized with each other. For example, each channel may change power states or perform refresh based on independent commands.

[0172] Each channel may include a plurality of memory banks 301. Each of the memory banks 301 may include a memory cell MC (eg, Figure 2 ), row decoder 130 (as shown in Figure 1 ), column decoder 140 (as shown in Figure 1 ), sense amplifier 150 (as shown in Figure 1 As shown in FIG. 1 , etc. For example, each of the channels CH0 to CH7 may include eight memory banks 301. However, the present disclosure is not limited thereto, and each of the channels CH0 to CH7 may include eight or more memory banks 301. Fig.26 It is shown that the memory banks included in one channel are included in one core die, but the memory banks included in one channel may be distributed in a plurality of core dies. For example, if each of the core dies 320 to 350 supports the first channel CH0, the memory banks included in the first channel CH0 may be distributed to the core dies 320 to 350.

[0173] In some embodiments, a channel can be divided into two pseudo channels that operate independently. For example, the pseudo channels can share the command and clock inputs of the channel (e.g., clock signal CK and clock enable signal CKE), but can decode and execute commands independently. For example, if a channel supports 128 data transmission paths, each pseudo channel can support 64 data transmission paths. For example, if a channel supports 64 data transmission paths, each pseudo channel can support 32 data transmission paths.

[0174] The buffer die 310 and the core die 320 to 350 may include a through silicon via (TSV) area 302. TSVs configured to pass through the die 310 to 350 may be placed in the TSV area 302. The buffer die 310 may send signals and / or data to the core die 320 to 350 through the TSVs, and receive signals and / or data from the core die 320 to 350. Each of the core die 320 to 350 may send signals and / or data to the buffer die 310 and other core die through the TSVs, and receive signals and / or data from the buffer die 310 and other core die. In this case, signals and / or data may be sent and received independently through the corresponding TSVs of each channel. For example, if an external host device sends a command and an address to the first channel CH0 to access the memory cell of the first core die 320, the buffer die 310 may send a control signal to the first core die 320 through the TSV corresponding to the first channel CH0 to access the memory cell of the first channel CH0.

[0175] The buffer die 310 and the core die 320 to 350 may also include control logic 114 (eg, Figure 1 ). The control logic may control access to the memory bank 301 based on a command and an address signal provided from the memory controller, and generate a control signal for accessing the memory bank 301.

[0176] The buffer die 310 and the core dies 320 to 350 may include a Figure 4 or Fig.23 In some embodiments, the charge transfer transistor driver circuits 180 and 180A may be placed or disposed in the bonding area of ​​the buffer die 310, and Figure 4 The voltage generator 170 may also be placed or disposed in a peripheral circuit region of the buffer die 310 .

[0177] The buffer die 310 may include a physical layer (PHY) 311. The physical layer 311 may include an interface circuit for communicating with an external host device. For example, the physical layer 311 may include an interface circuit for communicating with an external host device. Figure 1The signals and / or data received through the physical layer 311 may be transmitted to the core dies 320 to 350 through the TSVs.

[0178] In some embodiments, the buffer die 310 may include a channel controller corresponding to each channel. The channel controller may manage memory reference operations of the corresponding channel and may determine timing requirements of the corresponding channel.

[0179] In some embodiments, the buffer die 310 may include a plurality of pins for receiving signals from an external host device. The buffer die 310 may receive a clock signal CK, a command / address signal C / A, a write data select signal WDQS, and a data signal DQ through a plurality of pins, and send a read data select signal RDQS and a data signal DQ. For example, the buffer die 310 may include 2 pins for receiving the clock signal CK, 14 pins for receiving the command / address signal C / A, 8 pins for receiving the write data select signal WDQS, 8 pins for sending the read data select signal RDQS, and 128 pins for sending and receiving the data signal DQ of each channel.

[0180] Fig. 27 is a diagram for explaining a semiconductor package according to some embodiments.

[0181] Reference Fig. 27 , the semiconductor package 1000 may include a stacked memory device 1100, a system on chip 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and core dies 1120, 1130, 1140, and 1150. The buffer die 1110 may correspond to Fig.26 The buffer die 310 of FIG. 1 and each of the core dies 1120 to 1150 may correspond to Fig.26 Each of the core tube dies 320 to 350.

[0182] Each of the core dies 1120 to 1150 may include a memory cell array 110 (eg, Figure 1 110). The buffer die 1110 may include a physical layer (PHY) 1111 and a direct access area (DAB) 1112. The physical layer 1111 may be electrically connected to a physical layer 1210 of the system on chip 1200 through the interposer 1300. The stacked memory device 1100 may receive a signal from the system on chip 1200 or transmit a signal to the system on chip 1200 through the physical layer 1111. The physical layer 1111 may include a reference Fig.26 The interface circuitry of the buffer die 310 is described.

[0183] The direct access area 1112 may provide an access path that can be used to test the stacked memory device 1100 without passing through the system on chip 1200. The direct access area 1112 may include a conductive device (e.g., a port or pin) that can communicate directly with an external test device. The test signals and data received through the direct access area 1112 may be sent to the core dies 1120 to 1150 through the TSV 1101. The data read from the core dies 1120 to 1150 for testing the core dies 1120 to 1150 may be sent to the test device through the TSV 1101 and the direct access area 1112. Therefore, direct access testing can be performed on the core dies 1120 to 1150.

[0184] The buffer die 1110 and the core dies 1120 to 1150 may be electrically connected to each other through the TSV 1101 and the bumps 1102. The buffer die 1110 may receive a signal provided to each channel from the system on chip 1200 through the bumps 1102 allocated to each channel. For example, a single one of the bumps 1102 may include a micro bump.

[0185] The system on chip 1200 may use the stacked memory device 1100 to execute an application supported by the semiconductor package 1000. For example, the system on chip 1200 may perform dedicated computing by including at least one processor of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a visual processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP).

[0186] The system on chip 1200 may include a physical layer 1210 and a memory controller 1220. The physical layer 1210 may include an I / O circuit for transmitting and receiving signals to and from the physical layer 1111 of the stacked memory device 1100. The system on chip 1200 may provide various signals to the physical layer 1111 through the physical layer 1210. The signals provided to the physical layer 1111 may be transmitted to the core dies 1120 to 1150 through the interface circuit of the physical layer 1111 and the TSV 1101.

[0187] The memory controller 1220 may control the overall operation of the stacked memory device 1100. The memory controller 1220 may transmit a signal for controlling the stacked memory device 1100 to the stacked memory device 1100 through the physical layer 1210.

[0188] The interposer 1300 may connect the stacked memory device 1100 and the system on chip 1200. The interposer 1300 may be connected between the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system on chip 1200, and may provide a physical path formed using a conductive material. Therefore, the stacked memory device 1100 and the system on chip 1200 may be stacked on the interposer 1300 to transmit and receive signals to and from each other.

[0189] The bumps 1103 may be attached to the upper portion of the package substrate 1400, and the solder balls 1104 may be attached to the lower portion of the package substrate 1400. For example, the bumps 1103 may be flip chip bumps. The interposer 1300 may be stacked on the package substrate 1400 through the bumps 1103. The semiconductor package 1000 may send and receive signals to and from other external packages or semiconductor devices through the solder balls 1104. For example, the package substrate 420 may be a printed circuit board (PCB).

[0190] Fig.28 is a diagram for explaining a memory module and a memory controller including a memory device according to some embodiments.

[0191] Fig.28 A system including a memory controller 405 and a memory module 403 is shown. The memory element 400 formed on the memory module 403 may be configured as any one of the embodiments of the present disclosure described above.

[0192] Fig.29 is a diagram for illustrating a computer system including a memory device according to some embodiments.

[0193] Fig.29 An example of the structure of the computer system is shown, and the memory element 413 may be configured as any one of the embodiments of the present disclosure described above. Fig.29 The computer system shown in FIG. 4 may include a processor 410 , a cache 411 , a system controller 412 , a memory controller 414 , a memory element 413 , an input device 415 , an output device 416 , and a data storage device 417 .

[0194] The embodiments of the present disclosure have been described above with reference to the accompanying drawings, but the present disclosure is not limited thereto and can be implemented in various different forms. Therefore, it should be understood that the embodiments set forth herein are illustrative rather than restrictive.

Claims

1. A storage device, include: A memory cell array including a first memory cell connected to a bit line and a second memory cell connected to a complementary bit line; a bit line sense amplifier, comprising a sense bit line connected to the bit line, and a sense complementary bit line connected to the complementary bit line, wherein the bit line sense amplifier is configured to: output a signal of the sense bit line to the bit line and output a signal of the sense complementary bit line to the complementary bit line to sense data stored in the first storage unit and the second storage unit; a first charge transfer transistor connected between the bit line and the sensing bit line, wherein a gate of the first charge transfer transistor receives a first signal via a first node; a second charge transfer transistor connected between the complementary bit line and the sensing complementary bit line, wherein a gate of the second charge transfer transistor receives a second signal via a second node; A first precharge transistor configured to: precharge the bit line and the complementary bit line with a first precharge voltage; A second precharge transistor is configured to: precharge the sensing bit line and the sensing complementary bit line with a second precharge voltage different from the first precharge voltage; a first transfer gate transistor configured to: provide a first transfer gate voltage to a gate of the first charge transfer transistor in response to a first control signal; and The second transfer gate transistor is configured to provide a second transfer gate voltage different from the first transfer gate voltage to the gate of the second charge transfer transistor in response to the first control signal.

2. The storage device according to claim 1, further comprising: include: a first isolation transistor connected between a first isolation voltage line and the first node and turned on in response to a second control signal different from the first control signal to turn on the first charge transfer transistor; as well as The second isolation transistor is connected between the second isolation voltage line and the second node and is turned on in response to the second control signal to turn on the second charge transfer transistor.

3. The memory device according to claim 2, in, The first isolation transistor is turned on during a first interval and a second interval after the first interval, and the first charge transfer transistor is gated by the first transfer gate voltage during a third interval between the first interval and the second interval.

4. The memory device according to claim 3, in, The second isolation transistor is turned on during the first interval and the second interval, and the second charge transfer transistor is gated by the second transfer gate voltage during the third interval.

5. The storage device according to claim 1, further comprising: include: a third transfer gate transistor configured to: provide the second transfer gate voltage to the gate of the first charge transfer transistor in response to a second control signal different from the first control signal; as well as The fourth transfer gate transistor is configured to provide the first transfer gate voltage to the gate of the second charge transfer transistor in response to the second control signal.

6. The memory device according to claim 1, further comprising: include: a voltage generator configured to generate the first transmission gate voltage and the second transmission gate voltage, The voltage generator is arranged in a peripheral circuit region, and the peripheral circuit region is separated from a region where the memory cell array is arranged.

7. The memory device according to claim 1, in, In response to the bit line sense amplifier sensing data stored in the first memory cell, a magnitude of the first transmission gate voltage is greater than a magnitude of the second transmission gate voltage.

8. The memory device according to claim 1, in, In response to the bit line sense amplifier sensing data stored in the second memory cell, a magnitude of the first transmission gate voltage is smaller than a magnitude of the second transmission gate voltage.

9. The memory device according to claim 1, in, The bit line sense amplifier further comprises: A P-type amplifying part having a first end connected to a first control line, to which a third control signal is applied, and a second end connected to the sensing bit line and the sensing complementary bit line; an N-type amplifying portion having a first terminal connected to a second control line and a second terminal connected to the sensing bit line and the sensing complementary bit line, a fourth control signal different from the third control signal being applied to the second control line, The amplifying transistor of the P-type amplifying part and the amplifying transistor of the N-type amplifying part are connected to each other through cross coupling.

10. A memory device, include: A memory cell array including a first memory cell connected to a bit line and a second memory cell connected to a complementary bit line; a bit line sense amplifier, comprising a sense bit line connected to the bit line, and a sense complementary bit line connected to the complementary bit line, wherein the bit line sense amplifier is configured to: output a signal of the sense bit line to the bit line and output a signal of the sense complementary bit line to the complementary bit line to sense data stored in the first storage unit and the second storage unit; a first charge transfer transistor connected between the bit line and the sensing bit line and selected by a first signal provided to a first node; a second charge transfer transistor connected between the complementary bit line and the sensing complementary bit line and gated by a second signal connected to a second node; and A plurality of transmission gate transistors, the plurality of transmission gate transistors configured to: in response to the bit line sense amplifier sensing data stored in the first memory cell, provide a first transfer gate voltage to the gate of the first charge transfer transistor, and provide a second transfer gate voltage lower than the first transfer gate voltage to the gate of the second charge transfer transistor, and The device is configured to provide the second transfer gate voltage to the gate of the first charge transfer transistor and provide the first transfer gate voltage to the gate of the second charge transfer transistor in response to the bit line sense amplifier sensing data stored in the second memory cell.

11. The storage device according to claim 10, further comprising: include: A first precharge transistor is connected between a third node between the sensing bit line and the sensing complementary bit line and a first precharge voltage line, wherein the first precharge transistor precharges the bit line and the complementary bit line with a first precharge voltage.

12. The storage device according to claim 11, further comprising: include: A second precharge transistor is connected between the third node and the second precharge voltage line, wherein the second precharge transistor precharges the sensing bit line and the sensing complementary bit line with a second precharge voltage different from the first precharge voltage.

13. The memory device according to claim 12, in, The amplitude of the first pre-charge voltage is greater than the amplitude of the second pre-charge voltage.

14. The memory device according to claim 10, in, The plurality of pass-gate transistors include: a first transfer gate transistor connected between the first node and a first voltage line, and providing the first transfer gate voltage through the first voltage line, wherein the first transfer gate transistor is configured to: provide the first transfer gate voltage to the first node in response to a first control signal; and A second transfer gate transistor is connected between the second node and a second voltage line, and provides the second transfer gate voltage through the second voltage line, wherein the second transfer gate transistor is configured to: provide the second transfer gate voltage to the second node in response to the first control signal.

15. The memory device according to claim 14, in, The plurality of pass-gate transistors further include: a third transfer gate transistor connected between the first node and a third voltage line, and providing the second transfer gate voltage through the third voltage line, wherein the third transfer gate transistor is configured to: provide the second transfer gate voltage to the first node in response to a second control signal different from the first control signal; and A fourth transfer gate transistor is connected between the second node and a fourth voltage line, and provides the first transfer gate voltage through the fourth voltage line, wherein the fourth transfer gate transistor is configured to: provide the first transfer gate voltage to the second node in response to the second control signal.

16. A method for driving a sensing device, the sensing device being configured to sense data of a first memory cell connected to the bit line and a second memory cell connected to the complementary bit line by using a bit line sense amplifier including a sensing bit line and a sensing complementary bit line, a first charge transfer transistor connected to the sensing bit line and the bit line, and a second charge transfer transistor connected to the sensing complementary bit line and the complementary bit line, the method include: precharging the sensing bit line and the sensing complementary bit line using a first precharge voltage; providing a first transfer gate voltage to a gate of the first charge transfer transistor, and providing a second transfer gate voltage different from the first transfer gate voltage to a gate of the second charge transfer transistor; as well as An isolation voltage greater than the magnitude of each of the first transfer gate voltage and the second transfer gate voltage is applied to the gate of the first charge transfer transistor and the gate of the second charge transfer transistor, and data stored in at least one of the first storage cell and the second storage cell is sensed.

17. The method for driving a sensing device according to claim 16, further comprising: include: precharging the sensing bit line and the sensing complementary bit line by using the first precharge voltage, and at the same time, precharging the bit line and the complementary bit line by using the first precharge voltage; as well as A second precharge voltage different from the first precharge voltage is then applied to the sensing bit line and the sensing complementary bit line.

18. The method for driving a sensing device according to claim 17, in, In response to a first word line connected to the first memory cell being activated and a magnitude of the first precharge voltage being smaller than a magnitude of the second precharge voltage, a magnitude of the first transfer gate voltage is greater than a magnitude of the second transfer gate voltage.

19. The method for driving a sensing device according to claim 17, in, In response to a first word line connected to the first memory cell being activated and the first precharge voltage having a magnitude greater than the second precharge voltage, an absolute value of the first transmission gate voltage has a magnitude greater than an absolute value of the second transmission gate voltage.

20. The method for driving a sensing device according to claim 16, in, During a first interval, applying the first transfer gate voltage to the gate of the first charge transfer transistor and applying the second transfer gate voltage to the gate of the second charge transfer transistor, During a second interval prior to the first interval, applying the isolation voltage to each of the gate of the first charge transfer transistor and the gate of the second charge transfer transistor, and During a third interval after the first interval, the isolation voltage is applied to a gate of the first charge transfer transistor and a gate of the second charge transfer transistor.

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