Storage unit, memory and working method thereof
By introducing an amplification unit and a selection transistor design into the SRAM memory unit, the problem of insufficient accuracy and efficiency of the existing SRAM memory unit in the read and write operations is solved, and higher accuracy of the storage state judgment and Stability of write operations.
Patent Information
- Application Number
- CN202310733111.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-19
- Publication Date
- 2024-12-20
AI Technical Summary
The performance of existing SRAM memory cell structures needs to be improved, especially in terms of accuracy and efficiency of read and write operations.
A memory cell is designed, including a first inverter, a second inverter, an amplification unit and a selection transistor. By connecting the amplification unit at a latch point of the second inverter, current amplification is performed using a bipolar transistor. Accurate reading of the storage state of the memory cell is realized, and data reversal is reduced through the on-control of the selection transistor.
The amplification unit amplifies the read current, improves the accuracy and efficiency of the read operation, reduces data inversion caused by performance matching problems between the selection transistor and the pull-down transistor, and improves the write margin and working window .
Smart Images
Figure CN119170073A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a storage unit, a memory and a working method thereof. Background Art
[0002] With the continuous development of microelectronics technology, memory has shown a development trend of high integration, fast speed and low power consumption. Compared with dynamic random access memory (DRAM), static random read-write memory (SRAM) can save the internal stored data without refreshing circuit. Moreover, unlike dynamic random access memory, it does not need to be flushed and charged at regular intervals, otherwise the internal data will disappear. Therefore, static random read-write memory has better performance. Static random read-write memory has made great progress in recent years. As an important product in semiconductor memory, it has been widely used in high-speed data exchange systems such as computers, communications, and multimedia.
[0003] However, the performance of the existing SRAM storage cell structure needs to be further improved. Summary of the invention
[0004] The technical problem solved by the present invention is to provide a storage unit, a memory and a working method thereof, so as to improve the performance of the formed SRAM storage unit structure.
[0005] To solve the above technical problems, the technical solution of the present invention provides a storage unit, including: a first inverter, the first inverter has a first latch point; a second inverter, the second inverter has a second latch point; a first bit line, connected to the first latch point; a second bit line, connected to the second latch point; an amplification unit, including an input end and an output end, the input end is connected to the second latch point, and the output end is used to output a read current.
[0006] Optionally, the amplifying unit includes a bipolar transistor.
[0007] Optionally, the bipolar transistor is of NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor, and the emitter end of the bipolar transistor is grounded; the bipolar transistor is of PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
[0008] Optionally, it also includes: a first selection transistor, one of the source and drain terminals of the first selection transistor is connected to the first latch point, and the other of the source and drain terminals of the first selection transistor is connected to the first bit line; a second selection transistor, one of the source and drain terminals of the second selection transistor is connected to the second latch point, and the other of the source and drain terminals of the second selection transistor is connected to the second bit line; a first word line, the first word line is connected to the gate terminal of the first selection transistor and the gate terminal of the second selection transistor.
[0009] Optionally, it further includes: a switching transistor, one end of the source and drain ends of the switching transistor is connected to the second latch point, and the other end of the source and drain ends of the switching transistor is connected to the input end of the amplifying unit.
[0010] Optionally, it also includes: a second word line, wherein the second word line is connected to the gate terminal of the switching transistor.
[0011] Optionally, it also includes: a third bit line, wherein the third bit line is connected to the output end of the amplification unit.
[0012] Optionally, one end of the first inverter is connected to a power supply terminal, and the other end of the first inverter is grounded; one end of the second inverter is connected to the power supply terminal, and the other end of the second inverter is grounded.
[0013] Optionally, it also includes: the first inverter includes a first pull-up transistor and a first pull-down transistor connected to each other, one end of the source and drain ends of the first pull-up transistor is connected to the power supply end, the other end of the source and drain ends of the first pull-up transistor and one end of the source and drain ends of the first pull-down transistor are connected to the first latch point, the other end of the source and drain ends of the first pull-down transistor is grounded, and the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the second latch point; the second inverter includes a second pull-up transistor and a second pull-down transistor connected to each other, one end of the source and drain ends of the second pull-up transistor is connected to the power supply end, one end of the source and drain ends of the second pull-up transistor and the other end of the source and drain ends of the second pull-down transistor are connected to the second latch point, the other end of the source and drain ends of the second pull-down transistor is grounded, and the gate of the second pull-up transistor and the gate of the second pull-down transistor are connected to the first latch point.
[0014] Optionally, the first inverter includes a first pull-up transistor, one of the source and drain terminals of the first pull-up transistor is connected to the first latch point, the other of the source and drain terminals of the first pull-up transistor is connected to the power supply terminal, and the gate of the first pull-up transistor is connected to the second latch point; the second inverter includes a second pull-up transistor, one of the source and drain terminals of the second pull-up transistor is connected to the second latch point, the other of the source and drain terminals of the second pull-up transistor is connected to the power supply terminal, and the gate of the second pull-up transistor is connected to the first latch point.
[0015] Correspondingly, the technical solution of the present invention also provides a memory, comprising: a storage array, the storage array comprising a plurality of storage units as described in any one of the above items; a reading unit, used to apply a voltage to the output end of the amplifying unit in the storage unit to be operated, and read the current output from the output end.
[0016] Optionally, the reading unit is further used to apply a first voltage to the second word line in the memory cell to be operated to control conduction of the switching transistor.
[0017] Optionally, the reading unit is further used to apply a second voltage to the third bit line in the memory cell to be operated, so that the bipolar transistor operates in an amplification state.
[0018] Optionally, it also includes: a writing unit, used to apply a third voltage to the first word line in the memory cell to be operated to control the conduction of the first selection transistor and the second selection transistor, and load the state to be written to the first bit line and the second bit line in the memory cell to be operated respectively.
[0019] Correspondingly, the technical solution of the present invention also provides a working method of a memory, wherein the memory includes: a memory array, the memory array includes a plurality of memory cells distributed in an array; the memory cell includes: a first inverter, the first inverter has a first latch point; a second inverter, the second inverter has a second latch point; a first bit line, connected to the first latch point; a second bit line, connected to the second latch point; an amplifying unit, including an input end and an output end, the input end is connected to the second latch point, and the output end is used to output a read current; a method for performing a read operation on the memory cell to be operated includes: applying a voltage to the output end of the amplifying unit in the memory cell to be operated, and reading the current output from the output end.
[0020] Optionally, the amplifying unit includes a bipolar transistor; the method further includes: applying a voltage to the output end of the amplifying unit in the storage unit to be operated, so that the bipolar transistor operates in an amplifying state.
[0021] Optionally, the bipolar transistor is of NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor, and the emitter end of the bipolar transistor is grounded; the bipolar transistor is of PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
[0022] Optionally, the storage unit also includes: a first selection transistor, one of the source and drain terminals of the first selection transistor is connected to the first latch point, and the other of the source and drain terminals of the first selection transistor is connected to the first bit line; a second selection transistor, one of the source and drain terminals of the second selection transistor is connected to the second latch point, and the other of the source and drain terminals of the second selection transistor is connected to the second bit line; a first word line, the first word line is connected to the gate terminal of the first selection transistor and the gate terminal of the second selection transistor; the method for performing a read operation on the storage unit to be operated also includes: inputting a low level to the first word line to turn off the first selection transistor and the second selection transistor.
[0023] Optionally, before performing a read operation on the memory cell to be operated, a write operation is performed on the memory cell; the write operation includes: inputting a high level to the first word line so that the first selection transistor and the second selection transistor are turned on to write the states of the first bit line and the second bit line into the memory cell.
[0024] Optionally, the method for performing a read operation on the storage unit to be operated further includes: inputting a high level to the first bit line and the second bit line respectively.
[0025] Optionally, the storage unit also includes: a switching transistor, one end of the source and drain ends of the switching transistor is connected to the second latch point, and the other end of the source and drain ends of the switching transistor is connected to the input end of the amplification unit; the method for performing a reading operation on the storage unit to be operated also includes: inputting a high level at the gate end of the switching transistor to turn on the switching transistor.
[0026] Optionally, the storage unit further includes: a second word line, the second word line is connected to the gate terminal of the switching transistor; and the method of inputting a high level to the gate terminal of the switching transistor includes: inputting a high level to the second word line.
[0027] Optionally, the storage unit further includes: a third bit line, the third bit line being connected to the output end of the amplifying unit; and the method of applying a voltage to the output end of the amplifying unit in the storage unit to be operated includes: applying a voltage to the third bit line.
[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0029] In the storage unit provided by the technical solution of the present invention, an amplification unit is connected to the second latch point of the second inverter, the input end of the amplification unit is connected to the second latch point, and the output end is used to output a read current, and the storage state of the storage unit is obtained by reading the single-side signal of the storage unit. Specifically, when the second latch point is at a logic 1, that is, a high level, a read current can be obtained, and due to the amplification effect of the amplification unit on the current, a larger current signal can be obtained, and when the second latch point is at a logic 0, that is, a low level, the read current cannot be obtained, thereby, the storage state of the second latch point can be determined by reading the size of the current signal, and the storage state of the storage unit can be further determined. At the same time, due to the amplification effect of the amplification unit on the current, it is beneficial to improve the accuracy of the reading operation.
[0030] Furthermore, the amplification unit includes a bipolar transistor. When the second latch point is at logic 1, i.e., a high level, the bipolar transistor is turned on, and a current flows from the second latch point to the bipolar transistor. At the same time, the bipolar transistor is controlled to work in an amplification state, and a larger current signal can be obtained from the third end of the bipolar transistor. When the second latch point is at logic 0, i.e., a low level, the bipolar transistor is turned off, and a current signal cannot be obtained from the third end of the bipolar transistor. The storage state of the second latch point can be determined by the size of the current signal obtained from the third end of the bipolar transistor, and the storage state of the storage unit can be further determined. The amplification effect of the current signal when the bipolar transistor is turned on is conducive to improving the accuracy of the reading operation.
[0031] Furthermore, the memory cell further includes: a first selection transistor, a second selection transistor and a first word line, wherein the first word line is used to control the conduction state of the first selection transistor and the second selection transistor. When performing a write operation on the memory cell, a high voltage needs to be input to the first word line to turn on the first selection transistor and the second selection transistor, and in a read operation of the memory cell, the first selection transistor and the second selection transistor are turned off, thereby reducing the situation of storage data inversion caused by the performance matching problem between the first selection transistor (the second selection transistor) and the first pull-down transistor (the second pull-down transistor) in the read operation. At the same time, since the first selection transistor and the second selection transistor have little influence on the read operation, the first selection transistor and the second selection transistor with appropriate performance can be selected to facilitate the write operation and improve the write margin. In short, it is beneficial to improve the working window of the read operation and the write operation as a whole.
[0032] Furthermore, the memory cell further comprises a switch transistor. When the memory cell does not need to be read, the switch transistor is turned off, thereby reducing leakage of the device and improving the performance of the device.
[0033] In the working method of the memory provided by the technical solution of the present invention, a voltage is applied to the output end of the amplifying unit in the memory cell to be operated, and the current output from the output end is read, and the storage state of the memory cell is obtained by reading the single-side signal of the memory cell. Specifically, when the second latch point is at logic 1, that is, a high level, a read current can be obtained, and due to the amplification effect of the amplifying unit on the current, a larger current signal can be obtained, and when the second latch point is at logic 0, that is, a low level, the read current cannot be obtained, thereby, the storage state of the second latch point can be determined by reading the size of the current signal, and the storage state of the memory cell can be further determined. At the same time, due to the amplification effect of the amplifying unit on the current, it is beneficial to improve the accuracy of the reading operation.
[0034] Furthermore, the amplification unit includes a bipolar transistor, and a voltage is applied to the third bit line so that the bipolar transistor operates in an amplification state. When the second latch point is at a logic 1, i.e., a high level, the bipolar transistor is turned on, and a current flows from the second latch point to the bipolar transistor, and at the same time, the bipolar transistor is controlled to operate in an amplification state, and a larger current signal can be obtained from the third end of the bipolar transistor. When the second latch point is at a logic 0, i.e., a low level, the bipolar transistor is turned off, and a current signal cannot be obtained from the third end of the bipolar transistor. The storage state of the second latch point can be determined by the size of the current signal obtained from the third end of the bipolar transistor, and the storage state of the storage unit can be further determined. The amplification effect of the current signal when the bipolar transistor is turned on is conducive to improving the accuracy of the reading operation.
[0035] Furthermore, the method for performing a read operation on the memory cell to be operated further includes: inputting a low level to the first word line to turn off the first selection transistor and the second selection transistor, and when performing a write operation on the memory cell, a high voltage needs to be input to the first word line to turn on the first selection transistor and the second selection transistor, and in the read operation of the memory cell, the first selection transistor and the second selection transistor are turned off, thereby reducing the situation of storage data inversion caused by the performance matching problem between the first selection transistor (the second selection transistor) and the first pull-down transistor (the second pull-down transistor) in the read operation, and at the same time, since the first selection transistor and the second selection transistor have little influence on the read operation, the first selection transistor and the second selection transistor with suitable performance can be selected to facilitate the write operation and improve the write margin. In short, it is beneficial to improve the working window of the read operation and the write operation as a whole.
[0036] Furthermore, the storage unit further includes a switch transistor, and the method for performing a read operation on the storage unit to be operated further includes: inputting a high level to the first control terminal of the switch transistor to turn on the switch transistor. Accordingly, when the storage unit does not need to be read, the switch transistor is turned off, which can reduce the leakage of the device and improve the performance of the device.
[0037] Furthermore, the method for performing a read operation on the storage unit to be operated further includes: inputting a high level to the first bit line and the second bit line respectively. Inputting a high level to the first bit line and the second bit line can reduce leakage of the device and improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 It is a schematic diagram of the structure of a 6T storage unit;
[0039] Figure 2 is a schematic structural diagram of a storage unit in one embodiment of the present invention;
[0040] Figure 3 It is a schematic structural diagram of a storage unit in another embodiment of the present invention. DETAILED DESCRIPTION
[0041] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.
[0042] As described in the background art, the performance of the existing SRAM storage cell structure needs to be improved. Now, an SRAM structure of a 6T storage cell is described and analyzed.
[0043] Figure 1 It is a schematic diagram of the structure of a 6T storage unit.
[0044] Please refer to Figure 1 The storage unit of the 6T structure is composed of 6 MOS tubes. Each bit of data in the SRAM is stored in two cross-coupled inverters composed of M1, M2, M3 and M4, which are used to latch the signals of the storage nodes N1 and N2. BL and BLB are mutually locked bit lines (Bit Line), which are used to read and write data. WL is the word line (Word Line), which is used to control the read and write operations. The two NMOS tubes M5 and M6 are control switches, which are used to control the transfer of data from the storage unit to the bit line. Among them, M1, M3, M5 and M6 are NMOS tubes, which are turned on at a high level, and M2 and M4 are PMOS tubes, which are turned on at a low level.
[0045] The above storage unit has three states: standby, reading and writing.
[0046] In the idle state, the word line is pulled down, that is, the word line WL is at a low level, then the two transistors M5 and M6 are in the cut-off state, isolating the memory cell from the bit line. The two inverters composed of M1-M4 continue to maintain their state.
[0047] Before the write operation is performed, the state to be written is loaded into the bit line. If data 0 needs to be written, BL=0 and BLB=1 are set. Then the word line WL is set to a high level, the two transistors M5 and M6 are turned on, and the state of the bit line is written into the storage cell.
[0048] Before the start of the read cycle, the levels of the two bit lines are charged to logic "1" through the precharge circuit. Then WL is set to a high level, so that the two transistors M5 and M6 are turned on. Assuming N2 = "1", the high level at the N2 end turns on the transistor M1, and the high level previously precharged on the bit line BL is connected to the ground through M5 and M1, making its value logical "0"; on the side of the bit line BLB, because N1 = "0", transistors M4 and M6 are turned on, and the bit line BLB is pulled to a high level logic "1" through VDD.
[0049] During the read operation, the above SRAM memory cell structure determines the storage state of N1 / N2 by the potential difference between the bit line BL and the bit line BLB. When the potential difference is very small, it is easy to fail to read the storage state, resulting in unstable device performance.
[0050] In order to solve the above problems, the present invention provides a storage unit, a memory and a working method thereof, wherein an amplification unit is connected to the second latch point of the second inverter, the input end of the amplification unit is connected to the second latch point, and the output end is used to output a read current, and the storage state of the storage unit is obtained by reading the single-side signal of the storage unit. Specifically, when the second latch point is at a logic 1, that is, a high level, a read current can be obtained, and due to the amplification effect of the amplification unit on the current, a larger current signal can be obtained, and when the second latch point is at a logic 0, that is, a low level, the read current cannot be obtained, thereby, the storage state of the second latch point can be determined by reading the size of the current signal, and the storage state of the storage unit can be further determined. At the same time, due to the amplification effect of the amplification unit on the current, it is beneficial to improve the accuracy of the reading operation.
[0051] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0052] Figure 2 It is a schematic diagram of the structure of a storage unit in one embodiment of the present invention.
[0053] Please refer to Figure 2 The storage unit includes: a first inverter, the first inverter having a first latch point S1; a second inverter, the second inverter having a second latch point S2; a first bit line WBL connected to the first latch point S1; a second bit line WBLB connected to the second latch point S2; an amplification unit (such as Figure 2 The second latch point S2 is connected to the input terminal and the output terminal is used to output the read current.
[0054] In the storage unit, the second latch point S2 of the second inverter is connected to the amplification unit, the input end of the amplification unit is connected to the second latch point S2, and the output end is used to output the read current, and the storage state of the storage unit is obtained by reading the single-side signal of the storage unit. Specifically, when the second latch point is at logic 1, that is, a high level, the read current can be obtained, and due to the amplification effect of the amplification unit on the current, a larger current signal can be obtained, and when the second latch point is at logic 0, that is, a low level, the read current cannot be obtained, thereby, the storage state of the second latch point S2 can be determined by reading the size of the current signal, and the storage state of the storage unit can be further determined. At the same time, due to the amplification effect of the amplification unit on the current, it is beneficial to improve the accuracy of the reading operation.
[0055] In this embodiment, the amplification unit includes a bipolar junction transistor (BJT). When the second latch point is at logic 1, i.e., a high level, the bipolar transistor BJT is turned on, and a current flows from the second latch point S2 to the bipolar transistor BJT. At the same time, the bipolar transistor BJT is controlled to work in an amplification state, and a larger current signal can be obtained from the third end of the bipolar transistor BJT. When the second latch point is at logic 0, i.e., a low level, the bipolar transistor is turned off, and a current signal cannot be obtained from the third end of the bipolar transistor BJT. The storage state of the second latch point S2 can be determined by the size of the current signal obtained from the third end of the bipolar transistor BJT, and the storage state of the storage unit can be further determined. The amplification effect of the current signal when the bipolar transistor BJT is turned on is conducive to improving the accuracy of the reading operation.
[0056] In this embodiment, the bipolar transistor BJT is an NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor, and the emitter end of the bipolar transistor is grounded. In another embodiment, the bipolar transistor is a PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
[0057] In this embodiment, the storage unit also includes: a first selection transistor PG1, one end of the source and drain ends of the first selection transistor PG1 is connected to the first latch point S1, and the other end of the source and drain ends of the first selection transistor PG1 is connected to the first bit line WBL; a second selection transistor PG2, one end of the source and drain ends of the second selection transistor PG2 is connected to the second latch point S2, and the other end of the source and drain ends of the second selection transistor PG2 is connected to the second bit line WBLB; a first word line WWL, the first word line WWL is connected to the gate end of the first selection transistor PG1 and the gate end of the second selection transistor PG2.
[0058] In this embodiment, the first selection transistor PG1 and the second selection transistor PG2 are NMOS. In other embodiments, the first selection transistor PG1 and the second selection transistor PG2 may also be PMOS.
[0059] The first word line WWL is used to control the conduction state of the first selection transistor PG1 and the second selection transistor PG2. When performing a write operation on the memory cell, a high voltage needs to be input to the first word line WWL to turn on the first selection transistor PG1 and the second selection transistor PG2. In the read operation of the memory cell, the first selection transistor PG1 and the second selection transistor PG2 are turned off, thereby reducing the storage data inversion caused by the performance matching problem between the first selection transistor PG1 (the second selection transistor PG2) and the first pull-down transistor PD1 (the second pull-down transistor PD2) in the read operation. At the same time, since the first selection transistor PG1 and the second selection transistor PG2 have little influence on the read operation, the first selection transistor PG1 and the second selection transistor PG2 with appropriate performance can be selected to facilitate the write operation and improve the write margin. In short, it is beneficial to improve the working window of the read operation and the write operation as a whole.
[0060] In another embodiment, the storage unit further includes: a switching transistor, one of the source and drain terminals of the switching transistor is connected to the second latch point, and the other of the source and drain terminals of the switching transistor is connected to the input terminal of the amplification unit; and a second word line, the second word line is connected to the gate terminal of the switching transistor.
[0061] In this embodiment, the storage unit further includes: a third bit line RBL, and the third bit line RBL is connected to the output end of the amplifying unit.
[0062] In this embodiment, one end of the first inverter is connected to the power supply terminal VDD, and the other end of the first inverter is grounded VSS. One end of the second inverter is connected to the power supply terminal VDD, and the other end of the second inverter is grounded VSS.
[0063] In this embodiment, the storage unit also includes: the first inverter includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected to each other, one end of the source and drain ends of the first pull-up transistor PU1 is connected to the power supply end VDD, the other end of the source and drain ends of the first pull-up transistor PU1 and one end of the source and drain ends of the first pull-down transistor PD1 are connected to the first latch point S1, the other end of the source and drain ends of the first pull-down transistor PD1 is grounded, and the gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1 are connected to the second latch point S2; the second inverter includes a second pull-up transistor PU2 and a second pull-down transistor PD2 connected to each other, one end of the source and drain ends of the second pull-up transistor PU2 is connected to the power supply end VDD, one end of the source and drain ends of the second pull-up transistor PU2 and the other end of the source and drain ends of the second pull-down transistor PD2 are connected to the second latch point S2, the other end of the source and drain ends of the second pull-down transistor PD2 is grounded VSS, and the gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2 are connected to the first latch point S1.
[0064] In this embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS, and the first pull-down transistor PD1 and the second pull-down transistor PD2 are NMOS. Therefore, specifically, the source end of the first pull-up transistor PU1 is connected to the power supply end VDD, the drain end of the first pull-up transistor PU1 and the drain end of the first pull-down transistor PD1 are connected to the first latch point S1, and the source end of the first pull-down transistor PD1 is grounded; the source end of the second pull-up transistor PU2 is connected to the power supply end VDD, the drain end of the second pull-up transistor PU2 and the drain end of the second pull-down transistor PD2 are connected to the second latch point S2, and the source end of the second pull-down transistor PD2 is grounded VSS.
[0065] In another embodiment, the first inverter includes a first pull-up transistor, one of the source and drain terminals of the first pull-up transistor is connected to the first latch point, the other of the source and drain terminals of the first pull-up transistor is connected to the power supply terminal, and the gate of the first pull-up transistor is connected to the second latch point; the second inverter includes a second pull-up transistor, one of the source and drain terminals of the second pull-up transistor is connected to the second latch point, the other of the source and drain terminals of the second pull-up transistor is connected to the power supply terminal, and the gate of the second pull-up transistor is connected to the first latch point.
[0066] Accordingly, a memory is also provided in one embodiment of the present invention, please continue to refer to Figure 2 , comprising: a storage array, the storage array comprising a plurality of the storage units described above; a reading unit (not shown in the figure), used to apply a voltage to the output end of the amplifying unit in the storage unit to be operated, and read the current output from the output end.
[0067] In this embodiment, the reading unit is further used to apply a second voltage to the third bit line RBL in the memory cell to be operated, so that the bipolar transistor BJT operates in an amplification state.
[0068] In this embodiment, the memory also includes: a write unit (not shown in the figure), which is used to apply a third voltage to the first word line WWL in the memory cell to be operated to control the conduction of the first selection transistor PG2 and the second selection transistor PG2, and load the state to be written to the first bit line WBL and the second bit line WBL in the memory cell to be operated.
[0069] In another embodiment, the storage unit further includes: a switching transistor, one of the source and drain terminals of the switching transistor is connected to the second latch point, and the other of the source and drain terminals of the switching transistor is connected to the input terminal of the amplification unit; and a second word line, the second word line is connected to the gate terminal of the switching transistor.
[0070] In another embodiment, the reading unit is further used to apply a first voltage to the second word line in the memory cell to be operated, so as to control the conduction of the switch transistor.
[0071] Accordingly, an embodiment of the present invention further provides a working method of a memory, wherein the memory comprises: a memory array, wherein the memory array comprises a plurality of memory cells distributed in an array; Figure 2 , including: a first inverter, the first inverter having a first latch point S1; a second inverter, the second inverter connected to a second latch point S2; a first bit line WBL, connected to the first latch point S1; a second bit line WBLB, connected to the second latch point S2; an amplifying unit, including an input end and an output end, the input end is connected to the second latch point S2, and the output end is used to output a read current; the method for performing a read operation on the storage unit to be operated includes: applying a voltage to the output end of the amplifying unit in the storage unit to be operated, and reading the current output from the output end.
[0072] In the working method, a voltage is applied to the output end of the amplifying unit in the memory cell to be operated, and the current output from the output end is read, and the storage state of the memory cell is obtained by reading the single-side signal of the memory cell. Specifically, when the second latch point is at logic 1, that is, a high level, a read current can be obtained, and due to the amplification effect of the amplifying unit on the current, a larger current signal can be obtained, and when the second latch point is at logic 0, that is, a low level, the read current cannot be obtained, thus, the storage state of the second latch point S2 can be determined by reading the size of the current signal, and the storage state of the memory cell can be further determined. At the same time, due to the amplification effect of the amplifying unit on the current, it is beneficial to improve the accuracy of the reading operation.
[0073] In this embodiment, the amplification unit includes a bipolar transistor BJT; the method further includes: applying a voltage to the output terminal of the amplification unit in the storage unit to be operated so that the bipolar transistor works in an amplification state. When the second latch point S2 is at a logic 1, i.e., a high level, the bipolar transistor is turned on, and a current flows from the second latch point S2 to the bipolar transistor BJT. At the same time, the bipolar transistor BJT is controlled to work in an amplification state, and a larger current signal can be obtained from the third terminal of the bipolar transistor BJT. When the second latch point is at a logic 0, i.e., a low level, the bipolar transistor BJT is turned off, and a current signal cannot be obtained from the third terminal of the bipolar transistor BJT. The storage state of the second latch point S2 can be determined by the size of the current signal obtained from the third terminal of the bipolar transistor BJT, and the storage state of the storage unit can be further determined. The amplification effect of the current signal when the bipolar transistor BJT is turned on is conducive to improving the accuracy of the reading operation.
[0074] In this embodiment, the bipolar transistor BJT is an NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor BJT, and the emitter end of the bipolar transistor BJT is grounded. In another embodiment, the bipolar transistor is a PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
[0075] In this embodiment, the bipolar transistor is of NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor, and the emitter end of the bipolar transistor is grounded; the bipolar transistor is of PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
[0076] In this embodiment, the storage unit also includes: a first selection transistor PG1, one end of the source and drain ends of the first selection transistor PG1 is connected to the first latch point S1, and the other end of the source and drain ends of the first selection transistor PG1 is connected to the first bit line WBL; a second selection transistor, one end of the source and drain ends of the second selection transistor PG2 is connected to the second latch point S2, and the other end of the source and drain ends of the second selection transistor PG2 is connected to the second bit line WBLB; a first word line WWL, the first word line WWL is connected to the gate end of the first selection transistor PG1 and the gate end of the second selection transistor PG2.
[0077] In this embodiment, before the read operation is performed on the memory cell to be operated, a write operation is performed on the memory cell; the write operation includes: inputting a high level to the first word line WWL, so that the first selection transistor PG1 and the second selection transistor PG2 are turned on, so as to write the states of the first bit line WBL and the second bit line WBLB into the memory cell.
[0078] In this embodiment, the method for performing a read operation on the memory cell to be operated further includes: inputting a low level to the first word line WWL to turn off the first selection transistor PG1 and the second selection transistor PG2.
[0079] The first word line WWL is used to control the conduction state of the first selection transistor PG1 and the second selection transistor PG2. When performing a write operation on the memory cell, a high voltage needs to be input to the first word line WWL to turn on the first selection transistor PG1 and the second selection transistor PG2. In the read operation of the memory cell, the first selection transistor PG1 and the second selection transistor PG2 are turned off, thereby reducing the storage data inversion caused by the performance matching problem between the first selection transistor PG1 (the second selection transistor PG2) and the first pull-down transistor PD1 (the second pull-down transistor PD2) in the read operation. At the same time, since the first selection transistor PG1 and the second selection transistor PG2 have little influence on the read operation, the first selection transistor PG1 and the second selection transistor PG2 with appropriate performance can be selected to facilitate the write operation and improve the write margin. In short, it is beneficial to improve the working window of the read operation and the write operation as a whole.
[0080] In this embodiment, the method for performing a read operation on the memory cell to be operated further includes: inputting a high level to the first bit line WBL and the second bit line WBL respectively. Inputting a high level to the first bit line WBL and the second bit line WBL can reduce device leakage and improve device performance.
[0081] In another embodiment, the storage unit further includes: a switch transistor, one of the source and drain terminals of the switch transistor is connected to the second latch point, and the other of the source and drain terminals of the switch transistor is connected to the input terminal of the amplification unit.
[0082] In another embodiment, the method of performing a read operation on the memory cell to be operated further includes: inputting a high level at the gate terminal of the switch transistor to turn on the switch transistor.
[0083] In another embodiment, the storage unit further includes: a second word line, the second word line is connected to the gate terminal of the switch transistor; the method of inputting a high level to the gate terminal of the switch transistor includes: inputting a high level to the second word line.
[0084] In this embodiment, the storage unit further includes: a third bit line RBL, and the third bit line RBL is connected to the output end of the amplifying unit; the method of applying voltage to the output end of the amplifying unit in the storage unit to be operated includes: applying voltage to the third bit line RBL.
[0085] In this embodiment, one end of the first inverter is connected to the power supply terminal VDD, and the other end of the first inverter is grounded VSS. One end of the second inverter is connected to the power supply terminal VDD, and the other end of the second inverter is grounded VSS.
[0086] In this embodiment, the storage unit also includes: the first inverter includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected to each other, one end of the source and drain ends of the first pull-up transistor PU1 is connected to the power supply end VDD, the other end of the source and drain ends of the first pull-up transistor PU1 and one end of the source and drain ends of the first pull-down transistor PD1 are connected to the first latch point S1, the other end of the source and drain ends of the first pull-down transistor PD1 is grounded, and the gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1 are connected to the second latch point S2; the second inverter includes a second pull-up transistor PU2 and a second pull-down transistor PD2 connected to each other, one end of the source and drain ends of the second pull-up transistor PU2 is connected to the power supply end VDD, one end of the source and drain ends of the second pull-up transistor PU2 and the other end of the source and drain ends of the second pull-down transistor PD2 are connected to the second latch point S2, the other end of the source and drain ends of the second pull-down transistor PD2 is grounded VSS, and the gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2 are connected to the first latch point S1.
[0087] In another embodiment, the first inverter includes a first pull-up transistor, one of the source and drain terminals of the first pull-up transistor is connected to the first latch point, the other of the source and drain terminals of the first pull-up transistor is connected to the power supply terminal, and the gate of the first pull-up transistor is connected to the second latch point; the second inverter includes a second pull-up transistor, one of the source and drain terminals of the second pull-up transistor is connected to the second latch point, the other of the source and drain terminals of the second pull-up transistor is connected to the power supply terminal, and the gate of the second pull-up transistor is connected to the first latch point.
[0088] Figure 3 It is a schematic structural diagram of a storage unit in another embodiment of the present invention.
[0089] The main difference between this embodiment and the previous embodiment is that the storage unit in this embodiment further includes a switch transistor.
[0090] Please Figure 2 Based on this, continue to refer to Figure 3 The storage unit further includes: a switch transistor RPG, one end of the source and drain of the switch transistor RPG is connected to the second latch point S2, and the other end of the source and drain of the switch transistor RPG is connected to the input end of the amplification unit.
[0091] In this embodiment, the purpose of adding the switch transistor RPG is to turn off the switch transistor RPG when there is no need to perform a read operation on the storage unit, thereby reducing the leakage of the device and improving the performance of the device.
[0092] In this embodiment, the memory cell further includes: a second word line RWL, the second word line RWL is connected to the gate terminal of the switch transistor RPG, and the second word line RWL is used to control the conduction of the switch transistor RPG.
[0093] Correspondingly, another embodiment of the present invention further provides a memory, please continue to refer to Figure 3 The main difference between this embodiment and the previous embodiment is that:
[0094] In this embodiment, the storage unit also includes: a switching transistor RPG, one end of the source and drain ends of the switching transistor RPG is connected to the second latch point S2, and the other end of the source and drain ends of the switching transistor RPG is connected to the input end of the amplification unit; a second word line, and the second word line is connected to the gate end of the switching transistor.
[0095] In this embodiment, the reading unit is further used to apply a first voltage to the second word line RWL in the memory cell to be operated, so as to control the conduction of the switch transistor RPG.
[0096] Accordingly, another embodiment of the present invention further provides a memory operation method, please continue to refer to Figure 3 The main difference between this embodiment and the previous embodiment is that:
[0097] In this embodiment, the storage unit further includes: a switch transistor RPG, one end of the source and drain of the switch transistor RPG is connected to the second latch point S2, and the other end of the source and drain of the switch transistor RPG is connected to the input end of the amplification unit.
[0098] In this embodiment, the method of performing a read operation on the memory cell to be operated further includes: inputting a high level at the gate terminal of the switch transistor RPG to turn on the switch transistor RPG. Accordingly, when the memory cell does not need to be read, the switch transistor RPG is turned off, which can reduce the leakage of the device and improve the performance of the device.
[0099] In this embodiment, the storage unit further includes: a second word line RWL, the second word line RWL is connected to the gate terminal of the switch transistor RPG; the method of inputting a high level to the gate terminal of the switch transistor RPG includes: inputting a high level to the second word line RWL.
[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A storage unit, characterized in that: include: a first inverter having a first latch point; a second inverter having a second latch point; a first bit line connected to the first latch point; a second bit line connected to the second latch point; The amplifying unit comprises an input terminal and an output terminal, wherein the input terminal is connected to the second latch point, and the output terminal is used to output a read current.
2. The storage unit according to claim 1, characterized in that The amplifying unit includes a bipolar transistor.
3. The storage unit according to claim 2, characterized in that The bipolar transistor is of NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor, and the emitter end of the bipolar transistor is grounded; the bipolar transistor is of PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
4. The storage unit according to claim 1, wherein: Also includes: a first selection transistor, wherein one end of the source and drain of the first selection transistor is connected to the first latch point, and the other end of the source and drain of the first selection transistor is connected to the first bit line; a second selection transistor, wherein one end of the source and drain of the second selection transistor is connected to the second latch point, and the other end of the source and drain of the second selection transistor is connected to the second bit line; A first word line is connected to a gate terminal of the first selection transistor and a gate terminal of the second selection transistor.
5. The storage unit according to claim 1, wherein: Also includes: A switch transistor, one end of the source and drain of the switch transistor is connected to the second latch point, and the other end of the source and drain of the switch transistor is connected to the input end of the amplification unit.
6. The storage unit according to claim 5, characterized in that Also includes: A second word line is connected to a gate terminal of the switch transistor.
7. The storage unit according to claim 1, wherein: Also includes: A third bit line is connected to the output end of the amplifying unit.
8. The storage unit according to claim 1, wherein: One end of the first inverter is connected to a power supply terminal, and the other end of the first inverter is grounded. One end of the second inverter is connected to the power supply terminal, and the other end of the second inverter is grounded.
9. The storage unit according to claim 8, characterized in that Also includes: The first inverter includes a first pull-up transistor and a first pull-down transistor connected to each other, one end of the source and drain ends of the first pull-up transistor is connected to the power supply end, the other end of the source and drain ends of the first pull-up transistor and one end of the source and drain ends of the first pull-down transistor are connected to the first latch point, the other end of the source and drain ends of the first pull-down transistor is grounded, and the gate of the first pull-up transistor and the gate of the first pull-down transistor are connected to the second latch point; the second inverter includes a second pull-up transistor and a second pull-down transistor connected to each other, one end of the source and drain ends of the second pull-up transistor is connected to the power supply end, one end of the source and drain ends of the second pull-up transistor and the other end of the source and drain ends of the second pull-down transistor are connected to the second latch point, the other end of the source and drain ends of the second pull-down transistor is grounded, and the gate of the second pull-up transistor and the gate of the second pull-down transistor are connected to the first latch point.
10. The storage unit according to claim 8, characterized in that The first inverter includes a first pull-up transistor, one of the source and drain terminals of the first pull-up transistor is connected to the first latch point, the other of the source and drain terminals of the first pull-up transistor is connected to the power supply terminal, and the gate of the first pull-up transistor is connected to the second latch point; the second inverter includes a second pull-up transistor, one of the source and drain terminals of the second pull-up transistor is connected to the second latch point, the other of the source and drain terminals of the second pull-up transistor is connected to the power supply terminal, and the gate of the second pull-up transistor is connected to the first latch point.
11. A memory, characterized in that: include: A storage array, the storage array comprising a plurality of storage units according to any one of claims 1 to 10; The reading unit is used to apply a voltage to the output end of the amplifying unit in the storage unit to be operated, and read the current output from the output end.
12. The memory according to claim 11, wherein: The reading unit is further used to apply a first voltage to the second word line in the memory cell to be operated, so as to control the conduction of the switch transistor.
13. The memory according to claim 11, wherein: The reading unit is further used for applying a second voltage to the third bit line in the memory cell to be operated, so as to make the bipolar transistor work in an amplification state.
14. The memory according to claim 11, wherein: Also includes: A writing unit is used to apply a third voltage to the first word line in the memory cell to be operated to control the conduction of the first selection transistor and the second selection transistor, and to load the state to be written to the first bit line and the second bit line in the memory cell to be operated respectively.
15. A method for operating a memory, the memory comprising: A storage array, the storage array comprising a plurality of storage units distributed in an array; The storage unit includes: a first inverter, the first inverter having a first latch point; a second inverter, the second inverter having a second latch point; A first bit line connected to the first latch point; a second bit line connected to the second latch point; an amplification unit including an input end and an output end, the input end being connected to the second latch point, and the output end being used to output a read current; The method of performing a read operation on the storage unit to be operated comprises: A voltage is applied to the output terminal of the amplifying unit in the memory unit to be operated, and a current output from the output terminal is read.
16. The memory operating method according to claim 15, characterized in that: The amplifying unit includes a bipolar transistor; the method further includes: applying a voltage to the output terminal of the amplifying unit in the storage unit to be operated, so that the bipolar transistor works in an amplifying state.
17. The memory operating method according to claim 16, characterized in that: The bipolar transistor is of NPN type, the input end is the base end of the bipolar transistor, the output end is the collector end of the bipolar transistor, and the emitter end of the bipolar transistor is grounded; the bipolar transistor is of PNP type, the input end is the base end of the bipolar transistor, the output end is the emitter end of the bipolar transistor, and the collector end of the bipolar transistor is grounded.
18. The memory operating method according to claim 15, characterized in that: The memory cell further includes: a first selection transistor, one of the source and drain terminals of the first selection transistor is connected to the first latch point, and the other of the source and drain terminals of the first selection transistor is connected to the first bit line; a second selection transistor, one of the source and drain terminals of the second selection transistor is connected to the second latch point, and the other of the source and drain terminals of the second selection transistor is connected to the second bit line; a first word line, the first word line is connected to the gate terminal of the first selection transistor and the gate terminal of the second selection transistor; the method for performing a read operation on the memory cell to be operated further includes: inputting a low level to the first word line to turn off the first selection transistor and the second selection transistor.
19. The memory operating method according to claim 18, characterized in that: Before performing a read operation on the memory cell to be operated, performing a write operation on the memory cell; the write operation includes: inputting a high level to the first word line to turn on the first selection transistor and the second selection transistor to write the states of the first bit line and the second bit line into the memory cell.
20. The memory operating method according to claim 18, characterized in that: The method of performing a read operation on the memory cell to be operated further includes: inputting a high level to the first bit line and the second bit line respectively.
21. The memory operating method according to claim 15, characterized in that: The storage unit also includes: a switching transistor, one end of the source and drain ends of the switching transistor is connected to the second latch point, and the other end of the source and drain ends of the switching transistor is connected to the input end of the amplification unit; the method for performing a reading operation on the storage unit to be operated also includes: inputting a high level at the gate end of the switching transistor to turn on the switching transistor.
22. The memory operating method according to claim 21, characterized in that: The storage unit further includes: a second word line, the second word line is connected to the gate terminal of the switch transistor; the method of inputting a high level to the gate terminal of the switch transistor includes: inputting a high level to the second word line.
23. The memory operating method according to claim 15, characterized in that: The storage unit further includes: a third bit line, the third bit line is connected to the output end of the amplifying unit; the method of applying a voltage to the output end of the amplifying unit in the storage unit to be operated includes: applying a voltage to the third bit line.