Chip process angle difference elimination circuit, method and NAND flash memory chip

Abstract

The present invention discloses a chip process angle difference elimination circuit, method and NAND flash memory chip, which relates to the field of integrated circuit technology, including an input signal amplification module, a lossless capacitance simulation module, a signal switch control module, an equipotential element and a clock frequency detection module, wherein the input signal amplification module amplifies the electrical signal at the input end and transmits the amplified electrical signal, so that the amplified electrical signal is transmitted to a voltage divider element. The present invention can simulate the lossless current on the capacitor in the tested module, eliminate the adverse effect of the leakage current caused by the insulation resistance of the capacitor itself in the tested module on the test circuit, and at the same time eliminate the effect of the leakage current on the accuracy of the calculation result, and enable the RC oscillator to work under slow angle conditions, which is conducive to improving the independence of PVT detection and the detection accuracy of the PVT test of a high resistance and capacitance oscillator, and meets the test process of the capacitor C under slow angle conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip process angle difference elimination circuit, method and a NAND flash memory chip. Background Art

[0002] NAND flash memory chip is a non-volatile random access storage device with the advantages of large capacity, small size, fast data reading speed and low power consumption. Therefore, it is widely used in storage devices such as solid-state hard disks, USB flash drives, and memory cards. NAND flash memory chips are usually designed with multiple oscillator (OSC) structures inside. The timer composed of the oscillator OSC can provide accurate clock signals for NAND flash memory chips. In order to ensure the accuracy of the timer timing cycle, and also to prevent the inevitable changes and uncertainties accompanying the manufacturing process from affecting the chip's reading speed, power consumption and other characteristics, it is necessary to independently test the clock signal cycle under process corner conditions.

[0003] Generally speaking, process corners include typical corner (Typical Corner, TT), slow corner (Slow Corner, SS), fast corner (Fast Corner, FF), slow-fast corner (Slow-Fast Corner, SF) and fast-slow corner (Fast-Slow Corner, SF). The typical corner is the process parameter under ideal conditions, representing the average performance of the chip under normal working conditions; the slow corner indicates that the process parameter is in a slower range, representing a higher threshold voltage of the transistor, a slower switching speed, but lower power consumption; the fast corner describes that the process parameter is in a faster range, representing a lower threshold voltage of the transistor, a faster speed, but higher power consumption; the slow-fast corner describes a situation where some transistor parameters are slower and others are faster; the fast-slow corner indicates a situation where some transistor parameters are faster and others are slower. The fast-slow corner can test the performance of different parts of the circuit under different conditions. The factors that determine the process corner type can be generally divided into changes in manufacturing process, voltage, and temperature. Before the timer is used for a specific purpose, in order to eliminate the influence of manufacturing process, voltage, and temperature on the oscillator performance as much as possible, an independent PVT (Process, Voltage, Temperature) test is required.

[0004] For PVT testing, the traditional method is to use an odd number of gate circuits connected end to end to form a ring oscillator to generate a periodic oscillation signal, and combine certain methods to eliminate the chip performance changes caused by PVT. The existing method is to use a fine-tuning device to adjust the capacitance threshold and select the capacitance value of the trimming capacitor connected to the circuit according to different input signals.

[0005] However, when the MOS tube works in the linear amplification area, due to the existence of insulation resistance, the connected trimming capacitor will generate an equivalent resistance. At the same time, due to the influence of insulation resistance in the frequency range, the capacitance of the trimming capacitor will be greatly reduced, resulting in the oscillator being unable to be used in high-speed and high-frequency areas, which limits the working scenario of the oscillator. On the other hand, when the process parameters are in slow-angle conditions, the insulation resistance will cause a greater leakage current, further aggravating the degree of limitation of the oscillator's working scenario, which is not conducive to the promotion and application of NAND flash memory chips in different industrial fields. Summary of the invention

[0006] The purpose of the present invention is to eliminate the influence of the insulation resistance value on the detection result during the slow angle test in the PVT process angle by adopting a gate circuit to reflect the gate process angle signal of the switch MOS and simulating the lossless capacitance of the capacitor in the module under test, thereby solving the problem of limited oscillator working scenarios proposed in the above background technology.

[0007] On the one hand, to achieve the above-mentioned purpose, the present invention provides a chip process angle difference elimination circuit, including an input signal amplification module, a lossless capacitance simulation module, a signal switch control module, an equipotential element and a clock frequency detection module, wherein the input signal amplification module amplifies the electrical signal at the input end and transmits the amplified electrical signal, so that the amplified electrical signal is transmitted to the voltage divider element, and the amplified electrical signal can effectively reduce the difficulty of signal monitoring and improve the test accuracy at the same time. By connecting the lossless capacitance simulation module in parallel at both ends of the pull-up resistor, the lossless current on the capacitor in the tested module can be simulated, and the adverse effect of the leakage current caused by the insulation resistance of the capacitor itself in the tested module on the test circuit is eliminated, and the test process of the capacitor C under slow angle conditions can be satisfied;

[0008] The lossless capacitance simulation module includes a voltage divider element and a lossless capacitance simulation unit, one end of the voltage divider element is connected to the output end of the input signal amplification module, and the lossless capacitance simulation unit is connected in parallel to the two ends of the voltage divider element. The voltage divider element divides the voltage of the electrical signal amplified by the signal amplification unit, and by cooperating with the equipotential potential formed at the two ends of the equipotential element, the input voltage clocks of the first switch unit and the second switch unit can be kept at a high level and kept in a conducting state, so that the periodic signal generating device can send a periodic signal to the signal transmission control unit;

[0009] The signal switch control module includes a first switch unit connected to one end of the voltage divider element and a second switch unit connected in series with the first switch unit. The first switch unit and the second switch unit together constitute a control gate circuit for the input signal entering the signal transmission control unit, and can serve as a periodic signal generating device to send a periodic control signal to the signal transmission control unit. Control switch.

[0010] One end of the equipotential element is connected to an end of the lossless capacitance simulation module away from the input signal amplification module, and the other end of the equipotential element is connected between the first switch unit and the second switch unit, so as to keep the potential of the input end of the first switch unit and the second switch unit the same as the potential of the current outflow end of the voltage divider element;

[0011] The clock frequency detection module includes a periodic signal generating device and a signal transmission control unit. One end of the signal transmission control unit is connected to the module under test. The periodic signal generating device can send a periodic pulse signal to the signal transmission control unit and charge the capacitor element contained in the module under test. On the one hand, it can detect the charging and discharging speed of the capacitor element and at the same time detect the switching speed of the detection signal transmission control unit.

[0012] As a further solution of the present invention: the input signal amplification module includes a signal amplification unit, the in-phase input end of the signal amplification unit is the signal input end, a feedback element is connected between the inverting input end and the output end of the signal amplification unit, and an input element is connected between the feedback element and the ground end, and the signal amplification unit can adjust its own amplification factor by adjusting the ratio between the feedback element and the input element, so as to facilitate the range of electrical signals input to the control circuit;

[0013] The signal amplification unit is a common-mode proportional amplifier, which can provide higher input impedance. High input impedance helps to reduce the impact of the circuit on the previous load and maintain the stability and performance of the circuit. The feedback element is a resistor. , the input element is a resistor , the amplification factor of the signal amplification unit is:

[0014] A=1+ / , where A represents the amplification factor of the signal amplification unit, and the resistance With resistance satisfy > ;

[0015] The feedback element and the output end of the signal amplifying unit are electrically connected to a connection end of the lossless capacitance simulation unit, which can effectively ensure the amplification factor of the signal amplifying unit and is conducive to improving the reliability and stability of the circuit input.

[0016] As a further solution of the present invention: the voltage dividing element is a resistor ,resistance One end of the resistor is connected to the feedback element. The other end of the resistor is connected to the first switch unit. As a pull-up resistor between the signal amplification unit and the first switch unit, by cooperating with the equipotential effect of the equipotential element, the input ends of the first switch unit and the second switch unit can always be kept at a high potential. When the first switch unit and the second switch unit are MOS transistors, the conduction state between the drain and the source of the first switch unit and the second switch unit can be maintained.

[0017] As a further solution of the present invention: the equipotential element is a metal wire, one end of which is connected to the low potential end of the voltage divider element, and the other end of which is connected between the first switch unit and the second switch unit. The equipotential element synchronizes the potential value of the low potential end of the voltage divider element to the voltage input ends of the first switch unit and the second switch unit, so that the voltage input ends of the first switch unit and the second switch unit maintain a high level input relative to the ground end, thereby maintaining a stable working state of the first switch unit and the second switch unit.

[0018] As a further solution of the present invention: the first switch unit is an N-channel field effect transistor , N-channel field effect transistor The gate-source voltage is greater than that of the N-channel field effect transistor The on-state voltage is:

[0019] ;

[0020] in, N-channel field effect transistor The voltage between the gate and the source, is the on-state voltage of the field effect tube, and the second switch unit is an N-channel field effect tube , the N-channel FET The source of the N-channel FET is grounded. The drain of the N-channel field effect transistor is connected to the low potential end of the voltage divider element and one end of the equipotential element. The gate of the N-channel field effect transistor is electrically connected The gate, equipotential components and N-channel field effect transistor and N-channel FET When the gate of the N-channel field effect transistor is connected to point b, and N-channel FET The gates have pull-up resistors The same potential as the low potential end, when the pull-up resistor The potential of the low potential end is greater than the conduction voltage , which enables N-channel FETs and N-channel FET The first switch unit and the second switch unit are respectively turned on to keep the first switch unit and the second switch unit turned on, so that the periodic signal generating device can send a periodic signal to the signal transmission control unit;

[0021] The N-channel field effect transistor The source of the N-channel FET is grounded. The drain is electrically connected to one end of the clock frequency detection module.

[0022] As a further solution of the present invention: the lossless capacitance simulation module includes an N-channel field effect transistor and a P-channel FET , the N-channel FET The gate of the N-channel FET is connected to a high level. The drain of the N-channel field effect transistor is connected to the output end of the signal amplification unit. The source of the P-channel field effect transistor is electrically connected to the low potential end of the voltage divider element. The drain of the P-channel field effect transistor is electrically connected to the low potential end of the voltage divider element. The source is connected to the N-channel FET The drain and output end of the signal amplification unit, the P-channel field effect transistor The gate of the device is grounded, and one end of the voltage divider element, the lossless capacitance simulation unit and the first switch unit intersect at a connection point O;

[0023] When the current flowing out of the voltage divider is The current flowing out of the lossless capacitance simulation unit is , according to Kirchhoff's current law:

[0024] The current flowing into the first switch unit is = + ;

[0025] In the detection current When the resistor The potential difference between the two ends is used to calculate the detection current , specifically:

[0026] =( - ) / ;

[0027] therefore, = + =( - ) / + .

[0028] As a further solution of the present invention: the periodic signal generating device includes an odd number of gate circuit structures.

[0029] As a further solution of the present invention: the module under test is a capacitor C, the positive plate of the capacitor C and the N-channel field effect transistor The source electrode of the capacitor C is connected, the negative plate of the capacitor C is grounded, and the negative plate of the capacitor C is grounded. When the capacitor C is charged, it can discharge to the ground end through the negative plate.

[0030] As a further solution of the present invention: the periodic signal generating device includes a first inverter , the second inverter , the third inverter , the fourth inverter and P-channel FET , the P-channel FET The source of the P-channel FET is connected to a high level. The drain of the first inverter is electrically connected to the signal transmission control unit. The input terminal and the N-channel field effect transistor The drain of the first inverter is electrically connected to one end of the signal transmission control unit. The output of the second inverter is connected The input terminal of the second inverter The output terminal of the third inverter is connected The input terminal of the third inverter The output terminal of the fourth inverter is connected The input terminal of the fourth inverter The output end is connected to a P-channel field effect transistor The gate of the first inverter Input high level signal to the input terminal , the high level signal By the first inverter The output terminal will become a low level signal when it outputs , low level signal Enter the second inverter The input terminal of the second inverter The output terminal will output a high level signal , by the second inverter The output terminal outputs a high level signal Enter the third inverter The input terminal of the third inverter The output terminal outputs a low level signal , low level signal Enter the fourth inverter The input terminal of the fourth inverter The output terminal outputs a high level signal , high level signal Can make P-channel FET The periodic signal generating device is turned on to transmit the electrical signal to the signal transmission control unit.

[0031] As a further solution of the present invention: the signal transmission control unit includes an N-channel field effect transistor and P-channel FET , N-channel field effect transistor The gate of the device is connected to a timing interrupt signal, and the interrupt signal is , N-channel field effect transistor The drain of the N-channel field effect transistor The drain of the first inverter The input terminal of the P-channel field effect transistor The drain connection of the module under test is as follows: Since the capacitor C in the module under test is initially at , when the electrical signal of the periodic signal generating device is at a high level, the N-channel field effect transistor The positive plate of capacitor C is turned on, so that a potential difference is formed on the two plates of capacitor C. Capacitor C is in a charging state. The insulation resistance is affected by the change of temperature increase, which increases the leakage current of capacitor C. At this time, the lossless capacitance simulation unit is used to simulate the lossless current of capacitor C, which can eliminate the influence of leakage current on the calculation result, so that the RC oscillator can work under slow-angle conditions and form PVT independent detection, which is conducive to improving the monitoring accuracy of PVT test of RC oscillator.

[0032] The P-channel field effect transistor The drain of the P-channel FET is connected to one end of the module under test. The gate of the transistor is connected to TrmF0. When the current at point K flows to the N-channel field effect transistor P-channel FET When the current is P-channel FET There is always one end turned on, so that the current can charge the capacitor C. According to the cycle calculation formula:

[0033] ,in:

[0034] is the charge and discharge cycle constant of the measured capacitor,

[0035] C is the capacitance value of the module under test;

[0036] For resistance The high potential of

[0037] is the turn-on voltage of the field effect transistor;

[0038] R is the pull-up resistor The resistance value;

[0039] is the current value flowing out of the lossless capacitance simulation unit.

[0040] In a second aspect, a method for eliminating chip process angle differences is also provided, including the difference elimination circuit described in the above solution, and the method includes:

[0041] Get the current flowing out of the lossless capacitance simulation unit , by obtaining the current Able to calculate the current flowing into point a ;

[0042] Calculate the current flowing into the first switching unit ;

[0043] Obtaining a voltage drop value of a signal transmission control unit;

[0044] Calculate the time constant of the RC delay circuit according to the time constant formula.

[0045] As a further solution of the present invention: obtaining the current flowing out of the lossless capacitance simulation unit The method is to connect an ammeter in series between the lossless capacitance simulation unit and point O for measurement.

[0046] As a further solution of the present invention: the method of obtaining the voltage drop value of the signal transmission control unit is to connect a voltmeter in parallel to the input end and the output end of the signal transmission control unit for measurement.

[0047] As a further solution of the present invention: the time constant formula is:

[0048] t=R×C, where R is the equivalent resistance of the module under test.

[0049] In a third aspect, a NAND flash memory chip is also provided, wherein the chip includes the difference elimination circuit.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. The present invention can simulate the lossless current on the capacitor in the module under test by connecting a lossless capacitance simulation module in parallel at both ends of the pull-up resistor, thereby eliminating the adverse effect of the leakage current caused by the insulation resistance of the capacitor itself in the module under test on the test circuit, and at the same time can eliminate the influence of the leakage current on the accuracy of the calculation result, and enable the RC oscillator to work under slow-angle conditions, which is beneficial to improving the independence of PVT detection and the detection accuracy of the PVT test of a high-resistance-capacitance oscillator, and meeting the test process of the capacitor C under slow-angle conditions.

[0052] 2. The present invention adopts a resistor As a pull-up resistor between the signal amplification unit and the first switch unit, and in conjunction with the equipotential effect of the equipotential element, the input ends of the first switch unit and the second switch unit can always be kept at a high potential. When the first switch unit and the second switch unit are MOS transistors, the conduction state between the drain and the source of the first switch unit and the second switch unit can be maintained, which is beneficial to maintaining the stability and reliability of the circuit.

[0053] 3. The present invention sends a periodic pulse signal to the signal transmission control unit through a periodic signal generating device, which can charge the capacitor element contained in the module under test, which is beneficial to improving the convenience of detecting the charging and discharging speed of the capacitor element. On the other hand, it is convenient to observe the switching speed of the signal transmission control unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a functional module diagram of the present invention;

[0055] Figure 2 This is a diagram of an electrical signal transmission module of the present invention;

[0056] Figure 3 This is a clock frequency detection circuit diagram of the present invention.

[0057] In the figure: 1. Input signal amplification module; 101. Signal amplification unit; 102. Feedback element; 103. Input element; 2. Lossless capacitance simulation module; 201. Voltage divider element; 202. Lossless capacitance simulation unit; 3. Signal switch control module; 301. Equipotential element; 302. First switch unit; 303. Second switch unit; 4. Clock frequency detection module; 401. Periodic signal generating device; 402. Signal transmission control unit; 5. Module under test. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0059] like Figure 1 The functional module diagram of the present invention is shown, which provides a chip process angle difference elimination circuit, including an input signal amplification module 1, a lossless capacitance simulation module 2, a signal switch control module 3, an equipotential element 301 and a clock frequency detection module 4. The input signal amplification module 1 amplifies the electrical signal at the input end and transmits the amplified electrical signal, so that the amplified electrical signal is transmitted to the voltage divider element 201. The amplified electrical signal can effectively reduce the difficulty of signal monitoring and improve the test accuracy. By connecting the lossless capacitance simulation module 2 in parallel at both ends of the pull-up resistor, the lossless current on the capacitor in the tested module 5 can be simulated, eliminating the adverse effect of the leakage current caused by the insulation resistance of the capacitor itself in the tested module 5 on the test circuit, and can meet the test process of the capacitor C under slow angle conditions;

[0060] like Figure 2 The figure shows the electric signal transmission module diagram of the present invention; the lossless capacitance simulation module 2 includes a voltage divider element 201 and a lossless capacitance simulation unit 202, one end of the voltage divider element 201 is connected to the output end of the input signal amplification module 1, and the lossless capacitance simulation unit 202 is connected in parallel to the two ends of the voltage divider element 201. The voltage divider element 201 divides the electric signal amplified by the signal amplification unit 101, and the input voltage clock of the first switch unit 302 and the second switch unit 303 can be kept at a high voltage by cooperating with the equipotential potential formed at the two ends of the equipotential element 301. The periodic signal generating device 401 is kept in the on state, so as to facilitate the periodic signal generating device 401 to send the periodic signal to the signal transmission control unit 402; the signal switch control module 3 includes a first switch unit 302 connected to one end of the voltage dividing element 201 and a second switch unit 303 connected in series with the first switch unit 302. The first switch unit 302 and the second switch unit 303 together constitute a control gate circuit for the input signal to enter the signal transmission control unit 402, and can be used as a control switch for the periodic signal generating device 401 to send the periodic control signal to the signal transmission control unit 402.

[0061] Preferably, one end of the equipotential element 301 is connected to one end of the lossless capacitance simulation module 2 away from the input signal amplification module 1, and the other end of the equipotential element 301 is connected between the first switch unit 302 and the second switch unit 303, so that the potentials of the input ends of the first switch unit 302 and the second switch unit 303 can be kept the same as the potential of the current outflow end of the voltage divider element 201;

[0062] Preferably, the clock frequency detection module 4 includes a periodic signal generating device 401 and a signal transmission control unit 402. One end of the signal transmission control unit 402 is connected to the module under test 5. The periodic signal generating device 401 can send a periodic pulse signal to the signal transmission control unit 402 and charge the capacitor element included in the module under test 5. On the one hand, it can detect the charging and discharging speed of the capacitor element and at the same time detect the switching speed of the detection signal transmission control unit 402.

[0063] Preferably, the input signal amplification module 1 includes a signal amplification unit 101, the in-phase input terminal of the signal amplification unit 101 is the signal input terminal, a feedback element 102 is connected between the inverting input terminal and the output terminal of the signal amplification unit 101, and an input element 103 is connected between the feedback element 102 and the ground terminal. The signal amplification unit 101 can adjust its own amplification factor by adjusting the ratio between the feedback element 102 and the input element 103, so as to facilitate the control of the range of electrical signals input to the circuit;

[0064] Preferably, the signal amplification unit 101 is a common-mode proportional amplifier, which can provide a higher input impedance. The high input impedance helps to reduce the impact of the circuit on the front-stage load and maintain the stability and performance of the circuit. The feedback element 102 is a resistor. , the input element 103 is a resistor , the amplification factor of the signal amplification unit 101 is:

[0065] A=1+ / , where A represents the amplification factor of the signal amplification unit 101, and the resistance With resistance satisfy > ;

[0066] Preferably, the feedback element 102 and the output end of the signal amplifying unit 101 are electrically connected to a connection end of the lossless capacitance simulation module 2 , which can effectively ensure the amplification factor of the signal amplifying unit 101 and is conducive to improving the reliability and stability of the circuit input.

[0067] like Figure 3 The clock frequency detection circuit diagram of the present invention is shown, and the voltage divider element 201 is a resistor ,resistance One end of the resistor is connected in parallel with the feedback element 102. The other end of the resistor is connected to the first switch unit 302. As a pull-up resistor between the signal amplifying unit 101 and the first switch unit 302, by cooperating with the equipotential effect of the equipotential element 301, the input terminals of the first switch unit 302 and the second switch unit 303 can always be kept at a high potential. When the first switch unit 302 and the second switch unit 303 are MOS transistors, the conductive state between the drain and the source of the first switch unit 302 and the second switch unit 303 can be maintained; the signal transmission control unit 402 includes an N-channel field effect transistor and P-channel FET , N-channel field effect transistor The gate of the device is connected to a timing interrupt signal, and the interrupt signal is , N-channel field effect transistor The drain of the N-channel field effect transistor The drain of the first inverter The input terminal of the P-channel field effect transistor Since the capacitor C in the module under test 5 is 0 in the initial state, when the electrical signal of the periodic signal generating device 401 is at a high level, the N-channel field effect transistor The positive plate of capacitor C is turned on, so that the positive plate of capacitor C is charged, and a potential difference is formed on the two plates of capacitor C. Capacitor C is in a charging state, and the insulation resistance is affected by the change of temperature increase, which increases the leakage current of capacitor C. At this time, the lossless capacitance simulation unit 202 is used to simulate the lossless current of capacitor C, which can eliminate the influence of leakage current on the calculation result, so that the RC oscillator can work under slow angle conditions and form PVT independent detection, which is beneficial to improve the monitoring accuracy of PVT test of RC oscillator; P-channel field effect transistor The drain of the P-channel field effect transistor is connected to one end of the module under test 5. The gate of the transistor is connected to TrmF0. When the current at point K flows to the N-channel field effect transistor P-channel FET When the current is P-channel FET There is always one end turned on, so that the current can charge the capacitor C. According to the cycle calculation formula:

[0068] ,in:

[0069] is the charge and discharge cycle constant of the measured capacitor,

[0070] C is the capacitance value of the measured module 5;

[0071] For resistance The high potential of

[0072] is the turn-on voltage of the field effect transistor;

[0073] R is the pull-up resistor The resistance value;

[0074] is the current value flowing out of the lossless capacitance simulation unit 202 .

[0075] Preferably, the equipotential element 301 is a metal wire, one end of which is connected to the low potential end of the voltage divider element 201, and the other end of the wire is connected between the first switch unit 302 and the second switch unit 303. The equipotential element 301 synchronizes the potential value of the low potential end of the voltage divider element 201 to the voltage input ends of the first switch unit 302 and the second switch unit 303, so that the voltage input ends of the first switch unit 302 and the second switch unit 303 maintain a high level input relative to the ground end, thereby maintaining a stable working state of the first switch unit 302 and the second switch unit 303.

[0076] Preferably, the first switch unit 302 is an N-channel field effect transistor , N-channel field effect transistor The gate-source voltage is greater than that of the N-channel field effect transistor The on-state voltage is:

[0077] ;

[0078] in, N-channel field effect transistor The voltage between the gate and the source, is the conduction voltage of the field effect transistor, and the second switch unit 303 is an N-channel field effect transistor , N-channel field effect transistor The source of the N-channel field effect transistor is grounded. The drain of the N-channel field effect transistor is connected to the low potential end of the voltage divider element 201 and one end of the equipotential element 301. The gate of the N-channel field effect transistor is electrically connected The gate, equipotential element 301 and N-channel field effect transistor and N-channel FET When the gate of the N-channel field effect transistor is connected to point b, and N-channel FET The gates have pull-up resistors The same potential as the low potential end, when the pull-up resistor The potential of the low potential end is greater than the conduction voltage , which enables N-channel FETs and N-channel FET The first switch unit 302 and the second switch unit 303 are respectively turned on to keep the first switch unit 302 and the second switch unit 303 turned on, so that the periodic signal generating device 401 sends a periodic signal to the signal transmission control unit 402. The source of the N-channel field effect transistor is grounded. The drain is electrically connected to one end of the clock frequency detection module 4.

[0079] Preferably, the lossless capacitance simulation module 2 includes an N-channel field effect transistor and a P-channel FET , N-channel field effect transistor The gate of the N-channel field effect transistor is connected to a high level. The drain of the N-channel field effect transistor is connected to the output end of the signal amplification unit 101. The source of the P-channel field effect transistor is electrically connected to the low potential end of the voltage divider element 201. The drain of the P-channel field effect transistor is electrically connected to the low potential end of the voltage divider element 201. The source is connected to the N-channel field effect transistor The drain of the signal amplifying unit 101 and the output end of the P-channel field effect transistor The gate of the device is grounded, and one end of the voltage divider element 201, the lossless capacitance simulation unit 202 and the first switch unit 302 intersect at a connection point O;

[0080] When the current flowing out of the voltage divider element 201 is The current flowing out of the lossless capacitance simulation unit 202 is , according to Kirchhoff's current law:

[0081] The current flowing into the first switch unit 302 is = + ;

[0082] In the detection current When the resistor The potential difference between the two ends is used to calculate the detection current , specifically:

[0083] =( - ) / ;

[0084] therefore, = + =( - ) / + .

[0085] Preferably, the module under test 5 is a capacitor C, the positive plate of the capacitor C and the N-channel field effect transistor The source of capacitor C is connected, the negative plate of capacitor C is grounded, and the negative plate of capacitor C is grounded. When capacitor C is charged, it can discharge to the ground through the negative plate.

[0086] Preferably, the periodic signal generating device 401 includes an odd number of gate circuit structures, and the periodic signal generating device 401 includes a first inverter , the second inverter , the third inverter , the fourth inverter and P-channel FET , P-channel field effect transistor The source of the P-channel field effect transistor is connected to a high level. The drain of the first inverter is electrically connected to the signal transmission control unit 402. The input terminal and the N-channel field effect transistor The drain of the first inverter is electrically connected to one end of the signal transmission control unit 402. The output of the second inverter is connected The input terminal of the second inverter The output terminal of the third inverter is connected The input terminal of the third inverter The output terminal of the fourth inverter is connected The input terminal of the fourth inverter The output end is connected to a P-channel field effect transistor The gate of the first inverter Input high level signal to the input terminal , the high level signal By the first inverter The output terminal will become a low level signal when it outputs , low level signal Enter the second inverter The input terminal of the second inverter The output terminal will output a high level signal , by the second inverter The output terminal outputs a high level signal Enter the third inverter The input terminal of the third inverter The output terminal outputs a low level signal , low level signal Enter the fourth inverter The input terminal of the fourth inverter The output terminal outputs a high level signal , high level signal Can make P-channel FET The periodic signal generating device 401 is turned on to transmit the electrical signal to the signal transmission control unit 402 .

[0087] Combination Figure 1-Figure 3 , a chip process angle difference elimination method is also provided, including the difference elimination circuit of the above embodiment, the method comprising:

[0088] Obtain the current flowing out of the lossless capacitance simulation unit 202 , by obtaining the current Able to calculate the current flowing into point a ;

[0089] Calculate the current flowing into the first switch unit 302 ;

[0090] Obtaining a voltage drop value of the signal transmission control unit 402;

[0091] Calculate the time constant of the RC delay circuit according to the time constant formula.

[0092] Preferably, the current flowing out of the lossless capacitance simulation unit 202 is obtained The method is to connect an ammeter in series between the lossless capacitance simulation unit 202 and point O for measurement.

[0093] Preferably, the voltage drop value of the signal transmission control unit 402 is obtained by connecting a voltmeter in parallel to the input end and the output end of the signal transmission control unit 402 for measurement.

[0094] Preferably, the time constant formula is:

[0095] t=R×C, where R is the equivalent resistance of the module 5 under test.

[0096] A NAND flash memory chip is also provided, the chip comprising the difference elimination circuit in the above embodiment.

[0097] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A chip process angle difference elimination circuit, characterized in that: The difference elimination circuit comprises: An input signal amplifying module, the input signal amplifying module is used to amplify the electrical signal at the input end and transmit the amplified electrical signal; A lossless capacitance simulation module, the lossless capacitance simulation module comprising a voltage divider element and a lossless capacitance simulation unit, one end of the voltage divider element is connected to the output end of the input signal amplification module, and the lossless capacitance simulation unit is connected in parallel to both ends of the voltage divider element; A signal switch control module, the signal switch control module comprising a first switch unit connected to one end of the voltage dividing element and a second switch unit connected in series with the first switch unit; an equipotential element, one end of which is connected to an end of the lossless capacitance simulation module away from the input signal amplification module, and the other end of which is connected between the first switch unit and the second switch unit, and the equipotential element is used to keep the potentials of the input ends of the first switch unit and the second switch unit the same as the potential of the current outflow end of the voltage divider element; The difference elimination circuit also includes: A clock frequency detection module, wherein the clock frequency detection module comprises a periodic signal generating device and a signal transmission control unit, and one end of the signal transmission control unit is connected to the module under test.

2. The chip process angle difference elimination circuit according to claim 1, characterized in that: The input signal amplification module comprises a signal amplification unit, the in-phase input terminal of the signal amplification unit is the signal input terminal, a feedback element is connected between the inverting input terminal and the output terminal of the signal amplification unit, and an input element is connected between the feedback element and the ground terminal; The signal amplification unit is a common-mode proportional amplifier, and the feedback element is a resistor. , the input element is a resistor , the amplification factor of the signal amplification unit is: A=1+ / , where A represents the amplification factor of the signal amplification unit; The feedback element and the output end of the signal amplifying unit are electrically connected to a connection end of the lossless capacitance simulation unit.

3. The chip process angle difference elimination circuit according to claim 2, characterized in that: The voltage divider is a resistor ,resistance One end of the feedback element is connected to the resistor The other end is connected to the first switch unit.

4. The chip process angle difference elimination circuit according to claim 1, characterized in that: The equipotential element is a metal wire, one end of which is connected to the low potential end of the voltage divider element, and the other end of which is connected between the first switch unit and the second switch unit.

5. The chip process angle difference elimination circuit according to claim 1, characterized in that: The first switch unit is an N-channel field effect transistor , N-channel field effect transistor The gate and source voltage is equal to that of an N-channel field effect transistor The second switch unit is an N-channel field effect transistor. , the N-channel FET The source of the N-channel FET is grounded. The drain of the N-channel field effect transistor is connected to the low potential end of the voltage divider element and one end of the equipotential element. The gate of the N-channel field effect transistor is electrically connected The gate of The N-channel field effect transistor The source of the N-channel FET is grounded. The drain is electrically connected to one end of the clock frequency detection module.

6. The chip process angle difference elimination circuit according to claim 1, characterized in that: The lossless capacitance simulation module includes an N-channel field effect transistor and a P-channel FET , the N-channel FET The gate of the N-channel FET is connected to a high level. The drain of the N-channel field effect transistor is connected to the output end of the signal amplification unit. The source of the P-channel field effect transistor is electrically connected to the low potential end of the voltage divider element. The drain of the P-channel field effect transistor is electrically connected to the low potential end of the voltage divider element. The source is connected to the N-channel FET The drain and output end of the signal amplification unit, the P-channel field effect transistor The gate of is grounded.

7. The chip process angle difference elimination circuit according to claim 1, characterized in that: The periodic signal generating device comprises an odd number of gate circuit structures.

8. The chip process angle difference elimination circuit according to claim 7, characterized in that: The periodic signal generating device comprises a first inverter , the second inverter , the third inverter , the fourth inverter and P-channel FET The first inverter The input terminal and the N-channel field effect transistor The drain of the first inverter is electrically connected to one end of the signal transmission control unit. The output of the second inverter is connected The input terminal of the second inverter The output terminal of the third inverter is connected The input terminal of the third inverter The output terminal of the fourth inverter is connected The input terminal of the fourth inverter The output end is connected to a P-channel field effect transistor The gate of The P-channel field effect transistor The source of the P-channel FET is connected to a high level. The drain electrode is electrically connected to the signal transmission control unit.

9. The chip process angle difference elimination circuit according to claim 1, characterized in that: The module under test is a capacitor C, the positive plate of the capacitor C and the N-channel field effect transistor The source electrode of the capacitor C is connected to the ground.

10. The chip process angle difference elimination circuit according to claim 1, characterized in that: The signal transmission control unit includes an N-channel field effect transistor and P-channel FET , N-channel field effect transistor The gate of the N-channel field effect transistor is connected to the timing interrupt signal. The drain of the N-channel field effect transistor The drain of the first inverter Input terminal, P-channel field effect transistor The drain connection of The P-channel field effect transistor The drain of the P-channel FET is connected to one end of the module under test. The gate is connected to TrmF0.

11. The chip process angle difference elimination circuit according to claim 1, characterized in that: The voltage divider element, the lossless capacitance simulation unit and one end of the first switch unit meet at a connection point O; when the current flowing out of the voltage divider element is The current flowing out of the lossless capacitance simulation unit is , according to Kirchhoff's current law: The current flowing into the first switch unit is = + .

12. A method for calculating the time constant of a chip process angle difference elimination circuit, characterized in that: Based on the difference elimination circuit according to any one of claims 1 to 11, the method comprises: Get the current flowing out of the lossless capacitance simulation unit ; Calculate the current flowing into the first switching unit ; Obtaining a voltage drop value of a signal transmission control unit; Calculate the time constant of the RC delay circuit according to the time constant formula.

13. The method according to claim 12, characterized in that: Get the current flowing out of the lossless capacitance simulation unit The method is to connect an ammeter in series between the lossless capacitance simulation unit and point O for measurement; the method for obtaining the voltage drop value of the signal transmission control unit is to connect a voltmeter in parallel at the input and output ends of the signal transmission control unit for measurement.

14. The method according to claim 12, characterized in that: The time constant formula is: t=R×C, where R is the equivalent resistance of the module under test.

15. A NAND flash memory chip, characterized in that: The chip comprises the difference elimination circuit described in any one of claims 1-11.

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