Data caching method and computing device

Abstract

The invention provides a data caching method and computing equipment. The computing device comprises a hybrid memory, and the hybrid memory comprises a volatile memory and a persistent memory. The method comprises: reading first data from a persistent memory, the first data corresponding to a first mode in a plurality of modes; under the condition that it is determined that the first data is cached, the first data is written into a data page corresponding to the first mode in the volatile memory, the volatile memory comprises a plurality of data pages corresponding to the modes, and the data pages corresponding to the modes are organized according to the first data structure. In the method, under the condition of determining the cache data, the data is written into the data page corresponding to the mode corresponding to the data in the volatile memory, so that the space management efficiency of the volatile memory can be improved, and the efficiency of acquiring the cached data from the volatile memory is saved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data caching method and a computing device. Background Art

[0002] In the art, computing devices may use hybrid memory technology to improve their performance. For example, computing devices may use hybrid memory that combines volatile memory (random access memory, RAM) and persistent memory (persistent memory, PMEM). Among them, RAM will cache part of the data stored in PMEM.

[0003] When a computing device uses a database system to organize and manage data, the computing device will store data in different modes. Applications running on the computing device access the hybrid memory based on the database schema to obtain the required data. In the related art, the efficiency of applications in obtaining data from RAM is low, which seriously affects the user experience. Summary of the invention

[0004] The present application provides a data caching method and a computing device, which cache data according to the data mode and partition the data of different modes, thereby improving the efficiency of querying data.

[0005] In a first aspect, the present application provides a data caching method. The method can be applied to a computing device including a hybrid memory, the hybrid memory including a volatile memory and a persistent memory, and the persistent memory stores data corresponding to multiple modes. The method includes:

[0006] receiving a data access request, wherein the data access request includes an identifier of first data and an identifier of a first field, the first data includes values ​​of multiple fields, the multiple fields include the first field, the data corresponding to the multiple modes include the first data, and the first data corresponds to a first mode among the multiple modes;

[0007] In a case where it is determined to read the first data from the persistent memory, reading the first data from the persistent memory according to an identifier of the first data, extracting a value of the first field from the first data according to an identifier of the first field, and sending the value of the first field;

[0008] In the case of determining to cache the first data, the first data is written into a data page corresponding to the first mode in the volatile memory, the volatile memory including multiple data pages corresponding to each of the multiple modes, and the multiple data pages corresponding to each of the multiple modes are organized according to a first data structure.

[0009] In the above scheme, data pages corresponding to different modes are used in the volatile memory to store data of different modes. By partitioning the data of different modes, the space management efficiency of the volatile memory can be improved, thereby saving the efficiency of obtaining cached data from the volatile memory when the application of the computing device accesses data based on the mode.

[0010] In combination with the first aspect, in a possible implementation, the method further includes: determining whether to cache the first data based on the access information of the first mode. If the data accessed by the application does not hit the data cached in the RAM, it is necessary to read the data from the PMEM. The hit rate of the RAM is low, which means that more data needs to be read from the PMEM. Compared with PMEM, RAM has a read and write latency advantage. If PMEM is accessed to obtain data, it will increase the time for the application to obtain the data, seriously affecting the user experience. Therefore, determining whether to cache the data based on the access information of the mode can improve the hit rate of the RAM, thereby reducing the number of times data is obtained from PMEM and improving the user experience.

[0011] In combination with the first aspect, in a possible implementation, determining whether to cache the first data based on the access information of the first mode corresponding to the first data includes: determining an access rate of the first mode in a target time period based on the access information of the first mode; if the access rate of the first mode in the target time period is equal to or greater than an access rate threshold, determining to cache the first data; if the access rate of the first mode in the target time period is less than the access rate threshold, determining not to cache the first data.

[0012] In the above scheme, whether to cache the data in the volatile memory is determined according to the access rate corresponding to the data pattern, which can improve the hit rate of the data obtained by the application in the volatile memory when the application of the computing device accesses the data based on the pattern.

[0013] In combination with the first aspect, in a possible implementation, determining whether to cache the first data based on the access information of the first mode includes: determining an access rate of the first mode in a target time period based on the access information of the first mode; and determining to write the first data to the volatile memory when the access rate of the first mode in the target time period is equal to or greater than a first threshold.

[0014] In combination with the first aspect, in a possible implementation, the writing of the first data into a data page corresponding to the first mode in the volatile memory includes: when there is a first data page among multiple data pages corresponding to the first mode and there is a blank row in the first data page, writing the first data into the blank row of the first data page, wherein second data is stored in the first data page, and a distance between an identifier of the first data and an identifier of the second data in an index corresponding to the first mode is less than or equal to a distance threshold; when there is no first data page among multiple data pages corresponding to the first mode or there is no blank row in the first data page, writing the first data into the blank row of the second data page corresponding to the first mode.

[0015] In the above scheme, when writing data into the volatile memory, writing it into the data page corresponding to its adjacent data can further improve the efficiency of acquiring data. The adjacent data has a higher probability of being accessed later, and writing adjacent data into the same data page can improve the hit rate, thereby improving the efficiency of acquiring data.

[0016] In combination with the first aspect, in a possible implementation, before writing the first data into a blank row of a second data page corresponding to the first mode, the method further includes: determining the second data page according to metadata of each data page among a plurality of data pages corresponding to the first mode. The metadata of the data page includes identification information indicating whether each row in the data page stores data.

[0017] In combination with the first aspect, in a possible implementation, the method further includes: determining the number of unused data pages in the volatile memory; if the number is equal to or less than a number threshold, determining a target mode among the multiple modes according to the access rate of each mode among the multiple modes in the target time period, and deleting third data stored in each data page in the data page linked table corresponding to the target mode, wherein the life cycle of the third data is greater than a life cycle threshold corresponding to the target mode. The life cycle threshold corresponding to the target mode is determined according to the access rate of the target mode in the target time period and the row occupancy rate of the multiple data pages corresponding to the target mode.

[0018] In the above scheme, data is eliminated according to the access rate of each mode and the life cycle of the cached data of each mode in the volatile memory, which can save storage space and improve the space management efficiency of the volatile memory, and at the same time, can also ensure the hit rate of the volatile memory.

[0019] In combination with the first aspect, in a possible implementation, the method further includes: querying an index corresponding to the first mode according to an identifier of the first data to obtain location information of the first data:

[0020] Determine whether to read the first data from the persistent memory according to the location information of the first data. The index may adopt a data structure such as a hash table or a B-tree.

[0021] In the above solution, establishing indexes of different modes can improve the efficiency of querying indexes to obtain data locations.

[0022] In combination with the first aspect, in a possible implementation, extracting the value of the first field from the first data according to the identifier of the first field includes: extracting the value of the first field from the first data according to the identifier of the first field and the length of each field in the multiple fields, and sending the value of the first field.

[0023] In the above solution, the application running on the computing device can realize the function of accessing some fields of the data. In the related art, after the application obtains the complete data, it needs to parse the data to obtain the values ​​of some fields. This solution can shorten the time for the application to obtain the values ​​of some fields and improve the user experience.

[0024] In combination with the first aspect, in a possible implementation, the method further includes: updating location information of the first data in an index corresponding to the first mode, wherein the updated location information of the first data indicates that the first data is stored in the volatile memory.

[0025] In a second aspect, the present application further provides a data cache device, which can be applied to a computing device including a hybrid memory, wherein the hybrid memory includes a volatile memory and a persistent memory, and the device includes: an access module and a cache module.

[0026] The access module is used to receive a data access request, wherein the data access request includes an identifier of first data and an identifier of a first field, the first data includes values ​​of multiple fields, the multiple fields include the first field, the data corresponding to the multiple modes include the first data, and the first data corresponds to a first mode among the multiple modes;

[0027] Among them, the access module is also used to, when it is determined to read the first data from the persistent memory, read the first data from the persistent memory according to the identifier of the first data, extract the value of the first field from the first data according to the identifier of the first field, and send the value of the first field.

[0028] Among them, the cache module is used to write the first data into a data page corresponding to the first mode in the volatile memory when it is determined to cache the first data, and the volatile memory includes multiple data pages corresponding to each of the multiple modes, and the multiple data pages corresponding to each mode are organized according to the first data structure.

[0029] In combination with the second aspect, in a possible implementation, the cache module is further used to: determine whether to cache the first data according to access information of the first mode.

[0030] In combination with the second aspect, in a possible implementation, the cache module is specifically used to: determine the access rate of the first mode in the target time period based on the access information of the first mode; if the access rate of the first mode in the target time period is equal to or greater than the access rate threshold, determine to cache the first data; if the access rate of the first mode in the target time period is less than the access rate threshold, determine not to cache the first data.

[0031] In combination with the second aspect, in a possible implementation, the cache module is specifically used to: when there is a first data page among multiple data pages corresponding to the first mode and there is a blank row in the first data page, write the first data into the blank row of the first data page, wherein second data is stored in the first data page, and the distance between the identifier of the first data and the identifier of the second data in the index corresponding to the first mode is less than or equal to a distance threshold; when there is no first data page among multiple data pages corresponding to the first mode or there is no blank row in the first data page, write the first data into the blank row of the second data page corresponding to the first mode.

[0032] In combination with the second aspect, in a possible implementation, the cache module is further used to: determine the second data page according to metadata of each data page among a plurality of data pages corresponding to the first mode.

[0033] In combination with the second aspect, in a possible implementation, after writing the first data to a data page corresponding to the first mode in the volatile memory, the cache module is also used to: determine the number of unused data pages in the volatile memory; if the number is equal to or less than a quantity threshold, determine a target mode among the multiple modes according to an access rate of each mode in the multiple modes during the target time period, and delete third data stored in each data page in the data page linked list corresponding to the target mode, where a life cycle of the third data is greater than a life cycle threshold corresponding to the target mode.

[0034] In combination with the second aspect, in a possible implementation, the access module is also used to: query the index corresponding to the first pattern according to the identifier of the first data to obtain the location information of the first data; and determine whether to read the first data from the persistent memory according to the location information of the first data.

[0035] In combination with the second aspect, in a possible implementation, the access module is further used to: extract the value of the first field from the first data according to the identifier of the first field and the length of each field in the multiple fields, and send the value of the first field.

[0036] In combination with the second aspect, in a possible implementation, the cache module is further used to: update location information of the first data in the index corresponding to the first mode, and the updated location information of the first data indicates that the first data is stored in the volatile memory.

[0037] In a third aspect, the present application further provides a computing device, which includes: a processor and a memory, wherein the processor is configured to execute a computer program stored in the memory to implement the method in the first aspect or any optional implementation of the first aspect.

[0038] In a fourth aspect, the present application further provides a computer-readable storage medium, characterized in that it includes instructions, and when the instructions are executed on a computer, the computer implements the method in the first aspect or any optional implementation of the first aspect.

[0039] In a fifth aspect, the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method in the first aspect or any optional implementation of the first aspect.

[0040] Any of the above-mentioned devices or computing equipment or computer storage media or computer program products is used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding schemes in the corresponding methods provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of a hybrid memory provided in an embodiment of the present application;

[0042] Figure 2 It is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0043] Figure 3 is a flow chart of a data caching method provided in an embodiment of the present application;

[0044] Figure 4 It is a schematic diagram of performing mode-based management on DRAM cache space provided by an embodiment of the present application;

[0045] Figure 5 It is a schematic diagram of adding or releasing a data page to a DRAM cache space provided by an embodiment of the present application;

[0046] Figure 6 It is a structural schematic diagram of a data page provided in an embodiment of the present application;

[0047] Figure 7 is a flow chart of a data access method provided by an embodiment of the present application;

[0048] Figure 8 It is a schematic diagram of a cache conflict caused by concurrent access in an asynchronous cache mode provided by an embodiment of the present application;

[0049] Fig. 9 It is a structural diagram of a data cache device provided in an embodiment of the present application;

[0050] Fig.10 It is a structural diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0052] In the description of the embodiments of the present application, words such as "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a concrete way.

[0053] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "multiple" means two or more. For example, multiple systems refers to two or more systems, and multiple screen terminals refers to two or more screen terminals.

[0054] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprises", "has" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0055] Before introducing the embodiments of the present application, the terms appearing in the embodiments of the present application are explained below.

[0056] A schema is a logical structure used by a database system to organize and manage data. Each row of data in a database system has a unique schema corresponding to it. The schema can be defined by the type of the database table, primary key, foreign key, and / or field. For example, in a scenario, when a schema is defined from the type of a database table, primary key, foreign key, and field, the schema corresponding to the data can be determined based on the table name of the database table where the data is located, the primary key of the data, the foreign key of the data, and the type of each field included in the data. When a key-value (KV) storage method is used to store data in a database system, the key of the data can include the table name of the database table where the data is located and the primary key of the data in the database table. Therefore, when a KV storage method is used to store data in a database system, the table name of the database table where the data is located can be determined based on the key of the data.

[0057] Figure 1 It is a schematic diagram of a storage architecture in a computing device 100 provided in an embodiment of the present application.

[0058] Figure 1 The computing device 100 shown adopts a hybrid memory architecture. The computing device 100 includes a central processing unit (CPU), a volatile memory RAM and a persistent memory PMEM. Among them, the volatile memory RAM may include a dynamic random access memory (DRAM) and a static random access memory (SRAM), etc. The persistent memory PMEM may include a resistive random access memory (RRAM), a phase change memory (PCM), and a spin transfer torque RAM (STT RAM), etc. In the embodiment of the present application, the RAM in the hybrid memory architecture of the computing device 100 is DRAM as an example for introduction.

[0059] Generally speaking, a hybrid memory architecture can adopt a hierarchical architecture or a parallel architecture. Figure 1 The computing device 100 shown employs a hierarchical architecture. Figure 1 In the example, DRAM is the main memory of the computing device 100, PMEM is the auxiliary memory, and both DRAM and PMEM are mapped to a unified address space. In the initial state, all data are uniformly allocated in PMEM, and then hot data is cached in DRAM and cold data in DRAM is adjusted to PMEM according to the actual access situation of the application. For example, the hybrid memory of the computing device 100 uses data pages to store data. During the operation of the computing device 100, the CPU can record the number of accesses to the data page in DRAM, and when the number reaches a certain threshold, the cold data of the data page is migrated. In addition, in a computing device using a parallel architecture, DRAM and PMEM are both used as the main memory of the computing device, and DRAM and PMEM map different address spaces. In this way, the operating system and application of the computing device can use different address spaces according to actual needs, which is customizable.

[0060] In specific applications, hybrid memory architecture can use database systems to organize and store data to optimize data storage and retrieval and improve the efficiency and utilization of data processing.

[0061] Taking the relational database system using KV storage as an example, Figure 1 The computing device 100 shown may include a key-value access interface (hereinafter referred to as a KV interface). The KV interface may include a process (or thread) in the computing device 100. When the KV interface runs on the CPU of the computing device 100, the KV interface receives a data access request from an application running on the computing device 100, and accesses data stored in the hybrid memory of the computing device 100 according to the data access request.

[0062] The computing device 100 may be configured as follows: Figure 2 The key-value structure shown in Figure 2 stores data in a database table. Figure 2 As shown, the name of the database table is, for example, customer, and the fields in the table include a serial number (identity, ID), and fields A to D. The primary key of the table may be field ID. Figure 2In the table, the values ​​of the fields in the first row of data are 1, a1, b1, c1, and d1, respectively, and the values ​​of the fields in the second row of data are 2, a2, b2, c2, and d2, respectively. When KV storage is used, the computing device 100 can determine the key of each row of data based on the table name and the value of the primary key of each row of data. For example, the key of the first row of data can be customer_1, and the value is 1_a1_b1_c1_d1; the key of the second row of data is customer_2, and the value is 2_a2_b2_c2_d2.

[0063] When the hybrid memory adopts a hierarchical architecture, all key-value pairs are stored in PMEM, and DRAM caches a portion of the key-value pairs. In the related art, it takes a long time for the application to obtain the key-value pairs from DRAM, which is inefficient and affects the user experience.

[0064] To this end, an embodiment of the present application provides a data caching method based on pattern perception, which can solve the above problems.

[0065] The data caching method provided in the embodiment of the present application determines the mode of the data after reading the data from the PMEM, and writes the data into the data page corresponding to the mode corresponding to the data in the DRAM. Since the application running in the computing device accesses the data of the hybrid memory based on the mode, by partitioning the data of different modes in the DRAM, the query efficiency of the data can be improved, the waiting time of the application can be reduced, and the user experience can be improved.

[0066] Combine the following Figure 3 The data caching method provided in the embodiment of the present application is specifically introduced.

[0067] Figure 3 is a flow chart of a data caching method provided in an embodiment of the present application. The method can be applied to Figure 1 In the computing device 100 shown, after the KV interface is run on the CPU, the CPU executes the method. Figure 3 As shown, the method includes the following S301-S303.

[0068] S301, the CPU reads data 1 from PMEM.

[0069] In this embodiment, after the KV interface runs on the CPU, the KV interface can query the index of the database system to obtain the location information of the data 1 accessed by the application. In order to facilitate the efficiency of querying data, indexes can be created for data in different modes. In other words, the index of the database system can include indexes corresponding to each mode in multiple modes.

[0070] Specifically, the KV interface may first determine that data 1 corresponds to mode S1 among multiple modes according to the identifier of data 1. Then, Figure 4 As shown, the location information of data 1 is obtained according to the index corresponding to the identification query mode S1 of data 1. The KV interface can determine whether data 1 hits the data cached by DRAM according to the location information of data 1. If it hits, it means that DRAM has cached the data 1; if it does not hit, DRAM has not cached the data 1.

[0071] Wherein, when the KV storage method is adopted, the identification of the data may include the key of the data. That is to say, the KV interface can determine the mode S1 corresponding to the data 1 according to the key of the data 1. Wherein, the KV interface can first obtain the table name and primary key of the database table where the data 1 is located according to the key of the data 1, and then determine the mode S1 of the data 1 according to the table name of the database table, the primary key, foreign key, and field type corresponding to the data 1.

[0072] Specifically, the index corresponding to each mode includes the key and location information of the data corresponding to the mode. The index can be organized using a data structure such as a hash table, a B-tree, or a B+ tree. The location information of the data may include a pointer (ptr) to the data page storing the data and the state of the data. The state of the data includes cold or hot; when the state of the data is cold, it means that the data is stored in PMEM; when the state of the data is hot, it means that the data is stored in DRAM.

[0073] In this embodiment, after determining the location information of data 1, the data 1 is read according to the location information. Specifically, if the state of the data 1 is hot, the data is read from DRAM according to the pointer of the data page corresponding to the data 1; if the state of the data 1 is cold, the data 1 is read from PMEM according to the pointer of the data page corresponding to the data 1. In a specific implementation, PMEM can use a log structure to store key-value pairs. In S301, the KV interface can read data 1 from PMEM according to the identifier and pointer of data 1.

[0074] S302 , the CPU determines whether to cache the data 1 according to the access information of the mode S1 corresponding to the data 1 .

[0075] In this embodiment, the KV interface may record the access information of the mode of data accessed by each data access request after receiving the data access request of the application program each time, wherein the access information of the mode may include the access time of the mode.

[0076] In S302, the KV interface can determine the number of accesses corresponding to each mode from the current time to the historical time according to the access times corresponding to each mode, and determine the access rate of mode S1 in the target time period according to the access times corresponding to mode S1. Among them, the access rate corresponding to mode S1 is the ratio of the number of accesses of mode S1 to the sum of the number of accesses corresponding to each mode. It should be noted that historical time refers to the time whose distance from the current time is the target time length. In other words, current time - historical time = target time length.

[0077] In S302, after obtaining the access rate corresponding to mode S1, the KV interface determines whether to cache the data 1 according to the access rate corresponding to mode S1 and the access rate threshold. For example, when the access rate corresponding to mode S1 is equal to or greater than the access rate threshold, it is determined that data 1 is cached; when the access rate corresponding to mode S1 is less than the access rate threshold, it is determined that data 1 is not cached.

[0078] Since the applications running in the computing device access the data in the hybrid memory based on the pattern, by sensing the pattern of the data and determining whether to cache the data, the data with a higher access rate can be cached in the DRAM, which can improve the hit rate of the cache in the DRAM, thereby reducing the number of times data is read from PMEM. If the DRAM hit rate is low, the number of times the KV interface reads key-value pairs from PMEM will increase. However, the large number of times the KV interface reads key-value pairs from PMEM will reduce the efficiency of the KV interface in processing data access requests, affecting the user experience.

[0079] S303 , when determining to cache data 1 , the CPU writes data 1 into a data page corresponding to mode S1 in the DRAM.

[0080] In this embodiment, the storage space in the DRAM may include a page-based row buffer (PBRB). The space allocation and management of the PBRB is performed at the granularity of the memory page, which can reduce the metadata overhead of the PBRB. In other words, the PBRB includes multiple data pages, and the multiple data pages can be organized in a linked list. When the multiple data pages are not in use, Figure 5 When the data of a pattern needs to be stored, the KV interface can take a data page from the space data page list to store the data of the pattern, and use the list to organize the data pages corresponding to each pattern. When all the data pages in the page list corresponding to a pattern are full, such as Figure 5As shown, the KV interface can continue to take out an idle data page from the idle page list and add it to the page list corresponding to the mode. It should be noted that the data page can also be organized in other types of data structures, which are not specifically limited in this application. The structure of the data page is introduced below.

[0081] The data page can include Figure 6 The page header storage area and row storage area are shown.

[0082] The page header storage area is used to store page metadata, which can include Figure 6 The fields shown are type (magic), mode identifier (schema ID), number of hot data (hot row number), pointer to the previous page (pre page ptr), pointer to the next page (nxet page ptr), occupancy bitmap (occubitmap), and reserved. Among them, the magic field can indicate the data type of the data stored in the page, so that the KV interface can parse the data in the page according to the data type. The hot row number field indicates the number of rows occupied in the row storage area of ​​the page. The occubitmap bitmap field indicates whether each row in the row storage area is occupied. Among them, each bit in the occubitmap bitmap field corresponds to each row in the row storage area. When the value of a bit is 1, it indicates that the corresponding row in the row storage area is occupied; when the value of a bit is 0, it indicates that the corresponding row in the row storage area is not occupied. The size of the occubitmap bitmap field (occubitmap size) can be determined according to the size of the page (page size), the size of the page header storage area (head size) and the size of each row in the row storage area (row size), and can be specifically calculated according to the following formula (1).

[0083]

[0084] The row storage area includes Figure 6 The row header storage area and the row content storage area (rowcontent) are shown.

[0085] The row header storage area is used to store metadata of the row data of the database table, which may include Figure 6The cyclic redundancy check (CRC), time stamp, PMEM storage address (plogaddr), index pointer (index ptr), row size and other fields are shown. The CRC field is the CRC check code of the data stored in the row, which is updated whenever the row changes. When reading the data stored in the row, the CRC code of the read data can also be calculated, and then compared with the CRC code stored in the row to determine whether the data stored in the row has been tampered with. The timestamp indicates the last time the row stored data was accessed, that is, the timestamp is updated each time the row is accessed. The Plog addr field indicates the address of the row stored data in PMEM, where PMEM uses a log log structure to store the data. When the data stored in the DRAM data page is damaged, the data can be re-read according to the value of the plog addr field to repair the damaged data.

[0086] The row content storage area is used to store the values ​​of various fields of the row data of the database table, for example, Figure 6 The values ​​of field 1 (field1), field 2 (field2), and other valid fields and padding fields are shown. The padding field is used to align the length of each row to ensure that the total length or size of each row is aligned. It should be noted that the row content storage area uses structured storage data fields, that is, the values ​​of the data fields are stored in the rows of the row content storage area according to the order of the fields in the database table. This makes it easy to obtain the values ​​of the corresponding fields according to the size of the field, thereby improving the efficiency of obtaining the values ​​of some fields of the data.

[0087] Based on the above introduction, in S302, the KV interface can determine a data page in the page linked list corresponding to mode S1 when determining cache data 1, and write data 1 into the data page. The following specifically describes how the KV interface determines the data page storing data 1.

[0088] Specifically, based on access locality, data with continuous or adjacent keys have a higher probability of being continuously accessed within a period of time. Therefore, data with continuous or adjacent keys can be stored in the same data page, which can save the time of querying data pages and querying data. To this end, when determining the data page storing data 1, the index corresponding to mode S1 can be queried according to the target distance to determine whether there is location information of data 2 in the index corresponding to mode S1. Among them, data 2 refers to data that has been cached in DRAM and the distance between the location information of data 2 and the location information of data 1 in the index corresponding to mode S1 is less than or equal to the target distance. After finding the location information of data 2, the pointer of data page 1 storing data 2 is determined according to the location information of data 2. Then, the metadata of the page header area of ​​data page 1 is read according to the pointer of data page 1. It should be noted that setting the target distance can avoid excessive overhead of querying the index and reduce cache efficiency.

[0089] After obtaining the metadata of the page header area of ​​data page 1, find the value of the occupancy bitmap field by bitwise operation, and then traverse the value of this field. If the first bit with a value of 0 in this field is the i-th bit, the metadata corresponding to data 1 is written into the row header storage area of ​​the i-th row of data page 1, and data 1 is written into the row content storage area of ​​the i-th row of data page 1. Among them, the value of the i-th bit is 0, which means that the i-th row in data page 1 is a blank row, that is, no data is stored in this row. If no bit with a value of 0 is found in this field, it means that all rows of data page 1 are occupied and data is stored. In this case, find data page 2 according to the method in the next paragraph.

[0090] When data page 1 is not found from the index of mode S1 or data page 1 does not have a blank row, all data pages of mode S1 are traversed starting from the first data page of mode S1 (hereinafter referred to as the header page) to find data page 2 containing a blank row. The KV interface can read the header page of mode S1 according to the pointer of the header page corresponding to each mode stored in advance, and determine whether there is a blank row on the header page according to the occupancy bitmap stored in the page header of the header page of mode S1. If there is no blank row on the header page, read the next page according to the pointer of the next page stored in the page header of the header page, and then determine whether there is a blank row on the next page according to the occupancy bitmap stored in the page header of the next page. Use this method to traverse the page linked list of mode S1 in sequence. When the page linked list of mode S1 is traversed, data page 2 with a blank row is not found or, if Figure 5As shown, a blank page is taken out from the free page list, and the page is added to the page list of mode S1. The newly added page is data page 2. After determining data page 2, according to the occupied bitmap of data page 2, the metadata corresponding to data 1 is written into the row header storage area of ​​the first blank row of data page 2, and data 1 is written into the row content storage area of ​​the first blank row of data page 2. The metadata corresponding to data 1 can refer to the above introduction to the row storage area of ​​the page, which will not be repeated here.

[0091] exist Figure 3 In the method embodiment shown, after writing data 1 to DRAM, the KV interface updates the location information of data 1 in the index corresponding to mode S1, and the updated location information of data 1 indicates that data 1 is stored in DRAM. Updating the location information of data 1 in the index corresponding to mode S1 includes changing the state of data 1 in the index corresponding to S1 from cold to hot, and changing the pointer of data 1 to a pointer pointing to the data page where data 1 is located.

[0092] exist Figure 3 In the method embodiment shown, after writing data 1 to DRAM, the KV interface can determine whether to evict the data pages corresponding to each mode in the DRAM according to the number of unused data pages in the DRAM. Specifically, the KV interface can determine the number of unused data pages in the DRAM according to the free page list, and if the number is equal to or less than the number threshold, calculate the access rate of each mode in the target time period. After obtaining the access rate of each mode, Figure 7 As shown in FIG, data pages corresponding to each mode are evicted in the order of access rate from low to high. Figure 7 As shown in FIG. 1 , if the access rate of mode S1 is the lowest among the access rates of various modes, mode S1 is the target mode to be processed, that is, the data stored in the data page of mode S1 is first evicted. When the data page corresponding to S1 is evicted, if all the data stored in the row storage area of ​​a data page are deleted, the data page is deleted from the page linked list corresponding to S1, as shown in FIG. Figure 5 As shown, the data page is added to the free page list. The process of evicting the data page corresponding to mode S1 can be seen in the introduction in the next paragraph.

[0093] When the data stored in a data page of a pattern is evicted, the page chain list corresponding to the pattern is followed, starting from the head page corresponding to the pattern, until the last data page of the pattern. When traversing to a data page, the timestamp stored in each row in the row storage area of ​​the data page is obtained, and the life cycle corresponding to each row is obtained according to the timestamp stored in each row and the current time, and then the third data in the data page is determined according to the life cycle corresponding to each row and the life cycle threshold corresponding to the pattern. The life cycle corresponding to the row where the third data is located is equal to or greater than the life cycle threshold corresponding to the pattern.

[0094] Among them, the life cycle threshold lifetime of the i-th mode i It can be determined by the following formula (2).

[0095] lifetime i =2 -N ×H i ×(1-RO i )×RW i (2)

[0096] In formula (2), N represents the number of rounds of current data eviction, H i represents the access rate of the i-th mode, RO i Indicates the row occupancy rate of the page list corresponding to the i-th mode, RW i Represents the prior parameters of the i-th mode set by the user. The row occupancy rate corresponding to the mode can be determined according to the ratio of the sum of the number of rows of data actually stored in each page corresponding to the mode to the sum of the total number of rows of each page. When data is evicted for each mode, N is the initial value 0; when the number of data pages in the free page list does not meet the preset value after data is evicted for each mode, N is increased by 1 and a new round of data eviction is restarted. In this way, if the number of data pages in the free page list does not meet the preset value after the previous round of eviction, the next round of eviction will halve the life cycle threshold, thereby improving the eviction efficiency.

[0097] Based on formula (2), the life cycle threshold of each mode can be dynamically adjusted according to the access rate of each mode and the actual cache data of each mode. For example, when the row occupancy rate of the page list is high but the hit rate is very low, it means that a large part of the data is not worth caching. In this case, the life cycle threshold is dynamically shortened to promote efficient data recovery. When the row occupancy rate is very low but the hit rate is very high, it means that the data is very valuable. In this case, the life cycle threshold can be dynamically extended, so as to retain as much valuable data as possible.

[0098] It can be understood that after the KV interface evicts data from the data pages corresponding to each mode, it is also necessary to update the location information of the evicted data in the index corresponding to each mode. The updated location information of the evicted data indicates that the evicted data is stored in PMEM. The updated content of the location information of the updated evicted data is opposite to the updated content of the location information of the aforementioned updated data 1. Those skilled in the art can know the specific operations here based on the aforementioned introduction, and will not be repeated here.

[0099] Above Figure 3 In the method embodiment shown, different page linked lists are used to manage cache data of different modes, which can improve the management efficiency of DRAM cache space and the efficiency of the processor in obtaining data of a certain mode from DRAM. In addition, in the above method, when the application of the computing device is based on pattern access, it is determined whether to cache the data according to the access rate of the pattern corresponding to the data, and the data of the pattern with a higher access rate can be cached in DRAM, which can improve the hit rate of the accessed data in DRAM, thereby reducing the number of times data is read from PMEM. Among them, when the size of the data to be read is smaller than the access granularity of PMEM, read amplification will occur when reading the data from PMEM. Therefore, while using a pattern-aware cache method to improve the DRAM hit rate, the read amplification of PMEM can be reduced.

[0100] based on Figure 3 The method embodiment shown, the embodiment of the present application also provides a data access method.

[0101] In actual application scenarios, an application may only need to read some fields in the data, that is, to access some fields in a data. In related technologies, the application needs to call the KV interface and send the key of the data to the KV interface. After the KV interface obtains the data according to the key of the data, it returns the data to the application. The application parses the data to obtain the values ​​of some required fields. In other words, the application cannot directly call the KV interface to access some fields of the data, and the KV interface cannot directly return some fields of the data to the application, resulting in delays in users obtaining the values ​​of some fields, affecting the user experience. To this end, a data access method provided in an embodiment of the present application can solve this problem.

[0102] In the data access method provided in an embodiment of the present application, when the KV interface receives partial fields of data accessed by an application, it reads the data from DRAM or PMEM, then extracts the value of the field accessed by the application from the data based on the size of each field in the data, and returns the value of the field to the application.

[0103] Figure 7is a flow chart of a data access method provided in an embodiment of the present application. The method can be applied to Figure 1 In the computing device 100 shown, after the KV interface is run on the CPU, the CPU executes the method. Figure 4 As shown, the method may include the following S401 to S404.

[0104] S701, the KV interface receives a data access request sent by an application.

[0105] In this step, after the KV interface and the application are running on the CPU, the application calls the KV interface to send a data access request. The data access request may include the identifier of data 1 and the identifier of field 1 in data 1. For example Figure 2 As shown, the application determines the acquisition Figure 2 In the case of the second row of data shown, the key of the second row of data can be carried in the data access request. As mentioned above, the key of the second row of data can include the table name and primary key (ID) of the database table where the second row of data is located, that is, customer_2.

[0106] S702, the KV interface determines the mode S1 corresponding to the data 1 according to the identifier of the data 1.

[0107] Other specific processes of this step can refer to the above Figure 3 The description in will not be repeated here.

[0108] S703, the KV interface queries the index corresponding to the mode S1 to determine the storage location of the data 1. If the storage location of the data 1 is PMEM, S704 is executed. If the storage location of the data 1 is DRAM, S705 is executed.

[0109] S704, the KV interface reads data 1 from PMEM, and when the cached data 1 is determined, writes data 1 into a data page corresponding to mode S1 in DRAM. The present application embodiment does not specifically limit the process of reading data from PMEM. Other specific processes of this step can refer to the aforementioned Figure 3 The description is not repeated here.

[0110] S705, the KV interface reads data 1 from the DRAM.

[0111] In this step, when it is determined that the location information of data 1 indicates that data 1 is stored in DRAM, the row contents of each row stored in the row storage area of ​​the data page are read from DRAM according to the pointer of the data page in the location information of data 1. Then, data 1 is determined from the row contents of each row. Specifically, the primary key of data 1 is determined according to the identifier of data 1, and the value of the first L bits in the row content of each row is determined; then the row content of the row whose value of the first L bits in the row content of each row is the same as the primary key of data 1 is data 1, where L is the length of the primary key of data 1. For example, when the value of the first L bits in the row content of the mth row is the same as the primary key of data 1, the row content of the mth row is data 1.

[0112] S706, determine the offset corresponding to field 1 according to the size of each field in data 1, and extract the value of field 1 from data 1 according to the offset corresponding to field 1.

[0113] In this step, data 1 is used as Figure 2 Taking the second row of data shown as an example, when field 1 is field D, the KV interface can determine the offset of field D according to the size of each field from field A to field D, and extract the value "d2" of field D from "2_a2_b2_c2_d2". For example, when the sizes of field A to field D are 4 bits, 5 bits, 6 bits, and 5 bits, respectively, "2_a2_b2_c2_d2" is 20 bits in binary representation. Based on this, the KV interface can obtain that the offset of field D is 15 bits, and extract the values ​​of the 16th to 20th bits from them, thereby obtaining "d2".

[0114] Above Figure 7 In the method embodiment shown, the KV interface can support the function of the application program accessing partial fields. The KV interface can directly return the values ​​of the partial fields accessed by the application program to the application program, thereby saving the application program time in parsing and extracting data after obtaining complete data. This can improve the efficiency of the application program in obtaining partial fields and improve the user experience.

[0115] In the embodiment of the present application, the KV interface may include a point query interface (get interface), a delete interface (delete interface), an insert interface (put interface), an update interface (update interface), a range query interface (scan interface), and a schema creation interface (create schema interface). Each interface can be called by an application running on a computing device to implement a corresponding function. Each interface is introduced below.

[0116] Point query interface (get interface), the application can call the get interface to query a data, the get interface executes after receiving the call Figure 7 The steps in the method embodiment shown. And, when determining cache data, execute Figure 3 The steps in the method embodiment shown. When the application needs to access some fields of data, the get interface can be called and the identifier of the data and the identifier of the field can be specified. When the application needs to access the complete fields of data, the get interface can be called and the identifier of the data can be specified. In addition, the get interface access to data and cached data can be implemented asynchronously to improve its efficiency. For example, the process of accessing data and caching data is implemented separately by two threads. This part of the content is introduced later and will not be repeated here.

[0117] Delete interface (delete interface), the application can call the delete interface to delete the data stored in the hybrid memory. After receiving the call, the delete interface queries the index of the mode corresponding to the data according to the data identifier and deletes the PMEM stored data. If the data has been cached in DRAM, the DRAM stored data can also be deleted. It can be understood that after deleting the data, the delete interface needs to update the index of the mode corresponding to the data.

[0118] Insert interface (put interface), the application can call the put interface to insert data, that is, write new data in PMEM. After receiving the call, the put interface stores the data in PMEM and updates the index of the mode corresponding to the data. Specifically, the key of the data, the pointer of the data in PMEM, and the status of the data are added to the corresponding index.

[0119] Update interface (update interface), the application can call the update interface to update data, including updating the complete value of the data or updating the value of some fields of the data. The data access request called by the application to the update interface can include the identification of the data and the updated value. It can also include the identification of the data, the identification of the field, and the updated value of the field. After receiving the call, the update interface updates the data stored in PMEM or the value of the field specified by the application of the data. If the data has been cached in DRAM, it is also necessary to update the location information of the data in the index, including updating the pointer and status of the data.

[0120] Range query interface (scan interface), the application can call the scan interface to access multiple data of a pattern. The application can call the scan interface to specify the identifier and range length of the starting data. The scan interface reads multiple data of the corresponding pattern of the data from the specified identifier and range length of the starting data and returns it to the application.

[0121] Schema creation interface (create schema interface), applications can call the create schema interface to create a new schema. Applications can call the create schema interface to indicate the metadata of the schema, including the length of the schema data, the names of the fields corresponding to the schema data, the sizes of the fields, and the data types of the fields. After receiving the call, the create schema interface creates a new schema according to the schema metadata, assigns a schema identifier, and returns the schema identifier to the application.

[0122] In an embodiment of the present application, the above-mentioned get interface can implement data access and data caching asynchronously. For example, thread 1 of the get interface accesses data according to the data access request, and thread 3 caches the data. When thread 1 determines to cache data, it sends a cache request to thread 3. Thread 3 adds the cache request of thread 1 to the cache task queue, and then thread 3 executes each cache task in the cache task queue, and writes the data to be cached into a data page of the pattern corresponding to the data in DRAM. Through asynchronous caching, data reading and caching tasks are executed by different threads respectively, which can reduce cache latency.

[0123] In actual scenarios, in order to achieve concurrent access, the KV interface can usually include multiple threads, each of which can receive calls from applications. In this way, cache inconsistency problems may occur under the asynchronous caching solution, such as read-read conflicts, read-write conflicts, and write-write conflicts. In this regard, the embodiment of the present application adopts an optimistic concurrency control solution, which invalidates inconsistent cache data based on timestamps according to CAS operations. Figure 8 This section describes how to resolve cache inconsistency issues under three types of conflicts.

[0124] Read-read conflict, take the last access timestamp (ts) of data 1 as ts0 as an example, Figure 8 As shown, thread 1 responds to the access of application 1 and performs a read operation at ts1 to read data 1. Subsequently, thread 2 responds to the access of application 2 and performs a read operation at ts2 to read data 1. In the case that neither thread 1 nor thread 2 updates data 1, Figure 8 In the example, thread 2 requests thread 3 to cache data 1 earlier than thread 1. Thread 3 uses CAS operation to execute thread 2's cache task and terminates thread 1's cache task according to the order in the cache task queue.

[0125] Specifically, when thread 3 uses CAS operation to execute thread 2's cache task, the expected timestamp of the last access to data 1 is ts0, and the actual timestamp of the last access to data 1 is ts0, which are consistent. Thread 3 writes data 1 to DRAM and updates the timestamp of the last access to data 1 to the timestamp ts2 corresponding to thread 2. When thread 3 executes thread 1's cache task, the expected timestamp of the last access to data 1 is ts0. Since thread 2's cache task has been executed, the actual timestamp of the last access to data 1 becomes ts2, which are inconsistent. Therefore, thread 3 terminates thread 1's cache task.

[0126] Read-write conflicts, such as Figure 8 As shown, thread 1 responds to the access of application 1 and performs a read operation at time stamp 1 (time stamp 1, ts1) to read data 1. Subsequently, thread 2 responds to the access of application 2 and performs a read operation at time stamp 2 (time stamp1, ts1) to read and update data 1. Figure 8 In the example, thread 1 requests thread 3 to cache data 1 earlier than thread 2. Thread 3 uses CAS operation to execute the cache task of thread 1 and terminate the cache task of thread 2 according to the order in the cache task queue.

[0127] Specifically, when thread 3 uses CAS operation to execute thread 1's cache task, the expected timestamp of the last access to data 1 is ts0, and the actual timestamp of the last access to data 1 is ts0, which are consistent. Thread 3 writes data 1 to DRAM and updates the timestamp of the last access to data 1 to the timestamp ts1 corresponding to thread 1. When thread 3 executes thread 2's cache task, the expected timestamp of the last access to data 1 is ts0. Since thread 1's cache task has been executed, the actual timestamp of the last access to data 1 becomes ts1, which are inconsistent. Therefore, thread 3 terminates thread 2's cache task.

[0128] Write-write conflicts, such as Figure 8 As shown, thread 1 responds to the access of application 1 and performs a read operation at timestamp 1 (ts1) to read and update data 1. Subsequently, thread 2 responds to the access of application 2 and performs a read operation at timestamp 2 (ts1) to read and update data 1. Figure 8 In the same way, Figure 8 In the example, thread 2 requests thread 3 to cache data 1 earlier than thread 1. Thread 3 uses CAS operation to execute thread 2's cache task and terminates thread 1's cache task according to the order in the cache task queue.

[0129] Specifically, when thread 3 uses CAS operation to execute thread 2's cache task, the expected timestamp of the last access to data 1 is ts0, and the actual timestamp of the last access to data 1 is ts0, which are consistent. Thread 3 writes data 1 to DRAM and updates the timestamp of the last access to data 1 to the timestamp ts2 corresponding to thread 2. When thread 3 executes thread 1's cache task, the expected timestamp of the last access to data 1 is ts0. Since thread 2's cache task has been executed, the actual timestamp of the last access to data 1 becomes ts2, which are inconsistent. Therefore, thread 3 terminates thread 1's cache task.

[0130] based on Figure 3 and Figure 7 The method shown in the embodiment of the present application provides a data cache device. The data cache device can be applied to Figure 1 The computing device 100 shown is used to implement the aforementioned Figure 3 and Figure 7 The steps shown.

[0131] Fig. 9 1 is a schematic diagram of a data cache device 900 provided in an embodiment of the present application. The data cache device 900 includes an access module 901 and a cache module 902 .

[0132] The access module 901 is used to read first data among data corresponding to multiple modes from a persistent memory, where the first data corresponds to the first mode among the multiple modes.

[0133] The cache module 902 is used to write the first data into a data page corresponding to the first mode in the volatile memory when determining to cache the first data. The volatile memory includes multiple data pages corresponding to each of the multiple modes, and the multiple data pages corresponding to each mode are organized according to the first data structure.

[0134] It should be noted that Fig. 9 The data cache device 900 provided in the embodiment shown in the figure only uses the division of the above-mentioned functional modules as an example when executing the data cache method. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Figure 3 and Figure 7 The method embodiments shown belong to the same concept, and their specific implementation processes are detailed in the method embodiments, which will not be repeated here.

[0135] Fig.10 It is a schematic diagram of the hardware structure of a computing device 1000 provided in an embodiment of the present application.

[0136] The computing device 1000 may be the computing device or the terminal device mentioned above. Fig.10 The computing device 1000 includes a processor 10001, a memory 10002, a communication interface 10003, and a bus 10004. The processor 10001, the memory 10002, and the communication interface 10003 are connected to each other via the bus 10004. The processor 10001, the memory 10002, and the communication interface 10003 may also be connected in other connection modes besides the bus 10004.

[0137] Among them, memory 10002 can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical storage, hard disk, etc.

[0138] The processor 10001 may be a general-purpose processor, which may be a processor that performs specific steps and / or operations by reading and executing the contents stored in a memory (e.g., memory 10002). For example, the general-purpose processor may be a central processing unit (CPU). The processor 10001 may include at least one circuit to execute Figure 3 or Figure 7 The illustrated embodiments provide all or part of the steps of the method.

[0139] The communication interface 10003 includes input / output (I / O) interfaces, physical interfaces, and logical interfaces for interconnecting devices within the computing device 1000, and interfaces for interconnecting the computing device 1000 with other devices (such as other computing devices or user devices). The physical interface can be an Ethernet interface, a fiber optic interface, an ATM interface, etc.

[0140] The bus 10004 may be any type of communication bus for interconnecting the processor 10001 , the memory 10002 , and the communication interface 10003 , such as a system bus.

[0141] The above devices may be arranged on independent chips, or at least partially or completely on the same chip. Whether to arrange each device independently on different chips or to integrate them on one or more chips often depends on the needs of product design. The embodiments of the present application do not limit the specific implementation form of the above devices.

[0142] Fig.10 The computing device 1000 shown is merely exemplary. During implementation, the computing device 1000 may also include other components, which are not listed one by one in this article.

[0143] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0144] It is understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. It should be understood that in the embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0145] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the scope of protection of the present application.

Claims

1. A data caching method, characterized in that: Applied to a computing device including a hybrid memory, the hybrid memory including a volatile memory and a persistent memory, the persistent memory storing data corresponding to multiple modes, the method comprising: receiving a data access request, wherein the data access request includes an identifier of first data and an identifier of a first field, the first data includes values ​​of multiple fields, the multiple fields include the first field, the data corresponding to the multiple modes include the first data, and the first data corresponds to a first mode among the multiple modes; In a case where it is determined to read the first data from the persistent memory, reading the first data from the persistent memory according to an identifier of the first data, extracting a value of the first field from the first data according to an identifier of the first field, and sending the value of the first field; In the case of determining to cache the first data, the first data is written into a data page corresponding to the first mode in the volatile memory, the volatile memory including multiple data pages corresponding to each of the multiple modes, and the multiple data pages corresponding to each of the multiple modes are organized according to a first data structure.

2. The method according to claim 1, characterized in that: The method further comprises: Querying the index corresponding to the first mode according to the identifier of the first data to obtain the location information of the first data; Determine whether to read the first data from the persistent memory according to the location information of the first data.

3. The method according to claim 1 or 2, characterized in that: The extracting the value of the first field from the first data according to the identifier of the first field includes: A value of the first field is extracted from the first data according to an identifier of the first field and a length of each of the multiple fields.

4. The method according to claim 1, characterized in that The method further comprises: Determine whether to cache the first data according to the access information of the first mode.

5. The method according to claim 4, characterized in that The determining whether to cache the first data according to the access information of the first mode includes: determining an access rate of the first mode in a target period according to the access information of the first mode; If the access rate of the first mode in the target time period is equal to or greater than the access rate threshold, determine to cache the first data; If the access rate of the first mode in the target time period is less than the access rate threshold, it is determined not to cache the first data.

6. The method according to claim 1, characterized in that The step of writing the first data into a data page corresponding to the first mode in the volatile memory includes: When there is a first data page among the multiple data pages corresponding to the first mode and there is a blank row in the first data page, writing the first data into the blank row of the first data page, wherein the first data page stores second data, and the distance between the identifier of the first data and the identifier of the second data in the index corresponding to the first mode is less than or equal to a distance threshold; When the first data page does not exist in the plurality of data pages corresponding to the first mode or the first data page does not have a blank row, the first data is written into a blank row of a second data page corresponding to the first mode.

7. The method according to claim 6, characterized in that Before writing the first data into a blank row of a second data page corresponding to the first mode, the method further includes: The second data page is determined according to metadata of each data page among a plurality of data pages corresponding to the first mode.

8. The method according to claim 1, characterized in that After writing the first data into a data page corresponding to the first mode in the volatile memory, the method further includes: determining a number of unused data pages in the volatile memory; If the number is equal to or less than the number threshold, determine the target mode among the multiple modes according to the access rate of each mode in the target time period, delete the third data stored in each data page in the data page linked list corresponding to the target mode, and the life cycle of the third data is greater than the life cycle threshold corresponding to the target mode, wherein the life cycle threshold corresponding to the target mode is determined according to the access rate of the target mode in the target time period and the row occupancy rate of the multiple data pages corresponding to the target mode.

9. The method according to claim 1, characterized in that: The method further comprises: The location information of the first data in the index corresponding to the first mode is updated, and the updated location information of the first data indicates that the first data is stored in the volatile memory.

10. A data cache device, characterized in that: Applied to a computing device including a hybrid memory, the hybrid memory including a volatile memory and a persistent memory, the persistent memory storing data corresponding to multiple modes, the method comprising: an access module, configured to receive a data access request, wherein the data access request includes an identifier of first data and an identifier of a first field, the first data includes values ​​of multiple fields, the multiple fields include the first field, the data corresponding to the multiple modes include the first data, and the first data corresponds to a first mode among the multiple modes; The access module is further configured to, when it is determined to read the first data from the persistent memory, read the first data from the persistent memory according to an identifier of the first data, extract a value of the first field from the first data according to the identifier of the first field, and send the value of the first field; A cache module is used to write the first data into a data page corresponding to the first mode in the volatile memory when it is determined to cache the first data, the volatile memory including multiple data pages corresponding to each of the multiple modes, and the multiple data pages corresponding to each of the multiple modes are organized according to a first data structure.

11. The device according to claim 10, characterized in that The access module is also used for: Querying the index corresponding to the first mode according to the identifier of the first data to obtain the location information of the first data; Determine whether to read the first data from the persistent memory according to the location information of the first data.

12. The device according to claim 10 or 11, characterized in that The access module is specifically used for: A value of the first field is extracted from the first data according to an identifier of the first field and a length of each of the multiple fields.

13. The device according to claim 10, characterized in that The cache module is specifically used for: Determine whether to cache the first data according to the access information of the first mode.

14. The device according to claim 13, characterized in that The cache module is specifically used for: determining an access rate of the first mode in a target period according to the access information of the first mode; If the access rate of the first mode in the target time period is equal to or greater than the access rate threshold, determine to cache the first data; If the access rate of the first mode in the target time period is less than the access rate threshold, it is determined not to cache the first data.

15. The device according to claim 10, characterized in that The cache module is specifically used for: When there is a first data page among the multiple data pages corresponding to the first mode and there is a blank row in the first data page, writing the first data into the blank row of the first data page, wherein the first data page stores second data, and the distance between the identifier of the first data and the identifier of the second data in the index corresponding to the first mode is less than or equal to a distance threshold; When the first data page does not exist in the plurality of data pages corresponding to the first mode or the first data page does not have a blank row, the first data is written into a blank row of a second data page corresponding to the first mode.

16. The device according to claim 15, characterized in that The cache module is also used for: The second data page is determined according to metadata of each data page among a plurality of data pages corresponding to the first mode.

17. The device according to claim 10, characterized in that After writing the first data into a data page corresponding to the first mode in the volatile memory, the cache module is further used for: determining a number of unused data pages in the volatile memory; If the number is equal to or less than the number threshold, determine the target mode among the multiple modes according to the access rate of each mode in the target time period, delete the third data stored in each data page in the data page linked list corresponding to the target mode, and the life cycle of the third data is greater than the life cycle threshold corresponding to the target mode, wherein the life cycle threshold corresponding to the target mode is determined according to the access rate of the target mode in the target time period and the row occupancy rate of the multiple data pages corresponding to the target mode.

18. The device according to claim 10, characterized in that The cache module is also used for: The location information of the first data in the index corresponding to the first mode is updated, and the updated location information of the first data indicates that the first data is stored in the volatile memory.

19. A computing device, characterized in that The computing device comprises: a processor and a memory, wherein the processor is configured to execute a computer program stored in the memory to implement the method according to any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that: The method comprises instructions, which, when executed on a computer, enable the computer to execute the method according to any one of claims 1 to 9.

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