Memory management method and device, electronic equipment and storage medium

Abstract

The invention discloses a memory management method and device, electronic equipment and a storage medium, and relates to the technical field of memory management. The memory management method comprises the following steps: determining track point information and calculation chip information of a molecular dynamics calculation task, and matching a target memory pool according to the track point information; when the matching of the target memory pool fails, determining the number of memory pools and the to-be-occupied size of the memory pools according to the track point information and the calculation chip information; and constructing a target memory pool according to the number of the memory pools and the to-be-occupied size of the memory pools, and storing the computing chip information to the target memory pool. According to the embodiment of the invention, reasonable allocation of the memory is realized; meanwhile, the number of the memory pools is controlled according to the number of the calculated track points, the size of the memory pools is controlled according to the data size needing to be stored by each track point, the utilization rate of the memory is increased, the number of times of constructing the memory pools by program application is reduced, and storage of calculation chip information of molecular dynamics calculation tasks is conveniently determined.

Description

Technical Field

[0001] The present invention relates to the field of memory management technology, and in particular to a memory management method, device, electronic device and storage medium. Background Art

[0002] Molecular dynamics (MD) calculation is a computational method that simulates the evolution of molecular systems over time. It is widely used in physics, chemistry, biology and other scientific fields. With the development of computer technology and the increase in application demand, the scale and complexity of molecular dynamics calculations continue to increase, and the demand for computing resources is also increasing. In large-scale molecular dynamics simulations, efficient memory management is crucial because the utilization of memory resources directly affects the speed of calculations and the accuracy of results.

[0003] In molecular dynamics calculations, it is usually necessary to frequently allocate and release memory to store and process various data of molecular systems (such as atomic coordinates, velocity, force, etc.). Since the size and quantity of these data are not fixed, memory allocation and release operations are frequent, which easily leads to memory fragmentation problems. Memory fragmentation refers to the fact that the memory space is divided into many small blocks after multiple allocation and release operations. Although the total available memory is still sufficient, these small blocks of memory cannot be used continuously, resulting in a decrease in memory utilization and may even cause insufficient memory problems. Therefore, how to reasonably allocate memory for data storage has become a problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a memory management method, device, electronic device and storage medium to solve the problem in the prior art that memory cannot be reasonably allocated for data storage.

[0005] According to one aspect of the present invention, a memory management method is provided, wherein the method comprises:

[0006] Determine the trajectory point information and computing chip information of the molecular dynamics calculation task, and match the target memory pool according to the trajectory point information;

[0007] When the target memory pool fails to match, determining the number of memory pools and the size of the memory pools to be occupied according to the track point information and the computing chip information;

[0008] A target memory pool is constructed according to the number of memory pools and the size of the memory pools to be occupied, and the computing chip information is stored in the target memory pool.

[0009] According to another aspect of the present invention, a memory management device is provided, wherein the device comprises:

[0010] An information determination module, used to determine the trajectory point information and computing chip information of the molecular dynamics calculation task, and match the target memory pool according to the trajectory point information;

[0011] A memory determination module, used for determining the number of memory pools and the size of the memory pools to be occupied according to the track point information and the computing chip information when the target memory pool fails to match;

[0012] A memory pool construction module is used to construct a target memory pool according to the number of memory pools and the size of the memory pools to be occupied, and store the computing chip information in the target memory pool.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the memory management method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the memory management method described in any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention determines the trajectory point information and computing chip information of the molecular dynamics calculation task, matches the target memory pool according to the trajectory point information, and when the target memory pool fails to match, determines the number of memory pools and the size of the memory pool to be occupied according to the trajectory point information and the computing chip information, builds the target memory pool according to the number of memory pools and the size of the memory pool to be occupied, and stores the computing chip information in the target memory pool to achieve reasonable allocation of memory; at the same time, controls the number of memory pools according to the number of calculation trajectory points, and controls the size of the memory pool according to the amount of data that needs to be saved for each trajectory point, thereby improving the utilization rate of the memory, reducing the number of times the program applies to build the memory pool, and facilitating the determination of the storage of the computing chip information of the molecular dynamics calculation task.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a flowchart of a memory management method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 is a flowchart of a memory management method provided according to Embodiment 2 of the present invention;

[0023] Figure 3 is a flowchart of a memory management method provided according to Embodiment 3 of the present invention;

[0024] Figure 4 This is a structural example diagram of a jump table provided according to Embodiment 3 of the present invention;

[0025] Figure 5 is a structural example diagram of another skip table provided according to the third embodiment of the present invention;

[0026] Figure 6 is a structural diagram of a memory management device provided according to a fourth embodiment of the present invention;

[0027] Figure 7 It is a structural schematic diagram of an electronic device that implements the memory management method of an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Embodiment 1

[0031] Figure 1 1 is a flowchart of a memory management method provided according to Embodiment 1 of the present invention. This embodiment is applicable to the case of allocating a memory pool. The method can be executed by a memory management device. The memory management device can be implemented in the form of hardware and / or software. The memory management device can be configured in an electronic device. Figure 1 As shown, the method includes:

[0032] S110, determining the trajectory point information and computing chip information of the molecular dynamics calculation task, and matching the target memory pool according to the trajectory point information.

[0033] Among them, the molecular dynamics calculation task refers to a calculation task that simulates the evolution of a molecular system over time. As the calculation task proceeds, the positions of each molecule continue to change. Through the specified round of calculations, a trajectory point can be generated. In the actual operation process, the specified rounds can be pre-set. For example, the specified rounds can include but are not limited to 400,000 rounds, 500,000 rounds, etc. For a molecular dynamics calculation task, multiple trajectory points can be included, and each trajectory point can be calculated by one or more computing chips. Trajectory point information refers to information associated with trajectory points. For example, trajectory point information can include the number of trajectory points of molecular dynamics calculation tasks, trajectory point identification information, and calculation task identification information of molecular dynamics calculation tasks. Computing chip information refers to information associated with computing chips. For example, computing chip information can include the number of computing chips belonging to the same trajectory point, the calculation results of the computing chips, chip identification information, etc. Among them, the calculation results of the computing chips can also include the start round, the end round, the calculation data path, etc. The target memory pool refers to the memory area that stores the computing chip information. Generally speaking, the target memory pool corresponds to the track point one by one. Accordingly, each target memory pool can store multiple computing chip information, and the number of target memory pools can be multiple. The target memory pool can be constructed based on the track point information and the computing chip information. The corresponding target memory pool can be matched according to the track point information. When the target memory pool fails to match, the target memory pool corresponding to the track point can be constructed according to the track point information and the computing chip information.

[0034] In an embodiment, the number of trajectory points of a molecular dynamics calculation task can be determined, the calculation task identification information of the molecular dynamics calculation task and the trajectory point identification information of each trajectory point can be determined, and the number of trajectory points, the trajectory point identification information and the calculation task identification information can be used as the trajectory point information. Among them, the calculation task identification information can include but is not limited to the calculation task identifier (Identifier, ID); the trajectory point identification information can include the trajectory point ID. Then determine the computing chip corresponding to each trajectory point, determine the identification information of the computing chip, use the number of computing chips corresponding to each trajectory point as the total number of computing chips, determine the calculation result of each computing chip, and use the sum of the calculation results of the computing chip corresponding to each trajectory point as the chip data volume, and use the chip data volume, the calculation result of the computing chip, the chip identification information and the total number of computing chips as the computing chip information. In the actual operation process, each computing chip identification information can be pre-set randomly, or it can be set based on the associated setting of the belonging trajectory point. In an embodiment, the computing chip identification information can be set in sequence according to the corresponding trajectory point identification information. Exemplarily, when the trajectory point ID100 corresponds to 3 computing chips, the computing chip identification information can be ID100, ID101 and ID102 respectively.

[0035] After determining the trajectory point information and computing chip information, the target memory pool can be matched according to the trajectory point information. In the actual operation process, the affiliation of the target memory pool can be stored by a jump table. It is possible to first match whether there is a memory pool associated with the computing task identification information according to the computing task identification information. If there is a match, the corresponding memory pool is matched in the memory pool matched to the computing task identification information according to the trajectory point identification information as the target memory pool. In the actual operation process, when a memory pool is created in advance according to the trajectory point information and computing chip information of the molecular dynamics calculation task, the corresponding memory pool can be matched.

[0036] S120: When the target memory pool fails to match, the number of memory pools and the size of the memory pools to be occupied are determined according to the track point information and the computing chip information.

[0037] The number of memory pools refers to the number of memory pools that need to be built. Generally speaking, each track point can correspond to a memory pool, and the number of memory pools can be the same as the number of track points. The size of the memory pool to be occupied can be understood as the size of the memory space that the memory pool is expected to occupy. The size of the memory pool to be occupied can be related to the amount of chip data in the computing chip information. The larger the chip data volume, the larger the size of the memory pool to be occupied.

[0038] In an embodiment, if the target memory pool fails to match, the number of track points in the track point information is determined, and the number of track points is used as the number of memory pools. The chip data volume in the calculation chip information is then determined, and the chip data volume is used as the memory pool to be occupied.

[0039] S130. Build a target memory pool according to the number of memory pools and the size of the memory pools to be occupied, and store the computing chip information in the target memory pool.

[0040] In an embodiment, the memory pool or memory fragment can be determined according to the size of the memory pool to be occupied, a target memory pool of the number of memory pools can be constructed, and the computing chip information can be stored in the target memory pool. In the actual operation process, the pre-set memory pool can be extracted first to match whether there is a memory pool of the size to be occupied by the memory pool. If it exists, the memory pool of the size to be occupied by the memory pool is used as the target memory pool; if it does not exist, the memory fragments are matched according to the size to be occupied by the memory pool, and the memory fragments are constructed into a memory pool as the target memory pool. When the number of memory fragments is multiple, a pointer relationship between the memory fragments can be constructed. For example, the end address of the memory pool of the previous memory fragment can be pointed to the start address of the next memory pool to complete the construction of the target memory pool. At the same time, the computing task identification information is used as the primary index of the target memory pool, and the trajectory point identification information is used as the secondary index to construct the association relationship between the target memory pool and the molecular dynamics computing task and the trajectory point, so as to facilitate the search for the target memory pool corresponding to the trajectory point according to the computing task identification information and the trajectory point identification information. The calculation result of the computing chip corresponding to the computing chip information is uploaded to the target memory pool, and the chip identification information is used as the identification information of the calculation result, so as to confirm that the computing chip information corresponding to each chip identification information has completed storage. In one embodiment, after uploading the calculation result of the computing chip, the remaining memory size and the used memory size of the target memory pool can be determined, and the remaining memory size and the used memory size can be saved.

[0041] In actual operation, the memory pool can be stored in the preset memory pool linked list, and the constructed target memory pool can be added to the preset memory pool linked list. At the same time, since the ownership of the target memory pool can be stored by the skip list, the constructed target memory pool can be inserted into the skip list as a skip list node.

[0042] The embodiment of the present invention determines the trajectory point information and computing chip information of the molecular dynamics calculation task, matches the target memory pool according to the trajectory point information, and when the target memory pool fails to match, determines the number of memory pools and the size of the memory pool to be occupied according to the trajectory point information and the computing chip information, builds the target memory pool according to the number of memory pools and the size of the memory pool to be occupied, and stores the computing chip information in the target memory pool, thereby realizing reasonable allocation of memory; at the same time, controls the number of memory pools according to the number of calculation trajectory points, controls the size of the memory pool according to the amount of data that needs to be saved for each trajectory point, improves the utilization rate of the memory, reduces the number of times the program applies to build the memory pool, and facilitates the determination of the storage of the computing chip information of the molecular dynamics calculation task.

[0043] In one embodiment, after determining the trajectory point information and computing chip information of the molecular dynamics computing task and matching the target memory pool according to the trajectory point information, the method further includes:

[0044] When the target memory pool is successfully matched, the preset processing identifier of the trajectory point is extracted; wherein the preset processing identifier is used to indicate whether the computing chip information corresponding to the trajectory point has been stored;

[0045] When it is determined that the preset processing mark is not completed, matching is performed in the target memory pool according to the chip identification information in the calculation chip information;

[0046] If the computing chip information is not matched successfully, the calculation result of the computing chip corresponding to the chip identification information is uploaded to the target memory pool, and the chip identification information is used as the identification information of the calculation result until all the computing chip information is matched successfully, and the preset processing flag is updated to be completed.

[0047] The preset processing flag is used to indicate whether the computing chip information corresponding to the track point has been stored. Each track point can be pre-set with a preset processing flag. If the computing chip information corresponding to the track point is not uploaded successfully, the preset processing flag is set to uncompleted. When the computing chip information corresponding to the track point is uploaded successfully, the preset processing flag is updated to completed. In the actual operation process, the preset processing flag can be set to 1 for completion and 0 for incomplete.

[0048] In an embodiment, when determining the trajectory point information and computing chip information of a molecular dynamics calculation task, if the target memory pool is successfully matched according to the trajectory point information, the preset processing identifier of the trajectory point can be extracted. When the preset processing identifier is not completed, the chip identification information can be matched in the memory pool to determine the unstored chip information. In the case where the computing chip information is not successfully matched, the calculation result of the computing chip corresponding to the chip identification information can be uploaded to the target memory pool, and the chip identification information can be used as the identification information of the calculation result until all the computing chip information is successfully matched and the preset processing identifier is updated to be completed. Ensure that all the computing chip information corresponding to the trajectory point is uploaded and stored.

[0049] Embodiment 2

[0050] Figure 2 1 is a flowchart of a memory management method provided according to Embodiment 2 of the present invention. This embodiment is a further description of a memory management method based on the above embodiment. Figure 2 As shown, the method includes:

[0051] S201, determining the number of trajectory points, trajectory point identification information and calculation task identification information of the molecular dynamics calculation task, and using the number of trajectory points, trajectory point identification information and calculation task identification information as trajectory point information.

[0052] The number of trajectory points can be understood as the number of trajectory points generated for the molecular dynamics calculation task; the trajectory point identification information is identifiable information used to distinguish the trajectory points, and the trajectory point representation information can include the trajectory point ID; the calculation task identification information is identifiable information used to distinguish the dynamics calculation task, and the calculation task identification information can include the molecular dynamics calculation task ID. Generally speaking, the calculation task identification information and the trajectory point identification information can be composed of numbers, letters or strings.

[0053] In an embodiment, the number of trajectory points included in the molecular dynamics calculation task can be determined, and the calculation task identification information of the dynamics calculation task and the identification information of each trajectory point can be determined, and the number of trajectory points, trajectory point identification information and calculation task identification information are used as trajectory point information.

[0054] S202: Determine the trajectory points to which the computing chips belong, divide the computing chips into at least one chip set according to the trajectory points to which they belong, and determine chip identification information of each computing chip in the chip set.

[0055] In an embodiment, each trajectory point may correspond to multiple computing information, and the trajectory point to which each computing chip belongs may be determined. According to the ownership of the trajectory point, the computing chips belonging to the same trajectory point are divided into the same set as a chip set, and the chip identification information of each computing chip in the chip set is determined. In the actual operation process, the chip identification information of each computing chip may be related to the trajectory point to which it belongs. Exemplarily, the computing chip identification may be set according to the trajectory point identification.

[0056] S203: Determine the number of computing chips in the chip set as the total number of computing chips, and determine the sum of the computing results corresponding to the computing chips in the chip set in each set as the chip data amount.

[0057] In an embodiment, after the chip sets are divided, the number of computing chips in each computing chip set can be determined as the total number of computing chips, the computing result of each computing chip can be determined, and the sum of the computing results in the same chip set can be used as the chip data volume.

[0058] S204: Use the chip data volume, the calculation result of the calculation chip, the chip identification information and the total number of calculation chips as the calculation chip information.

[0059] In an embodiment, after the chip data volume, the calculation results of the computing chip, the chip identification information and the total number of computing chips are determined, the chip data volume, the calculation results of the computing chip, the chip identification information and the total number of computing chips can be used as computing chip information.

[0060] S205: Match the target memory pool according to the track point information.

[0061] S206: When the target memory pool fails to match, determine the number of track points in the track point information, and use the number of track points as the number of memory pools.

[0062] In an embodiment, the number of track points in the track point information may be extracted, and the number of track points may be used as the number of memory pools.

[0063] S207, determining the chip data volume in the calculation chip information, and using the chip data volume as the size to be occupied by the memory pool.

[0064] In an embodiment, the chip data volume in the chip information may be extracted and calculated, and the chip data volume may be used as the size to be occupied by the memory pool.

[0065] S208, extracting a preset memory pool linked list, traversing the preset memory pool linked list according to the size of each memory pool to be occupied, and determining a memory pool node of the size of the memory pool to be occupied as a target memory pool.

[0066] The preset memory pool linked list is composed of memory pool nodes and jump pointers. The preset memory pool linked list refers to a data management method that organizes memory blocks in a memory pool into a linked list structure. The preset memory pool linked list can be pre-set starting from the starting address of the memory pool. The memory pool is divided into multiple memory blocks, which are connected in a linked list manner. Each memory block serves as a new memory pool as a memory pool node in the memory pool linked list.

[0067] In an embodiment, a preset preset memory pool linked list may be extracted, and memory pools in the preset memory pool linked list may be matched in sequence according to the size of the memory pool to be occupied. Generally speaking, the match may be performed from the first memory pool node in the preset memory pool linked list, and if the match fails, the match may be performed by jumping the pointer to the next memory pool until a memory pool node of the size of the memory pool to be occupied is matched, and the memory pool node of the size of the memory pool to be occupied is used as the target memory pool.

[0068] S209. Determine index information of the target memory pool according to the track point identification information and the computing task identification information in the track point information; wherein the index information includes a primary index and a secondary index.

[0069] Among them, the primary index is the basic index in the index structure, which is usually an index built based on the primary key in the table; the secondary index is an index built based on the non-primary key columns in the table. It is an additional index created on the basis of the primary index to meet specific query requirements. In an embodiment, the trajectory point identification information and the computing task identification information in the trajectory point information can be used as index information of the target memory pool. In the actual operation process, the computing task identification information can be used as the primary index of the target memory pool, and the trajectory point identification information can be used as the secondary index of the target memory pool, so as to facilitate the subsequent query and identification of the target memory table.

[0070] S210: When the memory pool matching fails, determine the target memory fragment according to the size of the memory to be occupied, and construct the target memory pool according to the target memory fragment and the track point information.

[0071] Among them, memory fragmentation can include internal fragmentation and external fragmentation. Internal fragmentation refers to the unused free space generated inside the memory block during the memory allocation process because the allocated memory block is larger than the actual required memory space. The reason for this is that the system divides the memory into fixed-size blocks (partitions). When a process needs to allocate memory, the system will allocate a sufficiently large partition for it. If the actual memory demand of the process is less than the partition size, the remaining space forms internal fragmentation. Since the allocated memory block is larger than the actual demand, the unused part cannot be used by other processes, resulting in a decrease in memory utilization. Internal fragmentation will not significantly affect the memory allocation speed, but frequent memory allocation and recycling operations will still increase system overhead, resulting in memory waste that may lead to memory exhaustion and have a great impact on system stability. External fragmentation refers to the fact that during the memory allocation and release process, due to the inconsistent allocation and release order of memory blocks, a large number of small, non-continuous free memory blocks are scattered throughout the memory space, so that although the total available memory space is sufficient, it is impossible to find continuous memory blocks to meet the needs of new processes. The reason for this is that when a process dynamically requests and releases memory, the free blocks in the memory may be divided into many small blocks. These small blocks are separated by allocated memory blocks and cannot be merged into a large continuous block. Although there is enough free memory in the system, these free blocks are non-contiguous and cannot meet the process's demand for large continuous memory blocks, resulting in a waste of memory resources. When a process requests a large continuous memory block, the existence of external fragmentation may cause memory allocation failure, affecting system performance and the normal operation of applications. In a multitasking system, external fragmentation will affect the memory allocation requirements of multiple processes and reduce the system's multitasking capabilities.

[0072] In an embodiment, when the memory pool matching fails, the target memory fragments may be determined according to the size of the memory to be occupied, and the target memory pool may be constructed by the target memory fragments and the track point information.

[0073] In one embodiment, when the memory pool matching fails, the target memory fragment is determined according to the size of the memory to be occupied, and the target memory pool is constructed according to the target memory fragment and the track point information, including:

[0074] Determine the fragment size of the memory fragments, extract the memory fragments according to the fragment size, until the sum of the fragment sizes reaches the memory size to be occupied, and use the extracted memory fragments as target fragments;

[0075] A pointer relationship of the target memory fragment is constructed to generate a target memory pool, and index information of the target memory pool is determined according to the track point identification information and the computing task identification information in the track point information.

[0076] In an embodiment, when it is determined that the memory pool match fails, the fragment size of the memory fragment can be determined, and the corresponding memory fragment can be extracted according to the size of the memory to be occupied, and the extracted memory fragment is used as the target fragment, and a pointer relationship of the target memory fragment is constructed to generate a target memory pool, and the computing task identification information is used as the primary index of the target memory pool, and the track point identification information is used as the secondary index of the target memory pool. In the actual operation process, since the fragment sizes of the memory fragments are different, the memory fragments can be extracted in sequence until the sum of the fragment sizes reaches the size of the memory to be occupied.

[0077] S211. Upload the calculation result of the calculation chip corresponding to the calculation chip information to the target memory pool, and use the chip identification information as the identification information of the calculation result.

[0078] In an embodiment, the calculation result of the computing chip corresponding to the computing chip information can be saved to the target memory pool, and the chip identification information can be used as the identification information of the calculation result, so as to determine whether the corresponding calculation result has been stored according to the chip identification information.

[0079] In an embodiment of the present invention, by determining the number of trajectory points of a molecular dynamics calculation task, trajectory point identification information, and calculation task identification information of the molecular dynamics calculation task, the number of trajectory points, trajectory point identification information, and calculation task identification information are used as trajectory point information, the trajectory points to which a calculation chip belongs are determined, the calculation chips are divided into at least one chip set according to the trajectory points to which they belong, the chip identification information of each calculation chip in the chip set is determined, the number of calculation chips in the chip set is determined as the total number of calculation chips, the sum of the calculation results corresponding to the calculation chips in the chip set in each set is determined as the chip data amount, the chip data amount, the calculation results of the calculation chip, the chip identification information, and the total number of calculation chips are used as the calculation chip information, and the calculation chip information memory trajectory point information is realized. The invention can accurately determine the information; when the target memory pool fails to match, determine the number of track points in the track point information, use the number of track points as the number of memory pools, determine the chip data volume in the computing chip information, use the chip data volume as the size to be occupied by the memory pool, extract the preset memory pool linked list, traverse the preset memory pool linked list according to the size to be occupied by each memory pool, determine the memory pool node of the size to be occupied by the memory pool as the target memory pool, determine the index information of the target memory pool according to the track point identification information and the computing task identification information in the track point information, determine the target memory fragment according to the size to be occupied memory when the memory pool fails to match, build the target memory pool according to the target memory fragment and the track point information, and realize determining the target memory pool according to the priority, so as to avoid the waste of memory pool resources.

[0080] In one embodiment, a memory management method further includes:

[0081] Determine the number of traversals of each memory pool node in the preset memory pool linked list;

[0082] Delete memory pool nodes whose traversal times are greater than or equal to the preset traversal times.

[0083] The number of traversals refers to the number of matches in the memory pool.

[0084] In an embodiment, since it is necessary to extract a preset memory pool linked list to construct a target memory pool according to the number of memory pools and the size of the memory pool to be occupied, the preset memory pool linked list is traversed according to the size of each memory pool to be occupied, and the memory pool node of the size of the memory pool to be occupied is determined as the target memory pool, and the number of traversals of each memory pool is greater than or equal to the preset number of traversals, the manuscript memory pool node is deleted. In the actual operation process, it can be determined whether the memory pool node has index information. If it does, an exception is reported and the memory pool node information is recorded; if it does not exist, the memory pool node is deleted and the memory is released.

[0085] Embodiment 3

[0086] Figure 3 This is a flow chart of a memory management method provided according to Embodiment 3 of the present invention. This embodiment takes the initialization of a jump table and the storage of computing chip information according to the table adjustment as an example to further illustrate a memory management method.

[0087] In molecular dynamics calculations, multiple molecular dynamics calculation tasks can be processed in parallel. Each molecular dynamics calculation task contains several trajectory points, and each trajectory point has multiple computing chips for calculation. The calculation process is divided into multiple rounds. After a specified round is completed, each computing chip generates a calculation trajectory point data. The trajectory point data contains the following information: calculation start round, end round, calculation data path, total number of computing chips, computing chip ID, trajectory point ID and other information.

[0088] In one embodiment, Figure 4 1 is a structural example diagram of a skip list provided according to Embodiment 3 of the present invention. The method of initializing the skip list is as follows: illustratively, a skip list (Skip List) can be initialized by an initialization module.

[0089] Step 1.1: Initialize the first-level index of the skip list (molecular dynamics calculation task head). The first-level index is used to quickly locate the calculation task and the trajectory points it contains. Each first-level index node includes a pointer to the next task node (next) and a trajectory point jump pointer to facilitate efficient search.

[0090] Step 1.2: Initialize the secondary index of the jump table (track point head). The secondary index is used to manage and track the information of each track point. Each secondary index node includes the memory pool status and chip calculation track point data. Each track point node contains detailed information including the calculation track point ID, memory pool pointer, memory pool free memory (free), memory pool used memory, number of participating calculation chips, number of stored calculation chips, post-processing mark (preset processing mark), chip calculation track point data storage list head jump pointer, memory pool list jump pointer, which is used to efficiently access and manage calculation data.

[0091] Step 1.3: Initialize the data (chip data head) of the original linked list (chip data linked list) of the jump list. The chip data node is used to store the calculation data of each chip. The chip data node contains information such as the calculation start round, end round, calculation data path, total number of calculation chips, calculation chip ID, and track point ID. Each node corresponds to the calculation result of a chip, which is convenient for subsequent processing. Each chip data node can be considered as a calculation chip.

[0092] Step 1.4: Initialize the jump list (preset memory pool linked list) memory pool head. The memory pool linked list node contains the memory pool pointer, memory pool start address, memory pool end address, calculation task ID, memory pool remaining size, memory pool used size, calculation trajectory point ID, number of queries (number of traversals), etc.

[0093] like Figure 3 As shown, step 2.1: when a new chip calculation data message (the calculation result of the calculation chip) is received, the calculation task ID of the molecular dynamics calculation task can be matched. If there is a match, go to step 2.2. If there is no match, build the target memory pool based on the memory pool application processing function.

[0094] Step 2.2: Match the track point ID. If there is a match, go to step 2.3. If there is no match, build the target memory pool based on the memory pool application processing function.

[0095] Step 2.3: Check whether the post-processing flag (preset processing flag) is 0. If yes, proceed to step 2.4. If not, determine that the second round of data calculation message has been completed, do not process this message and report the duplicate.

[0096] Step 2.4: Match the computing chip ID. If there is a match, it is determined that the computing data message of this computing chip has been uploaded, and the message is not processed and reported as duplicate. If there is no match, the computing data message is uploaded to the target memory pool of the corresponding trajectory point and the data is stored in the jump table.

[0097] In one embodiment, Figure 5FIG. 2 is a diagram showing another example of a jump table structure according to the third embodiment of the present invention. Figure 5 As shown in the figure, there are three molecular dynamics calculation tasks as an example, and the calculation task IDs are molecular dynamics calculation task ID1, molecular dynamics calculation task ID2 and molecular dynamics calculation task ID3. Molecular dynamics calculation task ID1 contains trajectory point ID1 and trajectory point ID2, molecular dynamics calculation task ID2 contains trajectory point ID100 and trajectory point ID300, and molecular dynamics calculation task ID3 contains trajectory point ID456. Each trajectory point corresponds to a memory pool. The chip data contained in trajectory point ID1 includes ID1, ID2, ID3 and ID4; the chip data contained in trajectory point ID2 includes ID1, ID2 and ID3; the chip data contained in trajectory point ID100 includes ID100, ID101 and ID102; the chip data contained in trajectory point ID300 includes ID300, ID301, ID303 and ID304; the chip data contained in trajectory point ID456 includes ID456, ID457, ID458, ID459, ID460 and ID461. The memory pool linked lists can access each other through the memory pool pointer; the trajectory point can access the corresponding chip data through the linked list header jump pointer, and access the corresponding memory pool through the memory pool linked list jump pointer. When the computing chip is added to the jump list, the first-level index of the jump list is the linked list of the computing task ID, and the second-level index of the jump list is the linked list of the molecular dynamics calculation trajectory point ID. According to the first-level index, the chip original data linked list and the memory pool linked list can be queried. In an embodiment, the chip data content can be filled into the second-level index, the first-level index and the preset chip linked list.

[0098] In one embodiment, when the number of computing chips stored in the linked list node of the trajectory point ID in the secondary index molecular dynamics calculation task is equal to the total number of computing chips, the calculation data will be sent to another program through a message for post-calculation processing. When the other program is completed, the linked list node of the trajectory point ID of the secondary index molecular dynamics calculation task is updated and the post-processing flag is 1, and a unified jump list node deletion function is called.

[0099] In one embodiment, when all calculations are completed, there is only one linked list head in the linked list whose primary index in the jump list is the calculation task ID of the molecular dynamics calculation task, and there is only one linked list head in the linked list whose secondary index in the jump list is the trajectory point ID of the molecular dynamics calculation task. There are N memory pools in the memory pool linked list pointed to by the linked list node whose secondary index in the jump list is the trajectory point ID, all of which are in the initialized unused state. A unified memory pool destruction processing function can be called to destroy the unused memory pools.

[0100] In one embodiment, the memory pool application processing function may include an initial application and a non-initial application.

[0101] In the case of the first application, the total number of computing chips, the calculation results of the computing chips, the calculation task ID, and the calculation trajectory point ID can be determined. The size of the memory pool to be occupied and the object of use are determined according to the number of trajectory point IDs and the calculation results of the computing chips. Traverse the preset memory pool linked list to match whether there is a memory pool with a corresponding size and the calculation trajectory point ID in the calculation task ID is the initialization value. If a matching memory pool exists, it is used directly. If no matching memory pool exists, a new memory pool is applied and added to the linked list. At the same time, the memory pool pointer is returned and saved in the corresponding trajectory point ID node in the secondary index molecular dynamics trajectory point linked list. The memory pool pointer is saved in the trajectory point ID node. The free memory size of the memory pool is the memory pool size, and the used memory of the memory pool is 0.

[0102] In the case of non-first application, you can directly apply for memory according to the memory pool pointer saved in the secondary index and update the free memory size of the memory pool and the used memory size of the memory pool without traversing the preset memory pool linked list.

[0103] In one embodiment, it can be set that after the memory pool node in the preset memory pool linked list is traversed a number of times greater than or equal to the preset traversal number, the memory pool destruction processing function is called to delete the memory pool to avoid memory idleness.

[0104] Among them, the memory pool destruction processing function can be used to destroy all or specify the memory pool.

[0105] Among them, all destruction means traversing the preset memory pool linked list to query whether the calculation task ID and calculation trajectory point ID in each memory pool node are the initial values. If they are the initial values ​​(that is, the target memory pool does not store the data of the molecular dynamics calculation task), delete the node and release the memory. If it is not the initial value, report the exception and record the current node information, and continue to traverse until all nodes in the linked list are processed. Specify memory pool destruction means traversing the memory pool linked list according to the incoming calculation task ID and trajectory point ID. After matching the specified memory pool node, delete the node and release the memory.

[0106] In the embodiment of the present invention, a jump table is used to replace a single memory pool, the number of memory pools is controlled according to the number of calculated trajectory points, and the size of the memory pool is controlled according to the amount of data that needs to be saved for each trajectory point data. This method improves the utilization rate of memory, reduces the number of times the program applies for memory, reduces the frequency of memory release, solves the problem of memory fragmentation, is more suitable for large-scale, high-frequency memory operations, and improves the reliability of molecular dynamics calculations.

[0107] Embodiment 4

[0108] Figure 6is a schematic diagram of the structure of a memory management device provided according to Embodiment 4 of the present invention;. Figure 6 As shown, the device includes: an information determination module 61, a memory determination module 62 and a memory pool construction module 63.

[0109] The information determination module 61 is used to determine the trajectory point information and computing chip information of the molecular dynamics calculation task, and match the target memory pool according to the trajectory point information;

[0110] A memory determination module 62, used to determine the number of memory pools and the size of the memory pools to be occupied according to the track point information and the computing chip information when the target memory pool fails to match;

[0111] The memory pool construction module 63 is used to construct a target memory pool according to the number of memory pools and the size of the memory pools to be occupied, and store the computing chip information in the target memory pool.

[0112] In an embodiment of the present invention, the trajectory point information and computing chip information of a molecular dynamics calculation task are determined by an information determination module, and a target memory pool is matched according to the trajectory point information. When the target memory pool fails to match, the memory determination module determines the number of memory pools and the size of the memory pool to be occupied according to the trajectory point information and the computing chip information. The memory pool construction module constructs the target memory pool according to the number of memory pools and the size of the memory pool to be occupied, and stores the computing chip information in the target memory pool, thereby realizing reasonable allocation of memory. At the same time, the number of memory pools is controlled according to the number of calculation trajectory points, and the size of the memory pool is controlled according to the amount of data that needs to be saved for each trajectory point, thereby improving memory utilization, reducing the number of times the program applies to construct a memory pool, and facilitating the storage of computing chip information for determining the molecular dynamics calculation task.

[0113] In one embodiment, the information determination module 61 includes:

[0114] A trajectory point determination unit, used to determine the number of trajectory points of a molecular dynamics calculation task, trajectory point identification information and calculation task identification information of the molecular dynamics calculation task, and use the number of trajectory points, trajectory point identification information and calculation task identification information as trajectory point information;

[0115] A chip determination unit, used to determine the trajectory points to which the computing chips belong, divide the computing chips into at least one chip set according to the trajectory points to which they belong, and determine chip identification information of each computing chip in the chip set;

[0116] A quantity determination unit, used to determine the number of computing chips in the chip set as the total number of computing chips, and determine the sum of the calculation results corresponding to the computing chips in the chip set in each set as the chip data amount;

[0117] The information determination unit is used to use the chip data volume, the calculation result of the calculation chip, the chip identification information and the total number of the calculation chips as the calculation chip information.

[0118] In one embodiment, the memory determination module 62 includes:

[0119] A memory quantity determination unit, used to determine the number of track points in the track point information, and use the number of track points as the number of memory pools;

[0120] The memory size determination unit is used to determine the chip data volume in the calculation chip information and use the chip data volume as the size to be occupied by the memory pool.

[0121] In one embodiment, the memory pool construction module 63 includes:

[0122] A memory pool extraction unit is used to extract a preset memory pool linked list, traverse the preset memory pool linked list according to the size of each memory pool to be occupied, and determine the memory pool node of the memory pool to be occupied as the target memory pool; wherein the preset memory pool linked list is composed of memory pool nodes and jump pointers;

[0123] An index building unit, used to determine index information of a target memory pool according to the track point identification information and the computing task identification information in the track point information; wherein the index information includes a primary index and a secondary index;

[0124] A memory pool construction unit, used for determining the target memory fragment according to the size of the memory to be occupied when the memory pool matching fails, and constructing the target memory pool according to the target memory fragment and the track point information;

[0125] The data storage unit is used to upload the calculation results of the calculation chip corresponding to the calculation chip information to the target memory pool, and use the chip identification information as the identification information of the calculation result.

[0126] In one embodiment, the memory pool construction unit is specifically used to:

[0127] Determine the fragment size of the memory fragments, extract the memory fragments according to the fragment size, until the sum of the fragment sizes reaches the memory size to be occupied, and use the extracted memory fragments as target fragments;

[0128] A pointer relationship of the target memory fragment is constructed to generate a target memory pool, and index information of the target memory pool is determined according to the track point identification information and the computing task identification information in the track point information.

[0129] In one embodiment, the memory management device further includes:

[0130] An information matching module is used to extract a preset processing identifier of the trajectory point when the target memory pool is matched successfully; when the preset processing identifier is determined to be unfinished, the preset processing identifier is matched in the target memory pool according to the chip identifier information in the calculation chip information;

[0131] The identification update module is used to upload the calculation results of the computing chip corresponding to the chip identification information to the target memory pool when the computing chip information is not matched successfully, and use the chip identification information as the identification information of the calculation result until all the computing chip information is matched successfully and the preset processing identification is updated as completed.

[0132] In one embodiment, the memory management device further includes:

[0133] A times determination module is used to determine the times of traversal of each memory pool node in the preset memory pool linked list;

[0134] The node deletion module is used to delete the memory pool nodes whose traversal times are greater than or equal to the preset traversal times.

[0135] The memory management device provided in the embodiment of the present invention can execute the memory management method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0136] Embodiment 5

[0137] Figure 7 : is a schematic diagram of the structure of an electronic device that implements the memory management method of an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0138] like Figure 7As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0139] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0140] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a memory management method.

[0141] In some embodiments, the memory management method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the memory management method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the memory management method in any other appropriate manner (e.g., by means of firmware).

[0142] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0143] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0144] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0145] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0146] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0147] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0148] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0149] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory management method, characterized in that: include: Determine the trajectory point information and computing chip information of the molecular dynamics calculation task, and match the target memory pool according to the trajectory point information; When the target memory pool fails to match, determining the number of memory pools and the size of the memory pools to be occupied according to the track point information and the computing chip information; A target memory pool is constructed according to the number of memory pools and the size of the memory pools to be occupied, and the computing chip information is stored in the target memory pool.

2. The method according to claim 1, characterized in that The step of determining the trajectory point information and computing chip information of the molecular dynamics computing task includes: Determine the number of trajectory points, trajectory point identification information and calculation task identification information of the molecular dynamics calculation task, and use the number of trajectory points, the trajectory point identification information and the calculation task identification information as trajectory point information; Determine the trajectory points to which the computing chips belong, divide the computing chips into at least one chip set according to the trajectory points to which they belong, and determine chip identification information of each computing chip in the chip set; Determine the number of computing chips in the chip set as the total number of computing chips, and determine the sum of the computing results corresponding to the computing chips in the chip set in each set as the chip data amount; The chip data volume, the calculation result of the calculation chip, the chip identification information and the total number of the calculation chips are used as the calculation chip information.

3. The method according to claim 1, characterized in that The determining the number of memory pools and the size of the memory pools to be occupied according to the track point information and the computing chip information includes: Determine the number of track points in the track point information, and use the number of track points as the number of memory pools; The chip data volume in the computing chip information is determined, and the chip data volume is used as the size to be occupied by the memory pool.

4. The method according to claim 1, characterized in that The step of constructing a target memory pool according to the number of memory pools and the size of the memory pools to be occupied, and storing the computing chip information in the target memory pool includes: Extracting a preset memory pool linked list, traversing the preset memory pool linked list according to the size of each memory pool to be occupied, and determining a memory pool node of the size of the memory pool to be occupied as a target memory pool; wherein the preset memory pool linked list is composed of memory pool nodes and jump pointers; Determine the index information of the target memory pool according to the track point identification information and the computing task identification information in the track point information; wherein the index information includes a primary index and a secondary index; In the case where the memory pool fails to match, determining the target memory fragment according to the size of the memory to be occupied, and constructing the target memory pool according to the target memory fragment and the track point information; The calculation result of the calculation chip corresponding to the calculation chip information is uploaded to the target memory pool, and the chip identification information is used as the identification information of the calculation result.

5. The method according to claim 4, characterized in that The step of determining the target memory fragments according to the size of the memory to be occupied, and constructing the target memory pool according to the target memory fragments and the track point information includes: Determine the fragment size of the memory fragments, extract the memory fragments according to the fragment size, until the sum of the fragment sizes reaches the memory size to be occupied, and use the extracted memory fragments as target fragments; A pointer relationship of the target memory fragments is constructed to generate a target memory pool, and index information of the target memory pool is determined according to the track point identification information and the computing task identification information in the track point information.

6. The method according to claim 1, after determining the trajectory point information and computing chip information of the molecular dynamics computing task and matching the target memory pool according to the trajectory point information, further comprises: When the target memory pool is matched successfully, a preset processing identifier of the trajectory point is extracted; Preset processing identifier: When it is determined that the preset processing identifier is not completed, matching is performed in the target memory pool according to the chip identifier information in the computing chip information; In the case that the computing chip information is not matched successfully, the calculation result of the computing chip corresponding to the chip identification information is uploaded to the target memory pool, and the chip identification information is used as the identification information of the calculation result, until all the computing chip information is matched successfully, and the preset processing flag is updated to be completed.

7. The method according to claim 1, characterized in that Also includes: Determine the number of traversals of each memory pool node in the preset memory pool linked list; Delete the memory pool nodes whose traversal times are greater than or equal to the preset traversal times.

8. A memory management device, characterized in that: include: An information determination module, used to determine the trajectory point information and computing chip information of the molecular dynamics calculation task, and match the target memory pool according to the trajectory point information; A memory determination module, used for determining the number of memory pools and the size of the memory pools to be occupied according to the track point information and the computing chip information when the target memory pool fails to match; A memory pool construction module is used to construct a target memory pool according to the number of memory pools and the size of the memory pools to be occupied, and store the computing chip information in the target memory pool.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the memory management method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the memory management method according to any one of claims 1 to 7 when executed.

Images