Art operation detection for non-uniform erase of non-volatile memory

Abstract

The title of the invention is "abort operation detection for non-uniform erase of non-volatile memory". An apparatus is disclosed that includes one or more control circuits configured to be connected to a plurality of non-volatile memory cells. The one or more control circuits are configured to detect a first boundary between a written portion and an unwritten portion of the open block, and check a second boundary between the written portion and the unwritten portion of the open block in response to detecting the first boundary in order to determine whether the open block is subjected to a non-uniform erase operation.

Description

[0001] Priority declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 509,134, filed by Xu et al. on June 20, 2023, entitled “ABORTED OPERATION DETECTION FOR NONVOLATILE MEMORY WITH NON-UNIFORM ERASE,” which is incorporated herein by reference in its entirety. Background Art

[0003] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory), electrically erasable programmable read-only memory (EEPROM), and the like. Some memory cells store information by storing charge in a charge storage area. Other memory cells use other technologies (such as, through the resistance of the memory cell) to store information. Some memories use two data states (single-level cell or SLC) to store one bit per cell, while other memories use more than two data states (multi-level cell or MLC, which can store two bits per cell) to store more than one bit per cell. Sixteen data states (quadruple-level cell or QLC) can be used to store four bits per cell.

[0004] When the memory system is deployed in or connected to an electronic device (host), the memory system can be used to store data and read data. For example, data can be stored in response to a program (write) command. Data can be read in response to a read command that specifies the data to be read. Data can be erased in response to an erase command. In some cases, when the memory system loses power, an operation (e.g., write or erase) may be in progress. When power is restored, it may be difficult to determine the state of the memory system (e.g., some data may be partially written or partially erased). BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Like numbered elements refer to common parts in different drawings.

[0006] Figure 1A is a block diagram of one embodiment of a memory system connected to a host.

[0007] Figure 1Bis a block diagram of one embodiment of a front end processor circuit. In some embodiments, the front end processor circuit is part of a controller.

[0008] Figure 1C A block diagram of one embodiment of a back end processor circuit is shown. In some embodiments, the back end processor circuit is part of a controller.

[0009] Figure 1D A block diagram of one embodiment of a memory package is shown.

[0010] Figure 2A is a functional block diagram of one embodiment of a memory die.

[0011] Figure 2B is a functional block diagram of one embodiment of an integrated memory component.

[0012] Figure 3 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0013] Figure 4A is a block diagram of a memory structure with two planes.

[0014] Figure 4B Depicted is a top view of a portion of a block of memory cells.

[0015] Figure 4C A cross-sectional view of a portion of a block of memory cells is depicted.

[0016] Figure 5 An example of a sense block is shown.

[0017] Figure 6 An example of programming multiple data states of a non-volatile memory cell is shown.

[0018] Figure 7 An example of erasing a nonvolatile memory cell is shown.

[0019] FIG. 8A to FIG. 8F An example of an erasure scheme is shown.

[0020] 9A to 9D Examples of different conditions of a block are shown.

[0021] FIG. 10A to FIG. 10B An example of a binary search for boundaries in a block is shown.

[0022] FIG. 11A to FIG. 11B An example of determining the status of a block is shown.

[0023] FIG. 12A to FIG. 12B An example of determining the status of a block is shown.

[0024] Fig.13 An example of a method including checking for a second boundary in a block is shown.

[0025] Fig.14 An example of a method including checking for a second boundary in a block is shown.

[0026] Fig.15 An example of a method including determining whether to erase a test word line is shown. DETAILED DESCRIPTION

[0027] Disclosed herein are techniques for enabling a memory system to efficiently determine the status of a block (e.g., after an unexpected power loss when the status of the block may be unknown). Some memory systems use non-uniform erasure, such as erasing memory cells of odd and even word lines separately (odd-even erasure), which may result in a pattern of written and unwritten portions in a block. When a block does not contain valid data (e.g., is an erase abort block), such a pattern may result in the misidentification of the block as partially written with valid data (e.g., misidentified as a write abort block). Misidentification may result in improper handling of such blocks (e.g., attempting to copy data from a block that does not contain valid data), which may affect the operation of the memory system.

[0028] A scheme for accurately and efficiently determining the condition of a block includes detecting a first boundary between a written portion and an unwritten portion (e.g., finding at least one written word line and at least one unwritten word line). In response to detecting the first boundary, a second boundary of the block may be checked (e.g., an unwritten portion below a written word line in programming order). A test word line (or multiple word lines) may be selected and checked to see if it is erased. The selection of the test word line may depend on the non-uniform erase scheme used. For odd-even erase, a word line adjacent to a written word line may be checked (e.g., a test word line may be offset by one word line from a written word line). For other non-uniform erase schemes, the test word line may be selected differently. If the test word line is erased, it indicates that the block is partially erased by non-uniform erase (erase-stop block), and the block may be processed accordingly (e.g., a block ready for use without copying data or maintaining data in the block). If the test word line is not erased, it indicates that the block is partially written and includes valid data (write erase abort), and the block can be processed accordingly (eg, copy the data or continue programming and maintain the data in the block).

[0029] Figure 1A1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. The memory system 100 can implement the techniques proposed herein. Many different types of memory systems can be used with the techniques proposed herein. One exemplary memory system is a solid state drive (“SSD”); however, other types of memory systems can also be used. The memory system 100 includes a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM) 106. The controller 102 includes a front end processor circuit (FEP) 110 and one or more back end processor circuits (BEP) 112. In one embodiment, the FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. The ASIC for each of the BEP circuit 112 and the FEP circuit 110 is implemented on the same semiconductor, so that the controller 102 is manufactured as a system on a chip (“SoC”). The FEP 110 and the BEP 112 each include their own processor. In one embodiment, the FEP circuit 110 and the BEP 112 operate in a master-slave configuration, where the FEP circuit 110 is a master device and each BEP 112 is a slave device. For example, the FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logical to physical address translation, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuit 112 manages memory operations in the memory package / die according to the request of the FEP circuit 110. For example, the BEP circuit 112 can perform read, erase, and program processes. In addition, the BEP circuit 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), control the switching mode interface to the memory package, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages. The controller 102 is an example of a control circuit.

[0030] In one embodiment, non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Therefore, controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die in memory package 14 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, memory packages may include other types of memory.

[0031] Controller 102 communicates with host 120 via interface 130, which implements NVM Express (NVMe) on PCI Express (PCie). In order to work with memory system 100, host 120 includes host processor 122 connected to bus 128, host memory 124 and PCIe interface 126. Host memory 124 is the physical memory of the host and can be DRAM, SRAM, non-volatile memory or another type of storage device. Host 120 is external to memory system 100 and separate from the memory system. In one embodiment, memory system 100 is embedded in host 120.

[0032] Figure 1B is a block diagram of one embodiment of the FEP circuit 110 . Figure 1B A PCIe interface 150 is shown that communicates with the host 120, and a host processor 152 that communicates with the PCIe interface. The host processor 152 can be any type of processor known in the art that is suitable for implementation. The host processor 152 communicates with a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit, usually between cores in a SoC. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of NOC are shared by many signals. Since all links in NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and in communication with NOC 154 are memory processor 156, SRAM 160, and DRAM controller 162. DRAM controller 162 is used to operate and communicate with DRAM (e.g., DRAM 106). SRAM 160 is local RAM memory used by memory processor 156. Memory processor 156 is used to run FEP circuits and perform various memory operations. Also in communication with the NOC are two PCIe interfaces 164 and 166. Figure 1B In an embodiment, the SSD controller will include two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or less than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0033] Figure 1C is a block diagram of one embodiment of the BEP circuit 112 . Figure 1C A method for communicating with FEP circuit 110 (e.g., Figure 1B The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166 of the processor 200. The PCIe interface 200 communicates with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into a large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), the buffer (232 / 262), the processor (220 / 250) and the data path controller (222 / 252) through an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engine 226 / 256 is used to perform error correction, as known in the art. The XOR engine 224 / 254 is used to perform XOR on the data so that the data can be combined and stored in a recoverable manner in the presence of programming errors. The data path controller 22 is connected to the interface module for communicating with the memory package via four channels. Therefore, top NOC 202 is associated with interface 228 for four channels for communicating with memory package, and bottom NOC 204 is associated with interface 258 for four additional channels for communicating with memory package. Each interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers and four schedulers. There is a scheduler, buffer and TM interface for each of the channels. The processor can be any standard processor known in the art. Data path controller 222 / 252 can be a processor, FPGA, microprocessor or other type of controller. XOR engine 224 / 254 and ECC engine 226 / 256 are dedicated hardware circuits, referred to as hardware accelerators. In other embodiments, XOR engine 224 / 254 and ECC engine 226 / 256 can be implemented in software. Scheduler, buffer and TM interface are hardware circuits.

[0034] Figure 1D 1 is a block diagram of one embodiment of a memory package 104 including multiple memory dies 300 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 is connected to a switch mode interface 296 for communicating with the TM interface of the BEP circuit 112 (see, e.g., Figure 1C ). In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may have one or more memory dies. In one embodiment, each memory package includes eight or 16 memory dies; however, other numbers of memory dies may also be implemented. The technology described herein is not limited to any particular number of memory dies.

[0035] Figure 2A is a functional block diagram of one embodiment of memory die 300 . Figure 1D Each memory die in one or more memory dies 300 of can be implemented as the memory die 300 of Figure 2. The components depicted in Figure 2 are electronic circuits. In one embodiment, each memory die 300 includes a memory structure 326, a control circuit 310, and a read / write circuit 328, all of which are electronic circuits. The memory structure 326 can be addressed by a word line via a row decoder 324 and by a bit line via a column decoder 332. The read / write circuit 328 includes a plurality of sense blocks 350 (the plurality of sense blocks include SB1, SB2, ..., SBp (sense circuit)) and allows the data of one (or more) pages in a plurality of memory cells to be read or programmed in parallel. In one embodiment, each sense block includes a sense amplifier and a set of latches connected to the bit line. The latch stores the data to be written and / or the data that has been read. The sense block includes a bit line driver.

[0036] Commands and data are transmitted between the controller and the memory die 300 via line 318, which may form a bus between the memory die 300 and the controller (e.g., memory bus 294). In one embodiment, the memory die 300 includes a set of input and / or output (I / O) pins connected to line 318.

[0037] The control circuit 310 cooperates with the read / write circuit 328 to perform memory operations (e.g., write, read, erase, etc.) on the memory structure 326. In one embodiment, the control circuit 310 includes a state machine 312, an on-chip address decoder 314, a power control module 316 (power control circuit), and a temperature detection circuit 315. The state machine 312 provides die-level control of memory operations. In one embodiment, the state machine 312 is programmable by software. In other embodiments, the state machine 312 does not use software and is completely implemented in hardware (e.g., electronic circuits). In some embodiments, the state machine 312 can be replaced by a microcontroller or a microprocessor. In one embodiment, the control circuit 310 includes buffers such as registers, ROM fuses, and other storage devices for storing default values ​​such as base voltage and other parameters.

[0038] On-chip address decoder 314 provides an address interface between addresses used by controller 102 and hardware addresses used by decoders 324 and 332. Power control module 316 controls the power and voltage provided to word lines and bit lines during memory operations. Power control module 316 may include a charge pump for generating voltages.

[0039] For the purposes of this document, the control circuit 310 includes one or more control circuits for the memory structure 326, either alone or in combination with the read / write circuit 328 and the decoder 324 / 332. The one or more control circuits are circuits that perform the functions described below in the flow chart and signal diagram. In other embodiments, the one or more control circuits may consist of only the controller 102, which is a circuit combined with software that performs the functions described below in the flow chart and signal diagram. In another alternative, the one or more control circuits include the controller 102 and the control circuit 310, which perform the functions described below in the flow chart and signal diagram. In another embodiment, the one or more control circuits include a state machine 312 (or a microcontroller or a microprocessor) alone or in combination with the controller 102.

[0040] In one embodiment, the memory structure 326 includes a monolithic three-dimensional memory array of non-volatile memory cells, wherein multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of a memory cell array having an active region disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells of the memory structure 326 include vertical NAND strings with charge trapping materials, such as, for example, described in U.S. Pat. No. 9,721,662, which is incorporated herein by reference in its entirety. In another embodiment, the memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing a floating gate, such as, for example, described in U.S. Pat. No. 9,082,502, which is incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0041] In one embodiment, a control circuit (e.g., control circuit 310) is formed on a first die called a control die, and a memory array (e.g., memory structure 326) is formed on a second die called a memory die. For example, some or all control circuits associated with the memory (e.g., control circuit 310, row decoder 324, column decoder 332, and read / write circuit 328) may be formed on the same control die. The control die may be bonded to one or more corresponding memory die to form an integrated memory component. The control die and the memory die may have bonding pads arranged to be electrically connected to each other. The bonding pads of the control die and the memory die may be aligned and bonded together by any of a variety of bonding techniques, depending in part on the bonding pad size and the bonding pad spacing (i.e., the bonding pad spacing). In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In some examples, the die is bonded in a one-to-one arrangement (e.g., one control die to one memory die). In some examples, there may be more than one control die and / or more than one memory die in an integrated memory component. In some embodiments, the integrated memory component includes a stack of multiple control dies and / or multiple memory dies. In some embodiments, the control die is connected to or otherwise communicates with a memory controller. For example, the memory controller may receive data to be programmed into a memory array. The memory controller forwards the data to the control die so that the control die can program the data into the memory array on the memory die.

[0042] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 307 is depicted. One or more integrated memory components 307 may be used in a memory package 104 in a memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more succinctly, "dies"). The memory die 301 includes a memory array 326 (memory structure). The memory array 326 may include non-volatile memory cells.

[0043] Control die 311 includes column control circuitry 364, row control circuitry 320, and system control logic 360 (including state machine 312, power control module 316, storage device 366, and memory interface 368). In some embodiments, control die 311 is configured to connect to memory array 326 in memory die 301. Figure 2BAn example of peripheral circuitry is shown, including control circuits formed in a peripheral circuit or control die 311 that are coupled to a memory array 326 formed in a memory die 301. System control logic 360, row control circuitry 320, and column control circuitry 364 are located in the control die 311. In some embodiments, all or a portion of the column control circuitry 364 and all or a portion of the row control circuitry 320 are located on the memory die 301. In some embodiments, some of the circuitry in the system control logic 360 is located on the memory die 301.

[0044] System control logic 360, row control circuitry 320, and column control circuitry 364 may be formed by conventional processes (e.g., CMOS processes), such that adding elements and functionality more commonly found on memory controller 102 (such as ECC) may require few or no additional process steps (i.e., the same process steps used to manufacture controller 102 may also be used to manufacture system control logic 360, row control circuitry 320, and column control circuitry 364). Thus, while moving such circuitry away from a die (such as memory die 301) may reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as control die 311) may not require many additional process steps.

[0045] Figure 2B Column control circuitry 364 including sense blocks 350 on control die 311 is shown coupled to memory array 326 on memory die 301 via electrical paths 370. For example, electrical paths 370 may provide electrical connections between column decoders 332, driver circuits 372, block selectors 373, and bit lines of memory array (or memory structure) 326. Electrical paths may extend from column control circuitry 364 in control die 311 through pads on control die 311 that are bonded to corresponding pads of memory die 301 that are connected to bit lines of memory structure 326. Each bit line of memory structure 326 may have a corresponding electrical path in electrical paths 370 connected to column control circuitry 364, including a pair of bond pads. Similarly, row control circuitry 320 (including row decoders 324, array drivers 374, and block selectors 376) is coupled to memory array 326 via electrical paths 308. Each of the electrical paths 308 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 311 and the memory structure die 301 .

[0046] In some embodiments, there is more than one control die 311 and / or more than one memory die 301 in the integrated memory component 307. In some embodiments, the integrated memory component 307 includes a stack of multiple control dies 311 and multiple memory structure dies 301. In some embodiments, each control die 311 is attached (e.g., bonded) to at least one of the memory structure dies 301.

[0047] The exact type of memory array architecture or memory cell included in the memory structure 326 is not limited to the above examples. Many different types of memory array architectures or memory cell technologies can be used to form the memory structure 326. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of technologies suitable for the memory cells of the memory structure 326 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), phase change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of the memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0048] An example of ReRAM, or PCMRAM, cross-point memory includes a reversible resistance switching element arranged in a cross-point array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0049] Magnetoresistive memory (MRAM) stores data via magnetic storage elements. The element is formed by two ferromagnetic plates, each of which can remain magnetized, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. Memory devices are built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write wires that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated.

[0050] Phase change memory (PCM) exploits the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by changing the coordination state of the germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes (continuous or non-continuous) vibrations or pulse trains of sound, current, voltage light or other waves.

[0051] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by those of ordinary skill in the art.

[0052] Figure 3 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array that may include a memory structure 326 including a plurality of memory cells. For example, Figure 3 A portion of a memory block is shown. The depicted structure includes a set of bit lines BL located above a stack of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. One set of embodiments includes 108 to 278 alternating dielectric and conductive layers, for example, 127 data word line layers, 8 select layers, 4 dummy word line layers, and 139 dielectric layers.

[0053] More or less than 108 to 278 layers may also be used. As will be explained below, the alternating dielectric and conductive layers are divided into four "fingers" by the local interconnect LI. Figure 3 Two fingers and two local interconnects LI are shown. Below and between the alternating dielectric and word line layers is a source line layer SL. A memory hole is formed in the stack of alternating dielectric and conductive layers. For example, the memory hole is labeled MH. Note that Figure 3 In the , dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping layer to form vertical columns of memory cells. Each memory cell can store one or more bits of data. FIG. 4A to FIG. 4C Further details of the three-dimensional monolithic memory array including memory structure 326 are provided.

[0054] Figure 4A304 is a block diagram illustrating an exemplary organization of a memory structure 326, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes may also be used. In one embodiment, a block of memory cells is an erase unit. That is, all memory cells of a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize the memory structure 326 to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines.

[0055] FIG. 4B to FIG. 4C An exemplary three-dimensional ("3D") NAND structure is depicted. Figure 4B is a block diagram depicting a top view of a portion of one block from memory structure 326 . Figure 4B The portion of the block depicted in corresponds to Figure 4A 306 in block 2. Figure 4B As can be seen, Figure 4B The blocks depicted in FIG. extend in the direction 433. In one embodiment, the memory array has sixty layers. Other embodiments have fewer or more than sixty layers. However, Figure 4B Only the top layer is shown.

[0056] Figure 4B A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select gates (also referred to as select transistors) and a plurality of memory cells (also referred to as data memory cells). In one embodiment, each vertical column implements a NAND string. For example, Figure 4B Vertical columns 422, 432, 442, and 452 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details of these vertical columns are provided below. Figure 4B The block depicted in FIG. 4 extends in the direction of arrow 433, so the block includes Figure 4B More vertical columns as depicted in .

[0057] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4BTwenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines may be connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0058] Figure 4B The block depicted in includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various layers to the source lines below the vertical columns. The local interconnects 402, 404, 406, 408, and 410 are also used to divide each layer of the block into four regions; for example, Figure 4B The top layer depicted in FIG is divided into regions 420, 430, 440, and 450, which are referred to as fingers. In the layer implementing the block of memory cells, these four regions are referred to as word line fingers, which are separated by local interconnects. In one embodiment, the word line fingers on the common level of the block are connected together at the end of the block to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In an exemplary implementation, the bit line is connected to only one vertical column in each of the regions 420, 430, 440, and 450. In this implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line fingers on the same level connected together); therefore, the system uses source side select lines and drain side select lines to select one (or another subset) of the four to be subjected to memory operations (programming, verification, reading, and / or erasing).

[0059] although Figure 4B It is shown that each region has four rows of vertical columns in a block, and four regions have sixteen rows of vertical columns, but these exact numbers are exemplary embodiments. Other embodiments may include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block.

[0060] Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0061] Figure 4C A portion of one embodiment of a three-dimensional memory structure 326 is depicted, showing the Figure 4B The cross-sectional view passes through vertical columns 432 and 434 and region 430 (see Figure 4B ). Figure 4CThe structure includes: four drain side selection layers SGD0, SGD1, SGD2, and SGD3 associated with the drain side selection gate; four source side selection layers SGS0, SGS1, SGS2, and SGS3 associated with the source side selection gate; four dummy word line layers DD0, DD1, DS0, and DS1; and forty-eight data word line layers WLL0-WLL127 for connecting to data memory cells. Other embodiments may implement more or less than four drain side selection layers, more or less than four source side selection layers, more or less than four dummy word line layers, and more or less than one hundred and twenty-eight word line layers. Vertical columns 432 and 434 are depicted as protruding through the drain side selection layers, source side selection layers, dummy word line layers, and word line layers. In one embodiment, each vertical column includes a NAND string. For example, vertical column 432 includes NAND string 484. Below the vertical column and the layers listed below are the substrate 101, the insulating film 454 on the substrate, and the source line SL. The NAND strings of the vertical column 432 have source terminals at the bottom of the stack and drain terminals at the top of the stack. Figure 4B Consistent, Figure 4C A vertical column 432 is shown connected to the bit line 414 via a connector 418. Local interconnects 404 and 406 are also depicted.

[0062] For ease of reference, the following items are collectively referred to as conductive layers: drain side selection layers SGD0, SGD1, SGD2, and SGD3; source side selection layers SGS0, SGS1, SGS2, and SGS3; dummy word line layers DD0, DD1, DS0, and DS1; and word line layers WLL0-WLL127. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layers, such as doped polysilicon, metals (such as tungsten or metal silicide). In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers are dielectric layers DL0-DL141. For example, dielectric layer DL131 is above word line layer WLL123 and below word line layer WLL124. In one embodiment, the dielectric layers are made of SiO 2 In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0063] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0-WLL127 are connected to memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, and DS1 are connected to dummy memory cells. Dummy memory cells do not store host data (data provided from the host, such as data from a user of the host), while data memory cells are eligible to store host data. Drain side selection layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND string to the bit line. Source side selection layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND string to the source line SL.

[0064] Although Figures 3 to 4C An exemplary memory system of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0065] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within the distribution of threshold voltages for erased memory cells, as appropriate.

[0066] Figure 5 One embodiment of a sensing block 500 is depicted, such as FIG. 2A to FIG. 2B 570. A single sense block 500 can be divided into a core portion, referred to as a sense module 580, and a common portion 590. In one embodiment, there is a separate sense module 580 for each bit line and one common portion 590 for a group of multiple sense modules 580. In one example, a sense block will include one common portion 590 and eight sense modules 580. Each sense module in the group will communicate with the associated common portion via a data bus 572.

[0067] The sense module 580 includes a sense circuit 570 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sense module 580 also includes a bit line latch 582 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 582 may result in the connected bit line being pulled to a state of a specified program inhibit voltage (e.g., 1.5V-3V).

[0068] The common portion 590 includes a processor 592, a set of data latches 594, and an I / O interface 596 coupled between the set of data latches 594 and the data bus 520. The processor 592 performs calculations. For example, the processor 592 can determine the data stored in the sensed storage element and store the determined data in the set of data latches. The processor 592 can also move data between latches and perform operations on the data in the latches (e.g., perform logical operations such as exclusive OR (XOR) operations). The set of data latches 594 can be used to store data bits determined by the processor 592 during a read operation, or to store data bits imported from the data bus 520 during a program operation. The imported data bits represent data bits to be programmed into the memory array (such as Figure 5 The I / O interface 596 provides an interface between the data latch 594 and the data bus 520.

[0069] During a read operation or other storage element sensing operation, a state machine such as Figure 5 The state machine 512 in the core controls the supply of different control gate voltages to the addressed storage elements. As the state machine steps through various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense module 580 may trip at one of these voltages, and the output will be provided from the sense module 580 to the processor 592 via the data bus 572. At this point, the processor 592 determines the resulting memory state by taking into account the trip event of the sense module and the information about the control gate voltage applied from the state machine via the input line 593. It then calculates the binary encoding of the memory state and stores the resulting data bits in the data latch 594. In another embodiment of the core portion, the bit line latch 582 is used as both a latch for latching the output of the sense module 580 and a bit line latch as described above.

[0070] During a programming operation, the data to be programmed is stored in the group of data latches 594. Under the control of the state machine 512, the programming operation includes a series of programming voltage pulses applied to the control gate of the addressed storage element. Each programming pulse is followed by a readback (or verification process) to determine whether the storage element has been programmed to the desired memory state. The processor 592 monitors the readback memory state relative to the desired memory state. When the two are consistent, the processor 592 sets the bit line latch 582 so that the bit line is pulled to the state of the specified programming prohibition voltage. Even if a programming pulse appears at its control gate, this prohibits further programming of the storage element coupled to the bit line. In other embodiments, the processor initially loads the bit line latch 582, and the sensing circuit sets it to a prohibition value during the verification operation.

[0071] The data latch 594 includes a stack of data latches corresponding to the sense modules. In one embodiment, each sense module 580 has three or more data latches. The data latch can be implemented as a shift register so that the parallel data stored therein is converted into serial data of the data bus 520, and vice versa. All data latches corresponding to the read / write block can be linked together to form a block shift register so that a data block can be input or output by serial transmission. Specifically, the read / write module group can be configured so that each of its data latch groups shifts data into or out of the data bus in sequence, just as if they were part of the shift register of the entire read / write block.

[0072] Figure 6 An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores three data bits. Other embodiments may use other data capacities per memory cell (e.g., such as one, two, four, or five data bits per memory cell). Using more than two data states to store more than one data bit per memory cell is referred to as a multi-level cell (MLC), for example, using four data states to store two bits per cell is an example of an MLC. Using two data states to store one data bit per memory cell is referred to as a single-level cell (SLC). Using sixteen data states to store four data bits per memory cell is referred to as a quad-level cell (QLC). Figure 6 Eight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits.

[0073] Figure 6 Seven verification reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG are shown. When programming memory cells to data state A, the system will test whether these memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether these memory cells have a threshold voltage greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether these memory cells have a threshold voltage greater than or equal to VvC, and so on until state G.

[0074] Figure 6Also shown are seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from the memory cells. By testing whether the threshold voltage of a given memory cell is above or below the seven read reference voltages (e.g., using a sense block such as sense block 350 to perform a sense operation), the system can determine which data state (e.g., Er, A, B, C, ...) the memory cell is in. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. In one embodiment, data values ​​are assigned to a threshold voltage range using a Gray code assignment so that if the threshold voltage of the memory is erroneously shifted to its adjacent physical state, only one bit will be affected. Although Figure 6 All data states are shown being programmed together from the erased state, but in other examples, particularly with a large number of data states, programming may be performed in multiple operations.

[0075] Figure 7 An example of erasing a memory array when each memory cell stores three bits of data is shown (e.g., erasing Figure 6 Memory cells programmed in data states A to G (e.g., by increasing their threshold voltages to the range shown) are returned to the erased data state Er (e.g., by reducing their threshold voltages). An erase pulse may be applied to the memory cells. The memory cells may be verified to be in data state Er using an erase verify voltage VvEr, as shown. A group of memory cells may be considered erased when all or substantially all (e.g., greater than 99%) of the memory cells are found to have a threshold voltage below VvEr. The memory cells may be erased by charging the channel to a positive voltage and applying an erase enable voltage Ven (e.g., 0 volts) on the word line to generate a sufficient electric field to move charge from the charge storage elements of the memory cells.

[0076] In an example of an erase scheme, an erase enable voltage (e.g., Ven) is applied to all word lines of a block to erase the memory cells of all word lines of the block in parallel. Such an erase scheme erases the memory cells of all word lines uniformly and may be referred to as a uniform erase or full word line erase scheme.

[0077] In an alternative erasing scheme, the erase enable voltage is applied non-uniformly. For example, an erase enable voltage Ven (e.g., 0 volts) may be applied to a first subset of word lines of a block, while an erase inhibit voltage Vinh (e.g., 10 volts) may be applied to a second subset of word lines of a block. This allows the memory cells of the first subset of word lines to be erased without erasing the memory cells of the second subset of word lines. Subsequently, the erase enable voltage is applied to the second subset of word lines, and the erase inhibit voltage is applied to the first subset of word lines to erase the memory cells of the second subset of word lines. Such an erase scheme that erases memory cells non-uniformly may be referred to as a non-uniform erase scheme. Word lines may be erased in any number of subsets (e.g., two, three, four, or more subsets), which may be arranged in any manner (e.g., alternating, interleaved, or other arrangements). In one example, word lines are grouped into two subsets in an alternating pattern, wherein the first subset includes odd-numbered word lines, and the second subset includes even-numbered word lines. An erasing scheme that separately erases odd and even word lines (a non-uniform erasing scheme) may be referred to as an odd-even erasing scheme.

[0078] FIG. 8A to FIG. 8C Examples of word line voltages during different erase processes are shown. Fig. 8A As shown in , in full word line erase, all word lines are held at a low erase enable voltage (Ven) such as 0V while the channel of the NAND string is charged. This creates a large channel to control gate electric field for each memory cell, which drives hole injection into the trapping layer, thereby reducing the Vth of the memory cell. Figure 8B In even-odd word line erase, the odd word lines are held at Ven, while the even word lines are held at a higher erase inhibit voltage (Vinh), such as 10V, while the channel is charged. With Ven applied to the word lines, this creates a large channel-to-control gate electric field for each memory cell connected to the odd word lines, causing the memory cells connected to the odd word lines to be erased. However, with Vinh applied to the even word lines, the channel-to-control gate electric field is not large enough for erase, causing the memory cells connected to the even word lines to not be erased. Separately, before or after erasing the memory cells connected to the odd word lines, the even word lines are held at Ven and the odd word lines are held at Vinh, while the channel is charged, causing the memory cells connected to the even word lines to be erased, while the memory cells connected to the odd word lines are not erased (e.g., Figure 8C ).

[0079] In addition, when using odd-even word line erasure, the verification process may involve simultaneous verification testing of all memory cells, such that verification testing of memory cells connected to odd word lines is performed simultaneously with verification testing of memory cells connected to even word lines. Alternatively, the verification process may involve verification testing of memory cells connected to odd word lines, which is separate before or after verification testing of memory cells connected to even word lines.

[0080] Fig. 8A The word line voltages during a full word line erase process are depicted. For example, Ven = 0 V is applied to all data word lines WL0-WL127 (eg, as previously described in Figure 4C ), so that the memory cells connected to these word lines (including memory cells 703-714) are erased. The dummy word line can receive Vinh. The channel 700a of the NAND can be charged from the source terminal by applying an erase voltage to the substrate and / or charged from the drain using GIDL.

[0081] Figure 8B The word line voltages in the odd word line erase step are depicted. Ven=0V is applied to odd word lines (eg, WL1, WL3, ..., WL127), while Vinh=10V is applied to even word lines (eg, WL0, WL2, ..., WL126).

[0082] Figure 8C The word line voltages in the even word line erase step are depicted. Ven=0V is applied to the even word lines (eg, WL0, WL2, ..., WL126), while Vinh=10V is applied to the odd word lines (eg, WL1, WL3, ..., WL127).

[0083] Fig.8D Depicted is the word line voltage during the full word line verification process. While sensing the current in the NAND string, the verification voltage VvEr is applied to each word line. Compared with the parity verification process, the full word line verification process may be beneficial in terms of time consumption.

[0084] Fig. 8E Depicted is the word line voltage in the odd word line verification step. The memory cells connected to the odd word lines are subjected to a verification test by applying a verification voltage VvEr to these word lines. During the verification test, a pass voltage Vread (such as 8V) is applied to the even word lines to provide the associated memory cells in a strong conductive state so that the sense current in the NAND string will be primarily based on the threshold voltages of the memory cells connected to the odd word lines.

[0085] Figure 8FDepicted is the word line voltage during the even word line verification step. Memory cells connected to the even word lines are subjected to a verification test by applying a verification voltage, VvEr, to these word lines. Vread is applied to the odd word lines during the verification test to provide the associated memory cells in a strongly conductive state so that the sense current in the NAND string will be primarily based on the threshold voltage of the memory cells connected to the even word lines. The odd-even verification process ensures that the memory cells are erased uniformly.

[0086] In some cases, control circuitry (e.g., in controller 102) connected to the nonvolatile memory may attempt to determine the status of one or more blocks in the nonvolatile memory. For example, when power is lost without sufficient time to prepare the blocks for the power loss, the status (e.g., written, partially written, erased, partially erased) of blocks (e.g., blocks that may have undergone write or erase operations when power was lost) may not be recorded in the nonvolatile memory and may not be readily available after power is restored. The control circuitry may check individual blocks to determine their status (e.g., whether any data is present). In the case of using a non-uniform erase scheme, a suitable scheme for checking the status of such blocks may be more challenging than in the case of using only a uniform erase scheme.

[0087] 9A to 9D Examples of blocks under different conditions are illustrated, such as conditions that may be encountered when a control circuit attempts to determine a block condition after power is restored following a power loss.

[0088] Fig.9A An example of a partially written block 900 (e.g., in memory structure 326) is illustrated. A written portion 902 of block 900 is represented by shading, while an unwritten portion 904 is shown as blank. A boundary 906 extends between written portion 902 and unwritten portion 904. For example, a word line immediately below boundary 906 may be written, while a word line immediately above boundary 906 may not be written. Programming may proceed word line by word line in a predetermined order (in Fig.9A from bottom to top). Fig.9A The logical order of programming shown in may or may not correspond to a physical order (e.g., programming may proceed from physically higher word lines to physically lower word lines, or in some other order). As programming proceeds, the size of the written portion 902 increases, while the size of the unwritten portion 904 decreases, and the boundary 906 moves accordingly. In some cases, the status of an open block (a block that has not been closed or is not full and can be used to write data) may not be recorded in the non-volatile memory before the unexpected loss of power. When power is restored, it can be determined whether there is data stored in the block, and if so, the location of the boundary between the written portion and the unwritten portion. Any data stored in such a block can be maintained or copied to a new location.

[0089] Fig. 9B An example of a block 900 is shown after it has been completely written (e.g., all word lines of the block 900 have been written) so that the written portion 902 extends throughout the block 900. Because there is no unwritten portion in this case, there is no boundary between the written portion and the unwritten portion. When the block is completely written, the block can be closed, and the state of the block closure can be recorded in a non-volatile memory.

[0090] Fig. 9C An example of a block 900 is shown after it has been completely erased (e.g., after all word lines of the block 900 have been erased in a uniform or non-uniform erase) such that an unwritten portion 904 extends throughout the block 900. Because there is no written portion in this case, there is no boundary between the written portion and the unwritten portion. The completely erased block can be prepared for subsequent use (e.g., for storing data), and its condition can be recorded in non-volatile memory (e.g., it can be added to a pool of erased blocks). In some cases, when recording a block (e.g., as Fig. 9C An unexpected loss of power may occur before the erase condition of the block shown in FIG.

[0091] In a memory system that uses only uniform (full word line) erase, detecting a boundary between written and unwritten portions (e.g., boundary 906) may be sufficient to determine that a block is partially written. Detecting a boundary between written and unwritten portions may not be sufficient to indicate a partially written block in a memory system that uses non-uniform erase (e.g., parity erase).

[0092] Fig.9D shows that during a parity erase (e.g., Figure 8B After the odd-numbered word line erase step and in Figure 8C 900 is an example of a block 900 in an intermediate stage (before the even wordline erase step). The odd wordlines (e.g., WL1, WL3, WL5, ...) are erased (not written), while the even wordlines (e.g., WL0, WL2, WL4, ...) are not erased (written). This alternating pattern creates multiple boundaries between written and unwritten portions. For example, in addition to the boundary 908 between WL4 (written) and WL (unwritten), Fig.9D Also shown is the boundary 910 between WL2 (written) and WL3 (unwritten). Fig.9D The odd word line erasure of block 900 provides eleven such boundaries between written and unwritten portions. In other non-uniform erasure schemes, the number and location of such boundaries may be different. A pattern of written and unwritten portions with multiple boundaries (e.g., such as Fig.9Dor otherwise) can occur as a result of an erase abort (e.g., loss of power during a parity erase) and may be difficult to identify when trying to determine the condition of the block.

[0093] Fig. 10A exemplifies when block 900 is partially written (e.g., Fig.9A 906 is an example of a binary search for a boundary in a block when a block is written to (e.g., as shown in 907 ). The binary search begins by checking (e.g., performing a read or verify operation) the last logical word line (WL11) to determine whether the block is completely written. In response to determining that WL11 is not written, the word line in the middle of the block (WL5) is checked. In response to determining that WL5 is not written, the middle word line of the remaining portion of the block below WL5 is checked (WL2 in this example). In response to determining that WL2 is written (indicating a boundary somewhere between WL2 and WL5), the middle word line of the remaining portion (WL4 in this example) is checked. In response to determining that WL4 is written, it is determined that the boundary 906 is between WL4 and WL5. In response, it can be assumed that a write abort has occurred and the data stored at WL0-WL4 can be copied to another block.

[0094] Fig. 10B This example illustrates when block 900 is partially erased by non-uniform erasure (e.g., Figure 8B After the odd-numbered word line erase step and in Figure 8C An example of performing a binary search for boundaries in the block (before an even word line erase step). The binary search begins by checking (e.g., performing a read or verify operation) the last logical word line (WL11) to determine if the block is completely written. In response to determining that WL11 is not written, the word line in the middle of the block (WL5) is checked. In response to determining that WL5 is not written, the middle word line (WL2) of the remaining portion of the block below WL5 is checked. In response to determining that WL2 is written (indicating a boundary somewhere between WL2 and WL5), the middle word line of the remaining portion (WL4 in this example) is checked. In response to determining that WL4 is written, it is determined that boundary 906 is between WL4 and WL5 (indicating a boundary somewhere between WL2 and WL5). Fig. 10A In response, it may be assumed that a write abort has occurred and the data stored at WL0-WL4 may be copied to another block. Fig. 10B In the scenario shown, there is no valid data at WL0-WL4 (WL0 and WL3 are erased, while WL0, WL2, and WL4 have only stale data). Such misidentification of partially written blocks may be undesirable because it results in unnecessary copying of stale data and may affect the time to recover from an unexpected power loss.

[0095] Aspects of the present technology relate to techniques for accurately and efficiently determining block health, including identifying partially erased blocks in an aborted non-uniform erase (eg, a parity erase).

[0096] FIG. 11A to FIG. 11B An example of a scheme for determining the status of block 900 is shown, which includes distinguishing between a partially erased block (eg, after a partial non-uniform erase) and a partially written block (eg, after a write abort). Fig.11A Block 900 is shown after erasing only odd word lines in a partial non-uniform erase. Initially using a binary search (e.g. FIG. 10A to FIG. 10B ) to detect boundaries, starting with WL11, then WL5 (all erased or not written), followed by WL2 and WL4 (all written). Because WL4 is written and WL5 is not written, it is determined that there is a boundary 906 (first boundary) between WL4 and WL5. To further identify the status of block 900, Fig.11A The word line immediately adjacent to the last written word line WL4 found by the binary search (in this example, WL3) is shown checked to see if it is written or unwritten (e.g., searching for the second boundary below WL4). Because the test word line WL3 is not written and the second boundary 1150 is between WL3 and WL4, it is determined that block 900 is partially erased and block 900 can be processed accordingly (e.g., can be prepared for use, which may include filling with data and / or completing erasure).

[0097] Fig.11A The method used in uses a binary search to find a first boundary between a written portion and an unwritten portion, and then checks a test word line below (on the write side) the last written word line found by the binary search to see if there is a second boundary that would indicate non-uniform erase. The test word line (WL3) selected in this example is immediately adjacent to the last written word line (WL4) found in the binary search in this example (e.g., offset by one word line). The offset of one word line may be suitable for memory systems using parity erase. In other examples (e.g., using other non-uniform erase), the search for the second boundary may be performed differently. For example, the test word line (or multiple word lines) used to test non-uniform erase may be selected differently (e.g., offset by different amounts).

[0098] Fig. 11B Block 900 is shown with valid data partially written along WL0 to WL4 (e.g., after a write abort). Initially, the same binary search (e.g., Fig.11A ) to detect boundaries, starting with WL11, then WL5 (both erased or unwritten), followed by WL2 and WL4 (both written). Because WL4 is written and WL5 is not written, it is determined that there is a boundary 906 between WL2 and WL5. Fig. 11BThe word line immediately adjacent to the last written word line WL4 found by the binary search (in this example, WL3) is shown checked to see if it is written or unwritten (e.g., searching for a second boundary below WL4). Because WL3 is written, no second boundary is between WL3 and WL4, and it is determined that block 900 is partially written. Block 900 may be processed accordingly (e.g., may be prepared for use, may include writing additional data into WL5-WL11 or copying valid data from WL0-WL4 to another block).

[0099] Fig. 12A Shows FIG. 11A to FIG. 11B An alternative implementation is shown in . Initially using a binary search (such as Fig.11A ) to detect boundaries, starting with WL11, then WL5 (both erased or unwritten), followed by WL2 (written). Because WL2 is written and WL5 is not written, there must be a boundary (e.g., boundary 906) between WL2 and WL5, although its location is not determined at this time. A binary search can detect boundaries (not necessarily the exact location of the boundary) by identifying at least one written word line and at least one unwritten word line. Fig. 11B 2 shows that the word line (WL1) immediately adjacent to WL2 is checked to see whether it is written or unwritten (eg, searching for a second boundary below WL2), rather than continuing with a binary search to determine the location of the boundary (eg, as shown in FIG. 2 ). Fig.11A 11. In the example, the binary search is not completed (e.g., the location of the first boundary is not accurately determined) before checking the second boundary.

[0100] Fig. 12B FIG. 1 shows the AND operation applied to block 900 when the block is partially written with valid data along WL0 to WL4 (eg, after a write abort). Fig. 12A The same implementation was initially used using the same binary search (e.g. Fig. 12A ) to detect boundaries, starting with WL11, then WL5 (both erased or unwritten), and then WL2 (written). Because WL2 is written and WL5 is not written, there must be a boundary (e.g., boundary 906) between WL2 and WL5. Fig. 12BShown is checking the word line (WL1) immediately adjacent to WL2 to see if it is written or not written (e.g., searching for a second boundary below WL2), rather than immediately continuing with a binary search to determine the location of the boundary. Because WL1 is written, no second boundary is located between WL1 and WL2, and it is determined that block 900 is partially written. The binary search can then be continued by searching between WL2 and WL5. Checking WL4 can indicate that WL4 is written based on determining that boundary 906 is located between WL4 and WL5. This indicates that valid data exists in WL0-WL4 of block 900. Block 900 can be processed accordingly (e.g., valid data can be copied from WL0-WL4 before erasing block 900).

[0101] Fig.13 An example of a method is shown that includes identifying an open block of non-volatile memory 1360 and detecting a first boundary between a written portion and an unwritten portion of the open block 1362 (e.g., by performing a binary search of the open block). Subsequently, the method also includes, in response to detecting the first boundary between the written portion and the unwritten portion of the open block, checking a second boundary between the written portion and the unwritten portion of the open block to determine whether the open block is subject to a non-uniform erase operation 1364 (e.g., checking a test word line having a predetermined offset from the detected written word line).

[0102] Fig.14 An example of a recovery method after a power loss is shown, the method includes performing a binary search to find a first boundary 1470. A determination is made as to whether a boundary is detected 1472 (the first boundary may not be precisely located at this point). If a boundary is not detected at step 1472, the method includes treating the block as an erase-aborted block 1474 (e.g., the block may be checked to see if it is completely erased and available for writing or further erasing accordingly). If a boundary is detected (a first boundary), the method includes checking a second boundary 1476 and determining if a second boundary 1478 exists. For example, a test word line below a written word line (in a programmed logical order) may be checked to see if it is not written. If a second boundary does not exist, the block is treated as a program-aborted block 1480, which may include continuing to program an unprogrammed word line or copying valid data to another block. If a second boundary exists, the block is treated as an erase-aborted block 1482 (e.g., a partially erased block in a non-uniform erase). For example, in response to determining that an open block is subject to a non-uniform erase operation, the block may be prepared for erasure without copying data from the open block.

[0103] Fig.15 An example of a recovery method after a power loss is illustrated, the method includes performing a binary search 1570 on an open block starting from the last logical word line. For example, FIG. 8A to FIG. 8FWL127 of block 900 or WL11 of block 900 (where word lines are programmed according to numbering starting at zero, e.g., WL0, WL1, WL2, ...). Determine whether the last programmed word line is found 1572 (e.g., determine whether there is a boundary between the written portion and the unwritten portion). If the last programmed word line is not found, the block is considered an erase-stop block 1574 (e.g., a uniform erase stop or an odd-even erase stop after both the even word lines and the odd word lines are at least partially erased). This includes determining whether the first word line is erased 1576 (the first word line in the programming order, e.g., WL0). If the first word line is completely erased, the block can be made available for programming as a new block 1578 (e.g., considered as a completely erased block available for programming). If the first word line is not completely erased, the block can be flash-filled and released before programming (1580). Steps 1576, 1578, and 1580 provide examples of treating a block as an erase-stop block 1574. Other treatments are possible.

[0104] When the last programmed word line 1572 is found, the method includes selecting a test word line 1581, and determining whether the test word line is erased 1582. For example, the test word line may have a predetermined offset away from the last programmed word line (e.g., one word line offset for a system using parity erase). If the test word line is erased, the block is considered a partially erased block 1584 (e.g., a block partially erased by non-uniform erase such as parity erase). In this example, the block is flash filled and released 1586. In other examples, partially erased blocks may be treated differently. If the test word line is erased, the method includes treating the block as a program abort block with valid data 1588.

[0105] The above method (for example, in FIG. 11A to FIG. 15310, alone or in combination with the read / write circuit 328 and the decoder 324 / 332, includes one or more control circuits for the memory structure 326. The one or more control circuits are circuits that perform the functions described above in the flowchart. In other embodiments, the one or more control circuits may consist only of the controller 102, which is a circuit combined with software to perform the functions described above in the flowchart. In another alternative, the one or more control circuits include the controller 102 and the control circuit 310, which perform the functions described above in the flowchart. In another embodiment, the one or more control circuits include a state machine 312 (or a microcontroller or a microprocessor) alone or in combination with the controller 102. Any such control circuitry that is appropriately configured (e.g., by hardware configuration or a combination of hardware and software configuration) may be considered an example of a means for detecting a first boundary between a written portion and an unwritten portion of an open block, and in response to detecting the first boundary, checking a second boundary between the written portion and the unwritten portion of the open block to determine whether the open block is subject to a non-uniform erase operation.

[0106] An example of an apparatus includes one or more control circuits configured to be connected to a plurality of non-volatile memory cells. The one or more control circuits may be configured to detect a first boundary between a written portion and an unwritten portion of an open block. And the one or more control circuits may be further configured to check a second boundary between a written portion and an unwritten portion of the open block in response to detecting the first boundary to determine whether the open block is subject to a non-uniform erase operation.

[0107] The one or more control circuits may be configured to detect the first boundary by performing a binary search on the word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified. The one or more control circuits may be configured to check the second boundary by reading a test word line having a predetermined offset from the detected written word line. The non-uniform erase operation may be an odd-even erase operation that erases odd word lines and even word lines, respectively, and the test word line may be adjacent to the detected written word line. The one or more control circuits may be configured to prepare the open block for erasure without copying data from the open block in response to determining that the test word line is erased. The one or more control circuits may be further configured to find the location of the first boundary in response to not finding the second boundary between the written portion and the unwritten portion of the open block. The one or more control circuits may be further configured to copy the data on the written side of the first boundary from the open block to another block if the second boundary is not found between the written portion and the unwritten portion of the open block. The one or more control circuits may be configured to, in response to determining that the open block is subject to a non-uniform erase operation, prepare the open block for erasure without copying data from the open block. The one or more control circuits may be located on a control die configured to be connected to a memory die including the plurality of non-volatile memory cells.

[0108] An example of a method includes: identifying an open block of a non-volatile memory; detecting a first boundary between a written portion and an unwritten portion of the open block; and then, in response to detecting the first boundary between the written portion and the unwritten portion of the open block, checking a second boundary between the written portion and the unwritten portion of the open block to determine whether the open block is subject to a non-uniform erase operation.

[0109] Detecting the first boundary may include performing a binary search of the word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified. Checking the second boundary may include reading a test word line having a predetermined offset from the detected written word line. The non-uniform erase operation may be an odd-even erase operation that erases odd word lines and even word lines, respectively, and the test word line may be adjacent to the detected written word line. The method may also include preparing the open block for erasure without copying data from the open block in response to determining that the test word line is erased. The method may also include finding the location of the first boundary in response to not finding a second boundary between a written portion and an unwritten portion of the open block. The method may also include copying data on the written side of the first boundary from the open block to another block in response to not finding a second boundary between a written portion and an unwritten portion of the open block. The method may also include preparing the open block for erasure without copying data from the open block in response to determining that the open block is subjected to a non-uniform erase operation.

[0110] An example of a data storage system includes: a plurality of nonvolatile memory cells arranged in blocks; and a component for detecting a first boundary between a written portion and an unwritten portion of an open block, and checking a second boundary between a written portion and an unwritten portion of the open block in response to detecting the first boundary to determine whether the open block is subject to a non-uniform erase operation.

[0111] The non-uniform erase operation may be an odd-even erase operation that erases odd word lines and even word lines respectively, and checking the second boundary between the written portion and the unwritten portion may include checking a test word line located adjacent to a word line determined to be written. The plurality of nonvolatile memory cells may be located on a memory die, and the means for detecting the first boundary may be located on a control die connected to the memory die.

[0112] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0113] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0114] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0115] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0116] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0117] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device comprising: one or more control circuits configured to be connected to the plurality of non-volatile memory cells, The one or more control circuits are configured to: detecting a first boundary between a written portion and an unwritten portion of an open block, and checking a second boundary between a written portion and an unwritten portion of the open block in response to detecting the first boundary to determine whether the open block is subject to a non-uniform erase operation.

2. The apparatus of claim 1, wherein the one or more control circuits are configured to detect the first boundary by performing a binary search on word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified. 3 . The apparatus of claim 2 , wherein the one or more control circuits are configured to check the second boundary by reading a test word line having a predetermined offset from the detected written word line. 4 . The apparatus according to claim 3 , wherein the non-uniform erasing operation is an odd-even erasing operation of erasing odd word lines and even word lines respectively, and the test word line is adjacent to the detected written word line. 5 . The apparatus of claim 4 , wherein the one or more control circuits are configured to, in response to determining that the test word line is erased, prepare the open block for erasure without copying data from the open block. 6 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to find the location of the first boundary in response to not finding a second boundary between a written portion and an unwritten portion of the open block.

7. The apparatus of claim 6, wherein the one or more control circuits are further configured to copy data on the written side of the first boundary from the open block to another block if no second boundary is found between the written portion and the unwritten portion of the open block.

8. The apparatus of claim 1, wherein the one or more control circuits are configured to, in response to determining that the open block is subject to a non-uniform erase operation, prepare the open block for erasure without copying data from the open block.

9. The apparatus of claim 1, wherein the one or more control circuits are located on a control die, the control die being configured to connect to a memory die including the plurality of non-volatile memory cells.

10. A method comprising: identifying an open block of non-volatile memory; detecting a first boundary between a written portion and an unwritten portion of the open block; as well as Subsequently, in response to detecting the first boundary between the written and unwritten portions of the open block, a second boundary between the written and unwritten portions of the open block is checked to determine whether the open block is subject to a non-uniform erase operation.

11. The method of claim 10, wherein detecting the first boundary comprises performing a binary search of word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified.

12. The method of claim 11, wherein checking the second boundary comprises reading a test word line having a predetermined offset from the detected written word line. 13 . The method according to claim 12 , wherein the non-uniform erasing operation is an odd-even erasing operation of erasing odd word lines and even word lines respectively, and the test word line is adjacent to the detected written word line.

14. The method of claim 13, further comprising, in response to determining that the test word line is erased, preparing the open block for erasure without copying data from the open block.

15. The method of claim 10, further comprising finding a location of the first boundary in response to not finding a second boundary between written and unwritten portions of the open block.

16. The method of claim 15, further comprising copying data on the written side of the first boundary from the open block to another block in response to not finding a second boundary between written and unwritten portions of the open block.

17. The method of claim 11, further comprising, in response to determining that the open block is subject to a non-uniform erase operation, preparing the open block for erasure without copying data from the open block.

18. A data storage system comprising: a plurality of nonvolatile memory cells arranged in a block; and Means for detecting a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, checking a second boundary between written and unwritten portions of the open block to determine whether the open block is subject to a non-uniform erase operation.

19. The data storage system of claim 18, wherein the non-uniform erasing operation is an odd-even erasing operation that erases odd word lines and even word lines respectively, and checking the second boundary between a written portion and an unwritten portion comprises checking a test word line positioned adjacent to a word line determined to be written.

20. The data storage system of claim 18, wherein the plurality of nonvolatile memory cells are located on a memory die and the means for detecting the first boundary are located on a control die connected to the memory die.

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