Output matching network to reduce self-inductance and mutual inductance of output inductive components in cavity packages

Abstract

An output matching network that reduces self-inductance and mutual inductance of output inductive components in a cavity package is disclosed. A semiconductor device includes a cavity package including a substrate and at least one output lead disposed higher than the substrate in a side view to create a cavity. The transistor die is disposed within the cavity. A top surface of the transistor die is lower than a top surface of the output lead when viewed in a side view. The first substrate is disposed within the cavity and separated from the transistor die. In a side view, a top surface of the first substrate is lower than a top surface of the output lead. A shunt wire connects the output of the transistor die to the first substrate, and an output wire connects the output of the transistor die to the output lead. The shunt wire or the output wire is arranged and shaped to minimize self-inductance and to minimize mutual inductance with the shunt wire.

Description

Technical Field

[0001] The present disclosure relates to an output matching network that reduces the self-inductance and mutual inductance of an inductive component within a cavity of a cavity package and a method for manufacturing the output matching network. Background Art

[0002] Radio frequency (RF) power amplifiers are used in a variety of applications, including base stations for wireless communications (such as cellular communications). The signals amplified by the RF power amplifier include signals having a high frequency modulated carrier signal. For example, a high frequency carrier signal is modulated using a significantly lower frequency baseband signal, and the ratio of the bandwidth of the resulting signal to the frequency of the carrier signal is the relative bandwidth of the modulated carrier signal. The operating bandwidth (relative bandwidth or partial bandwidth) of the RF power amplifier needs to cover the entire bandwidth of the modulated carrier signal. In view of the demand for wider band signals and / or multi-carrier signals, the operating bandwidth requirements of the RF power amplifier can be fractions of 20% or more.

[0003] Conventional RF power amplifiers typically output 40W to 60W of power or more with the input and output ports terminated in 50 ohm impedance. However, this can lead to bottlenecks in the RF power amplifier because the optimal load impedance of typical switching devices within the RF power amplifier is much less than 10 ohms, which is much lower than a 50 ohm termination. In addition, for large operating bandwidths, the impedance may be dispersed across the frequency range. At the frequencies at which the RF power amplifier operates, performance is very sensitive to output impedance mismatches, and even relatively small mismatches can result in significant degradation. Therefore, broadband output impedance matching is critical to maintaining RF power amplifier performance in broadband and / or large operating bandwidth applications.

[0004] Conventional RF power amplifiers typically use semiconductor switching devices, such as GaN HEMT devices, to amplify signals. For thermal management reasons, the packaging of these devices typically includes a base metal, where the input and output leads are insulated from and placed higher than the base metal, for example, 600 μm higher than the base metal for a 100 μm thick transistor device. As a result, the wires connecting the transistor device to the leads result in parasitic inductance, which is caused by the length and shape of the wires connecting the output of the transistor to the corresponding output lead and to the capacitor intended to cancel other parasitic inductances. The parasitic inductance of the wires originates from the self-inductance and mutual inductance of the wires. Summary of the invention

[0005] According to an exemplary aspect of the present disclosure, a semiconductor device includes a cavity package, the cavity package including a substrate and at least one output lead, the at least one output lead being arranged higher than the substrate in a side view to create a cavity. A transistor die is arranged in the cavity. When observed in a side view, the top surface of the transistor die is lower than the top surface of the output lead. A first substrate is arranged in the cavity and separated from the transistor die. In a side view, the top surface of the first substrate is lower than the top surface of the output lead. A shunt wire connects the output of the transistor die to the first substrate, and an output wire connects the output of the transistor die to the output lead. The shunt wire or the output wire is arranged and shaped to minimize self-inductance and minimize mutual inductance with the shunt wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A more complete appreciation of the present disclosure and its many attendant advantages will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a side view of a cavity package including a transistor device, a substrate, wiring, and output leads;

[0008] Figure 2 is a side view of a cavity package including a transistor device, a substrate, wiring, and output leads according to an exemplary aspect of the present disclosure;

[0009] Figure 3 is another side view of a cavity package including a transistor device, a substrate, wiring, and output leads according to an exemplary aspect of the present disclosure;

[0010] Figure 4 is a side view of a cavity package including a transistor device, a first substrate and a second substrate, wiring and output leads according to an exemplary aspect of the present disclosure;

[0011] Figure 5 is a side view of a cavity package including a transistor device, a first substrate and a second substrate, wiring and output leads according to an exemplary aspect of the present disclosure;

[0012] Figure 6 is a side view of a cavity package including a transistor device, a first substrate and a second substrate, wiring and output leads according to an exemplary aspect of the present disclosure;

[0013] Figure 7 is a side view of a bending process of wiring within a cavity package according to an exemplary aspect of the present disclosure;

[0014] Figure 8 is an algorithm flow chart of a bending process for routing within a cavity package according to an exemplary aspect of the present disclosure;

[0015] Fig. 9 is another algorithm flow chart of a bending process for routing within a cavity package according to an exemplary aspect of the present disclosure; and

[0016] Fig.10 is a further algorithm flow chart of a bending process for routing within a cavity package according to an exemplary aspect of the present disclosure. DETAILED DESCRIPTION

[0017] As used herein, an element or step recited in the singular and beginning with the word "a" or "an" should be understood as not excluding multiple elements or steps, unless such exclusion is explicitly stated. In addition, reference to "one embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also include the described features.

[0018] Figure 1 1 is a side view of a cavity package with an output lead 108 and a shunt lead 110 before being bent into a shape that reduces mutual inductance and self-inductance according to an exemplary aspect of the present disclosure. The cavity package includes a base metal 112 on which the transistor die 102, the substrate 104, and the output lead 106 are disposed. As can be appreciated, the transistor die can be a GaN high electron mobility transistor (HEMT). However, other transistor devices are possible without departing from the scope of the present disclosure.

[0019] The substrate 104 forms an output matching network together with the inductance of the shunt wire 110. In one exemplary aspect, the substrate 104 can be a capacitive substrate, but the substrate 104 can be an inductive substrate, or can exhibit both capacitance and inductance. Therefore, the specific structure and properties of the substrate 104 are not limited to the present disclosure.

[0020] As from Figure 1 As can be seen in FIG. 1 , the output lead 106 is higher than the transistor die 102 and the substrate 104. In one aspect, the output lead can be formed of several layers 106a, 106b, 106c of materials including semiconductor materials, resistive materials, conductive materials, insulators / insulating materials, etc. For example, layer 106c can be a ceramic layer, and layer 106b can be a thin metallization layer to which the conductive lead 106a is attached. Unless otherwise specified, the output lead 106 including the different layers 106a, 106b and 106c will be simply referred to as the output lead 106 in this specification.

[0021] Of course, other structures for the output leads are also possible. For example, the output leads can be a two-layer structure: a conductive lead 106a and an insulating plastic (not shown) that insulates the conductive lead 106a from the base metal 112. In addition to the output lead being isolated from the base metal 112, the output lead 106 can also be composed of a single material.

[0022] As described above, the shunt wire 110 and substrate 104 are used as an output matching network. The shunt wire 110 is connected to the output of the transistor die 102 and the substrate 104, which is connected to ground by virtue of being disposed on the base metal 112. Thus, the shunt wire 110 and substrate 104 form an inductive / capacitive (LC) circuit.

[0023] Output conductor 108 is also connected to the output of transistor die 102 and to output lead 106. Thus, output conductor 108 passes the output of transistor die 102 to output lead 106.

[0024] As from Figure 1 As can be seen in FIG. 1 , both the output conductor 108 and the shunt conductor 110 are upwardly convex and may be parallel to each other for at least a portion of their lengths. This may result in mutual inductance between the output conductor 108 and the shunt conductor 110, and the upwardly convex shape of the output conductor may also result in self-inductance in the output conductor 108. Mutual inductance and self-inductance are parasitic because they are undesirable and may degrade the performance of the circuit.

[0025] Figure 2 is another side view of a cavity package according to an exemplary aspect of the present disclosure. Figure 2 In the embodiment, the shunt wire 208 connecting the transistor die 202 to the substrate 204 is maintained at the same Figure 1 204. However, output conductor 206 is bent so that a portion thereof is no more than a distance 210 from the surface of substrate 204. This causes shunt conductor 208 and output conductor 206 to intersect at a substantially right angle, thereby minimizing the distance that shunt conductor 208 is parallel to output conductor 206. This minimizes the mutual inductance between shunt conductor 208 and output conductor 206 and reduces the parasitic effects of the mutual inductance on the performance of the device. Keeping a portion of output conductor 206 at a distance 210 or less from the surface of transistor die 202 also reduces the self-inductance in the output conductor, thereby reducing the parasitic effects of the self-inductance on the performance of the device. Base metal 212 and Figure 1 The base metal 112 is the same as that of FIG. 1 and therefore will not be described further for the sake of brevity.

[0026] like Figure 3 As shown, the distance 210 can be determined. Figure 3, the distance 210 is determined based on a point P(x1, y1) calculated as the difference 308 between the straight line projected between the bonding point on the transistor die 302 and the bonding point on the output lead 106 (given by y=f(x)) and the projection of the output conductor 306 (given by y=g(x)). That is, the distance P(x1, y1)=g(x)-f(x), such that x1 is in the middle of the conductor, and g(x1)-f(x1) can be, for example, 100 μm. Figure 3 The transistor die 302 , substrate 304 , and base metal 312 are the same as the transistor die 102 , substrate 104 , and base metal 112 , and therefore are not described further.

[0027] The shape of the output wire 306 can be as follows Figure 3 is described. Figure 3 In the coordinate system shown in , the projection of the output wire 306 can be described as y=g(x). Since the self-inductance depends on the height of each part of the wire 306, it is desirable to make g(x) low for most of the x coordinate. However, since the wire is naturally protruding upward, the wire cannot be placed lower than the straight line projected between the junction on the transistor die 302 and the edge of the lead 106, given by y=f(x). In other words, g(x) is always greater than f(x). Various aspects of the present disclosure enable g(x) to be less than f(x), and this effect can be quantified by some criteria defined by g(x) and f(x). An example is the farthest distance D and position x1, which is defined as D=max(f(x)-g(x)), and x1 is such an x. D describes how much lower the wire 306 is made than the limit of conventional wires and can be a design goal. For example, D>=100um.

[0028] The shape of the output conductor 306 can be described by another pair of parameters, Ymax and x2, where Ymax is a value that determines the height, and x2 is the x-position where the output conductor crosses the height of Ymax, x2 and Ymax have a relationship of Ymax=f(x2), and these parameters ensure that the output conductor is below the Ymax of the portion defined by x2. For example, as a design target for the conductor 306, Ymax can be set to 200 μm, and x2 can be set to more than 60% of the full extension of 306 on the x-axis, while for straight conductors 308, this fraction is typically less than 30%.

[0029] As can be appreciated, the distance 210 ( Figure 2 The portion of the output conductor 306 (shown) may be larger than the output conductor 306 (or Figure 2For example, only a small portion of the output conductor 206 / 306 that needs to rise to the level of the output lead 106 can be greater than the distance 210. However, in Figure 2 In the exemplary aspect of the cavity package shown, other portions of the output conductors 206 may also exceed the distance 210 as will be appreciated, except that at least some portions of the output conductors 206 should be no higher than the distance 210 from the substrate 204 .

[0030] In the above about Figure 2 In the discussion of FIG. 2 , the distance 210 of the output lead 206 is determined relative to the transistor die 202. However, this is exemplary only. The distance 210 may also be determined relative to the substrate 204, which may be a different thickness than the transistor die 202, or may be determined relative to the base metal 212. In fact, it may be preferred to determine the distance relative to the base metal 212 so as to remove the variability of the thickness of the substrate within the cavity from the calculation. As will be appreciated by those of ordinary skill, the distance 210 may also be calculated relative to the top of the output lead 106.

[0031] Figure 4 is a side view of another cavity package according to an exemplary aspect of the present disclosure. Figure 4 , the output conductor 410 is divided into two output conductors 410a and 410b. The output conductor 410b connects the output of the transistor die 402 to the substrate 406, and the output conductor 410a connects the substrate 406 to the output lead 106. The output conductor 410b is kept as low as possible and at least below the top of the shunt conductor 408 and the output lead 106. The design goal can be defined as, for example, D>=50~300μm, or for Ymax=50~300μm, x2 exceeds 40~80% relative to the full length.

[0032] The substrate 406 is placed between the substrate 404 and the output lead 106. The substrate 406 serves as Figure 1 The substrate 104 has substantially the same function as the substrate 104. Figure 4 As shown, this results in that output conductor 410b is longer than output conductor 410a. However, substrate 406 may also be placed between transistor die 402 and substrate 404, which results in that output conductor 410a is longer than output conductor 410b. If output conductor 410a is longer than output conductor 410b, the majority of the length of output conductor 410a should be kept as low as possible to reduce self-inductance. In addition, no matter which of output conductor 410a and output conductor 410b is longer, or whether they have equal lengths, any one of the two output conductors 410a and 410b crossing with shunt conductor 408 should be substantially at right angles relative to shunt conductor 408 to reduce mutual inductance.

[0033] As can be appreciated, substrate 406 can be inductive, capacitive, or a combination of inductive and capacitive. Furthermore, substrates 406 and 404 can both be of the same type, inductive or capacitive, or a combination, or can be of different types without departing from the scope of the present disclosure. Likewise, the dimensions of substrates 406 and 404 are not limited to the present disclosure and can be larger or smaller than Figure 4 (or any other figure). Substrates 406 and 404 may also be the same thickness or different thicknesses, and may be as thick, thicker, or thinner than transistor die 402 without limitation.

[0034] certainly, Figure 4 It is also shown that the transistor die 402, substrates 406 and 404, and output leads 106 are disposed on a base metal 412. However, since the base metal 412 is the same as the base metals 112, 312, and 212 described above, further description is omitted for the sake of brevity.

[0035] Next, about Figure 5 Another exemplary configuration of wiring within a cavity package is described. Figure 5 5. In the embodiment of the present invention, base metal 512, transistor die 502, and substrates 506 and 504 are substantially the same as, for example, base metal 412, transistor die 402, substrates 406 and 404 described above. However, shunt wire 510 is divided into two shunt wires 510a and 510b. Shunt wire 510a connects the output of transistor die 502 to substrate 506, and shunt wire 510b connects substrate 506 to substrate 504. Output wire 508 connects the output of transistor die 502 to output lead 106.

[0036] like Figure 5 As shown, output conductor 508 remains lower than shunt conductors 510a and 510b for at least a portion of its length. Output conductor 508 also crosses shunt conductors 510a and 510b at substantially right angles to minimize mutual inductance between output conductor 508 and one or more of shunt conductors 510b and 510a. Although output conductor 508 is shown as crossing both shunt conductors 510a and 510b, as will be appreciated by those of ordinary skill, output conductor 508 may only cross one of shunt conductors 510 or 510b. Design goals may be defined as, for example, D>=50-300μm, or for Ymax=50-300μm, x2 exceeds 40-80% relative to the full length.

[0037] Shunt wires 510a and 510b may be of equal length, or one may be longer than the other without limitation. Thus, the relative positions of substrates 506 and 504 may be adjusted relative to each other and also relative to transistor die 502 and output leads 106 as desired.

[0038] Both shunt wires 510a and 510b can maintain the same distance relative to the top of output lead 106, but this is not limiting. For example, shunt wire 510a can be higher or lower than shunt wire 510b. As in the previously described configuration, the exact dimensions of substrates 506 and 504 and their electrical characteristics (inductive / capacitive) are not limited to the present disclosure.

[0039] Figure 6 is another exemplary configuration of wiring within a cavity package. Figure 6 As shown, both the output conductor 614 and the shunt conductor 610 are divided into two. Specifically, the output conductor 614 is divided into an output conductor 614a and an output conductor 614b, and the shunt conductor 610 is divided into a shunt conductor 610a and a shunt conductor 610b. The output conductor 614a is kept as low as possible and at least lower than the shunt conductors 610a and 610b. To the extent that the output conductors 614a and 614b cross one or more of the shunt conductors 610a and 610b, they are substantially at right angles to minimize self-inductance. The design goal can be defined as, for example, D>=50~300μm, or for Ymax=50~300μm, x2 exceeds 40~80% relative to the full length.

[0040] Substrates 606 and 608 are used to separate shunt wires 610 and output wires 614, respectively. For example, output wire 614a connects the output of transistor die 602 to substrate 608, and output wire 614b connects substrate 608 to the output lead. Shunt wire 610a connects the output of transistor die 602 to substrate 606, and shunt wire 610b connects substrate 606 to substrate 604. Similar to the above-mentioned substrates, substrates 604, 606, and 608 can be capacitive, inductive, or a combination without limitation. Likewise, the size of substrates 604, 606, and 608 can vary without limitation.

[0041] exist Figure 6 In the embodiment shown in FIG. 6 , substrate 606 is closer to transistor die 602 than substrate 608, but the positions of substrates 606 and 608 may be interchanged without departing from the scope of the present disclosure. Substrate 608 may also be placed between substrate 604 and output lead 106. Base metal 612 is the same as the base metal previously described.

[0042] Preferably, shunt conductor 610a is taller than shunt conductor 610b and output conductor 614a. However, depending on other design considerations, shunt conductor 610a may be lower than or equal to shunt conductor 610b in height as long as output conductor 614a remains below both shunt conductors 610a and 610b.

[0043] The lengths of output conductors 614a and 614b may be the same or different, where, for example, output conductor 614a is longer than output conductor 614b. Likewise, the lengths of shunt conductors 610a and 610b may be the same or different.

[0044] In the above about Figure 1-Figure 6 In the description of FIG. 1 , the cavity package is described with respect to a cross-sectional view. However, a person of ordinary skill will recognize that the cavity package may include multiple transistor dies and / or multiple transistors on one die, and a corresponding substrate, which requires multiple output conductors and shunt conductors. In this case, the shunt conductors and output conductors of all transistors may be configured to be the same, such as Figure 1-Figure 6 Any one, or some, of the may be configured differently from the others based on design requirements.

[0045] Next, about Figure 7 A method of bending the output conductor 706 to a predetermined height to reduce self-inductance and mutual inductance is described. For clarity, Figure 7 The shunt wire is not shown in FIG. However, a person of ordinary skill will appreciate that the shunt wire can be bent to a specified height in a substantially similar manner as described herein with respect to the output wire 706. Figure 7 In FIG. 7 , transistor die 702 , substrate 704 , and base metal 716 are substantially similar to the transistor die, substrate, and base metal described above.

[0046] exist Figure 7 , output conductor 706 is first attached to the output of transistor die 702 and output lead 106. Whether output conductor 706 is first attached to the output of transistor die 702 and then to output lead 106, or whether output conductor 706 is first attached to output lead 106 and then to the output of transistor die 704 is not limited to the present disclosure.

[0047] Once the output conductor 706 is secured to both the transistor die 702 and the output lead 106, a force is applied to the output conductor 706 using the structure 714 so that the output conductor 706 is bent to a desired shape. Of course, in the case where there are multiple output conductors connecting multiple transistor outputs to multiple output leads, the structure 714 can be long enough to span all of the output conductors so that all of the output conductors are bent to a desired shape simultaneously. Alternatively, each output conductor can be bent into shape individually.

[0048] As will be described in more detail below, structure 714 can be a tool, such as a rod, that is introduced into the cavity package during manufacture to bend the output conductor 706 and then removed. Structure 714 can also be a wire that is temporarily attached to one side of the cavity and then pulled on the (multiple) output conductors 706 to bend the output conductors 706. The (multiple) output conductors 706 can also be bent into shape by the tool that attaches the output conductors 706 when attached to the transistor die 702 and / or the output leads 106. Many other structures 714 for bending the (multiple) output conductors 706 are also possible without departing from the scope of the present disclosure.

[0049] Figure 8 8 is a flow chart of an exemplary process for inserting wires into a cavity package according to the present disclosure. The process begins at step 802 and proceeds to step 804, in which (multiple) shunt wires are attached / bonded to the output of the transistor die and the substrate, as described above with respect to Figure 2-Figure 6 At step 806, the output conductor(s) are attached / bonded to the output and output leads (or substrate and output leads) of the transistor die as described above. At step 808, the output conductors are bent using a structure such as structure 714. The process then ends at step 810.

[0050] Fig. 9 is a flow chart of an exemplary process for inserting a wire into a cavity package while using another wire to bend the output wire. Fig. 9 The process assumes that the shunt wire(s) and output wire(s) are already installed in the cavity package. Then, Fig. 9 It starts at step 902 and proceeds to step 904 where another wire is bonded / attached to one side of the cavity package. In step 906, the other wire is pulled, for example, over the output wire, and once the output wire is bent into the desired shape, the other wire is removed at step 908. The process ends at step 910.

[0051] Fig.10 is a flow chart of an exemplary process for inserting wires into a cavity enclosure using a rod to bend, for example, output wire(s) into a desired shape. Fig.10It is also assumed that the shunt conductor(s) and the output conductor(s) have already been installed in the cavity package. The process then begins at step 1002 and proceeds to step 1004, where a rod is positioned at a predetermined location on the conductor to be bent (e.g., on the output conductor). Then at step 1006, the rod is pressed down into the output conductor to bend the output conductor into a predetermined shape. At step 1008, the rod is removed and the process ends at step 1010.

[0052] Obviously, many modifications and variations of the present disclosure are possible in light of the above teachings.It is therefore to be understood that within the scope of the appended claims, the present disclosure may be practiced otherwise than as specifically described herein.

Claims

1. A semiconductor device, comprising: a cavity package comprising a substrate and at least one output lead, the at least one output lead being disposed higher than the substrate when viewed in a side view to create a cavity; a transistor die disposed within the cavity, the transistor die having a top surface lower than a top surface of the output lead when viewed in the side view; a first substrate disposed in the cavity and separated from the transistor die, the top surface of the first substrate being lower than the top surface of the output lead when viewed in the side view; a shunt conductor configured to connect an output of the transistor die to the first substrate; and an output conductor configured to connect an output of the transistor die to an output lead of the cavity package, Wherein, at least one of the shunt conductor and the output conductor is arranged and shaped to minimize self-inductance and minimize mutual inductance with the shunt conductor.

2. The semiconductor device according to claim 1, wherein When viewed in the side view, a first portion of an output conductor over the transistor die and the first substrate is maintained below a top surface of an output lead.

3. The semiconductor device according to claim 2, wherein: When viewed in the side view, the first portion of the output conductor is maintained a predetermined distance above the substrate.

4. The semiconductor device according to claim 2, wherein: The first portion of the output conductor is the longest portion of the output conductor.

5. The semiconductor device according to claim 2, wherein: The length of the first portion of the output conductor is given by the distance from the connection point of the output conductor on the transistor die to the lowest point of the output conductor relative to a straight line between the connection point of the transistor die and the edge of the output lead.

6. The semiconductor device according to claim 1, wherein When viewed in the side view, the shunt wire has an upwardly convex shape.

7. The semiconductor device according to claim 6, wherein: In the side view, the shunt conductor and the output conductor cross at a substantially right angle relative to each other.

8. The semiconductor device according to claim 1, further comprising: a second substrate, the second substrate being disposed in the cavity and electrically separated from the transistor die and the first substrate, The output wire comprises a first output wire connected between the output of the transistor core and the second substrate and a second output wire connected between the second substrate and the output lead, and when observed in the side view, the first wire is maintained below the top surface of the output lead.

9. The semiconductor device according to claim 8, wherein: The second output wire is shorter than the first output wire.

10. The semiconductor device according to claim 8, wherein The first substrate is disposed between the transistor die and the second substrate when viewed in the side view.

11. The semiconductor device according to claim 8, wherein The second substrate and the first substrate are formed as a single integrated passive device (IPD).

12. The semiconductor device according to claim 8, further comprising: a third substrate, the third substrate being disposed in the cavity and being separated from the transistor die, the first substrate and the second substrate, The shunt wires include a first shunt wire connected from the output of the transistor die to the third substrate and a second shunt wire connected from the third substrate to the first substrate.

13. The semiconductor device according to claim 12, wherein: In the side view, the second substrate and the third substrate are disposed between the transistor die and the first substrate, and the third substrate is disposed between the transistor die and the second substrate.

14. The semiconductor device according to claim 12, wherein: In the side view, the second substrate is disposed between the transistor die and the first substrate, and the second substrate is disposed between the third substrate and the output lead.

15. The semiconductor device according to claim 1, wherein The semiconductor device comprises a radio frequency power amplifier, and the transistor die comprises a GaN HEMT transistor.

16. The semiconductor device according to claim 1, further comprising: a second substrate, the second substrate being disposed in the cavity and being separated from the transistor die and the first substrate, The shunt wires include a first shunt wire connected from the output of the transistor die to the second substrate and a second shunt wire connected from the second substrate to the first substrate.

17. The semiconductor device according to claim 16, wherein: The second substrate is disposed between the transistor die and the first substrate when viewed in the side view.

18. The semiconductor device according to claim 3, further comprising: a second substrate, the second substrate being disposed in the cavity and being separated from the transistor die and the first substrate, The shunt wires include a first shunt wire connected from the output of the transistor die to the second substrate and a second shunt wire connected from the second substrate to the first substrate.

19. The semiconductor device according to claim 4, further comprising: a second substrate, the second substrate being disposed in the cavity and being separated from the transistor die and the first substrate, The shunt wires include a first shunt wire connected from the output of the transistor die to the second substrate and a second shunt wire connected from the second substrate to the first substrate.

20. The semiconductor device according to claim 1, wherein The first substrate is a capacitive substrate.

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