Display substrate and display device

Abstract

The invention discloses a display substrate and a display device, the display substrate is provided with a display area and a non-display area, and comprises a substrate, a plurality of data signal lines which are arranged on the substrate and are at least partially positioned in the display area, and at least two selection signal lines, a plurality of data output lines and a multiplexer which are positioned in the non-display area, the demultiplexer comprises a plurality of selection transistors which are electrically connected with a selection signal line, a data signal line and a data output line respectively; the selection transistor comprises a shading pattern, an active pattern and a gate electrode, for the same selection transistor, one of the shading pattern and the gate electrode is located on the side, close to the substrate, of the active pattern, the other one of the shading pattern and the gate electrode is located on the side, away from the substrate, of the active pattern, and the orthographic projection of the shading pattern on the substrate is at least partially overlapped with the gate electrode on the substrate; the light shielding pattern and the gate electrode of the selection transistor are electrically connected to the selection signal line to which the selection transistor is connected, respectively.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Mainstream display products include: liquid crystal displays and organic light-emitting diode displays. The above displays include: data driver chips, data lines, data transmission lines and pixels, wherein the data driver chip outputs data signals to the pixels in the display through the data lines. Since there are a large number of data lines in the display, the data driver chip requires more pins accordingly, so the number of data transmission lines that transmit data signals to each data line is also correspondingly large, which is not conducive to achieving a narrow border of the display. In order to achieve a full screen, a multiplexer is set between the data driver chip and the data line. The data driver chip can be connected to at least two sub-pixels through the multiplexer, which can greatly reduce the number of data transmission lines, reduce the size of the data driver chip, and reduce the size of the display border. Summary of the invention

[0003] The following is a summary of the subject matter described in detail in this application. This summary is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate, which is provided with a display area and a non-display area, comprising: a substrate, and a plurality of data signal lines disposed on the substrate and at least partially located in the display area, at least two selection signal lines located in the non-display area, a plurality of data output lines, and a demultiplexer, wherein the demultiplexer comprises: a plurality of selection transistors, wherein the selection transistors are electrically connected to the selection signal lines, the data signal lines, and the data output lines, respectively;

[0005] The selection transistor comprises: a light shielding pattern, an active pattern and a gate electrode, and for the same selection transistor, one of the light shielding pattern and the gate electrode is located on a side of the active pattern close to the substrate, and the other is located on a side of the active pattern away from the substrate, and the orthographic projection of the light shielding pattern on the substrate at least partially overlaps with the gate electrode on the substrate;

[0006] The light shielding pattern and the gate electrode of the selection transistor are respectively electrically connected to a selection signal line to which the selection transistor is connected.

[0007] In an exemplary embodiment, for the same selection transistor, an orthographic projection of the light shielding pattern on the substrate covers an orthographic projection of the active pattern on the substrate, and an orthographic projection of the gate electrode on the substrate at least partially overlaps an orthographic projection of the active pattern on the substrate.

[0008] In an exemplary embodiment, the selection signal line includes: a first selection signal line to an Mth selection signal line, and the data output line includes: a first data output line to an Nth data output line;

[0009] The demultiplexer comprises: N distributors, the nth distributor is electrically connected to the first selection signal line to the Mth selection signal line, the nth data output line and the M data signal lines respectively, and at least one of the distributors comprises: first selection transistors to the Mth selection transistors;

[0010] In the nth distributor, the light shielding pattern of the mth selection transistor and the gate electrode of the mth selection transistor are electrically connected to the mth selection signal line respectively, 1≤m≤M, 1≤n≤N;

[0011] The data signal line and the data output line extend at least partially along a first direction, the selection signal line extends at least partially along a second direction, and the first direction and the second direction intersect.

[0012] In an exemplary embodiment, the light shielding pattern is a single-layer structure or a double-layer structure;

[0013] When the shading pattern is a double-layer structure, the shading pattern includes: a first shading pattern and a second shading pattern, the first shading pattern is located on a side of the second shading pattern close to the substrate, and the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second shading pattern on the substrate;

[0014] The first light-shielding pattern of the selection transistor is insulated from the selection signal line connected to the selection transistor, and the second light-shielding pattern of the selection transistor is electrically connected to the selection signal line connected to the selection transistor.

[0015] In an exemplary embodiment, when the light shielding pattern has a double-layer structure, a length of the second light shielding pattern along the second direction is greater than a length of the gate electrode of the selection transistor along the second direction.

[0016] In an exemplary embodiment, when M=2, the nth distributor includes: at least one first selection transistor and at least one second selection transistor;

[0017] The first electrode of the first selection transistor and the first electrode of the second selection transistor are respectively electrically connected to the nth data output line, the second electrode of the first selection transistor is electrically connected to the first data signal line connected to the nth distributor, and the second electrode of the second selection transistor is electrically connected to the second data signal line connected to the nth distributor.

[0018] In an exemplary embodiment, when the shading pattern is a single-layer structure, the shading pattern of the first selection transistor located in the same distributor is spaced apart from the shading pattern of the second selection transistor and arranged along the second direction, and the active pattern of the first selection transistor located in the same distributor is spaced apart from the active pattern of the second selection transistor and arranged along the second direction.

[0019] In an exemplary embodiment, when the shading pattern is a double-layer structure, the first shading pattern of the first selection transistor and the first shading pattern of the second selection transistor are the same shading pattern, the second shading pattern of the first selection transistor and the second shading pattern of the second selection transistor are spaced apart and arranged along the second direction, and the active pattern of the first selection transistor and the active pattern of the second selection transistor are the same active pattern.

[0020] In an exemplary embodiment, when the shading pattern is a double-layer structure, the first shading pattern of the first selection transistor and the first shading pattern of the second selection transistor are spaced apart and arranged along the second direction, the second shading pattern of the first selection transistor and the second shading pattern of the second selection transistor are spaced apart and arranged along the second direction, and the active pattern of the first selection transistor and the active pattern of the second selection transistor are spaced apart and arranged along the second direction.

[0021] In an exemplary embodiment, at least a portion of the structure of the first selection transistor and the structure of the second selection transistor in the same distributor are symmetrical with respect to a first virtual straight line, and an extending direction of the first virtual straight line is parallel to the first direction.

[0022] In an exemplary embodiment, when M=2, and the light shielding pattern is a single-layer structure, the nth distributor includes: two first selection transistors and two second selection transistors;

[0023] For the nth distributor, the first electrode of the first first selection transistor is electrically connected to the nth data output line, the second electrode of the first first selection transistor is electrically connected to the first data signal line connected to the nth distributor, the first electrode of the second first selection transistor is electrically connected to the first selection signal line, and the second electrode of the second first selection transistor is electrically connected to the shading pattern of the first first selection transistor; the first electrode of the first second selection transistor is electrically connected to the nth data output line, the second electrode of the first second selection transistor is electrically connected to the second data signal line connected to the nth distributor, the first electrode of the second second selection transistor is electrically connected to the second selection signal line, and the second electrode of the second second selection transistor is electrically connected to the shading pattern of the first second selection transistor.

[0024] In an exemplary embodiment, the shading pattern of the first first selection transistor and the shading pattern of the first second selection transistor are the same shading pattern, and the active pattern of the first first selection transistor and the active pattern of the first second selection transistor are the same shading pattern; the shading pattern of the second first selection transistor and the shading pattern of the second second selection transistor are spaced apart and arranged along the second direction, and the active pattern of the second first selection transistor and the active pattern of the second second selection transistor are spaced apart and arranged along the second direction.

[0025] In an exemplary embodiment, any one of the selection signal lines includes: a first sub-selection signal line and a second sub-selection signal line, the first sub-selection signal line of any one of the selection signal lines is located at a side of the demultiplexer close to the display area, and the second sub-selection signal line of any one of the selection signal lines is located at a side of the demultiplexer away from the display area;

[0026] The gate electrode of the first first selection transistor is electrically connected to the first sub-selection signal line of the first selection signal line, the gate electrode of the first second selection transistor is electrically connected to the first sub-selection signal line of the second selection signal line, the gate electrode and the first electrode of the second first selection transistor are respectively electrically connected to the second sub-selection signal line of the first selection signal line, and the gate electrode and the first electrode of the second second selection transistor are respectively electrically connected to the second sub-selection signal line of the second selection signal line.

[0027] In an exemplary embodiment, a first first selection transistor and a second first selection transistor are arranged along the first direction, and a first second selection transistor and a second second selection transistor are arranged along the first direction;

[0028] The structure of the first first selection transistor and the structure of the first second selection transistor are at least partially symmetrical with respect to a second virtual straight line, the structure of the second first selection transistor and the structure of the second second selection transistor are at least partially symmetrical with respect to the second virtual straight line, and the extension direction of the second virtual straight line is parallel to the first direction.

[0029] In an exemplary embodiment, the nth distributor further includes: a third selection transistor and a fourth selection transistor; a first of the first selection transistors is electrically connected to a first data signal line connected to the nth distributor through the third selection transistor, and a first of the second selection transistors is electrically connected to a second data signal line connected to the nth distributor through the fourth selection transistor;

[0030] The gate electrode and the light shielding pattern of the third selection transistor are electrically connected to the first sub-selection signal line of the first selection signal line, respectively, the first electrode of the third selection transistor is electrically connected to the first data signal line connected to the nth distributor, and the second electrode of the third selection transistor is electrically connected to the second electrode of the first of the first selection transistors;

[0031] The gate electrode and the shading pattern of the fourth selection transistor are respectively electrically connected to the first sub-selection signal line of the second selection signal line, the first electrode of the fourth selection transistor is electrically connected to the second data signal line connected to the nth distributor, and the second electrode of the fourth selection transistor is electrically connected to the second electrode of the first second selection transistor.

[0032] In an exemplary embodiment, the light shielding pattern of the third selection transistor is spaced apart from the light shielding pattern of the fourth selection transistor and arranged along the second direction, and the active pattern of the third selection transistor is spaced apart from the active pattern of the fourth selection transistor and arranged along the second direction.

[0033] In an exemplary embodiment, the third selection transistor and the fourth selection transistor are located on a side of the first sub-selection signal line close to the display area, and the structures of the third selection transistor and the fourth selection transistor are at least partially symmetrical with respect to the second virtual straight line.

[0034] In an exemplary embodiment, when the light shielding pattern comprises: a single-layer structure, the display substrate comprises: a light shielding layer, a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on the base;

[0035] The light shielding layer at least includes: the light shielding pattern of the selection transistor;

[0036] The semiconductor layer at least includes: the active pattern of the selection transistor;

[0037] The first conductive layer at least includes: the gate electrode of the selection transistor and the selection signal line;

[0038] The second conductive layer at least includes: the data signal line, the data output line, and the first electrode and the second electrode of the selection transistor.

[0039] In an exemplary embodiment, when the light shielding pattern is a double-layer structure, the display substrate includes: a first light shielding layer, a second light shielding layer, a semiconductor layer, a first conductive layer, and a second conductive layer sequentially stacked on the base;

[0040] The first light shielding layer at least includes: a first light shielding pattern of the selection transistor;

[0041] The second light shielding layer at least includes: a second light shielding pattern of the selection transistor;

[0042] The semiconductor layer at least includes: the active pattern of the selection transistor;

[0043] The first conductive layer at least includes: a gate electrode of the selection transistor and a selection signal line;

[0044] The second conductive layer at least includes: the data signal line, the data output line, and the first electrode and the second electrode of the selection transistor.

[0045] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0046] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0048] Figure 1 It is a structural schematic diagram of a display substrate;

[0049] Figure 2 A connection diagram for selecting a transistor;

[0050] Figure 3 is a partial cross-sectional view of a selection transistor;

[0051] Figure 4 It is a structural schematic diagram of a multiplexer;

[0052] Figure 5 It is the working timing diagram for selecting signal line and data output line;

[0053] Figure 6 The equivalent circuit of the distributor is Figure 1 ;

[0054] Figure 7 for Figure 6 A schematic diagram of the structure of the corresponding multiplexer;

[0055] Figure 8 for Figure 7 Cross-section along AA direction;

[0056] Fig. 9 The equivalent circuit of the distributor is Figure 2 ;

[0057] Fig.10 for Fig. 9 A schematic diagram of the structure of the corresponding multiplexer;

[0058] Fig.11 for Fig.10 Cross-section along BB direction;

[0059] Fig.12 The equivalent circuit of the distributor is Figure 3 ;

[0060] Fig.13 for Fig.12 A schematic diagram of the structure of the corresponding multiplexer;

[0061] Fig.14 for Fig.13 Cross-section along CC direction;

[0062] Fig.15 The equivalent circuit of the distributor is Figure 4 ;

[0063] Fig.16 for Fig.15 A schematic diagram of the structure of the corresponding multiplexer;

[0064] Fig.17 The equivalent circuit of the distributor is Figure 5 ;

[0065] Fig.18 for Fig.17 A schematic diagram of the structure of the corresponding multiplexer;

[0066] Fig.19 for Fig.16 and Fig.18 Cross-section along DD direction;

[0067] Fig. 20 The structure of the display area is shown in FIG. Figure 1 ;

[0068] Fig.21 The structure of the display area is shown in FIG. Figure 2 ;

[0069] Fig. 22 for Figure 7 A schematic diagram of a light shielding layer pattern in FIG.

[0070] Fig.23 for Fig.16 A schematic diagram of a light shielding layer pattern in FIG.

[0071] Fig.24 for Fig.18 A schematic diagram of a light shielding layer pattern in FIG.

[0072] Fig.25 for Figure 7 A schematic diagram of a semiconductor layer pattern in FIG.

[0073] Fig.26 for Figure 7 A schematic diagram after forming a semiconductor layer pattern;

[0074] Fig. 27 for Fig.16 A schematic diagram of a semiconductor layer pattern in FIG.

[0075] Fig.28 for Fig.16 A schematic diagram after forming a semiconductor layer pattern;

[0076] Fig.29 for Fig.18 A schematic diagram of a semiconductor layer pattern in FIG.

[0077] Fig.30 for Fig.18 A schematic diagram after forming a semiconductor layer pattern;

[0078] Fig.31 for Figure 7 A schematic diagram of a first conductive layer pattern in FIG.

[0079] Fig.32 for Figure 7 A schematic diagram after forming a first conductive layer pattern;

[0080] Fig.33 for Fig.16 A schematic diagram of a first conductive layer pattern in FIG.

[0081] Fig.34 for Fig.16 A schematic diagram after forming a first conductive layer pattern;

[0082] Fig.35 for Fig.18A schematic diagram of a first conductive layer pattern in FIG.

[0083] Fig.36 for Fig.18 A schematic diagram after forming a first conductive layer pattern;

[0084] Fig.37 for Figure 7 A schematic diagram of a third insulating layer pattern in FIG.

[0085] Fig.38 for Fig.16 Schematic diagram of the third insulating layer pattern in

[0086] Fig.39 for Fig.18 A schematic diagram of a third insulating layer pattern in FIG.

[0087] Fig.40 for Figure 7 A schematic diagram of a second conductive layer pattern in FIG.

[0088] Fig.41 for Figure 7 A schematic diagram after forming a second conductive layer pattern;

[0089] Fig.42 for Fig.16 A schematic diagram of a second conductive layer pattern in FIG.

[0090] Fig.43 for Fig.16 A schematic diagram after forming a second conductive layer pattern;

[0091] Fig.44 for Fig.18 A schematic diagram of a second conductive layer pattern in FIG.

[0092] Fig.45 for Fig.18 A schematic diagram after forming a second conductive layer pattern;

[0093] Fig.46 for Fig.10 A schematic diagram of a first light shielding layer pattern in FIG.

[0094] Fig.47 for Fig.13 A schematic diagram of a first light shielding layer pattern in FIG.

[0095] Fig.48 for Fig.10 A schematic diagram of a second light shielding layer pattern in FIG.

[0096] Fig.49 for Fig.10 A schematic diagram after forming a second light shielding layer pattern;

[0097] Fig.50 for Fig.13 A schematic diagram of a second light shielding layer pattern in FIG.

[0098] Fig.51 for Fig.13 A schematic diagram after forming a second light shielding layer pattern;

[0099] Fig.52 for Fig.10 A schematic diagram of a semiconductor layer pattern in FIG.

[0100] Fig.53 for Fig.10 A schematic diagram after forming a semiconductor layer pattern;

[0101] Fig.54 for Fig.13 A schematic diagram of a semiconductor layer pattern in FIG.

[0102] Fig.55 for Fig.13 A schematic diagram after forming a semiconductor layer pattern;

[0103] Fig.56 for Fig.10 A schematic diagram of a first conductive layer pattern in FIG.

[0104] Fig.57 for Fig.10 A schematic diagram after forming a first conductive layer pattern;

[0105] Fig.58 for Fig.13 A schematic diagram of a first conductive layer pattern in FIG.

[0106] Fig.59 for Fig.13 A schematic diagram after forming a first conductive layer pattern;

[0107] Fig.60 for Fig.10 A schematic diagram of a third insulating layer pattern in FIG.

[0108] Fig.61 for Fig.13 A schematic diagram of a third insulating layer pattern in FIG.

[0109] Fig.62 for Fig.10 A schematic diagram of a second conductive layer pattern in FIG.

[0110] Fig.63 for Fig.10 A schematic diagram after forming a second conductive layer pattern;

[0111] Fig.64 for Fig.13 A schematic diagram of a second conductive layer pattern in FIG.

[0112] Fig.65 for Fig.13 Schematic diagram after forming the second conductive layer pattern. DETAILED DESCRIPTION

[0113] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0114] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0115] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0116] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0117] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0118] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0119] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0120] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0121] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0122] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0123] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0124] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0125] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0126] A multiplexer in a display may include: a plurality of transistors, the transistors including a shading pattern and an active pattern. The on-state current and mobility of the transistors in the multiplexer are low, and the shading pattern of the transistors in the multiplexer is in a floating state. When the mobility of the active pattern in the transistor is high, the shading pattern in the floating state may cause a negative drift effect on the characteristics of the transistor, thereby affecting the signal transmission capability of the multiplexer. Therefore, the performance of the transistors in the multiplexer is poor, affecting the reliability of the display product.

[0127] Figure 1 is a schematic diagram of the structure of a display substrate. Figure 2 The connection diagram of the selection transistor is shown below. Figure 3 is a partial cross-sectional view of the selection transistor. Figures 1 to 3 As shown, the display substrate provided by the embodiment of the present disclosure is provided with a display area AA and a non-display area NA. The display substrate may include: a substrate 10, and a plurality of data signal lines Data provided on the substrate 0 and at least partially located in the display area, at least two selection signal lines MUX located in the non-display area, a plurality of data output lines SL, and a multiplexer DEMUX, wherein the multiplexer DEMUX includes: a plurality of selection transistors, wherein the selection transistors T are electrically connected to the selection signal line MUX, the data signal line Data, and the data output line SL, respectively.

[0128] In an exemplary embodiment, if Figure 2 and Figure 3As shown, the selection transistor includes: a shading pattern LS, an active pattern TA and a gate electrode TG. For the same selection transistor, one of the shading pattern LS and the gate electrode TG is located on the side of the active pattern LS close to the substrate 10, and the other is located on the side of the active pattern LS away from the substrate 10, and the positive projection of the shading pattern LS on the substrate 10 at least partially overlaps with the gate electrode TG on the substrate 10; the shading pattern LS and the gate electrode of the selection transistor are respectively electrically connected to the selection signal line MUX connected to the selection transistor.

[0129] In an exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and a conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0130] In the present disclosure, the shading pattern LS and the gate electrode TG are respectively located on both sides of the active pattern TA, and the positive projection of the shading pattern LS on the substrate 10 at least partially overlaps with the gate electrode TG on the substrate 10, and the shading pattern LS and the gate electrode of the selection transistor are respectively electrically connected to the selection signal line MUX connected to the selection transistor, which means that the shading pattern LS can also serve as a gate electrode of the selection transistor, forming a dual-gate structure with the gate electrode TG.

[0131] In an exemplary embodiment, the display substrate HA may include: a source driver 100 located in the non-display area NA. The source driver 100 is electrically connected to a plurality of data output lines SL. A demultiplexer is located on a side of the source driver close to the display area.

[0132] In an exemplary embodiment, the display substrate may be an array substrate in a liquid crystal display, or may be an organic light emitting diode display substrate.

[0133] The display substrate provided by the embodiment of the present disclosure is provided with a display area and a non-display area, including: a substrate and a plurality of data signal lines arranged on the substrate and at least partially located in the display area and at least two selection signal lines located in the non-display area, a plurality of data output lines and a multiplexer, the multiplexer including: a plurality of selection transistors, the selection transistors are electrically connected to the selection signal lines, the data signal lines and the data output lines, respectively; the selection transistor includes: a shading pattern, an active pattern and a gate electrode, for the same selection transistor, one of the shading pattern and the gate electrode is located on a side of the active pattern close to the substrate, and the other is located on a side of the active pattern away from the substrate, and the positive projection of the shading pattern on the substrate at least partially overlaps with the gate electrode on the substrate; the shading pattern and the gate electrode of the selection transistor are electrically connected to the selection signal line connected to the selection transistor, respectively. The positive projection of the shading pattern in the present invention on the substrate at least partially overlaps with the gate electrode on the substrate; the shading pattern and the gate electrode of the selection transistor are respectively electrically connected to the selection signal line connected to the selection transistor, which not only avoids the shading pattern of the selection transistor from being in a floating state, but also reduces the impact of negative drift on the characteristics of the transistor and improves the signal transmission capability of the multiplexer, and also forms a double-gate structure through the shading pattern and the gate electrode, thereby improving the on-state current and mobility of the selection transistor, thereby improving the reliability of the display product.

[0134] In an exemplary embodiment, if Figure 2 As shown, for the same selection transistor, the orthographic projection of the light shielding pattern LS on the substrate 10 covers the orthographic projection of the active pattern TA on the substrate, and the orthographic projection of the gate electrode TG on the substrate 10 at least partially overlaps with the orthographic projection of the active pattern TA on the substrate 10 .

[0135] Figure 4 Figure 1 is a schematic diagram of the structure of a multiplexer. Figure 4 As shown, the selection signal lines include: a first selection signal line to an Mth selection signal line, and the data output lines include: a first data output line to an Nth data output line. Figure 4 In the description, M=2 is taken as an example, and FIG. 4 only shows four data output lines SL1 to SL4 and a first selection signal line MUX1 and a second selection signal line MUX2.

[0136] In an exemplary embodiment, if Figure 1 and Figure 4 As shown, the multiplexer DEMUX includes: N distributors DM, the nth distributor DM is electrically connected to the first selection signal line to the Mth selection signal line, the nth data output line and the M data signal lines respectively, and at least one distributor includes: the first selection transistor to the Mth selection transistor. Figure 4 The description is made by taking the example that at least one distributor includes: a first selection transistor T1 to a second selection transistor T2.

[0137] In an exemplary embodiment, if Figure 4 As shown, the transistor type of all the selection transistors in the demultiplexer can be the same. Exemplarily, any one of the first selection transistor to the Mth selection transistor can be an N-type transistor.

[0138] In an exemplary embodiment, if Figure 4 As shown, in the nth distributor, the shading pattern of the mth selection transistor and the gate electrode of the mth selection transistor are electrically connected to the mth selection signal line, 1≤m≤M, 1≤n≤N. Exemplarily, the shading pattern of the first selection transistor T1 and the gate electrode of the first selection transistor are electrically connected to the first selection signal line MUX1, and the shading pattern of the second selection transistor T2 and the gate electrode of the second selection transistor are electrically connected to the second selection signal line MUX2.

[0139] In an exemplary embodiment, Figure 5 This is the working timing diagram for selecting signal lines and data output lines. Figure 5 As shown, when one of the multiple selection signal lines is a valid level signal, the other selection signal lines are invalid level signals. Figure 4 and Figure 5 As shown, when M=2, the signal of the first selection signal line MUX1 and the signal of the second selection signal line MUX2 are not valid level signals at the same time. When the signal of the first selection signal line MUX1 is a valid level signal, the first selection transistor T1 is turned on, and the signal of the data output line SL is written into the data signal line connected to the first selection transistor T1. At this stage, when the signal of the second selection signal line MUX2 is an invalid level signal, the second selection transistor T2 is turned off. When the signal of the second selection signal line MUX2 is a valid level signal, the second selection transistor T2 is turned on, and the signal of the data output line SL is written into the data signal line connected to the second selection transistor T2.

[0140] In an exemplary embodiment, if Figure 1 and Figure 4 As shown, the data signal line Data and the data output line SL at least partially extend along the first direction D1, and the selection signal line MUX at least partially extends along the second direction D2, and the first direction D1 and the second direction D2 intersect.

[0141] In exemplary embodiments, the light shielding pattern may have a single-layer structure or may have a double-layer structure.

[0142] In an exemplary embodiment, when the shading pattern is a double-layer structure, the shading pattern includes: a first shading pattern and a second shading pattern, the first shading pattern is located on a side of the second shading pattern close to the substrate, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second shading pattern on the substrate.

[0143] In an exemplary embodiment, a first light shielding pattern of the selection transistor is insulated from a selection signal line connected to the selection transistor, and a second light shielding pattern of the selection transistor is electrically connected to the selection signal line connected to the selection transistor.

[0144] In an exemplary embodiment, when the light shielding pattern has a double-layer structure, a length of a second light shielding pattern in the light shielding patterns of the selection transistor along the second direction is greater than a length of a gate electrode of the selection transistor along the second direction.

[0145] Figure 6 The equivalent circuit of the distributor is Figure 1 , Figure 7 for Figure 6 The corresponding schematic diagram of the multiplexer structure, Figure 8 for Figure 7 Cross-section along AA. Figures 6 to 8 The following description is made by taking M=2 and the light shielding pattern as a single-layer structure as an example. Figures 6 to 8 As shown, when M=2, the nth distributor includes: a first selection transistor T1 and a second selection transistor T2. The light shielding pattern LS1 and the gate electrode of the first selection transistor T1 are electrically connected to the first selection signal line MUX1, respectively, the light shielding pattern LS2 and the gate electrode of the second selection transistor T2 are electrically connected to the second selection signal line MUX2, respectively, the first electrode of the first selection transistor T1 and the first electrode of the second selection transistor T2 are electrically connected to the nth data output line SLn, respectively, the second electrode of the first selection transistor T1 is electrically connected to the first data signal line Data1 connected to the nth distributor, and the second electrode of the second selection transistor T2 is electrically connected to the second data signal line Data2 connected to the nth distributor.

[0146] In an exemplary embodiment, if Figures 6 to 8 As shown, the shading pattern LS1 of the first selection transistor located in the same distributor is spaced apart from the shading pattern LS2 of the second selection transistor and arranged along the second direction D2, and the active pattern T11 of the first selection transistor located in the same distributor is spaced apart from the active pattern T12 of the second selection transistor and arranged along the second direction D2.

[0147] In an exemplary embodiment, Figures 6 to 8The provided multiplexer avoids the shading pattern of the selection transistor from being in a floating state, which can reduce the impact of negative drift on the characteristics of the transistor and improve the signal transmission capability of the multiplexer. It also forms a double-gate structure with the shading pattern and the gate electrode, thereby improving the on-state current and mobility of the selection transistor, thereby improving the reliability of the display product without adding a mask and causing an increase in cost.

[0148] Fig. 9 The equivalent circuit of the distributor is Figure 2 , Fig.10 for Fig. 9 The corresponding schematic diagram of the multiplexer structure, Fig.11 for Fig.10 Cross-sectional view along BB direction. Figures 9 to 11 The following description is made by taking M=2 and the light shielding pattern being a double-layer structure as an example. Figures 9 to 11 As shown, when M=2, the nth distributor includes: a first selection transistor T1 and a second selection transistor T2. The shading pattern LS1 of the first selection transistor T1 includes: a first shading pattern LS11 and a second shading pattern LS12, and the shading pattern LS2 of the second selection transistor T2 includes: a first shading pattern LS21 and a second shading pattern LS22. The first shading pattern LS11 of the shading pattern LS1 of the first selection transistor T1 is insulated from the first selection signal line MUX1, the gate electrode of the first selection transistor T1 and the second shading pattern LS12 of the shading pattern LS1 are electrically connected to the first selection signal line MUX1, the first shading pattern LS21 of the shading pattern LS2 of the second selection transistor T2 is insulated from the second selection signal line MUX2, the gate electrode of the second selection transistor T2 and the second shading pattern LS22 of the shading pattern LS2 are electrically connected to the second selection signal line MUX2, the first electrode of the first selection transistor T1 and the first electrode of the second selection transistor T2 are electrically connected to the nth data output line SLn respectively, the second electrode of the first selection transistor T1 is electrically connected to the first data signal line Data1 connected to the nth distributor, and the second electrode of the second selection transistor T2 is electrically connected to the second data signal line Data2 connected to the nth distributor.

[0149] In an exemplary embodiment, if Figures 9 to 11 As shown, the first light shading pattern LS11 of the first selection transistor T1 and the first light shading pattern L21 of the second selection transistor T2 are the same light shading pattern, the second light shading pattern LS12 of the first selection transistor and the second light shading pattern LS22 of the second selection transistor are arranged at intervals and along the second direction D2, and the active pattern T11 of the first selection transistor and the active pattern T12 of the second selection transistor are the same active pattern.

[0150] Fig.12 The equivalent circuit of the distributor is Figure 3 , Fig.13 for Fig.12 The corresponding schematic diagram of the multiplexer structure, Fig.14 for Fig.13 Cross-sectional view along CC direction. Figure 12 to Figure 14 The following description is made by taking M=2 and the light shielding pattern being a double-layer structure as an example. Figure 12 to Figure 14 As shown, when M=2, the nth distributor includes: a first selection transistor T1 and a second selection transistor T2. The shading pattern LS1 of the first selection transistor T1 includes: a first shading pattern LS11 and a second shading pattern LS12, and the shading pattern LS2 of the second selection transistor T2 includes: a first shading pattern LS21 and a second shading pattern LS22. The first shading pattern LS11 of the shading pattern LS1 of the first selection transistor T1 is insulated from the first selection signal line MUX1, the gate electrode of the first selection transistor T1 and the second shading pattern LS12 of the shading pattern LS1 are electrically connected to the first selection signal line MUX1, the first shading pattern LS21 of the shading pattern LS2 of the second selection transistor T2 is insulated from the second selection signal line MUX2, the gate electrode of the second selection transistor T2 and the second shading pattern LS22 of the shading pattern LS2 are electrically connected to the second selection signal line MUX2, the first electrode of the first selection transistor T1 and the first electrode of the second selection transistor T2 are electrically connected to the nth data output line SLn respectively, the second electrode of the first selection transistor T1 is electrically connected to the first data signal line Data1 connected to the nth distributor, and the second electrode of the second selection transistor T2 is electrically connected to the second data signal line Data2 connected to the nth distributor.

[0151] In an exemplary embodiment, if Figure 12 to Figure 14 As shown, the first light shading pattern LS11 of the first selection transistor T1 and the first light shading pattern LS21 of the second selection transistor T2 are arranged at intervals and arranged along the second direction D2, the second light shading pattern LS12 of the first selection transistor T1 and the second light shading pattern LS22 of the second selection transistor T2 are arranged at intervals and arranged along the second direction D2, and the active pattern T11 of the first selection transistor T1 and the active pattern T21 of the second selection transistor T2 are arranged at intervals and arranged along the second direction D2.

[0152] In an exemplary embodiment, if Fig.10 and Fig.13As shown, when the light shielding structure is a double-layer structure, the length of the second light shielding pattern LS12 of the first selection transistor T1 along the second direction D2 is greater than the length of the gate electrode T12 of the first selection transistor, and the length of the second light shielding pattern LS22 of the second selection transistor T2 along the second direction D2 is greater than the length of the gate electrode T22 of the second selection transistor. The length of the second light shielding pattern LS12 of the first selection transistor T1 along the second direction D2 is greater than the length of the gate electrode T12 of the first selection transistor, so that the second light shielding pattern LS12 of the first selection transistor T1 can shield the interference of the first light shielding pattern LS11 of the first selection transistor T1 on the active pattern T11 of the first selection transistor T1, and the length of the second light shielding pattern LS22 of the second selection transistor T2 along the second direction D2 is greater than the length of the gate electrode T22 of the second selection transistor, so that the second light shielding pattern LS22 of the second selection transistor T2 can shield the interference of the first light shielding pattern LS21 of the second selection transistor T2 on the active pattern T21 of the second selection transistor T2, thereby improving the reliability of the multiplexer.

[0153] In an exemplary embodiment, if Figure 7 , Fig.10 and Fig.13 As shown, any one of the selection signal lines is located at a side of the demultiplexer close to the display area, and a plurality of the selection signal lines are arranged along the first direction D1.

[0154] In an exemplary embodiment, if Figure 7 , Fig.10 and Fig.13 As shown, at least part of the structure of the first selection transistor T1 and the structure of the second selection transistor T2 in the same distributor are symmetrical with respect to the first virtual straight line O1, and the extension direction of the first virtual straight line O1 is parallel to the first direction D1. The first virtual straight line O1 is the center line of the positive projection of the data output line SLn on the substrate at the angle of the top view plane.

[0155] In an exemplary embodiment, Figures 9 to 14 The provided multiplexer avoids the shading pattern of the selection transistor being in a floating state, which can reduce the impact of negative drift on the characteristics of the transistor and improve the signal transmission capability of the multiplexer. It also forms a double-gate structure through the shading pattern and the gate electrode, thereby improving the on-state current and mobility of the selection transistor, thereby improving the reliability of the display product and reducing the parasitic capacitance of the multiplexer.

[0156] Fig.15 The equivalent circuit of the distributor is Figure 4 , Fig.16 for Fig.15 The corresponding schematic diagram of the multiplexer structure, Fig.17 The equivalent circuit of the distributor is Figure 5 , Fig.18 for Fig.17 The corresponding schematic diagram of the multiplexer structure, Fig.19 for Fig.16 and Fig.18 Cross-sectional view along DD direction. Figures 15 to 19 The following description is made by taking M=2 and the light shielding pattern as a single-layer structure as an example. Figures 15 to 19 As shown, when M=2, and the shading pattern is a single-layer structure, the nth distributor includes: two first selection transistors T1-1 and T1-2 and two second selection transistors T2-1 and T2-2. For the nth distributor, the gate electrode of the first first selection transistor T1-1 is electrically connected to the first selection signal line MUX1, the shading structure LS1-1 of the first first selection transistor T1-1 is electrically connected to the second electrode of the second first selection transistor T1-2, the shading structure LS1-2 and the gate electrode of the second first selection transistor T1-2 are electrically connected to the first selection signal line MUX1, respectively, the first electrode of the first first selection transistor T1-1 is electrically connected to the nth data output line SLn, the second electrode of the first first selection transistor T1-1 is electrically connected to the first data signal line Data1 connected to the nth distributor, the first electrode of the second first selection transistor T1-2 is electrically connected to the first selection signal line MUX1, and the second electrode of the second first selection transistor T1-2 is electrically connected to the shading pattern L of the first first selection transistor S1-1 is electrically connected; the gate electrode of the first second selection transistor T2-1 is electrically connected to the second selection signal line MUX2, the shading structure LS2-1 of the first second selection transistor T2-1 is electrically connected to the second electrode of the second second selection transistor T2-2, the shading structure LS2-2 and the gate electrode of the second second selection transistor T2-2 are respectively electrically connected to the second selection signal line MUX2, the first electrode of the first second selection transistor T2-1 is electrically connected to the nth data output line SLn, the second electrode of the first second selection transistor T2-1 is electrically connected to the second data signal line Data2 connected to the nth distributor, the first electrode of the second second selection transistor T2-2 is electrically connected to the second selection signal line MUX2, and the second electrode of the second second selection transistor is electrically connected to the shading pattern LS2-1 of the first second selection transistor.

[0157] In an exemplary embodiment, if Fig.16 and Fig.18 As shown, any selection signal line includes: a first sub-selection signal line and a second sub-selection signal line, the first sub-selection signal line of any selection signal line is located on the side of the multiplexer close to the display area, and the second sub-selection signal line of any selection signal line is located on the side of the multiplexer far from the display area. Fig.16 and Fig.18As shown, the first selection signal line includes: a first sub-selection signal line MUX1A and a second sub-selection signal line MUX1B, and the second selection signal line includes: a first sub-selection signal line MUX2A and a second sub-selection signal line MUX2B.

[0158] In an exemplary embodiment, if Fig.16 and Fig.18 As shown, the gate electrode of the first first selection transistor T1-1 is electrically connected to the first sub-selection signal line MUX1A of the first selection signal line, the gate electrode of the first second selection transistor T2-1 is electrically connected to the first sub-selection signal line MUX2A of the second selection signal line, the gate electrode and the first electrode of the second first selection transistor T1-2 are respectively electrically connected to the second sub-selection signal line MUX1B of the first selection signal line, and the gate electrode and the first electrode of the second second selection transistor T2-2 are respectively electrically connected to the second sub-selection signal line MUX2B of the second selection signal line.

[0159] In an exemplary embodiment, the first sub-selection signal line MUX1A of the first selection signal line may be located on a side of the first sub-selection signal line MUX2A of the second selection signal line close to or away from the display area, and the second sub-selection signal line MUX1B of the first selection signal line may be located on a side of the second sub-selection signal line MUX2B of the second selection signal line close to or away from the display area. Fig.16 and Fig.19 The explanation is given by taking the example that the first sub-selection signal line MUX1A of the first selection signal line is located on the side of the first sub-selection signal line MUX2A of the second selection signal line away from the display area, and the second sub-selection signal line MUX1B of the first selection signal line is located on the side of the second sub-selection signal line MUX2B of the second selection signal line away from the display area.

[0160] In an exemplary embodiment, if Fig.17 and Fig.18As shown, the nth distributor may further include: a third selection transistor T3 and a fourth selection transistor T4; the first first selection transistor T1-1 is electrically connected to the first data signal line Data1 connected to the nth distributor through the third selection transistor T3, and the first second selection transistor T2-1 is electrically connected to the second data signal line Data2 connected to the nth distributor through the fourth selection transistor T4. Wherein, the gate electrode and the light shielding pattern LS2 of the third selection transistor T3 are electrically connected to the first sub-selection signal line MUX1A of the first selection signal line, the first electrode of the third selection transistor T3 is electrically connected to the first data signal line Data1 connected to the nth distributor, and the second electrode of the third selection transistor T3 is electrically connected to the second electrode of the first first selection transistor T1-1; the gate electrode and the light shielding pattern of the fourth selection transistor T4 are electrically connected to the first sub-selection signal line MUX2A of the second selection signal line, the first electrode of the fourth selection transistor T4 is electrically connected to the second data signal line Data2 connected to the nth distributor, and the second electrode of the fourth selection transistor T4 is electrically connected to the second electrode of the first second selection transistor T2-1.

[0161] In an exemplary embodiment, if Fig.16 and Fig.18 As shown, the shading pattern LS1-1 of the first first selection transistor T1-1 and the shading pattern LS2-1 of the first second selection transistor T2-1 are the same shading pattern, and the active pattern T11-1 of the first first selection transistor T1-1 and the active pattern T21-1 of the first second selection transistor T2-1 are the same shading pattern; the shading pattern LS1-2 of the second first selection transistor T1-2 and the shading pattern LS2-2 of the second second selection transistor T2-2 are spaced apart and arranged along the second direction D2, and the active pattern T11-1 of the second first selection transistor T1-2 and the active pattern T21-2 of the second second selection transistor T2-2 are spaced apart and arranged along the second direction D2.

[0162] In an exemplary embodiment, if Fig.16 and Fig.18 As shown, the first first selection transistor T1-1 and the second first selection transistor T1-2 are arranged along the first direction D1, and the first second selection transistor T2-1 and the second second selection transistor T2-2 are arranged along the first direction D1.

[0163] In an exemplary embodiment, if Fig.16 and Fig.18As shown, the structure of the first first selection transistor T1-1 and the structure of the first second selection transistor T2-1 are at least partially symmetrical with respect to the second virtual straight line O2, and the structure of the second first selection transistor T1-2 and the structure of the second second selection transistor T2-2 are at least partially symmetrical with respect to the second virtual straight line O2. The extension direction of the second virtual straight line O2 is parallel to the first direction D1, wherein the second virtual straight line O2 is the center line of the positive projection of the data output line SLn on the substrate at the angle of the top view plane.

[0164] In an exemplary embodiment, if Fig.18 As shown, the shading pattern LS3 of the third selection transistor T3 and the shading pattern LS4 of the fourth selection transistor T4 are spaced apart and arranged along the second direction D2, and the active pattern T31 of the third selection transistor T3 and the active pattern T41 of the fourth selection transistor T4 are spaced apart and arranged along the second direction D2.

[0165] In an exemplary embodiment, if Fig.18 As shown, the third selection transistor T3 and the fourth selection transistor T4 are located on the side of the first sub-selection signal line close to the display area, and the structure of the third selection transistor T3 and the structure of the fourth selection transistor T4 are at least partially symmetrical relative to the second virtual straight line O2.

[0166] In an exemplary embodiment, Figures 15 to 19 The provided multiplexer avoids the shading pattern of the selection transistor from being in a floating state, which can reduce the impact of negative drift on the characteristics of the transistor and improve the signal transmission capability of the multiplexer. It also forms a double-gate structure through the shading pattern and the gate electrode, thereby improving the on-state current and mobility of the selection transistor. On the basis of improving the reliability of the display product, the width of the multiplexer can be reduced, which is beneficial to the arrangement of the display substrate and can increase the screen resolution of the display substrate.

[0167] In an exemplary embodiment, Fig.15 and Fig.16The provided multiplexer, when the signal of the first selection signal line is a valid level signal, the shading structure and gate electrode of the first first selection transistor, the shading structure and gate electrode of the second first selection transistor, and the shading structure and gate electrode of the first selection transistor are respectively connected to the first selection signal line, so that the two first selection transistors and the third selection transistor are turned on, and the signal of the data output line is written to the first data signal line connected to the distributor. However, since the shading structure of the first first selection transistor and the shading structure of the first second selection transistor are an integrated structure, when the shading structure of the first first selection transistor writes the signal of the first selection signal line as a valid level signal, the shading structure of the second first selection transistor also writes the signal of the first selection signal line as a valid level signal. Due to the existence of parasitic capacitance, the first second selection transistor may be turned on, so that the first data signal line connected to the distributor will also have an output, resulting in an erroneous output. Fig.17 and Fig.18 Demultiplexers provided with Fig.15 and Fig.16 Compared with the provided multiplexer, the added third selection transistor and fourth selection transistor can make the signal of the first selection signal line a valid level signal, the third selection transistor is turned on, and the fourth selection transistor is turned off. Even if the first second selection transistor is turned on, it will not be output to the second data signal line connected to the distributor. The signal of the second selection signal line is a valid level signal, the fourth selection transistor is turned on, and the third selection transistor is turned off. Even if the first first selection transistor is turned on, it will not be output to the first data signal line connected to the distributor. The output of the multiplexer can be guaranteed to be normal, erroneous output can be avoided, and the reliability of the multiplexer is improved.

[0168] In an exemplary embodiment, in combination with Figure 7 , Figure 8 , Fig.16 , Fig.18 and Fig.19 As shown, when the light shielding pattern includes: a single-layer structure, the display substrate includes: a light shielding layer, a semiconductor layer, a first conductive layer and a second conductive layer sequentially stacked on the base 10;

[0169] The light shielding layer at least includes: a light shielding pattern for selecting a transistor;

[0170] The semiconductor layer includes at least: an active pattern of a selection transistor;

[0171] The first conductive layer includes at least: a gate electrode of a selection transistor and a selection signal line;

[0172] The second conductive layer at least includes: a data signal line, a data output line, and a first electrode and a second electrode of a selection transistor.

[0173] In an exemplary embodiment, if Fig.10 , Fig.11 , Fig.13 and Fig.14 As shown, when the light shielding pattern is a double-layer structure, the display substrate includes: a first light shielding layer, a second light shielding layer, a semiconductor layer, a first conductive layer and a second conductive layer sequentially stacked on the substrate 10;

[0174] The first light shielding layer at least includes: a first light shielding pattern for the selection transistor;

[0175] The second light shielding layer at least includes: a second light shielding pattern for the selection transistor;

[0176] The semiconductor layer includes at least: an active pattern of a selection transistor;

[0177] The first conductive layer includes at least: a gate electrode of a selection transistor and a selection signal line;

[0178] The second conductive layer at least includes: a data signal line, a data output line, a first electrode and a second electrode of a selection transistor.

[0179] In an exemplary embodiment, Fig. 20 The structure of the display area is shown in FIG. Figure 1 , Fig.21 The structure of the display area is shown in FIG. Figure 2 .like Figure 8 , Fig.11 , Fig.14 , Fig.19 Fig. 20 and Fig.21 As shown, the display substrate may further include: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a first planar layer 14, a fourth insulating layer 15 and a second planar layer 15. The first insulating layer 11 is located between the light shielding layer and the semiconductor layer, the second insulating layer 12 is located between the semiconductor layer and the first conductive layer, the third insulating layer 13 is located between the first conductive layer and the second conductive layer, and the first planar layer 14, the fourth insulating layer 15 and the second planar layer 15 are sequentially stacked on a side of the third insulating layer 13 away from the substrate 10.

[0180] In an exemplary embodiment, the first insulating layer 11 may be a single-layer structure or a multi-layer structure. When the light shielding pattern is a single-layer structure, the first insulating layer 11 is a single-layer structure. When the light shielding pattern is a double-layer structure, the first insulating layer 11 is a double-layer structure. In this case, the first insulating layer 11 may include: a first sub-insulating layer 111 and a second sub-insulating layer 112, wherein the first sub-insulating layer 111 is located between the first light shielding layer and the second light shielding layer, and the second sub-insulating layer 112 is located between the second light shielding layer and the semiconductor layer.

[0181] In an exemplary embodiment, the display substrate includes: a driving structure layer. When the light shielding structure is a single-layer structure, the driving structure layer includes: a light shielding layer, a semiconductor layer, a first conductive layer, and a second conductive layer. When the light shielding structure is a double-layer structure, the driving structure layer includes: a first light shielding layer, a second light shielding layer, a semiconductor layer, a first conductive layer, and a second conductive layer.

[0182] In an exemplary embodiment, if Fig. 20 As shown, when the display substrate is an array substrate, the driving structure layer may further include: a transistor 21, a pixel electrode 22 and a common electrode 23 located in the display area. The orthographic projection of the pixel electrode 22 on the substrate and the orthographic projection of the common electrode 23 on the substrate at least partially overlap. The pixel electrode may be electrically connected to the transistor 21 and located on the side of the second flat layer away from the substrate, and the common electrode may be located between the fourth insulating layer and the second flat layer. Exemplarily, the gate electrode of the transistor located in the display area is arranged in the same layer as the gate electrode of the control transistor in the non-display area, the active pattern of the transistor located in the display area is arranged in the same layer as the active pattern of the control transistor in the non-display area, and the first and second electrodes of the transistor located in the display area are arranged in the same layer as the first and second electrodes of the control transistor in the non-display area.

[0183] In an exemplary embodiment, if Fig.21 As shown, when the display substrate is an organic light-emitting display substrate, the driving structure layer may further include: a driving circuit located in the display area, and the display substrate may further include: a light-emitting structure layer, and the light-emitting structure layer includes: a light-emitting device. The driving circuit includes a plurality of transistors 31, and the light-emitting device is electrically connected to the driving circuit and is located on a side of the driving circuit away from the display area. The light-emitting structure layer may include: a pixel definition layer 32, a first electrode 33, an organic light-emitting layer 34, and a second electrode 35. Exemplarily, the gate electrode of the transistor located in the display area is arranged in the same layer as the gate electrode of the control transistor in the non-display area, the active pattern of the transistor located in the display area is arranged in the same layer as the active pattern of the control transistor in the non-display area, and the first and second electrodes of the transistor located in the display area are arranged in the same layer as the first and second electrodes of the control transistor in the non-display area.

[0184] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0185] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate. The display substrate may include other film layers, such as a touch control structure layer, etc., which are not limited in the present disclosure.

[0186] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0187] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0188] The following is an explanation of a distributor Figure 7 , Fig.16 and Fig.18 The preparation process of the display substrate provided, Figure 7 , Fig.16 and Fig.18 The light shielding pattern in the display substrate is a single-layer structure. A preparation process of a display substrate provided by an exemplary embodiment may include:

[0189] (1) forming a light shielding layer pattern on a substrate, including: depositing a light shielding film on the substrate, and patterning the light shielding film through a patterning process to form a light shielding layer pattern, such as Figure 22 to Figure 24 As shown, Fig. 22 for Figure 7 Schematic diagram of the light shielding layer pattern in Fig.23 for Fig.16 Schematic diagram of the light shielding layer pattern in Fig.24 for Fig.18 Schematic diagram of the light-shielding layer pattern in FIG.

[0190] In an exemplary embodiment, if Fig. 22 As shown, the light shielding layer pattern may include at least: a light shielding pattern LS1 of a first selection transistor and a light shielding pattern LS2 of a second selection transistor located in at least one dispenser.

[0191] In an exemplary embodiment, if Fig. 22 As shown, the light shielding pattern LS1 of the first selection transistor and the light shielding pattern LS2 of the second selection transistor in the same distributor are separately provided and arranged along the second direction D2.

[0192] In an exemplary embodiment, if Fig. 22 As shown, a protruding connection portion may be provided on one side of the light shielding pattern LS1 of the first selection transistor and the light shielding pattern LS2 of the second selection transistor close to the display area.

[0193] In an exemplary embodiment, if Fig. 22 As shown, the light shielding pattern LS1 of the first selection transistor may be in a strip shape and may extend along the first direction D1. The light shielding pattern LS2 of the second selection transistor may be in a strip shape and may extend along the first direction D1.

[0194] In an exemplary embodiment, if Fig. 22 As shown, the light shielding pattern LS1 of the first selection transistor and the light shielding pattern LS2 of the second selection transistor may be symmetrical with respect to the first virtual straight line.

[0195] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the light shielding layer pattern may include at least: a light shielding pattern LS1-1 of a first first selection transistor located in at least one distributor, a light shielding pattern LS1-2 of a second first selection transistor, a light shielding pattern LS2-1 of a first second selection transistor, and a light shielding pattern LS2-2 of a second second selection transistor.

[0196] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the shading pattern LS1-1 of the first first selection transistor and the shading pattern LS2-1 of the first second selection transistor in the same distributor are integrated. The shading pattern LS1-2 of the second first selection transistor and the shading pattern LS2-2 of the second second selection transistor are separately set and arranged along the second direction D2.

[0197] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the shape of the first light shielding pattern LS1-1 of the first first selection transistor (also the first light shielding pattern LS2-1 of the second selection transistor) can be block-shaped, and two protruding connecting parts are provided on the side away from the non-display area.

[0198] In an exemplary embodiment, if Fig.23 and Fig.24As shown, the shading pattern LS1-2 of the second first selection transistor and the shading pattern LS2-2 of the second second selection transistor are located on the side of the protruding connection portion away from the display area. The shading pattern LS1-2 of the second first selection transistor and one of the protruding connection portions are arranged along the first direction D1. The shading pattern LS2-2 of the second second selection transistor and the other protruding connection portion are arranged along the first direction D1.

[0199] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the light shielding pattern LS1 - 2 of the second first selection transistor and the light shielding pattern LS2 - 2 of the second second selection transistor may be in the shape of strips and extend along the first direction D1 .

[0200] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the light shielding pattern LS1 - 1 of the first first selection transistor (also the light shielding pattern LS2 - 1 of the first second selection transistor) is an axisymmetric structure, and the axis of symmetry extends along the first direction D1 .

[0201] In an exemplary embodiment, if Fig.23 and Fig.24 As shown, the light shielding pattern LS1 - 2 of the second first selection transistor and the light shielding pattern LS2 - 2 of the second second selection transistor may be symmetrical with respect to the second virtual straight line.

[0202] In an exemplary embodiment, if Fig.24 As shown, the light shielding layer pattern may further include: a light shielding pattern LS3 of a third selection transistor and a light shielding pattern LS4 of a fourth selection transistor located in at least one distributor.

[0203] In an exemplary embodiment, if Fig.24 As shown, the light shielding pattern LS3 of the third selection transistor and the light shielding pattern LS4 of the fourth selection transistor in the same distributor are separately provided and arranged along the second direction D2. The light shielding pattern LS3 of the third selection transistor and the light shielding pattern LS4 of the fourth selection transistor are located on the side of the light shielding pattern LS1-1 of the first first selection transistor (also the light shielding pattern LS2-1 of the first second selection transistor) close to the display area.

[0204] In an exemplary embodiment, if Fig.24 As shown, the light shielding pattern LS3 of the third selection transistor may be in the shape of a Chinese character "┌". The light shielding pattern LS4 of the fourth selection transistor may be in the shape of a Chinese character "┐".

[0205] In an exemplary embodiment, if Fig.24As shown, the light shielding pattern LS3 of the third selection transistor and the light shielding pattern LS4 of the fourth selection transistor may be symmetrical with respect to the second virtual straight line.

[0206] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate of the aforementioned pattern, patterning the semiconductor film through a patterning process, and forming a first insulating layer covering the light shielding layer and a semiconductor layer pattern located on the first insulating layer, such as Figures 25 to 30 shown. Fig.25 for Figure 7 Schematic diagram of the semiconductor layer pattern in Fig.26 for Figure 7 Schematic diagram after forming a semiconductor layer pattern, Fig. 27 for Fig.16 Schematic diagram of the semiconductor layer pattern in Fig.28 for Fig.16 Schematic diagram after forming a semiconductor layer pattern, Fig.29 for Fig.18 Schematic diagram of the semiconductor layer pattern in Fig.30 for Fig.18 Schematic diagram after patterning the semiconductor layer.

[0207] In an exemplary embodiment, if Fig.25 and Fig.26 As shown, the semiconductor layer pattern may include at least an active pattern T11 of a first selection transistor and an active pattern T21 of a second selection transistor located at least in the distributor.

[0208] In an exemplary embodiment, if Fig.25 and Fig.26 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor are separately provided and arranged along the second direction D2.

[0209] In an exemplary embodiment, if Fig.25 and Fig.26 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor may be strip-shaped and extend along the first direction D1.

[0210] In an exemplary embodiment, if Fig.25 and Fig.26 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor are symmetrical with respect to the first virtual straight line.

[0211] In an exemplary embodiment, if Fig.26As shown, the orthographic projection of the light shielding pattern of the first selection transistor on the substrate covers the orthographic projection of the active pattern T11 of the first selection transistor on the substrate. The orthographic projection of the light shielding pattern of the second selection transistor on the substrate covers the orthographic projection of the active pattern T21 of the second selection transistor on the substrate.

[0212] In an exemplary embodiment, the active pattern of the transistor may include a first region, a second region, and a channel region between the first region and the second region. Fig.25 and Fig.26 As shown, a first region T11_1 of an active pattern T11 of a first selection transistor, a second region T11_2 of an active pattern T11 of a first selection transistor, a first region T21_1 of an active pattern T21 of a second selection transistor, and a second region T21_2 of an active pattern T21 of a second selection transistor are separately provided.

[0213] In an exemplary embodiment, if Figures 27 to 30 As shown, the semiconductor layer pattern may include at least: an active pattern T11-1 of a first first selection transistor located at least in the distributor, an active pattern T11-2 of a second first selection transistor, an active pattern T21-1 of a first second selection transistor, and an active pattern T21-2 of a second second selection transistor.

[0214] In an exemplary embodiment, if Figures 26 to 30 As shown, the first active pattern T11-1 of the first selection transistor and the first active pattern T21-1 of the second selection transistor are integrated, and the second active pattern T11-2 of the first selection transistor and the second active pattern T21-2 of the second selection transistor are separately provided and arranged along the second direction D2.

[0215] In an exemplary embodiment, if Figures 26 to 30 As shown, the active pattern T11-1 of the first first selection transistor (also the active pattern T21-1 of the first second selection transistor) may be in the shape of a stripe and extend along the first direction D1. The active pattern T11-2 of the second first selection transistor and the active pattern T21-2 of the second second selection transistor may be in the shape of a stripe and extend along the first direction D1.

[0216] In an exemplary embodiment, if Figures 26 to 30 As shown, the active pattern T11-1 of the first first selection transistor (also the active pattern T21-1 of the first second selection transistor) can be an axisymmetric structure, and the symmetry axis extends along the first direction D1. The active pattern T112 of the second first selection transistor and the active pattern T21-2 of the second second selection transistor are symmetrical with respect to the second virtual straight line.

[0217] In an exemplary embodiment, if Figures 26 to 30 As shown, the orthographic projection of the light shielding pattern of the first first selection transistor (also the light shielding pattern of the first second selection transistor) on the substrate covers the orthographic projection of the active pattern T11-1 of the first first selection transistor (also the active pattern T21-1 of the first second selection transistor) on the substrate. The orthographic projection of the light shielding pattern of the second first selection transistor on the substrate covers the orthographic projection of the active pattern T21-1 of the second first selection transistor on the substrate. The orthographic projection of the light shielding pattern of the second second selection transistor on the substrate covers the orthographic projection of the active pattern T21-2 of the second second selection transistor on the substrate.

[0218] In an exemplary embodiment, the active pattern of the transistor may include a first region, a second region, and a channel region between the first region and the second region. Figures 26 to 30 As shown, the first area T11-1_1 of the active pattern T11-1 of the first first selection transistor and the first area T21-1_1 of the active pattern T21-1 of the first second selection transistor are an integrated structure, the second area T11-1_2 of the active pattern T11 of the first first selection transistor, the second area T21-1_2 of the active pattern T21 of the first second selection transistor, the first area T11-2_1 and the second area T11-2_2 of the active pattern T11-2 of the second first selection transistor, and the first area T21-2_1 and the second area T21-2_2 of the active pattern T21-2 of the second second selection transistor are separately set.

[0219] In an exemplary embodiment, if Fig.29 and Fig.30 As shown, the semiconductor layer pattern may further include at least: an active pattern T31 of a third selection transistor and an active pattern T41 of a fourth selection transistor located at least in the distributor.

[0220] In an exemplary embodiment, if Fig.29 and Fig.30 As shown, the active pattern T31 of the third selection transistor and the active pattern T41 of the fourth selection transistor are separately provided and arranged along the second direction D2.

[0221] In an exemplary embodiment, if Fig.29 and Fig.30 As shown, the active pattern T31 of the third selection transistor and the active pattern T41 of the fourth selection transistor may be strip-shaped and extend along the first direction D1.

[0222] In an exemplary embodiment, if Fig.29 and Fig.30As shown, the active pattern T31 of the third selection transistor and the active pattern T41 of the fourth selection transistor are symmetrical with respect to the second virtual straight line.

[0223] In an exemplary embodiment, if Fig.29 and Fig.30 As shown, the orthographic projection of the light shielding pattern of the third selection transistor on the substrate covers the orthographic projection of the active pattern T31 of the third selection transistor on the substrate. The orthographic projection of the light shielding pattern of the fourth selection transistor on the substrate covers the orthographic projection of the active pattern T41 of the fourth selection transistor on the substrate.

[0224] In an exemplary embodiment, the active pattern of the transistor may include a first region, a second region, and a channel region between the first region and the second region. Fig.29 and Fig.30 As shown, the first and second regions T31_1 and T31_2 of the active pattern T31 of the third selection transistor and the first and second regions T41_1 and T41_2 of the active pattern T41 of the fourth selection transistor are separately provided.

[0225] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, and forming a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern located on the second insulating layer, such as Figure 31 to Figure 36 As shown, Figure 31 to Figure 36 shown. Fig.31 for Figure 7 A schematic diagram of the first conductive layer pattern in FIG. Fig.32 for Figure 7 A schematic diagram after forming the first conductive layer pattern, Fig.33 for Fig.16 A schematic diagram of the first conductive layer pattern in FIG. Fig.34 for Fig.16 A schematic diagram after forming the first conductive layer pattern, Fig.35 for Fig.18 A schematic diagram of the first conductive layer pattern in FIG. Fig.36 for Fig.18 Schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a gate metal layer.

[0226] In an exemplary embodiment, if Fig.31 and Fig.32 As shown, the first conductive layer pattern may include at least: a first selection signal line MUX1, a second selection signal line MUX2, and a gate electrode T12 of a first selection transistor and a gate electrode T22 of a second selection transistor located in at least one distributor.

[0227] In an exemplary embodiment, if Fig.31 and Fig.32 As shown, the first selection signal line MUX1 and the gate electrode T12 of the first selection transistor are an integrated structure. The first selection signal line MUX1 and the second selection signal line MUX2 are located on the side of the distributor close to the display area. The gate electrode T12 of the first selection transistor and the gate electrode T22 of the second selection transistor are arranged along the second direction D2.

[0228] In an exemplary embodiment, if Fig.31 and Fig.32 As shown, the first selection signal line MUX1 and the second selection signal line MUX2 extend along the second direction D2 and are arranged along the first direction D1.

[0229] In an exemplary embodiment, if Fig.31 and Fig.32 As shown, the gate electrode T12 of the first selection transistor and the gate electrode T22 of the second selection transistor are strip-shaped and extend along the first direction D1.

[0230] In an exemplary embodiment, the first selection signal line MUX1 and the second selection signal line MUX2 can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the distributor structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0231] In an exemplary embodiment, the gate electrode T12 of the first selection transistor is disposed across the active pattern of the first selection transistor, and the gate electrode T22 of the second selection transistor is disposed across the active pattern of the second selection transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0232] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first selection transistor and the second selection transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active pattern of any one of the first selection transistor and the second selection transistor are both conductorized.

[0233] In an exemplary embodiment, if Figure 33 to Figure 36As shown, the first conductive layer pattern may at least include: a first sub-selection signal line MUX1A and a second sub-selection signal line MUX1B of a first selection signal line, a first sub-selection signal line MUX2A and a second sub-selection signal line MUX2B of a second selection signal line, and a gate electrode T12-1 of a first first selection transistor, a gate electrode T12-2 of a second first selection transistor, a gate electrode T22-1 of a first second selection transistor, and a gate electrode T22-2 of a second second selection transistor located in at least one distributor,

[0234] In an exemplary embodiment, if Figure 33 to Figure 36 As shown, the first sub-selection signal line MUX1A of the first selection signal line and the gate electrode T12-1 of the first first selection transistor are an integrated structure. The second sub-selection signal line MUX1B of the first selection signal line, the second sub-selection signal line MUX1B of the first selection signal line, the first sub-selection signal line MUX2A and the second sub-selection signal line MUX2B of the second selection signal line, the gate electrode T12-2 of the second first selection transistor, the gate electrode T22-1 of the first second selection transistor, and the gate electrode T22-2 of the second second selection transistor are separately provided.

[0235] In an exemplary embodiment, if Figure 33 to Figure 36 As shown, the gate electrode T12-1 of the first first selection transistor and the gate electrode T22-1 of the first second selection transistor are arranged along the second direction D2. The gate electrode T12-2 of the second first selection transistor and the gate electrode T22-2 of the second second selection transistor are arranged along the second direction D2. The gate electrode T12-1 of the first first selection transistor and the gate electrode T22-1 of the first second selection transistor are located on the side of the gate electrode T12-2 of the second first selection transistor and the gate electrode T22-2 of the second second selection transistor close to the display area, the first sub-selection signal line MUX1A of the first selection signal line and the first sub-selection signal line MUX2A of the second selection signal line are located on the side of the gate electrode T22-1 of the first second selection transistor close to the display area, and the second sub-selection signal line MUX1B of the first selection signal line and the second sub-selection signal line MUX2B of the second selection signal line are located on the side of the gate electrode T22-2 of the second second selection transistor away from the display area.

[0236] In an exemplary embodiment, if Figure 33 to Figure 36 As shown, the first sub-selection signal line MUX1A of the first selection signal line and the second sub-selection signal line MUX1B of the second selection signal line are in a line shape and extend along the second direction D2.

[0237] In an exemplary embodiment, if Fig.33and Fig.34 As shown, the shape of the first sub-selection signal line MUX2A of the second selection signal line is a line shape and extends along the second direction D2.

[0238] In an exemplary embodiment, if Fig.35 and Fig.36 As shown, the first sub-selection signal line MUX2A of the second selection signal line includes: a main body extending along the second direction D2 and a signal connection part. The main body is in a straight line shape and extends along the second direction D2. The signal connection part is located on one side of the main body close to the display area and is in a folded line shape.

[0239] In an exemplary embodiment, if Figure 33 to Figure 36 As shown, the gate electrode T12 - 1 of the first first selection transistor and the gate electrode T22 - 1 of the first second selection transistor are strip-shaped and extend along the first direction D1 .

[0240] In an exemplary embodiment, if Figure 33 to Figure 36 As shown, the gate electrode T12-2 of the second first selection transistor and the gate electrode T22-2 of the second second selection transistor are groove-shaped, and the opening of the gate electrode T12-2 of the second first selection transistor faces the gate electrode T22-2 of the second second selection transistor, and the opening of the groove of the gate electrode T22-2 of the second second selection transistor faces the gate electrode T12-2 of the second first selection transistor.

[0241] In an exemplary embodiment, if Fig.33 and Fig.36 As shown, the gate electrode T12 - 2 of the second first selection transistor and the gate electrode T22 - 2 of the second second selection transistor are symmetrical with respect to the second virtual straight line.

[0242] In an exemplary embodiment, the first sub-selection signal line MUX1A and the second sub-selection signal line MUX1B of the first selection signal line, and the first sub-selection signal line MUX2A and the second sub-selection signal line MUX2B of the second selection signal line can be designed with equal width, or can be designed with unequal width, and can be straight lines or broken lines, which can not only facilitate the layout of the distributor structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0243] In an exemplary embodiment, the gate electrode T12-1 of the first first selection transistor is arranged across the active pattern of the first first selection transistor, the gate electrode T12-2 of the second first selection transistor is arranged across the active pattern of the first first selection transistor, the gate electrode T22-1 of the first second selection transistor is arranged across the active pattern of the second selection transistor, and the gate electrode T22-2 of the second second selection transistor is arranged across the active pattern of the second selection transistor, that is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0244] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, and the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first selection transistor and the second selection transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active pattern of any one of the first first selection transistor, the second first selection transistor, the first second selection transistor and the second second selection transistor are both conductorized.

[0245] In an exemplary embodiment, if Fig.35 and Fig.36 As shown, the first conductive layer pattern may further include: a gate electrode T32 of a third selection transistor and a gate electrode T42 of a fourth selection transistor located in at least one distributor.

[0246] In an exemplary embodiment, if Fig.35 and Fig.36 As shown, the gate electrode T42 of the fourth selection transistor is integrated with the first sub-selection signal line MUX2A of the second selection signal line. The gate electrode T32 of the third selection transistor is separately provided and arranged with the gate electrode T42 of the fourth selection transistor along the second direction D2.

[0247] In an exemplary embodiment, if Fig.35 and Fig.36 As shown, the gate electrode T32 of the third selection transistor and the gate electrode T42 of the fourth selection transistor are located on a side of the first sub-selection signal line MUX2A of the second selection signal line close to the display area.

[0248] In an exemplary embodiment, if Fig.35 and Fig.36 As shown, the gate electrode T42 of the fourth selection transistor is connected to the signal connection portion of the first sub-selection signal line MUX2A of the second selection signal line.

[0249] In an exemplary embodiment, if Fig.35 and Fig.36As shown, the gate electrode T32 of the third selection transistor and the gate electrode T42 of the fourth selection transistor are in the shape of strips and extend along the second direction D2.

[0250] In an exemplary embodiment, if Fig.35 and Fig.36 As shown, the gate electrode T32 of the third selection transistor and the gate electrode T42 of the fourth selection transistor are symmetrical with respect to the second virtual straight line.

[0251] In an exemplary embodiment, the gate electrode T32 of the third selection transistor is disposed across the active pattern of the third selection transistor, and the gate electrode T42 of the fourth selection transistor is disposed across the active pattern of the fourth selection transistor.

[0252] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the first conductive layer, wherein a plurality of via holes are provided on the third insulating layer, such as Figure 37 to Figure 39 As shown, Fig.37 for Figure 7 A schematic diagram of a third insulating layer pattern in FIG. Fig.38 for Fig.16 A schematic diagram of a third insulating layer pattern in FIG. Fig.39 for Fig.18 Schematic diagram of the third insulating layer pattern in FIG.

[0253] In an exemplary embodiment, if Fig.37 As shown, the plurality of via holes in the third insulating layer may include at least: a first via hole V1 to a ninth via hole V9 located in at least one distributor.

[0254] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the first selection transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the light-shielding pattern of the first selection transistor, and the first via hole V1 is configured to connect a subsequently formed first connecting line to the light-shielding pattern of the first selection transistor through the via hole.

[0255] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the second selection transistor on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the light-shielding pattern of the second selection transistor, and the second via hole V2 is configured to connect a subsequently formed second connecting line to the light-shielding pattern of the second selection transistor through the via hole.

[0256] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first selection transistor on the substrate, the second insulating layer in the third via hole V3 is etched away to expose the surface of the first area of ​​the active pattern of the first selection transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed first selection transistor (also the first electrode of the second selection transistor) to the first area of ​​the active pattern of the first selection transistor through the via hole.

[0257] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first selection transistor on the substrate, the second insulating layer in the fourth via V4 is etched away to expose the surface of the second area of ​​the active pattern of the first selection transistor, and the fourth via V4 is configured to connect the second electrode of the subsequently formed first selection transistor to the second area of ​​the active pattern of the first selection transistor through the via.

[0258] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second selection transistor on the substrate, the second insulating layer in the fifth via V5 is etched away to expose the surface of the first area of ​​the active pattern of the second selection transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed first selection transistor (also the first electrode of the second selection transistor) to the first area of ​​the active pattern of the second selection transistor through the via.

[0259] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second selection transistor on the substrate, the second insulating layer in the sixth via V6 is etched away to expose the surface of the second area of ​​the active pattern of the second selection transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed second selection transistor to the second area of ​​the active pattern of the second selection transistor through the via.

[0260] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the gate electrode of the second selection transistor on the substrate, the seventh via V7 exposes the surface of the gate electrode of the second selection transistor, and the seventh via V7 is configured to connect a subsequently formed third connecting line to the gate electrode of the second selection transistor through the via.

[0261] In an exemplary embodiment, if Fig.37As shown, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the first selection signal line on the substrate, the eighth via V8 exposes the surface of the first selection signal line, and the eighth via V8 is configured to connect the subsequently formed first connection line to the first selection signal line through the via.

[0262] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the second selection signal line on the substrate, the ninth via V9 exposes the surface of the second selection signal line, and the ninth via V9 is configured to connect the subsequently formed second connection line and the third connection line to the second selection signal line through the via.

[0263] In an exemplary embodiment, if Fig.37 As shown, the number of any one of the third via hole V3, the fourth via hole V4, the fifth via hole V5 and the sixth via hole V6 is at least one, illustratively, it can be one, or it can be multiple, and they are arranged along the first direction D1. Fig.37 The description is made by taking the case where any one of the third via hole V3 , the fourth via hole V4 , the fifth via hole V5 and the sixth via hole V6 is multiple as an example.

[0264] In an exemplary embodiment, if Fig.38 As shown, the plurality of via holes in the third insulating layer may include at least: a first via hole V1 to a seventeenth via hole V17 located in at least one distributor.

[0265] In an exemplary embodiment, if Fig.39 As shown, the plurality of via holes in the third insulating layer may include at least: a first via hole V1 to a twenty-sixth via hole V26 located in at least one distributor.

[0266] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the first first selection transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the light-shielding pattern of the first first selection transistor, and the first via hole V1 is configured to connect the second electrode of the subsequently formed second first selection transistor to the light-shielding pattern of the first first selection transistor through the via hole.

[0267] In an exemplary embodiment, if Fig.38 and Fig.39As shown, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the first second selection transistor on the substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the light-shielding pattern of the first second selection transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed second second selection transistor to the light-shielding pattern of the second selection transistor through the via.

[0268] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the second first selection transistor on the substrate, the first insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the light-shielding pattern of the second first selection transistor, and the third via hole V3 is configured to connect the first electrode of the second first selection transistor formed subsequently to the light-shielding pattern of the second first selection transistor through the via hole.

[0269] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the second second selection transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the light-shielding pattern of the second second selection transistor, and the fourth via hole V4 is configured to connect the first electrode of the second second selection transistor formed subsequently to the light-shielding pattern of the second second selection transistor through the via hole.

[0270] In an exemplary embodiment, if Fig.37 As shown, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first first selection transistor (also the first area of ​​the active pattern of the first second selection transistor) on the substrate, the second insulating layer in the fifth via V5 is etched away to expose the surface of the first area of ​​the active pattern of the first first selection transistor (also the first area of ​​the active pattern of the first second selection transistor), and the fifth via V5 is configured to connect the first electrode of the subsequently formed first first selection transistor (also the first electrode of the first second selection transistor) to the first area of ​​the active pattern of the first first selection transistor (also the first area of ​​the active pattern of the first second selection transistor) through the via.

[0271] In an exemplary embodiment, if Fig.38 and Fig.39As shown, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first first selection transistor on the substrate, the second insulating layer in the sixth via V6 is etched away to expose the surface of the second area of ​​the active pattern of the first first selection transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed first first selection transistor to the second area of ​​the active pattern of the first first selection transistor through the via.

[0272] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first second selection transistor on the substrate, the second insulating layer in the seventh via V7 is etched away to expose the surface of the second area of ​​the active pattern of the first second selection transistor, and the seventh via V7 is configured to connect the second electrode of the first second selection transistor formed subsequently to the second area of ​​the active pattern of the second selection transistor through the via.

[0273] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second first selection transistor on the substrate, the second insulating layer in the eighth via V8 is etched away to expose the surface of the first area of ​​the active pattern of the second first selection transistor, and the eighth via V8 is configured to connect the first electrode of the subsequently formed second first selection transistor to the first area of ​​the active pattern of the second first selection transistor through the via.

[0274] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second first selection transistor on the substrate, the second insulating layer in the ninth via V9 is etched away to expose the surface of the second area of ​​the active pattern of the second first selection transistor, and the ninth via V9 is configured to connect the second electrode of the subsequently formed second first selection transistor to the second area of ​​the active pattern of the second first selection transistor through the via.

[0275] In an exemplary embodiment, if Fig.38 and Fig.39As shown, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second second selection transistor on the substrate, the second insulating layer in the tenth via hole V10 is etched away to expose the surface of the first area of ​​the active pattern of the second second selection transistor, and the tenth via hole V10 is configured to connect the first electrode of the second second selection transistor formed subsequently to the first area of ​​the active pattern of the second second selection transistor through the via hole.

[0276] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second second selection transistor on the substrate, the second insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second area of ​​the active pattern of the second second selection transistor, and the eleventh via hole V11 is configured to connect the second electrode of the second second selection transistor formed subsequently to the second area of ​​the active pattern of the second second selection transistor through the via hole.

[0277] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the gate electrode of the first second selection transistor on the substrate, the twelfth via hole V12 exposes the surface of the gate electrode of the first second selection transistor, and the twelfth via hole V12 is configured to connect a subsequently formed fourth connecting line to the gate electrode of the first second selection transistor through the via hole.

[0278] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the gate electrode of the second first selection transistor on the substrate, the thirteenth via V13 exposes the surface of the gate electrode of the second first selection transistor, and the thirteenth via V13 is configured to connect the first electrode of the subsequently formed second first selection transistor to the gate electrode of the second first selection transistor through the via.

[0279] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the gate electrode of the second second selection transistor on the substrate, the fourteenth via V14 exposes the surface of the gate electrode of the second second selection transistor, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed second second selection transistor to the gate electrode of the second second selection transistor through the via.

[0280] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first sub-selection signal line of the second selection signal line on the substrate, the fifteenth via V15 exposes the surface of the first sub-selection signal line of the second selection signal line, and the fifteenth via V15 is configured to connect a subsequently formed fourth connecting line to the first sub-selection signal line of the second selection signal line through the via.

[0281] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second sub-selection signal line of the first selection signal line on the substrate, the sixteenth via V16 exposes the surface of the second sub-selection signal line of the first selection signal line, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed second first selection transistor to the second sub-selection signal line of the first selection signal line through the via.

[0282] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the second sub-selection signal line of the second selection signal line on the substrate, the seventeenth via V17 exposes the surface of the second sub-selection signal line of the second selection signal line, and the seventeenth via V17 is configured to connect the first electrode of the second second selection transistor formed subsequently to the second sub-selection signal line of the second selection signal line through the via.

[0283] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the third selection transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the light-shielding pattern of the third selection transistor, and the eighteenth via hole V18 is configured to connect the subsequently formed fifth connecting line to the light-shielding pattern of the third selection transistor through the via hole.

[0284] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the light-shielding pattern of the fourth selection transistor on the substrate, the first insulating layer and the second insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the light-shielding pattern of the fourth selection transistor, and the nineteenth via hole V19 is configured to connect the subsequently formed sixth connecting line to the light-shielding pattern of the fourth selection transistor through the via hole.

[0285] In an exemplary embodiment, if Fig.39As shown, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third selection transistor on the substrate, the second insulating layer in the twentieth via V20 is etched away to expose the surface of the first area of ​​the active pattern of the third selection transistor, and the twentieth via V20 is configured to connect the first electrode of the subsequently formed third selection transistor to the first area of ​​the active pattern of the third selection transistor through the via.

[0286] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third selection transistor on the substrate, the second insulating layer in the twenty-first via V21 is etched away to expose the surface of the second area of ​​the active pattern of the third selection transistor, and the twenty-first via V21 is configured to connect the second electrode of the first first selection transistor (also the second electrode of the third selection transistor) formed subsequently to the second area of ​​the active pattern of the third selection transistor through the via.

[0287] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth selection transistor on the substrate, the second insulating layer in the twenty-second via V22 is etched away to expose the surface of the first area of ​​the active pattern of the fourth selection transistor, and the twenty-second via V22 is configured to connect the first electrode of the subsequently formed fourth selection transistor to the first area of ​​the active pattern of the fourth selection transistor through the via.

[0288] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth selection transistor on the substrate, the second insulating layer in the twenty-third via V23 is etched away to expose the surface of the second area of ​​the active pattern of the fourth selection transistor, and the twenty-third via V23 is configured to connect the second electrode of the first second selection transistor (also the second electrode of the fourth selection transistor) formed subsequently to the second area of ​​the active pattern of the fourth selection transistor through the via.

[0289] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the gate electrode of the third selection transistor on the substrate, the twenty-fourth via V24 exposes the surface of the gate electrode of the third selection transistor, and the twenty-fourth via V24 is configured to connect the subsequently formed fifth connecting line to the gate electrode of the third selection transistor through the via.

[0290] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth selection transistor on the substrate, the twenty-fifth via V25 exposes the surface of the gate electrode of the fourth selection transistor, and the twenty-fifth via V25 is configured to connect the subsequently formed sixth connecting line to the gate electrode of the fourth selection transistor through the via.

[0291] In an exemplary embodiment, if Fig.39 As shown, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first sub-selection signal line of the first selection signal line on the substrate, the twenty-sixth via V26 exposes the surface of the first sub-selection signal line of the first selection signal line, and the twenty-sixth via V26 is configured to connect the subsequently formed fifth connecting line to the first sub-selection signal line of the first selection signal line through the via.

[0292] In an exemplary embodiment, if Fig.38 and Fig.39 As shown, the number of any one of the fifth via hole V5, the sixth via hole V6 and the seventh via hole V7 is at least one. For example, the number of any one of the fifth via hole V5, the sixth via hole V6 and the seventh via hole V7 may be one, or may be multiple, and are arranged along the first direction D1. Fig.38 and Fig.39 The description is made by taking the case where any one of the fifth via hole V5 , the sixth via hole V6 and the seventh via hole V7 is plural as an example.

[0293] (5) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern disposed on the third insulating layer, such as Figures 40 to 45 shown. Fig.40 for Figure 7 A schematic diagram of a second conductive layer pattern in FIG. Fig.41 for Figure 7 A schematic diagram after forming the second conductive layer pattern, Fig.42 for Fig.16 A schematic diagram of a second conductive layer pattern in FIG. Fig.43 for Fig.16 A schematic diagram after forming the second conductive layer pattern, Fig.44 for Fig.18 A schematic diagram of a second conductive layer pattern in FIG. Fig.45 for Fig.18 Schematic diagram after forming a second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as a source-drain metal (SD) layer.

[0294] In an exemplary embodiment, if Fig.40 and Fig.41 As shown, the second conductive layer pattern may include at least: a first data signal line Data1, a second data signal line Data2 and a data output line SLn connected to the distributor, and a first electrode T13 and a second electrode T14 of a first selection transistor located in at least one distributor, a first electrode T23 and a second electrode T24 of a second selection transistor, a first connection line L1, a second connection line L2 and a third connection line L3.

[0295] In an exemplary embodiment, the first data signal line Data1 , the second data signal line Data2 , and the data output line SLn to which the distributor is connected extend in the first direction D1 .

[0296] In an exemplary embodiment, if Fig.40 and Fig.41 As shown, the first electrode T13 of the first selection transistor, the first electrode T23 of the second selection transistor and the data output line SLn are an integrated structure, the second electrode T14 of the first selection transistor and the first data signal line Data1 connected to the distributor are an integrated structure, and the second electrode T24 of the second selection transistor and the second data signal line Data2 connected to the distributor are an integrated structure.

[0297] In an exemplary embodiment, the first electrode T13 of the first selection transistor and the first electrode T23 of the second selection transistor are shaped as a groove type with an opening toward the display area. The first electrode T13 of the first selection transistor (also the first electrode T23 of the second selection transistor) is connected to the first area of ​​the active pattern of the first selection transistor through the third via hole, and is connected to the first area of ​​the active pattern of the second selection transistor through the fifth via hole.

[0298] In an exemplary embodiment, the second electrode T14 of the first selection transistor is connected to the second region of the active pattern of the first selection transistor through a fourth via hole. The second electrode T24 of the second selection transistor is connected to the second region of the active pattern of the second selection transistor through a sixth via hole.

[0299] In an exemplary embodiment, the first connection line L1 is in a strip shape and extends along the first direction D1. The first connection line L1 is connected to the light shielding pattern of the first selection transistor through the first via hole and is connected to the first selection signal line through the eighth via hole.

[0300] In an exemplary embodiment, the second connection line L2 is in a strip shape and extends along the first direction D1. The second connection line L2 is connected to the light shielding pattern of the second selection transistor through a second via hole and is connected to the second selection signal line through a ninth via hole.

[0301] In an exemplary embodiment, the third connection line L3 is in a strip shape and extends along the first direction D1. The third connection line L3 is connected to the gate electrode of the second selection transistor through the seventh via hole and is connected to the second selection signal line through the ninth via hole.

[0302] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the second conductive layer pattern may at least include: a first data signal line Data1, a second data signal line Data2 and a data output line SLn connected to the distributor, and a first electrode T13-1 and a second electrode T14-1 of a first first selection transistor, a first electrode T13-2 and a second electrode T14-2 of a second first selection transistor, a first electrode T23-1 and a second electrode T24-1 of a first second selection transistor, a first electrode T23-2 and a second electrode T24-2 of a second second selection transistor and a fourth connecting line L4 located in at least one distributor.

[0303] In an exemplary embodiment, the first data signal line Data1 , the second data signal line Data2 , and the data output line SLn to which the distributor is connected extend in the first direction D1 .

[0304] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the data output line SLn, the first electrode T13-1 of the first first selection transistor and the first electrode T23-1 of the first second selection transistor are an integrated structure. The second electrode T14-1 of the first first selection transistor and the first data signal line Data1 connected to the distributor are an integrated structure, the second electrode T24-1 of the first second selection transistor and the second data signal line Data2 connected to the distributor are an integrated structure, and the first electrode T13-2 and the second electrode T14-2 of the second first selection transistor and the first electrode T23-2 and the second electrode T24-2 of the second second selection transistor are separately provided.

[0305] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the first electrode T13-1 of the first first selection transistor (also the first electrode T23-1 of the first second selection transistor) is in a strip shape and extends D1 along the first direction. The first electrode T13-1 of the first first selection transistor (also the first electrode T23-1 of the first second selection transistor) is connected to the first region of the active pattern of the first first selection transistor (also the first region of the active pattern of the first second selection transistor) through a fifth via hole.

[0306] In an exemplary embodiment, if Figure 42 to Figure 45As shown, the second electrode T14-1 of the first first selection transistor is in a strip shape and extends along the first direction D1. The second electrode T14-1 of the first first selection transistor is connected to the second region of the active pattern of the first first selection transistor through a sixth via hole.

[0307] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the second electrode T24-1 of the first second selection transistor is in a strip shape and extends along the first direction D1. The second electrode T24-1 of the first second selection transistor is connected to the second region of the active pattern of the first second selection transistor through the seventh via hole.

[0308] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the first electrode T13-2 of the second first selection transistor is in a strip shape and extends D1 along the first direction. The first electrode T13-2 of the second first selection transistor is connected to the light shielding pattern of the second first selection transistor through the third via hole, connected to the first region of the active pattern of the second first selection transistor through the eighth via hole, connected to the gate electrode of the second first selection transistor through the thirteenth via hole, and connected to the second sub-selection signal line of the first selection signal line through the sixteenth via hole.

[0309] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the second electrode T14-2 of the second first selection transistor is in a strip shape and extends along the first direction D1. The second electrode T14-2 of the second first selection transistor is connected to the light shielding pattern of the first first selection transistor through the first via hole, and is connected to the second region of the active pattern of the second first selection transistor through the ninth via hole.

[0310] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the first electrode T23-2 of the second second selection transistor is in a strip shape and extends D1 along the first direction. The first electrode T23-2 of the second second selection transistor is connected to the light shielding pattern of the second second selection transistor through the fourth via hole, connected to the first area of ​​the active pattern of the second second selection transistor through the tenth via hole, connected to the gate electrode of the second second selection transistor through the fourteenth via hole, and connected to the second sub-selection signal line of the second selection signal line through the seventeenth via hole.

[0311] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the second electrode T24-2 of the second second selection transistor is in the shape of a strip and extends D1 along the first direction. The second electrode T24-2 of the second second selection transistor is connected to the light shielding pattern of the second selection transistor through the second via hole, and is connected to the second region of the active pattern of the second second selection transistor through the eleventh via hole.

[0312] In an exemplary embodiment, if Figure 42 to Figure 45 As shown, the fourth connection line L4 is strip-shaped and extends along the first direction D1. The fourth connection line L4 is connected to the gate electrode of the first second selection transistor through the twelfth via hole and is connected to the first sub-selection signal line of the second selection signal line through the fifteenth via hole.

[0313] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the second conductive layer pattern may further include at least: a first electrode T33 and a second electrode T34 of a third selection transistor located in at least one distributor, a first electrode T43 and a second electrode T44 of a fourth selection transistor, and a fifth connection line L5 and a sixth connection line L6.

[0314] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the second electrode T14-1 of the first first selection transistor and the second electrode T34 of the third selection transistor are integrated. The second electrode T24-1 of the first second selection transistor and the second electrode T44 of the fourth selection transistor are integrated. The first electrode T33 of the third selection transistor and the first electrode T43 of the fourth selection transistor are separately provided.

[0315] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the second electrode T14-1 of the first first selection transistor (also the second electrode T34 of the third selection transistor) is in a strip shape and extends along the first direction D1. The second electrode T14-1 of the first first selection transistor (also the second electrode T34 of the third selection transistor) is also connected to the second region of the active pattern of the third selection transistor through a twenty-first via hole.

[0316] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the second electrode T24-1 of the first second selection transistor (also the second electrode T44 of the fourth selection transistor) is in a strip shape and extends along the first direction D1. The second electrode T24-1 of the first second selection transistor (also the second electrode T44 of the fourth selection transistor) is also connected to the second region of the active pattern of the fourth selection transistor through a twenty-third via hole.

[0317] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the first electrode T33 of the third selection transistor is in a strip shape and extends along the first direction D1. The first electrode T33 of the third selection transistor is connected to the first region of the active pattern of the third selection transistor through the twentieth via hole.

[0318] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the first electrode T43 of the fourth selection transistor is in a strip shape and extends along the first direction D1. The first electrode T43 of the fourth selection transistor is connected to the first region of the active pattern of the fourth selection transistor through the twenty-second via hole.

[0319] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the fifth connection line L5 is in a zigzag shape and at least partially extends along the first direction D1. The fifth connection line L5 is connected to the light shielding pattern of the third selection transistor through the eighteenth via hole, connected to the gate electrode of the third selection transistor through the twenty-fourth via hole, and connected to the first sub-selection signal line of the first selection signal line through the twenty-sixth via hole.

[0320] In an exemplary embodiment, if Fig.44 and Fig.45 As shown, the sixth connection line L6 is in a zigzag shape and at least partially extends along the first direction D1. The sixth connection line L6 is connected to the light shielding pattern of the fourth selection transistor through the nineteenth via hole and is connected to the gate electrode of the fourth selection transistor through the twenty-fifth via hole.

[0321] (6) forming a second flat layer pattern, comprising: coating a first flat film, depositing a fourth insulating film and coating a second flat film in sequence on a substrate having the aforementioned pattern, and patterning the first flat film, the fourth insulating film and the second flat film through a patterning process to form a first flat layer, a fourth insulating layer and a second flat layer pattern covering the aforementioned pattern.

[0322] The following is an explanation of a distributor Fig.10 and Fig.13 The preparation process of the display substrate provided, Fig.10 and Fig.13 The light shielding pattern in the display substrate is a double-layer structure. A preparation process of a display substrate provided by an exemplary embodiment may include:

[0323] (1) forming a first light shielding layer pattern on a substrate, including: depositing a first light shielding film on the substrate, patterning the first light shielding film through a patterning process to form a first light shielding layer pattern, such as Fig.46 and Fig.47 As shown, Fig.46 for Fig.10 A schematic diagram of the first light shielding layer pattern in FIG. Fig.47 for Fig.13 Schematic diagram of the first light shielding layer pattern in FIG.

[0324] In an exemplary embodiment, if Fig.46 and Fig.47As shown, the light shielding layer pattern may include at least: a first light shielding pattern LS11 of a first selection transistor and a first light shielding pattern LS21 of a second selection transistor located in at least one distributor.

[0325] In an exemplary embodiment, if Fig.46 As shown, the first light shielding pattern LS11 of the first selection transistor and the first light shielding pattern LS21 of the second selection transistor located in the same distributor are an integrated structure.

[0326] In an exemplary embodiment, if Fig.46 As shown, the first light shielding pattern LS11 of the first selection transistor (also the first light shielding pattern LS21 of the second selection transistor) in the same distributor may be in a strip shape and may extend along the first direction D1.

[0327] In an exemplary embodiment, if Fig.47 As shown, the first light shielding pattern LS11 of the first selection transistor and the first light shielding pattern LS21 of the second selection transistor in the same distributor are separately provided and arranged along the second direction D2.

[0328] In an exemplary embodiment, if Fig.47 As shown, the first light-shielding pattern LS11 of the first selection transistor and the first light-shielding pattern LS21 of the second selection transistor may be strip-shaped and may extend along the first direction D1.

[0329] In an exemplary embodiment, if Fig.47 As shown, the first light-shielding pattern LS11 of the first selection transistor and the first light-shielding pattern LS21 of the second selection transistor may be symmetrical with respect to the first virtual straight line.

[0330] (2) forming a second light shielding layer pattern on the substrate, comprising: forming a first sub-insulating film and a second light shielding film on the substrate in sequence, patterning the second light shielding film by a patterning process, forming a first sub-insulating layer covering the substrate and a second light shielding layer pattern disposed on the first sub-insulating layer, such as Figures 48 to 51 As shown, Fig.48 for Fig.10 A schematic diagram of a second light shielding layer pattern in FIG. Fig.49 for Fig.10 A schematic diagram after forming the second light shielding layer pattern, Fig.50 for Fig.13 A schematic diagram of a second light shielding layer pattern in FIG. Fig.51 for Fig.13 Schematic diagram after forming the second light shielding layer pattern.

[0331] In an exemplary embodiment, if Figures 48 to 51As shown, the second light shielding layer pattern may include at least: a second light shielding pattern LS12 of a first selection transistor and a second light shielding pattern LS22 of a second selection transistor located at at least one distributor.

[0332] In an exemplary embodiment, if Figures 48 to 51 As shown, the second light shielding pattern LS12 of the first selection transistor and the second light shielding pattern LS22 of the second selection transistor in the same distributor are separately provided and arranged along the second direction D2.

[0333] In an exemplary embodiment, if Fig.48 and Fig.49 As shown, the first light-shielding pattern LS11 of the first selection transistor and the first light-shielding pattern LS21 of the second selection transistor may be strip-shaped and may extend along the first direction D1.

[0334] In an exemplary embodiment, if Fig.50 and Fig.51 As shown, the shape of the first light-shielding pattern LS11 of the first selection transistor may be “┌”, and the shape of the first light-shielding pattern LS21 of the second selection transistor may be “┐”.

[0335] In an exemplary embodiment, if Figures 48 to 51 As shown, the first light-shielding pattern LS11 of the first selection transistor and the first light-shielding pattern LS21 of the second selection transistor may be symmetrical with respect to the first virtual straight line.

[0336] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a second sub-insulating film and a semiconductor film on the substrate of the aforementioned pattern, patterning the semiconductor film through a patterning process, and forming a second sub-insulating layer covering the second light shielding layer and a semiconductor layer pattern located on the second sub-insulating layer, such as Figure 52 to Figure 55 shown. Fig.52 for Fig.10 Schematic diagram of the semiconductor layer pattern in Fig.53 for Fig.10 Schematic diagram after forming a semiconductor layer pattern, Fig.54 for Fig.13 Schematic diagram of the semiconductor layer pattern in Fig.55 for Fig.13 Schematic diagram after patterning the semiconductor layer.

[0337] In an exemplary embodiment, if Figure 52 to Figure 55 As shown, the semiconductor layer pattern may include at least an active pattern T11 of a first selection transistor and an active pattern T21 of a second selection transistor located at least in the distributor.

[0338] In an exemplary embodiment, if Fig.52 and Fig.53 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor are an integrated structure.

[0339] In an exemplary embodiment, if Fig.52 and Fig.53 As shown, the active pattern T11 of the first selection transistor (the active pattern T21 of the second selection transistor) may be in a strip shape and extend along the first direction D1.

[0340] In an exemplary embodiment, if Fig.52 and Fig.53 As shown, the orthographic projection of the light shielding pattern of the first selection transistor (the light shielding pattern of the first selection transistor) on the substrate covers the active pattern T11 of the first selection transistor (the active pattern T21 of the second selection transistor).

[0341] In an exemplary embodiment, the active pattern of the transistor may include a first region, a second region, and a channel region between the first region and the second region. Fig.52 and Fig.53 As shown, the first region T11_1 of the active pattern T11 of the first selection transistor and the first region T21_1 of the active pattern T21 of the second selection transistor are an integrated structure, and the second region T11_2 of the active pattern T11 of the first selection transistor and the second region T21_2 of the active pattern T21 of the second selection transistor are separately provided.

[0342] In an exemplary embodiment, if Fig.54 and Fig.55 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor are separately provided and arranged along the second direction D2.

[0343] In an exemplary embodiment, if Fig.54 and Fig.55 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor may be strip-shaped and extend along the first direction D1.

[0344] In an exemplary embodiment, if Fig.54 and Fig.55 As shown, the active pattern T11 of the first selection transistor and the active pattern T21 of the second selection transistor are symmetrical with respect to the first virtual straight line.

[0345] In an exemplary embodiment, if Fig.55As shown, the orthographic projection of the light shielding pattern of the first selection transistor on the substrate covers the orthographic projection of the active pattern T11 of the first selection transistor on the substrate. The orthographic projection of the light shielding pattern of the second selection transistor on the substrate covers the orthographic projection of the active pattern T21 of the second selection transistor on the substrate.

[0346] In an exemplary embodiment, the active pattern of the transistor may include a first region, a second region, and a channel region between the first region and the second region. Fig.54 and Fig.55 As shown, a first region T11_1 of an active pattern T11 of a first selection transistor, a second region T11_2 of an active pattern T11 of a first selection transistor, a first region T21_1 of an active pattern T21 of a second selection transistor, and a second region T21_2 of an active pattern T21 of a second selection transistor are separately provided.

[0347] (4) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, and forming a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern located on the second insulating layer, such as Figure 56 to Figure 59 As shown, Fig.56 for Fig.10 A schematic diagram of the first conductive layer pattern in FIG. Fig.57 for Fig.10 A schematic diagram after forming the first conductive layer pattern, Fig.58 for Fig.13 A schematic diagram of the first conductive layer pattern in FIG. Fig.59 for Fig.13 Schematic diagram after forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a gate metal layer.

[0348] In an exemplary embodiment, if Figure 56 to Figure 59 As shown, the first conductive layer pattern may include at least: a first selection signal line MUX1, a second selection signal line MUX2, and a gate electrode T12 of a first selection transistor and a gate electrode T22 of a second selection transistor located in at least one distributor.

[0349] In an exemplary embodiment, if Fig.56 and Fig.57 As shown, the first selection signal line MUX1 and the second selection signal line MUX2 are located on a side of the distributor close to the display area. The gate electrode T12 of the first selection transistor and the gate electrode T22 of the second selection transistor are arranged along the second direction D2.

[0350] In an exemplary embodiment, if Fig.56 and Fig.57 As shown, the gate electrode T12 of the first selection transistor and the gate electrode T22 of the second selection transistor are separately provided.

[0351] In an exemplary embodiment, if Fig.56 and Fig.57 As shown, the orthographic projection of the second light shielding pattern of the first selection transistor on the substrate covers the orthographic projection of the gate electrode of the first selection transistor on the substrate. The orthographic projection of the second light shielding pattern of the second selection transistor on the substrate covers the orthographic projection of the gate electrode of the second selection transistor on the substrate.

[0352] In an exemplary embodiment, if Fig.58 and Fig.59 As shown, the first selection signal line MUX1 and the gate electrode T12 of the first selection transistor are an integrated structure.

[0353] In an exemplary embodiment, if Fig.58 and Fig.59 As shown, the orthographic projection of the second light shielding pattern of the first selection transistor on the substrate partially overlaps with the orthographic projection of the gate electrode of the first selection transistor on the substrate. The orthographic projection of the second light shielding pattern of the second selection transistor on the substrate partially overlaps with the orthographic projection of the gate electrode of the second selection transistor on the substrate.

[0354] In an exemplary embodiment, if Figure 56 to Figure 59 As shown, the length of the second light shielding pattern of the first selection transistor along the second direction is greater than the length of the gate electrode of the first selection transistor along the second direction. The length of the second light shielding pattern of the second selection transistor along the second direction is greater than the length of the gate electrode of the second selection transistor along the second direction.

[0355] In an exemplary embodiment, if Figure 56 to Figure 59 As shown, the first selection signal line MUX1 and the second selection signal line MUX2 extend along the second direction D2 and are arranged along the first direction D1.

[0356] In an exemplary embodiment, if Figure 56 to Figure 59 As shown, the gate electrode T12 of the first selection transistor and the gate electrode T22 of the second selection transistor are strip-shaped and extend along the first direction D1.

[0357] In an exemplary embodiment, the first selection signal line MUX1 and the second selection signal line MUX2 can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which can not only facilitate the layout of the distributor structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0358] In an exemplary embodiment, the gate electrode T12 of the first selection transistor is disposed across the active pattern of the first selection transistor, and the gate electrode T22 of the second selection transistor is disposed across the active pattern of the second selection transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0359] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield, the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first selection transistor and the second selection transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the active pattern of any one of the first selection transistor and the second selection transistor are both conductorized.

[0360] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer covering the first conductive layer, wherein a plurality of vias are provided on the third insulating layer, such as Fig.60 and Fig.61 As shown, Fig.60 for Fig.10 A schematic diagram of a third insulating layer pattern in FIG. Fig.61 for Fig.13 Schematic diagram of the third insulating layer pattern in FIG.

[0361] In an exemplary embodiment, if Fig.60 As shown, the plurality of via holes in the third insulating layer may include at least: a first via hole V1 to a ninth via hole V9 located in at least one distributor.

[0362] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the second light-shielding pattern of the first selection transistor on the substrate, the first insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the second light-shielding pattern of the first selection transistor, and the first via hole V1 is configured to connect a subsequently formed first connecting line to the second light-shielding pattern of the first selection transistor through the via hole.

[0363] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second light-shielding pattern of the second selection transistor on the substrate, the first insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second light-shielding pattern of the second selection transistor, and the second via hole V2 is configured to connect a subsequently formed second connecting line to the second light-shielding pattern of the second selection transistor through the via hole.

[0364] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first selection transistor (also the first area of ​​the active pattern of the second selection transistor) on the substrate, the second insulating layer in the third via V3 is etched away to expose the surface of the first area of ​​the active pattern of the first selection transistor (also the first area of ​​the active pattern of the second selection transistor), and the third via V3 is configured to connect the first electrode of the subsequently formed first selection transistor (also the first electrode of the second selection transistor) to the first area of ​​the active pattern of the first selection transistor (also the first area of ​​the active pattern of the second selection transistor) through the via.

[0365] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first selection transistor on the substrate, the second insulating layer in the fourth via V4 is etched away to expose the surface of the second area of ​​the active pattern of the first selection transistor, and the fourth via V4 is configured to connect the second electrode of the subsequently formed first selection transistor to the second area of ​​the active pattern of the first selection transistor through the via.

[0366] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second selection transistor on the substrate, the second insulating layer in the fifth via V5 is etched away to expose the surface of the second area of ​​the active pattern of the second selection transistor, and the fifth via V5 is configured to connect the second electrode of the subsequently formed second selection transistor to the second area of ​​the active pattern of the second selection transistor through the via.

[0367] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the gate electrode of the first selection transistor on the substrate, the sixth via V6 exposes the surface of the gate electrode of the first selection transistor, and the sixth via V6 is configured to connect the subsequently formed first connecting line to the gate electrode of the first selection transistor through the via.

[0368] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the gate electrode of the second selection transistor on the substrate, the seventh via V7 exposes the surface of the gate electrode of the second selection transistor, and the seventh via V7 is configured to connect a subsequently formed second connecting line to the gate electrode of the second selection transistor through the via.

[0369] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the first selection signal line on the substrate, the eighth via V8 exposes the surface of the first selection signal line, and the eighth via V8 is configured to connect the subsequently formed first connection line to the first selection signal line through the via.

[0370] In an exemplary embodiment, if Fig.60 As shown, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the second selection signal line on the substrate, the ninth via V9 exposes the surface of the second selection signal line, and the ninth via V9 is configured to connect the subsequently formed second connection line and the third connection line to the second selection signal line through the via.

[0371] In an exemplary embodiment, if Fig.60 As shown, the number of any one of the third via hole V3, the fourth via hole V4 and the fifth via hole V5 is at least one. Exemplarily, the number of any one of the third via hole V3, the fourth via hole V4 and the fifth via hole V5 may be one, or may be multiple, and are arranged along the first direction D1. Fig.60 The description is made by taking the case where any one of the third via hole V3 , the fourth via hole V4 and the fifth via hole V5 is plural.

[0372] In an exemplary embodiment, if Fig.61 As shown, the plurality of via holes in the third insulating layer may include at least: a first via hole H1 to a ninth via hole H9 located in at least one distributor.

[0373] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the first via H1 on the substrate is located within the range of the orthographic projection of the second light-shielding pattern of the first first selection transistor on the substrate, the first insulating layer and the second insulating layer in the first via H1 are etched away to expose the surface of the second light-shielding pattern of the first first selection transistor, and the first via H1 is configured to connect a subsequently formed first connecting line to the second light-shielding pattern of the first selection transistor through the via.

[0374] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the second via H2 on the substrate is located within the range of the orthographic projection of the second light-shielding pattern of the second selection transistor on the substrate, the first insulating layer and the second insulating layer in the second via H2 are etched away to expose the surface of the second light-shielding pattern of the second selection transistor, and the second via H2 is configured to connect a subsequently formed second connecting line to the second light-shielding pattern of the second selection transistor through the via.

[0375] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the third via H3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first selection transistor on the substrate, the second insulating layer in the third via H3 is etched away to expose the surface of the first area of ​​the active pattern of the first selection transistor, and the third via H3 is configured to connect the first electrode of the subsequently formed first selection transistor (also the first electrode of the second selection transistor) to the first area of ​​the active pattern of the first selection transistor through the via.

[0376] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the fourth via H4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first selection transistor on the substrate, the second insulating layer in the fourth via H4 is etched away to expose the surface of the second area of ​​the active pattern of the first selection transistor, and the fourth via H4 is configured to connect the second electrode of the subsequently formed first selection transistor to the second area of ​​the active pattern of the first selection transistor through the via.

[0377] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the fifth via H5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second selection transistor on the substrate, the second insulating layer in the fifth via H5 is etched away to expose the surface of the first area of ​​the active pattern of the second selection transistor, and the fifth via H5 is configured to connect the first electrode of the subsequently formed first selection transistor (also the first electrode of the second selection transistor) to the first area of ​​the active pattern of the second selection transistor through the via.

[0378] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the sixth via H6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second selection transistor on the substrate, the second insulating layer in the sixth via H6 is etched away to expose the surface of the second area of ​​the active pattern of the second selection transistor, and the sixth via H6 is configured to connect the second electrode of the subsequently formed second selection transistor to the second area of ​​the active pattern of the second selection transistor through the via.

[0379] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the seventh via H7 on the substrate is located within the range of the orthographic projection of the gate electrode of the second selection transistor on the substrate, the seventh via H7 exposes the surface of the gate electrode of the second selection transistor, and the seventh via H7 is configured to connect the subsequently formed third connecting line to the gate electrode of the second selection transistor through the via.

[0380] In an exemplary embodiment, if Fig.61As shown, the orthographic projection of the eighth via H8 on the substrate is within the range of the orthographic projection of the first selection signal line on the substrate, the eighth via H8 exposes the surface of the first selection signal line, and the eighth via H8 is configured to connect the subsequently formed first connection line to the first selection signal line through the via.

[0381] In an exemplary embodiment, if Fig.61 As shown, the orthographic projection of the ninth via H9 on the substrate is within the range of the orthographic projection of the second selection signal line on the substrate, the ninth via H9 exposes the surface of the second selection signal line, and the ninth via H9 is configured to connect the subsequently formed second connection line and the third connection line to the second selection signal line through the via.

[0382] In an exemplary embodiment, if Fig.61 As shown, the number of any one of the third via hole H3, the fourth via hole H4, the fifth via hole H5 and the sixth via hole H6 is at least one. For example, the number of any one of the third via hole H3, the fourth via hole H4, the fifth via hole H5 and the sixth via hole H6 may be one, or may be multiple, and are arranged along the first direction D1. Fig.61 The description is made by taking the case where any one of the third via hole H3 , the fourth via hole H4 , the fifth via hole H5 and the sixth via hole H6 is plural as an example.

[0383] (6) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern disposed on the third insulating layer, such as Figure 62 to Figure 65 shown. Fig.62 for Fig.10 A schematic diagram of a second conductive layer pattern in FIG. Fig.63 for Fig.10 A schematic diagram after forming the second conductive layer pattern, Fig.64 for Fig.13 A schematic diagram of a second conductive layer pattern in FIG. Fig.65 for Fig.13 Schematic diagram after forming a second conductive layer pattern. In an exemplary embodiment, the second conductive layer may be referred to as a source-drain metal (SD) layer.

[0384] In an exemplary embodiment, if Figure 62 to Figure 65 As shown, the second conductive layer pattern may include at least: a first data signal line Data1, a second data signal line Data2 and a data output line SLn connected to the distributor, and a first electrode T13 and a second electrode T14 of a first selection transistor located in at least one distributor, a first electrode T23 and a second electrode T24 of a second selection transistor, and a first connection line L1 and a second connection line L2.

[0385] In an exemplary embodiment, if Fig.64 and Fig.65 As shown, the second conductive layer pattern may at least include: a third connection line L3.

[0386] In an exemplary embodiment, the first data signal line Data1 , the second data signal line Data2 , and the data output line SLn to which the distributor is connected extend in the first direction D1 .

[0387] In an exemplary embodiment, the data output line SLn, the first electrode T13 of the first selection transistor and the first electrode T23 of the second selection transistor are an integrated structure, the second electrode T14 of the first selection transistor and the first data signal line Data1 connected to the distributor are an integrated structure, and the second electrode T24 of the second selection transistor and the second data signal line Data2 connected to the distributor are an integrated structure.

[0388] In an exemplary embodiment, if Fig.62 and Fig.63 As shown, the shapes of the first electrode T13 of the first selection transistor and the first electrode T23 of the second selection transistor are line shapes.

[0389] In an exemplary embodiment, if Fig.64 and Fig.65 As shown, the shapes of the first electrode T13 of the first selection transistor and the first electrode T23 of the second selection transistor are groove types with their openings facing the display area.

[0390] In an exemplary embodiment, if Figure 62 to Figure 65 As shown, the first electrode T13 of the first selection transistor (also the first electrode T23 of the second selection transistor) at least partially extends along the first direction D1. Fig.63 As shown, the first electrode T13 of the first selection transistor (also the first electrode T23 of the second selection transistor) is connected to the first area of ​​the active pattern of the first selection transistor (also the first area of ​​the active pattern of the second selection transistor) through the third via hole, as shown in FIG. Fig.65 As shown, the first electrode T13 of the first selection transistor (also the first electrode T23 of the second selection transistor) is connected to the first area of ​​the active pattern of the first selection transistor through the third via hole, and is connected to the first area of ​​the active pattern of the second selection transistor through the fifth via hole.

[0391] In an exemplary embodiment, if Fig.62 and Fig.63 As shown, the shape of the first electrode T13 of the first selection transistor (also the first electrode T23 of the second selection transistor) may be a line shape.

[0392] In an exemplary embodiment, if Fig.64 and Fig.65 As shown, the shape of the first electrode T13 of the first selection transistor (also the first electrode T23 of the second selection transistor) can be a zigzag line.

[0393] In an exemplary embodiment, if Figure 62 to Figure 65 As shown, the second electrode T14 of the first selection transistor is in a strip shape and extends along the first direction D1. Fig.63 and Fig.65 As shown, the second electrode T14 of the first selection transistor is connected to the second region of the active pattern of the first selection transistor through a fourth via hole.

[0394] In an exemplary embodiment, if Figure 62 to Figure 65 As shown, the second electrode T24 of the second selection transistor is in the shape of a strip and extends along the first direction D1. Fig.63 As shown, the second electrode T24 of the second selection transistor is connected to the second region of the active pattern of the second selection transistor through the fifth via hole. Fig.65 As shown, the second electrode T24 of the second selection transistor is connected to the second region of the active pattern of the second selection transistor through a sixth via hole.

[0395] In an exemplary embodiment, if Figure 62 to Figure 65 As shown, the first connection line L1 is in a strip shape and extends along the first direction D1. Fig.63 As shown, the first connection line L1 is connected to the light shielding pattern of the first selection transistor through the first via hole, connected to the gate electrode of the first selection transistor through the sixth via hole, and connected to the first selection signal line through the eighth via hole. Fig.65 As shown, the first connection line L1 is connected to the light shielding pattern of the first selection transistor through the first via hole, and is connected to the first selection signal line through the eighth via hole.

[0396] In an exemplary embodiment, if Figure 62 to Figure 65 As shown, the second connection line L2 is in a strip shape and extends along the first direction D1. Fig.63 As shown, the second connection line L2 is connected to the light shielding pattern of the second selection transistor through the second via hole, connected to the gate electrode of the second selection transistor through the seventh via hole, and connected to the second selection signal line through the ninth via hole. Fig.65 As shown, the second connection line L2 is connected to the light shielding pattern of the second selection transistor through the second via hole, and is connected to the second selection signal line through the ninth via hole.

[0397] In an exemplary embodiment, if Fig.64 and Fig.65As shown, the third connection line L3 is in a strip shape and extends along the first direction D1. The third connection line L3 is connected to the gate electrode of the second selection transistor through the seventh via hole and is connected to the second selection signal line through the ninth via hole.

[0398] (7) forming a second flat layer pattern, comprising: coating a first flat film, depositing a fourth insulating film, and coating a second flat film in sequence on a substrate having the aforementioned pattern, and patterning the first flat film, the fourth insulating film, and the second flat film through a patterning process to form a first flat layer, a fourth insulating layer, and a second flat layer pattern covering the aforementioned pattern.

[0399] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0400] In an exemplary embodiment, the shading layer, the first shading layer, the second shading layer, the first conductive layer and the second conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0401] In an exemplary embodiment, the first sub-insulating layer, the second sub-insulating layer, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer.

[0402] In an exemplary embodiment, the first planarization layer and the second planarization layer may employ an organic material such as resin or the like.

[0403] The embodiment of the present disclosure further provides a display device, including: a display substrate.

[0404] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0405] In an exemplary embodiment, the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0406] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0407] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0408] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, provided with a display area and a non-display area, characterized in that: The invention comprises: a substrate, and a plurality of data signal lines disposed on the substrate and at least partially located in the display area, at least two selection signal lines located in the non-display area, a plurality of data output lines and a multiplexer, wherein the multiplexer comprises: a plurality of selection transistors, wherein the selection transistors are electrically connected to the selection signal lines, the data signal lines and the data output lines respectively; The selection transistor comprises: a light shielding pattern, an active pattern and a gate electrode, and for the same selection transistor, one of the light shielding pattern and the gate electrode is located on a side of the active pattern close to the substrate, and the other is located on a side of the active pattern away from the substrate, and the orthographic projection of the light shielding pattern on the substrate at least partially overlaps with the gate electrode on the substrate; The light shielding pattern and the gate electrode of the selection transistor are respectively electrically connected to a selection signal line to which the selection transistor is connected.

2. The display substrate according to claim 1, characterized in that: For the same selection transistor, the orthographic projection of the light shielding pattern on the substrate covers the orthographic projection of the active pattern on the substrate, and the orthographic projection of the gate electrode on the substrate at least partially overlaps with the orthographic projection of the active pattern on the substrate.

3. The display substrate according to claim 1 or 2, characterized in that: The selection signal lines include: a first selection signal line to an Mth selection signal line, and the data output lines include: a first data output line to an Nth data output line; The demultiplexer comprises: N distributors, the nth distributor is electrically connected to the first selection signal line to the Mth selection signal line, the nth data output line and the M data signal lines respectively, and at least one of the distributors comprises: first selection transistors to the Mth selection transistors; In the nth distributor, the light shielding pattern of the mth selection transistor and the gate electrode of the mth selection transistor are electrically connected to the mth selection signal line respectively, 1≤m≤M, 1≤n≤N; The data signal line and the data output line extend at least partially along a first direction, the selection signal line extends at least partially along a second direction, and the first direction and the second direction intersect.

4. The display substrate according to claim 3, characterized in that: The shading pattern is a single-layer structure or a double-layer structure; When the shading pattern is a double-layer structure, the shading pattern includes: a first shading pattern and a second shading pattern, the first shading pattern is located on a side of the second shading pattern close to the substrate, and the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second shading pattern on the substrate; The first light-shielding pattern of the selection transistor is insulated from the selection signal line connected to the selection transistor, and the second light-shielding pattern of the selection transistor is electrically connected to the selection signal line connected to the selection transistor.

5. The display substrate according to claim 4, characterized in that: When the light shielding pattern has a double-layer structure, a length of the second light shielding pattern along the second direction is greater than a length of the gate electrode of the selection transistor along the second direction.

6. The display substrate according to claim 4 or 5, characterized in that: When M=2, the nth distributor includes: at least one first selection transistor and at least one second selection transistor; The first electrode of the first selection transistor and the first electrode of the second selection transistor are respectively electrically connected to the nth data output line, the second electrode of the first selection transistor is electrically connected to the first data signal line connected to the nth distributor, and the second electrode of the second selection transistor is electrically connected to the second data signal line connected to the nth distributor.

7. The display substrate according to claim 6, characterized in that: When the shading pattern is a single-layer structure, the shading pattern of the first selection transistor and the shading pattern of the second selection transistor located in the same distributor are spaced apart and arranged along the second direction, and the active pattern of the first selection transistor and the active pattern of the second selection transistor located in the same distributor are spaced apart and arranged along the second direction.

8. The display substrate according to claim 6, characterized in that: When the shading pattern is a double-layer structure, the first shading pattern of the first selection transistor and the first shading pattern of the second selection transistor are the same shading pattern, the second shading pattern of the first selection transistor and the second shading pattern of the second selection transistor are spaced apart and arranged along the second direction, and the active pattern of the first selection transistor and the active pattern of the second selection transistor are the same active pattern.

9. The display substrate according to claim 6, characterized in that: When the shading pattern is a double-layer structure, the first shading pattern of the first selection transistor and the first shading pattern of the second selection transistor are spaced apart and arranged along the second direction, the second shading pattern of the first selection transistor and the second shading pattern of the second selection transistor are spaced apart and arranged along the second direction, and the active pattern of the first selection transistor and the active pattern of the second selection transistor are spaced apart and arranged along the second direction.

10. The display substrate according to any one of claims 7 to 9, characterized in that: At least a portion of the structure of the first selection transistor and the structure of the second selection transistor in the same distributor are symmetrical with respect to a first virtual straight line, and an extending direction of the first virtual straight line is parallel to the first direction.

11. The display substrate according to claim 4, characterized in that: When M=2, and the light shielding pattern is a single-layer structure, the nth distributor includes: two first selection transistors and two second selection transistors; For the nth distributor, the first electrode of the first first selection transistor is electrically connected to the nth data output line, the second electrode of the first first selection transistor is electrically connected to the first data signal line connected to the nth distributor, the first electrode of the second first selection transistor is electrically connected to the first selection signal line, and the second electrode of the second first selection transistor is electrically connected to the shading pattern of the first first selection transistor; the first electrode of the first second selection transistor is electrically connected to the nth data output line, the second electrode of the first second selection transistor is electrically connected to the second data signal line connected to the nth distributor, the first electrode of the second second selection transistor is electrically connected to the second selection signal line, and the second electrode of the second second selection transistor is electrically connected to the shading pattern of the first second selection transistor.

12. The display substrate according to claim 11, characterized in that: The shading pattern of the first first selection transistor and the shading pattern of the first second selection transistor are the same shading pattern, and the active pattern of the first first selection transistor and the active pattern of the first second selection transistor are the same shading pattern; the shading pattern of the second first selection transistor and the shading pattern of the second second selection transistor are spaced apart and arranged along the second direction, and the active pattern of the second first selection transistor and the active pattern of the second second selection transistor are spaced apart and arranged along the second direction.

13. The display substrate according to claim 11 or 12, characterized in that: Any one of the selection signal lines includes: a first sub-selection signal line and a second sub-selection signal line, the first sub-selection signal line of any one of the selection signal lines is located at a side of the demultiplexer close to the display area, and the second sub-selection signal line of any one of the selection signal lines is located at a side of the demultiplexer far from the display area; The gate electrode of the first first selection transistor is electrically connected to the first sub-selection signal line of the first selection signal line, the gate electrode of the first second selection transistor is electrically connected to the first sub-selection signal line of the second selection signal line, the gate electrode and the first electrode of the second first selection transistor are respectively electrically connected to the second sub-selection signal line of the first selection signal line, and the gate electrode and the first electrode of the second second selection transistor are respectively electrically connected to the second sub-selection signal line of the second selection signal line.

14. The display substrate according to claim 13, characterized in that: A first first selection transistor and a second first selection transistor are arranged along the first direction, and a first second selection transistor and a second second selection transistor are arranged along the first direction; The structure of the first first selection transistor and the structure of the first second selection transistor are at least partially symmetrical with respect to a second virtual straight line, the structure of the second first selection transistor and the structure of the second second selection transistor are at least partially symmetrical with respect to the second virtual straight line, and the extension direction of the second virtual straight line is parallel to the first direction.

15. The display substrate according to claim 13, characterized in that: The nth distributor further comprises: a third selection transistor and a fourth selection transistor; a first of the first selection transistors is electrically connected to a first data signal line connected to the nth distributor through the third selection transistor, and a first of the second selection transistors is electrically connected to a second data signal line connected to the nth distributor through the fourth selection transistor; The gate electrode and the light shielding pattern of the third selection transistor are electrically connected to the first sub-selection signal line of the first selection signal line, respectively, the first electrode of the third selection transistor is electrically connected to the first data signal line connected to the nth distributor, and the second electrode of the third selection transistor is electrically connected to the second electrode of the first of the first selection transistors; The gate electrode and the shading pattern of the fourth selection transistor are respectively electrically connected to the first sub-selection signal line of the second selection signal line, the first electrode of the fourth selection transistor is electrically connected to the second data signal line connected to the nth distributor, and the second electrode of the fourth selection transistor is electrically connected to the second electrode of the first second selection transistor.

16. The display substrate according to claim 15, characterized in that: The light shielding pattern of the third selection transistor and the light shielding pattern of the fourth selection transistor are arranged at intervals and arranged along the second direction, and the active pattern of the third selection transistor and the active pattern of the fourth selection transistor are arranged at intervals and arranged along the second direction.

17. The display substrate according to claim 16, characterized in that: The third selection transistor and the fourth selection transistor are located on a side of the first sub-selection signal line close to the display area, and the structures of the third selection transistor and the fourth selection transistor are at least partially symmetrical with respect to the second virtual straight line.

18. The display substrate according to claim 4, characterized in that: When the light shielding pattern comprises: a single-layer structure, the display substrate comprises: a light shielding layer, a semiconductor layer, a first conductive layer and a second conductive layer sequentially stacked on the base; The light shielding layer at least includes: the light shielding pattern of the selection transistor; The semiconductor layer at least includes: the active pattern of the selection transistor; The first conductive layer at least includes: the gate electrode of the selection transistor and the selection signal line; The second conductive layer at least includes: the data signal line, the data output line, and the first electrode and the second electrode of the selection transistor.

19. The display substrate according to claim 4, characterized in that: When the light shielding pattern is a double-layer structure, the display substrate comprises: a first light shielding layer, a second light shielding layer, a semiconductor layer, a first conductive layer and a second conductive layer sequentially stacked on the base; The first light shielding layer at least includes: a first light shielding pattern of the selection transistor; The second light shielding layer at least includes: a second light shielding pattern of the selection transistor; The semiconductor layer at least includes: the active pattern of the selection transistor; The first conductive layer at least includes: a gate electrode of the selection transistor and a selection signal line; The second conductive layer at least includes: the data signal line, the data output line, and the first electrode and the second electrode of the selection transistor.

20. A display device, characterized in that: include: A display substrate as claimed in any one of claims 1 to 19.

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