Preparation method of display panel, display panel and display device

Abstract

The invention belongs to the technical field of display, and particularly relates to a preparation method of a display panel, the display panel and a display device.The method comprises the following steps that an array substrate is provided, and the array substrate is coated with a layer of first alignment film; the first alignment film is coated with a layer of photoinitiator, and at least part of the photoinitiator is located in the via hole; carrying out inactivation treatment on the photoinitiator outside the via hole; performing alignment treatment on the first alignment film; a liquid crystal layer and a color film substrate are provided, the color film substrate, the array substrate and the liquid crystal layer are subjected to box forming treatment, the liquid crystal layer comprises liquid crystal molecules and a reaction part, the reaction part can generate a second alignment film with the photoinitiator in the via hole under the illumination effect, and the second alignment film is formed. And the second alignment film can be used for aligning the liquid crystal molecules in the via holes. According to the scheme, alignment of the liquid crystal molecules in the via holes can be achieved, and then the problem of trace moire patterns during pressing is relieved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a method for preparing a display panel, a display panel, and a display device. Background Art

[0002] With the development of display technology, liquid crystal display (LCD) panels have become popular among consumers due to their low cost and mature technology.

[0003] Liquid crystal display panels generally use a rubbing alignment process to define the initial direction of liquid crystal molecules. Since the vias are deep, the alignment film in the vias is not easily rubbed by the rubbing device during the subsequent rubbing alignment process, resulting in the alignment film in the vias having no binding force on the liquid crystal molecules in the vias, causing the liquid crystal molecules in the vias to flow out when the liquid crystal panel is pressed, resulting in the problem of trace mura. Summary of the invention

[0004] The purpose of the present application is to provide a method for manufacturing a display panel, a display panel and a display device, which can realize the alignment of liquid crystal molecules in via holes, thereby reducing the problem of trace mura when pressed.

[0005] A first aspect of the present application provides a method for preparing a display panel, comprising the following steps:

[0006] An array substrate is provided, and a first alignment film is coated on the array substrate; the array substrate comprises a base substrate, and a transistor, a first insulating layer and a pixel electrode arranged on the base substrate, the transistor comprises a first electrode and a second electrode arranged spaced apart from each other, the pixel electrode is arranged on a side of the first insulating layer away from the base substrate, a via hole is provided on the first insulating layer, the via hole exposes a portion of the first electrode, the pixel electrode is connected to the first electrode through the via hole, and the first alignment film covers the pixel electrode;

[0007] Coating a layer of photoinitiator on the first alignment film, wherein at least a portion of the photoinitiator is located in the via hole;

[0008] Deactivating the photoinitiator outside the via hole;

[0009] performing an alignment process on the first alignment film;

[0010] A liquid crystal layer and a color filter substrate are provided, and the color filter substrate, the array substrate and the liquid crystal layer are processed into a box, the liquid crystal layer is sealed between the color filter substrate and the array substrate, the liquid crystal layer includes liquid crystal molecules and a reaction element, the liquid crystal molecules located outside the via hole can be aligned under the action of the first alignment film, the reaction element can generate a second alignment film with the photoinitiator in the via hole under the action of light, and the second alignment film can align the liquid crystal molecules in the via hole.

[0011] In an exemplary embodiment of the present application, a preparation method for deactivating a photoinitiator located outside the via hole includes:

[0012] A light treatment is performed on a side of the substrate away from the pixel electrode.

[0013] In an exemplary embodiment of the present application, before performing alignment treatment on the first alignment film, the preparation method further includes:

[0014] The array substrate is subjected to a temperature increase process to sublime the inactivated photoinitiator.

[0015] In an exemplary embodiment of the present application, a preparation method for performing a temperature-raising treatment on the array substrate includes:

[0016] The array substrate is subjected to a baking process.

[0017] In an exemplary embodiment of the present application, a method for preparing the second alignment film in which the reaction element can react with the photoinitiator in the via hole under the action of light comprises:

[0018] Using ultraviolet rays to perform light treatment on a side of the base substrate away from the pixel electrode, so as to move the reaction element toward the via hole;

[0019] The reaction element is combined with the photoinitiator to form the second alignment film.

[0020] In an exemplary embodiment of the present application, a method for preparing the first alignment film by performing an alignment treatment includes:

[0021] The first alignment film is rubbed and aligned.

[0022] A second aspect of the present application provides a display panel prepared by any of the above preparation methods, the display panel comprising:

[0023] An array substrate, the array substrate comprising a base substrate and a transistor, a first insulating layer and a pixel electrode arranged on the base substrate, the transistor comprising a gate, a semiconductor layer, a first pole and a second pole, the semiconductor layer being arranged on a side of the gate away from the base substrate, a gate insulating layer being arranged between the gate and the semiconductor layer, the first pole and the second pole being respectively overlapped at two ends of the semiconductor layer, a via hole being arranged on the first insulating layer, the via hole leaking a portion of the first pole, the pixel electrode being connected to the first pole through the via hole, and a photoinitiator being arranged in the via hole;

[0024] A first alignment film is provided on a side of the first insulating layer away from the base substrate and covers the pixel electrode;

[0025] A reaction element, the reaction element is arranged on a side of the first alignment film away from the base substrate, and the reaction element is arranged in the via hole;

[0026] Color film substrate; and

[0027] A liquid crystal layer is arranged between the array substrate and the color film substrate, and the liquid crystal layer includes liquid crystal molecules and a reaction element. The reaction element can generate a second alignment film with the photoinitiator under the action of light. The second alignment film can align the liquid crystal molecules in the via holes, and the liquid crystal molecules outside the via holes can be aligned under the action of the first alignment film.

[0028] In another exemplary embodiment of the present application, the pixel electrode covers the inner wall of the via hole.

[0029] In another exemplary embodiment of the present application, the orthographic projection of the photoinitiator on the substrate is located within the orthographic projection of the first electrode on the substrate, and the orthographic projection of the photoinitiator on the substrate is located within the orthographic projection of the gate on the substrate.

[0030] A third aspect of the present application provides a display device, comprising a backlight module and a display panel as described in any one of the above items, wherein the display panel is arranged on a light emitting side of the backlight module.

[0031] The display panel manufacturing method, display panel and display device of the present application have at least the following beneficial effects:

[0032] The present application scheme utilizes the reaction elements in the liquid crystal layer and the photoinitiator in the via to generate a second alignment film under the action of light, and utilizes the second alignment film to align the liquid crystal molecules in the via, thereby forming an alignment force on the disordered liquid crystal in the via. When pressed by external force, the liquid crystal in the via will not move to the display area and cause disordered arrangement of the liquid crystal in the display area, thereby reducing or avoiding the problem of scratch moiré.

[0033] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0034] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of a method for manufacturing a display panel provided in Embodiment 1 of the present application is shown;

[0037] Figure 2 A schematic diagram showing the structure of the combination of the reaction element and the photoinitiator provided in the first, second or third embodiment of the present application;

[0038] Figure 3 A schematic diagram of a process for preparing an array substrate provided in Embodiment 1 of the present application is shown;

[0039] Figure 4 A schematic diagram of the structure of an array substrate provided in Embodiment 1, Embodiment 2 or Embodiment 3 of the present application is shown;

[0040] Figure 5 A schematic diagram of the structure of preparing a first alignment film on an array substrate provided in Embodiment 1, Embodiment 2 or Embodiment 3 of the present application is shown;

[0041] Figure 6 A schematic diagram of the structure of coating a layer of photoinitiator on the first alignment film provided in Embodiment 1, Embodiment 2 or Embodiment 3 of the present application is shown;

[0042] Figure 7 A schematic diagram of the process of removing the photoinitiator outside the via hole provided in the first embodiment of the present application is shown;

[0043] Figure 8 It shows that the photoinitiator is treated with ultraviolet light provided in the first, second or third embodiment of the present application;

[0044] Fig. 9 A schematic diagram of a structure in which a photoinitiator is provided in a via hole provided in Embodiment 1, Embodiment 2 or Embodiment 3 of the present application is shown;

[0045] Fig.10 A schematic diagram of the structure of performing rubbing alignment on the first alignment film provided in the first, second or third embodiment of the present application is shown;

[0046] Fig.11 A schematic diagram showing the structure of the reaction element provided in Example 1, Example 2 or Example 3 of the present application without being combined with a photoinitiator;

[0047] Fig.12 A schematic diagram of the process of combining a reaction element and a photoinitiator under light provided in the first embodiment of the present application is shown;

[0048] Fig.13 A schematic diagram of the structure of the reaction element and the photoinitiator combined under the action of light provided in the first, second or third embodiment of the present application is shown;

[0049] Fig.14 A schematic structural diagram of a display panel provided in the third embodiment of the present application is shown, which is arranged on the light-emitting side of the backlight module.

[0050] Description of reference numerals:

[0051] 10. Display device; 100. Display panel; 110. Array substrate; 111. Base substrate; 112. Transistor; 1120. Gate; 1121. Semiconductor layer; 1122. First electrode; 1123. Second electrode; 113. First insulating layer; 114. Pixel electrode; 115. Gate insulating layer; 120. Color filter substrate; 121. Black matrix; 122. Base; 123. Color resist layer; 1230. Color resist unit; 130. Liquid crystal layer; 131. Liquid crystal molecules; 132. Reactor; 140. First alignment film; 150. Photoinitiator; 160. Via hole; 170. Support column; 200. Backlight module. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0053] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0054] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0055] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0056] Embodiment 1

[0057] Embodiment 1 of the present application provides a method for preparing a display panel 100 , and the display panel 100 may be a liquid crystal display panel 100 (Liquid Crystal Display, LCD), which includes an array substrate 110 , a color film substrate 120 , and a liquid crystal layer 130 located between the array substrate 110 and the color film substrate 120 .

[0058] See also Figure 1 and Figure 2 As shown, the method for preparing the display panel 100 includes the following steps:

[0059] Step S100, providing an array substrate 110, and coating a first alignment film 140 on the array substrate 110;

[0060] Step S200 , coating a layer of photoinitiator 150 on the first alignment film 140 , at least a portion of the photoinitiator 150 is located in the via hole 160 ;

[0061] Step S300, deactivating the photoinitiator 150 outside the via hole 160;

[0062] Step S400, performing an alignment process on the first alignment film 140;

[0063] Step S500, providing a liquid crystal layer 130 and a color filter substrate 120, and boxing the color filter substrate 120, the array substrate 110 and the liquid crystal layer 130, wherein the liquid crystal layer 130 is sealed between the color filter substrate 120 and the array substrate 110, and the liquid crystal layer 130 includes liquid crystal molecules 131 and reaction elements 132, and the liquid crystal molecules 131 located outside the via hole 160 can be aligned under the action of the first alignment film 140, and the reaction element 132 can generate a second alignment film with the photoinitiator 150 in the via hole 160 under the action of light, and the second alignment film can align the liquid crystal molecules 131 in the via hole 160.

[0064] In step S100, see Figure 2 As shown, the array substrate 110 includes a base substrate 111 and a transistor 112 , a first insulating layer 113 and a pixel electrode 114 disposed on the base substrate 111 . The transistor 112 includes a gate 1120, a semiconductor layer 1121, a first electrode 1122 and a second electrode 1123. The gate 1120 is disposed on a side of the semiconductor layer 1121 close to the base substrate 111, and a gate insulating layer 115 is disposed between the gate 1120 and the semiconductor layer 1121. The first electrode 1122 and the second electrode 1123 are respectively overlapped at opposite ends of the semiconductor layer 1121, and the first electrode 1122 and the second electrode 1123 are spaced apart from each other. The first insulating layer 113 is disposed on a side of the gate insulating layer 115 away from the base substrate 111, and the first insulating layer 113 covers the first electrode 1122, the semiconductor layer 1121 and the second electrode 1123. A via hole 160 is disposed on the first insulating layer 113, and the via hole 160 exposes a portion of the first electrode 1122. The pixel electrode 114 is electrically connected to the exposed portion of the first electrode 1122 through the via hole 160.

[0065] Among them, see Figure 3 and Figure 4 As shown, the method for preparing the array substrate 110 includes the following steps:

[0066] In step S110 , a first metal layer is formed on the base substrate 111 , and the first metal layer is patterned to form a gate 1120 and a scan line, wherein the scan line is connected to the gate 1120 .

[0067] This step S110 includes:

[0068] A first metal layer is deposited on the base substrate 111 by using a physical vapor deposition (PVD) method.

[0069] The first metal layer is patterned by using a first photomask process to obtain a gate 1120 and a scan line.

[0070] The substrate 111 may be made of glass, quartz or other suitable materials; the material of the first metal layer includes molybdenum (Mo), copper (Cu) and the like.

[0071] Furthermore, the first photomask process includes photoresist coating, exposure, development, wet etching and photoresist stripping processes. A plurality of gate electrodes 1120 are formed on the base substrate 111 by the first photomask process, and adjacent gate electrodes 1120 are spaced apart from each other.

[0072] Step S120 , forming a gate insulating layer 115 and a semiconductor layer 1121 in sequence on the base substrate 111 , wherein the gate insulating layer 115 covers the gate electrode 1120 and the scan line.

[0073] The material of the gate insulating layer 115 includes one or more of silicon oxide (SiOx) and silicon nitride (SiNx); the material of the semiconductor layer 1121 includes one or more of amorphous silicon, polycrystalline silicon, and metal oxide.

[0074] In addition, the gate insulating layer 115 and the semiconductor layer 1121 are both deposited by chemical vapor deposition (CVD).

[0075] Step S130 , depositing a second metal layer on the gate insulating layer 115 and the semiconductor layer 1121 , and patterning the second metal layer to form a first electrode 1122 , a second electrode 1123 and a data line that are spaced apart from each other.

[0076] It should be noted that the method of depositing the second metal layer is physical vapor deposition (PVD).

[0077] In addition, patterning the second metal layer includes photoresist coating, exposure, development, wet etching and photoresist stripping processes.

[0078] The material of the second metal layer includes molybdenum (Mo), copper (Cu), etc.

[0079] It is worth mentioning that the first electrode 1122 can be one of the source and the drain, and the second electrode 1123 can be the other of the source and the drain.

[0080] For example, the first electrode 1122 is a drain electrode, and the second electrode 1123 is a source electrode, which are spaced apart from each other on the gate insulating layer 115 . One end of the first electrode 1122 and one end of the second electrode 1123 are respectively overlapped on opposite sides of the semiconductor layer 1121 .

[0081] In step S140 , a first insulating layer 113 is formed on the gate insulating layer 115 and the semiconductor layer 1121 , and the first insulating layer 113 is patterned to obtain a via hole 160 .

[0082] The first insulating layer 113 covers the first electrode 1122 , the second electrode 1123 and the data line. The via hole 160 exposes at least a portion of the first electrode 1122 , so that the pixel electrode 114 is subsequently connected to the first electrode 1122 through the via hole 160 .

[0083] In step S150 , a pixel electrode 114 is formed on the first insulating layer 113 , and the pixel electrode 114 is connected to the first electrode 1122 through the via hole 160 .

[0084] The material of the pixel electrode 114 can be indium tin oxide (ITO) or indium tin zinc oxide (ITZO). The pixel electrode 114 can be in a block or strip structure.

[0085] In addition, in order to prevent the photoinitiator 150 and the first alignment film 140 described below from damaging the first electrode 1122, the pixel electrode 114 completely covers the exposed portion of the first electrode 1122. In order to ensure the protective effect, the pixel electrode 114 is connected to the inner wall of the via hole 160, that is, the pixel electrode 114 is attached to the inner wall of the via hole 160.

[0086] In step S100, see Figure 5 As shown, a first alignment film 140 is coated on the first insulating layer 113 .

[0087] The first alignment film 140 is prepared after the pixel electrode 114 is prepared, and can cover the pixel electrode 114 .

[0088] In step S200, see Figure 6 As shown, the photoinitiator 150 is located on a side of the first alignment film 140 away from the base substrate 111 , so as to facilitate the subsequent generation of a second alignment film in the via hole 160 .

[0089] In the embodiment of the present application, a layer of photoinitiator 150 is distributed in the via hole 160 , which can cover the pixel electrode 114 in the via hole 160 .

[0090] In step S300, see Figure 7As shown, the photoinitiator 150 located outside the via hole 160 is deactivated to ensure that the liquid crystal molecules 131 located outside the via hole 160 are only subjected to the alignment effect of the first alignment film 140, and the photoinitiator 150 located outside the via hole 160 will not react with the reaction element 132 described below to generate the second alignment film, thereby ensuring the alignment of the liquid crystal molecules 131 outside the via hole 160. The photoinitiator 150 inside the via hole 160 is not deactivated, and the photoinitiator 150 inside the via hole 160 can generate the second alignment film with the reaction element 132 described below, so that the liquid crystal molecules 131 inside the via hole 160 can be aligned under the action of the second alignment film, and the liquid crystal molecules 131 inside the via hole 160 have a restraining force. When the display panel 100 is pressed, the liquid crystal molecules 131 inside the via hole 160 will not move to the display area, and thus the problem of trace mura will not occur.

[0091] Among them, see Figure 7 As shown, the preparation method for deactivating the photoinitiator 150 located outside the via hole 160 includes:

[0092] In step S310 , a light treatment is performed on a side of the base substrate 111 away from the pixel electrode 114 .

[0093] like Figure 8 As shown, ultraviolet (UV) light is used to perform exposure treatment on the back side of the base substrate 111, so that the photoinitiator 150 outside the via hole 160 loses its activity and cannot react with the reaction element 132 described below to generate a second alignment film.

[0094] Since the ultraviolet light is irradiated from the side of the substrate 111 away from the pixel electrode 114, and because the metal wiring is opaque, and the orthographic projection of the photoinitiator 150 in the via hole 160 on the substrate 111 is located within the orthographic projection of the first pole 1122 on the substrate 111. Therefore, when the ultraviolet light is irradiated from the side of the substrate 111 away from the pixel electrode 114, the first pole 1122 will shield the photoinitiator 150 in the via hole 160, thereby preventing the photoinitiator 150 in the via hole 160 from being inactivated by the ultraviolet light, and ensuring that the photoinitiator 150 in the via hole 160 can generate a second alignment film with the reaction element 132 in the liquid crystal layer 130, and align the liquid crystal molecules 131 in the via hole 160. When pressed by external force, the liquid crystal molecules 131 in the via hole 160 will not move into the display area to cause disordered arrangement of the liquid crystal in the display area, thereby reducing or avoiding the problem of scratch moiré.

[0095] In step S300, after the photoinitiator 150 outside the via hole 160 is deactivated, the following steps are further included:

[0096] Step S320, the array substrate 110 is subjected to a temperature treatment to sublimate the inactive photoinitiator 150, thereby removing the photoinitiator 150 on the side of the first alignment film 140 away from the base substrate 111, and ensuring that the first alignment film 140 aligns the liquid crystal molecules 131 outside the via hole 160, see Fig. 9 shown.

[0097] It is understandable that the temperature increase process performed on the array substrate 110 may include heating, baking or other temperature increase methods.

[0098] In addition, the photoinitiator 150 on the side of the first alignment film 140 away from the base substrate 111 is removed to prevent the photoinitiator 150 on the outside of the via 160 from being inactivated completely and reacting with the reaction element 132 in the liquid crystal layer 130 to generate a second alignment film, thereby affecting the alignment of the liquid crystal molecules 131 on the outside of the via 160.

[0099] In the embodiment of the present application, the array substrate 110 is baked to sublime the inactivated photoinitiator 150 , so as to completely remove the photoinitiator 150 on the first alignment film 140 away from the base substrate 111 .

[0100] It is worth mentioning that due to the small size of the via 160, during the traditional friction alignment process, the first alignment film 140 in the via 160 cannot be affected by the friction alignment, which results in the first alignment film 140 of the via 160 being unable to be aligned, causing the liquid crystal molecules 131 in the via 160 to be disorderly arranged. When the display panel 100 is pressed, the liquid crystal molecules 131 in the via 160 will move toward the display area, resulting in a trace mura problem.

[0101] In step S400, Fig.10 As shown, when the first alignment film 140 is rubbed and aligned, the photoinitiator 150 and the first alignment film 140 in the via hole 160 will not be rubbed and aligned, and will not affect the subsequent generation of the second alignment film by the photoinitiator 150 and the reaction element 132.

[0102] After the first alignment film 140 is rubbed and aligned, the first alignment film 140 can provide an alignment force for the liquid crystal molecules 131 outside the via hole 160 .

[0103] In step S500, Fig.11 As shown, the reaction element 132 in the liquid crystal layer 130 may be hexyl methacrylate (HMA monomers) ions, which are mixed with the liquid crystal molecules 131 between the array substrate 110 and the color filter substrate 120 .

[0104] When the second alignment film is generated, the reaction element 132 in the liquid crystal layer 130 can react with the photoinitiator 150 in the via hole 160 under the action of light to generate the second alignment film, and the second alignment film can align the liquid crystal molecules 131 in the via hole 160 .

[0105] See also Fig.12 and Fig.13 As shown, the preparation method for generating the second alignment film includes:

[0106] Step S510, using ultraviolet light to perform light treatment on a side of the base substrate 111 away from the pixel electrode 114, so that the reaction element 132 moves toward the via hole 160;

[0107] In step S520 , the reaction element 132 is combined with the photoinitiator 150 to form a second alignment film.

[0108] In step S510, not only can light treatment be performed on the side of the base substrate 111 away from the pixel electrode 114, but ultraviolet exposure treatment can also be performed on the side of the color filter substrate 120 away from the array substrate 110. The black matrix 121 on the color filter substrate 120 is used to shield the photoinitiator 150 in the via 160 to prevent the photoinitiator 150 in the via 160 from losing its activity, thereby ensuring the generation of a second alignment film with the reaction element 132, and further ensuring the alignment of the liquid crystal molecules 131 in the via 160.

[0109] During the ultraviolet exposure treatment, the reaction element 132 in the liquid crystal layer 130 gradually moves into the via hole 160 and combines with the photoinitiator 150 in the via hole 160 to form a second alignment film that has a binding force on the liquid crystal molecules 131 in the via hole 160 .

[0110] It is understandable that, since the photoinitiator 150 outside the via hole 160 is exposed to ultraviolet light (UV) and loses its activity, the reaction element 132 can only be combined with the photoinitiator 150 inside the via hole 160 .

[0111] The present application scheme utilizes the photoinitiator 150 in the via 160 to combine with the reaction element 132 in the liquid crystal layer 130 to generate a second alignment film that has a binding force on the liquid crystal molecules 131, so that the liquid crystal molecules 131 in the via 160 have a binding force. When pressed by external force, the liquid crystal molecules 131 in the via 160 will not move to the display area, thereby avoiding or reducing the occurrence of scratch moiré (Trace mura) phenomenon.

[0112] Embodiment 2

[0113] Embodiment 2 of the present application provides a display panel 100 prepared by the preparation method in Embodiment 1. The display panel 100 may be a liquid crystal display panel 100 (Liquid Crystal Display, LCD).

[0114] like Figure 2 As shown, the display panel 100 includes a color filter substrate 120, a liquid crystal layer 130, a support column 170, an array substrate 110, and a first alignment film 140 arranged on the array substrate 110. The array substrate 110 and the color filter substrate 120 are arranged in a box. The liquid crystal layer 130 and the support column 170 are arranged between the array substrate 110 and the color filter substrate 120. The support column 170 is arranged on the side of the color filter substrate 120 and extends toward the side of the array substrate 110. The array substrate 110 includes a base substrate 111 and a gate 1120, a gate insulating layer 115, a semiconductor layer 1121, a first pole 1122, a second pole 1123, a first insulating layer 113 and a pixel electrode 114 arranged on the base substrate 111. The gate 1120 is arranged on the base substrate 111, and a gate insulating layer 115 is arranged between the gate 1120 and the semiconductor layer 1121. The first pole 1122 and the second pole 1123 are overlapped at two ends of the semiconductor layer 1121. The first insulating layer 113 is arranged on a side of the gate insulating layer 115 away from the base substrate 111, and the first insulating layer 113 covers the first pole 1122, the second pole 1123 and the semiconductor layer 1121.

[0115] It should be noted that if Figure 2 As shown, the liquid crystal layer 130 includes liquid crystal molecules 131 and reactive elements 132 . The liquid crystal layer 130 includes a plurality of liquid crystal molecules 131 and a plurality of reactive elements 132 that are spaced apart. The reactive elements 132 may be hexyl methacrylate (HMA monomers).

[0116] In addition, if Figure 2 As shown, a via hole 160 is provided on the array substrate 110. The via hole 160 is provided on the first insulating layer 113. The via hole 160 exposes a portion of the first pole 1122 so that the pixel electrode 114 is connected to the first pole 1122 located in the via hole 160, thereby enabling the pixel electrode 114 to receive an electrical signal and drive the liquid crystal molecules 131 in the liquid crystal layer 130 to deflect.

[0117] Since the first alignment film 140 cannot be rubbed in the via hole 160 during the rubbing alignment, the first alignment film 140 in the via hole 160 cannot be aligned, and thus cannot generate a binding force on the liquid crystal molecules 131 in the via hole 160. Therefore, in order to ensure that the liquid crystal molecules 131 in the via hole 160 have a binding force, the display panel 100 further includes a photoinitiator 150, which is disposed in the via hole 160 and covers the pixel electrode 114 in the via hole 160, and the orthographic projection of the photoinitiator 150 on the base substrate 111 is located within the orthographic projection of the gate electrode 1120 on the base substrate 111, so that the photoinitiator 150 in the via hole 160 will not lose its activity under subsequent ultraviolet irradiation.

[0118] It is understandable that if Figure 2 As shown, a black matrix 121 is provided on the color filter substrate 120, and the black matrix 121 corresponds to the transistor 112 of the array substrate 110, and the orthographic projection of the black matrix 121 on the base substrate 111 covers the orthographic projection of the transistor 112 on the base substrate 111. Therefore, the black matrix 121 on the color filter substrate 120 can also shield the photoinitiator 150 in the via hole 160, so that ultraviolet light can be irradiated from the array substrate 110 side or from the color filter substrate 120 side, and the photoinitiator 150 will not lose its activity, and can react with the reaction element 132 to generate a second alignment film, which has an alignment effect on the liquid crystal molecules 131 in the via hole 160.

[0119] like Figure 2 As shown, the color filter substrate 120 also includes a substrate 122, a color resist layer 123 disposed on the substrate 122, and a common electrode. The color resist layer 123 includes a plurality of color resist units 1230 arranged in an array. Adjacent color resist units 1230 have different colors, and adjacent color resist units 1230 are provided with the above-mentioned black matrix 121 to avoid cross-color. The common electrode is disposed on a side of the color resist layer 123 away from the substrate 122. The common electrode can control the deflection angle of the liquid crystal molecules 131 together with the pixel electrode 114 on the array substrate 110 side.

[0120] It is worth mentioning that Figure 2 As shown, in order to avoid damage to the first electrode 1122 when preparing the first alignment film 140 and the photoinitiator 150 , the pixel electrode 114 completely covers the inner wall of the via hole 160 , that is, the inner wall of the via hole 160 is provided with the pixel electrode 114 .

[0121] The photoinitiator 150 in the via hole 160 covers the first alignment film 140 so as to be able to combine with the reaction element 132 in the liquid crystal layer 130 .

[0122] When ultraviolet rays are used for exposure treatment, the reaction element 132 in the liquid crystal layer 130 moves toward the via 160, and the reaction element 132 combines with the photoinitiator 150 in the via 160 to form a second alignment film, thereby forming an alignment force on the disordered liquid crystal molecules 131 in the via 160, so as to prevent the liquid crystal molecules 131 in the via 160 from moving to the display area when the display panel 100 is pressed by external force, thereby avoiding or reducing the occurrence of scratch moiré.

[0123] Embodiment 3

[0124] This embodiment 3 provides a display device 10, see Fig.14 As shown, it includes the display panel 100 described in the second embodiment, and may also be provided with a backlight module 200 , wherein the display panel 100 is located at the light emitting side of the backlight module 200 .

[0125] According to the embodiments of the present application, the specific type of the display device 10 is not particularly limited, and any type of display device 10 commonly used in the art can be used, such as liquid crystal display screens, mobile phones, laptop computers and other mobile devices, watches and other wearable devices, VR devices, etc. Those skilled in the art can make corresponding selections based on the specific purpose of the display device, which will not be repeated here.

[0126] It should be noted that, in addition to the display panel 100, the display device 10 also includes other necessary components and components. Taking the display as an example, it may also include a housing, a main circuit board, a power cord, etc. Those skilled in the art may make corresponding supplements based on the specific use requirements of the display device 10, which will not be repeated here.

[0127] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0128] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A method for preparing a display panel, characterized in that: The steps include: An array substrate is provided, and a first alignment film is coated on the array substrate; the array substrate comprises a base substrate, and a transistor, a first insulating layer and a pixel electrode arranged on the base substrate, the transistor comprises a first electrode and a second electrode arranged spaced apart from each other, the pixel electrode is arranged on a side of the first insulating layer away from the base substrate, a via hole is provided on the first insulating layer, the via hole exposes a portion of the first electrode, the pixel electrode is connected to the first electrode through the via hole, and the first alignment film covers the pixel electrode; Coating a layer of photoinitiator on the first alignment film, wherein at least a portion of the photoinitiator is located in the via hole; Deactivating the photoinitiator outside the via hole; performing an alignment process on the first alignment film; A liquid crystal layer and a color filter substrate are provided, and the color filter substrate, the array substrate and the liquid crystal layer are processed into a box, the liquid crystal layer is sealed between the color filter substrate and the array substrate, the liquid crystal layer includes liquid crystal molecules and a reaction element, the liquid crystal molecules located outside the via hole can be aligned under the action of the first alignment film, the reaction element can generate a second alignment film with the photoinitiator in the via hole under the action of light, and the second alignment film can align the liquid crystal molecules in the via hole.

2. The method for preparing a display panel according to claim 1, characterized in that: The preparation method of deactivating the photoinitiator outside the via hole comprises: A light treatment is performed on a side of the substrate away from the pixel electrode.

3. The method for preparing a display panel according to claim 1, characterized in that: Before performing alignment treatment on the first alignment film, the preparation method further comprises: The array substrate is subjected to a temperature increase process to sublime the inactivated photoinitiator.

4. The method for preparing a display panel according to claim 3, characterized in that: The preparation method of performing a temperature-raising treatment on the array substrate comprises: The array substrate is subjected to a baking process.

5. The method for preparing a display panel according to claim 1, characterized in that: The method for preparing the reaction element capable of generating a second alignment film with the photoinitiator in the via hole under the action of light comprises: Using ultraviolet rays to perform light treatment on a side of the base substrate away from the pixel electrode, so as to move the reaction element toward the via hole; The reaction element is combined with the photoinitiator to form the second alignment film.

6. The method for preparing a display panel according to any one of claims 1 to 5, characterized in that: The preparation method of performing alignment treatment on the first alignment film comprises: The first alignment film is rubbed and aligned.

7. A display panel manufactured by the manufacturing method according to any one of claims 1 to 6, characterized in that: The display panel comprises: An array substrate, the array substrate comprising a base substrate and a transistor, a first insulating layer and a pixel electrode arranged on the base substrate, the transistor comprising a gate, a semiconductor layer, a first pole and a second pole, the semiconductor layer being arranged on a side of the gate away from the base substrate, a gate insulating layer being arranged between the gate and the semiconductor layer, the first pole and the second pole being respectively overlapped at two ends of the semiconductor layer, a via hole being arranged on the first insulating layer, the via hole leaking a portion of the first pole, the pixel electrode being connected to the first pole through the via hole, and a photoinitiator being arranged in the via hole; A first alignment film is provided on a side of the first insulating layer away from the base substrate and covers the pixel electrode; A reaction element, the reaction element is arranged on a side of the first alignment film away from the base substrate, and the reaction element is arranged in the via hole; Color film substrate; and A liquid crystal layer is arranged between the array substrate and the color film substrate, and the liquid crystal layer includes liquid crystal molecules and a reaction element. The reaction element can generate a second alignment film with the photoinitiator under the action of light. The second alignment film can align the liquid crystal molecules in the via holes, and the liquid crystal molecules outside the via holes can be aligned under the action of the first alignment film.

8. The display panel according to claim 7, characterized in that: The pixel electrode covers the inner wall of the via hole.

9. The display panel according to claim 7, characterized in that: The orthographic projection of the photoinitiator on the substrate is located within the orthographic projection of the first electrode on the substrate, and the orthographic projection of the photoinitiator on the substrate is located within the orthographic projection of the gate on the substrate.

10. A display device, characterized in that: The display device comprises a backlight module and the display panel according to any one of claims 7 to 9, wherein the display panel is arranged on the light emitting side of the backlight module.

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