Data writing method and storage device

Abstract

The present invention provides a data writing method and storage device. The method includes: establishing multiple virtual units, wherein the multiple virtual units each span a portion of a chip enable region in the storage device; establishing multiple idle groups, wherein the multiple idle groups each correspond to the multiple virtual units; determining a target idle group from the multiple idle groups based on a data write event; extracting a target virtual unit from the target idle group and performing a data write operation on the target virtual unit; and returning the target virtual unit to the target idle group if the target virtual unit meets a preset condition. This method effectively improves the overall operational efficiency of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data writing method and a storage device. Background Art

[0002] As the capacity of storage devices gradually increases, multiple physical areas are usually configured inside the storage devices. Each physical area is connected to a chip enable (CE) pin. Therefore, each physical area is also called a chip enable area. When a physical area is to be accessed, the signal of the chip enable pin connected to this physical area can be pulled up. When the signal of the chip enable pin connected to a physical area is pulled up, data can be stored in this physical area or read from this physical area. In addition, some types of storage devices can support simultaneous access to multiple physical areas to improve overall access performance. For example, some types of storage devices can access physical blocks in multiple physical areas at the same time through additionally configured virtual blocks.

[0003] However, as storage device capacity continues to increase, the number of physical blocks contained in a virtual block also increases. This significantly increases the time required to program, erase, or rotate virtual blocks between the storage area and the idle area. In the long run, this can significantly reduce the overall operating efficiency of the storage device.

[0004] Therefore, how to effectively improve the overall operating efficiency of the storage device while maintaining the existing operation strategy using virtual blocks is a problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a data writing method and a storage device, which can improve the above-mentioned problem by adopting a virtual unit across chip enable regions to manage the operation strategy of the memory module, thereby effectively improving the overall operation efficiency of the storage device.

[0006] An embodiment of the present invention provides a data writing method for a storage device, wherein the storage device includes a memory module, the memory module includes multiple chip enable regions, and the data writing method includes: establishing multiple virtual units, wherein the multiple virtual units respectively span a portion of the chip enable regions of the multiple chip enable regions; establishing multiple idle groups, wherein the multiple idle groups respectively correspond to at least one of the multiple virtual units; detecting a data writing event; determining a target idle group from the multiple idle groups based on the data writing event; extracting a target virtual unit from the target idle group and performing a data writing operation on the target virtual unit; and returning the target virtual unit to the target idle group if the target virtual unit meets a preset condition.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The memory controller is connected to the connection interface and the memory module. The memory module includes multiple chip enable regions, and the memory controller is used to: establish multiple virtual units, wherein the multiple virtual units respectively span a portion of the chip enable regions of the multiple chip enable regions; establish multiple idle groups, wherein the multiple idle groups respectively correspond to at least one of the multiple virtual units; detect a data write event; determine a target idle group from the multiple idle groups based on the data write event; extract a target virtual unit from the target idle group and perform a data write operation on the target virtual unit; and if the target virtual unit meets a preset condition, return the target virtual unit to the target idle group.

[0008] Based on the above, after establishing multiple virtual units that each span a portion of the chip enable region and idle groups corresponding to the multiple virtual units, a target idle group can be determined from the multiple idle groups based on a detected data write event, and a target virtual unit can be extracted from the target idle group. A data write operation can be performed on the target virtual unit. Thereafter, if the target virtual unit meets a preset condition, the target virtual unit can be returned to the target idle group.

[0009] In other words, by establishing multiple virtual units across different chip enable regions and their corresponding idle groups, the flexibility of virtual unit usage is increased, and the efficiency of withdrawing and returning virtual units from and to their corresponding idle groups is improved. This effectively improves the overall operational efficiency of a storage device by employing a strategy that manages memory module operations using virtual units across chip enable regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 is a schematic diagram of a memory module according to an embodiment of the present invention;

[0013] Figure 4 is a schematic diagram showing that a plurality of chip enable regions respectively include a plurality of entity units according to an embodiment of the present invention;

[0014] Figure 5 is a schematic diagram of establishing multiple virtual units spanning different chip enable regions according to an embodiment of the present invention;

[0015] Figure 6 is a schematic diagram of establishing multiple virtual units spanning different chip enable regions according to an embodiment of the present invention;

[0016] Figure 7 is a schematic diagram of establishing multiple virtual units spanning different chip enable regions according to an embodiment of the present invention;

[0017] Figure 8 FIG. 4 is a flow chart of a data writing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0019] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0020] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0021] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0022] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0023] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0024] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0025] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0026] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0027] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0028] Figure 3 FIG is a schematic diagram of a memory module according to an embodiment of the present invention. Figure 3 The memory module 122 may include a plurality of chip enable (CE) regions CE(1)-CE(m). For example, each of the chip enable regions CE(1)-CE(m) may include one or more planes (also referred to as memory planes). Each plane may include a plurality of physical units. Each physical unit includes a plurality of memory cells and is used to store data in a non-volatile manner.

[0029] In one embodiment, when the signal corresponding to chip enable region CE(i) (also referred to as a chip enable signal) is pulled down, memory module 122 can read data from chip enable region CE(i) or store data in chip enable region CE(i). In one embodiment, the chip enable signals corresponding to multiple chip enable regions among chip enable regions CE(1) to CE(m) can be pulled up simultaneously to access the multiple chip enable regions simultaneously. However, if the chip enable signal corresponding to chip enable region CE(i) is not pulled up, memory module 122 cannot access chip enable region CE(i).

[0030] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0031] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs and are not limited by the present invention. In one embodiment, a physical programming unit may be considered a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, but the present invention is not limited to this.

[0032] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0033] In one embodiment, a physical erase unit may include multiple physical programming units. Multiple physical programming units in a physical erase unit may be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to multiple physical programming units in the physical erase unit to change the threshold voltages of at least some of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, data stored in the physical erase unit may be cleared.

[0034] In one embodiment, the memory control circuit 23 may be connected to the memory module 122 via channels CH(1)-CH(n). The memory control circuit 23 may access physical cells in the chip enable regions CE(1)-CE(m) via the channels CH(1)-CH(n). For example, each of the channels CH(1)-CH(n) may be connected to and used to access physical cells in at least one of the chip enable regions CE(1)-CE(m). In one embodiment, the total number of channels CH(1)-CH(n) is 16, but the present invention is not limited thereto.

[0035] In one embodiment, the memory control circuit 23 may establish multiple virtual units (also referred to as virtual blocks). The multiple virtual units may respectively span (or cover) a portion of the chip enable regions CE(1) to CE(m). It should be noted that the present invention does not limit the total number of chip enable regions spanned by a virtual unit. Each virtual unit may include multiple physical units. The memory control circuit 23 may manage and access the physical units in the memory module 122 based on the established virtual units.

[0036] In one embodiment, the memory control circuit 23 may configure multiple logical units to map the physical units in the memory module 122. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. If a physical unit is mapped by a logical unit, the memory control circuit 23 may determine that the data stored in the physical unit includes valid data. However, if a physical unit is not mapped by any logical unit, the memory control circuit 23 may determine that the data stored in the physical unit does not include valid data.

[0037] In one embodiment, if the physical cells included in a virtual unit are mapped by logical units, the memory control circuit 23 may determine that the data stored in the virtual unit includes valid data. However, if all the physical cells in a virtual unit are not mapped by any logical units, the memory control circuit 23 may determine that the data stored in the virtual unit does not include valid data.

[0038] In one embodiment, the memory control circuit 23 may establish a plurality of idle groups (also referred to as idle pools). Each of the plurality of idle groups corresponds to at least one of the plurality of virtual units. In one embodiment, if a virtual unit does not store valid data, the memory control circuit 23 may add the virtual unit to the idle group corresponding to the virtual unit in the plurality of idle groups. In one embodiment, if multiple virtual units do not store valid data, the memory control circuit 23 may add the virtual units that do not store valid data to the idle groups corresponding to the virtual units that do not store valid data.

[0039] In one embodiment, the plurality of idle groups include a first idle group and a second idle group. The first idle group corresponds to a portion of the plurality of virtual units (also referred to as the first virtual unit). The second idle group corresponds to another portion of the plurality of virtual units (also referred to as the second virtual unit).

[0040] In one embodiment, the first dummy unit may span at least a portion of the chip enable regions CE(1)-CE(m) (also referred to as the first chip enable region). The second dummy unit may span another portion of the chip enable regions CE(1)-CE(m) (also referred to as the second chip enable region).

[0041] It should be noted that the first chip-enable region and the second chip-enable region do not overlap. For example, if the first dummy unit spans chip-enable regions CE(1) to CE(j) (i.e., the first chip-enable region), the second dummy unit can span chip-enable regions CE(j+1) to CE(m) (i.e., the second chip-enable region), but the present invention is not limited to this.

[0042] In one embodiment, the total number of the first chip-enable regions may be the same as the total number of the second chip-enable regions. In one embodiment, the total number of the first chip-enable regions may be different from the total number of the second chip-enable regions.

[0043] In one embodiment, the memory control circuit 23 can detect a data write event. In one embodiment, the data write event can be generated in response to a write instruction from the host system 11. For example, the write instruction obtained from the host system 11 can instruct the storage of specific data (also referred to as first data). In one embodiment, the data write event can be generated in response to a data cleanup operation within the memory module 122. For example, the data cleanup operation can include a garbage collection (GC) operation, a wear leveling (WL) operation, a bad block replacement operation, or other operations involving data movement within the storage device 12, the present invention is not limited hereto.

[0044] In one embodiment, based on the aforementioned data write event, the memory control circuit 23 may determine at least one idle group (also referred to as a target idle group) from the aforementioned plurality of idle groups. After determining the target idle group, the memory control circuit 23 may extract at least one virtual unit (also referred to as a target virtual unit) from the target idle group and perform a data write operation on the target virtual unit. For example, in this data write operation, the memory control circuit 23 may send a write command sequence to the memory module 122 via at least one of the channels CH(1) to CH(n). This write command sequence may instruct the memory module 122 to store the data to be stored corresponding to the aforementioned data write event in the target virtual unit.

[0045] In one embodiment, after storing data in the target virtual unit, the memory control circuit 23 may determine whether the target virtual unit meets a specific condition (also referred to as a preset condition). If the target virtual unit meets the preset condition, the memory control circuit 23 may return the target virtual unit to the target idle group. However, if the target virtual unit does not meet the preset condition, the memory control circuit 23 may not return the target virtual unit to the target idle group. In one embodiment, the operations of extracting the target virtual unit from the target idle group and returning the target virtual unit to the target idle group are both logical operations, and the physical location of the target virtual unit may not be moved.

[0046] In one embodiment, the memory control circuit 23 may determine whether the target virtual unit still stores valid data. If the target virtual unit still stores valid data (e.g., at least one physical unit in the target virtual unit still stores valid data), the memory control circuit 23 may determine that the target virtual unit does not meet a predetermined condition and does not return the target virtual unit to the target idle group. However, if the target virtual unit does not store valid data (e.g., all physical units in the target virtual unit do not store valid data), the memory control circuit 23 may determine that the target virtual unit meets the predetermined condition and returns the target virtual unit to the target idle group.

[0047] Figure 4 FIG is a schematic diagram showing that a plurality of chip enable regions include a plurality of entity units according to an embodiment of the present invention. Figure 4 , assuming Figure 3 The memory module 122 includes chip enable regions CE(1) to CE(8). Each of the chip enable regions CE(1) to CE(8) includes physical units PB(1) to PB(k) arranged in sequence. In one embodiment, the total number of physical units included in different chip enable regions may also be different, which is not limited by the present invention. In addition, the arrangement of the multiple physical units in each chip enable region may also be adjusted according to practical needs, which is not limited by the present invention.

[0048] Figure 5 FIG is a schematic diagram showing a method of establishing multiple virtual units across different chip enable regions according to an embodiment of the present invention. Figure 5 In one embodiment, the memory control circuit 23 may establish virtual cells VB1(1)-VB1(s) and VB2(1)-VB2(s). Each of the virtual cells VB1(1)-VB1(s) spans the chip enable regions CE(1)-CE(4). For example, the virtual cell VB1(i) may include Figure 4 Multiple physical cells PB(i) in the chip enable region CE(1) to CE(4). Each of the virtual cells VB2(1) to VB2(s) spans the chip enable region CE(5) ​​to CE(8). For example, the virtual cell VB2(i) may include Figure 4 Multiple physical cells PB(i) in the chip enable area CE(5)~CE(8).

[0049] On the other hand, the memory control circuit 23 can establish idle groups 51 and 52. Virtual cells VB1(1)-VB1(s) correspond to idle group 51. Virtual cells VB2(1)-VB2(s) correspond to idle group 52. In one embodiment, it is assumed that in the initial state, virtual cells VB1(1)-VB1(s) are all located in idle group 51, and virtual cells VB2(1)-VB2(s) are all located in idle group 52.

[0050] In one embodiment, based on a detected data write event, the memory control circuit 23 may determine at least one of the idle groups 51 and 52 as a target idle group. If the memory control circuit 23 determines the idle group 51 as the target idle group, the memory control circuit 23 may determine the virtual unit VB1(p) from the virtual units VB1(1) to VB1(s) as the target virtual unit. Alternatively, if the memory control circuit 23 determines the idle group 52 as the target idle group, the memory control circuit 23 may determine the virtual unit VB2(q) from the virtual units VB2(1) to VB2(s) as the target virtual unit. The memory control circuit 23 may then perform a data write operation on the target virtual unit (e.g., virtual unit VB1(p) and / or VB2(q)) to store the data to be stored corresponding to the data write event in the target virtual unit.

[0051] In one embodiment, if the target virtual cell (e.g., virtual cell VB1(p) and / or VB2(q)) satisfies a predetermined condition, the memory control circuit 23 may return the target virtual cell to the target idle group. For example, if virtual cell VB1(p) satisfies a predetermined condition, the memory control circuit 23 may return virtual cell VB1(p) to the idle group 51. Alternatively, if virtual cell VB2(q) satisfies a predetermined condition, the memory control circuit 23 may return virtual cell VB2(q) to the idle group 52.

[0052] It should be noted that the present invention does not limit the total number of chip enable regions spanned by a virtual unit and the total number of the idle groups.

[0053] Figure 6 FIG is a schematic diagram showing a method of establishing multiple virtual units across different chip enable regions according to an embodiment of the present invention. Figure 6 In one embodiment, the memory control circuit 23 may establish virtual cells VB1(1) to VB1(s), VB2(1) to VB2(s), VB3(1) to VB3(s), and VB4(1) to VB4(s). Each of the virtual cells VB1(1) to VB1(s) spans the chip enable regions CE(1) and CE(2). For example, the virtual cell VB1(i) may include Figure 4Each of the virtual cells VB2(1) and VB2(s) spans the chip enable regions CE(3) and CE(4). For example, the virtual cell VB2(i) may include the multiple physical cells PB(i) in the chip enable regions CE(3) and CE(4). Each of the virtual cells VB3(1) and VB3(s) spans the chip enable regions CE(5) ​​and CE(6). For example, the virtual cell VB3(i) may include the multiple physical cells PB(i) in the chip enable regions CE(5) ​​and CE(6). Each of the virtual cells VB4(1) and VB4(s) spans the chip enable regions CE(7) and CE(8). For example, the virtual cell VB4(i) may include the multiple physical cells PB(i) in the chip enable regions CE(7) and CE(8).

[0054] On the other hand, the memory control circuit 23 can establish idle groups 61 to 64. Virtual cells VB1(1) to VB1(s) correspond to idle group 61. Virtual cells VB2(1) to VB2(s) correspond to idle group 62. Virtual cells VB3(1) to VB3(s) correspond to idle group 63. Virtual cells VB4(1) to VB4(s) correspond to idle group 64. In one embodiment, it is assumed that in the initial state, virtual cells VB1(1) to VB1(s) are all located in idle group 61, virtual cells VB2(1) to VB2(s) are all located in idle group 62, virtual cells VB3(1) to VB3(s) are all located in idle group 63, and virtual cells VB4(1) to VB4(s) are all located in idle group 64.

[0055] In one embodiment, based on a detected data write event, the memory control circuit 23 may determine at least one of the idle groups 61-64 as a target idle group. Taking idle group 63 as an example, after idle group 63 is determined as the target idle group, the memory control circuit 23 may determine virtual unit VB3(r) from virtual units VB3(1)-VB3(s) as the target virtual unit. The memory control circuit 23 may then perform a data write operation on the target virtual unit (e.g., virtual unit VB3(r)) to store the data to be stored corresponding to the data write event in the target virtual unit.

[0056] In one embodiment, if the target virtual cell (e.g., virtual cell VB3(r)) satisfies a predetermined condition, the memory control circuit 23 may return the target virtual cell to the target idle group. For example, if the virtual cell VB3(r) satisfies a predetermined condition, the memory control circuit 23 may return the virtual cell VB3(r) to the idle group 63.

[0057] In one embodiment, different virtual units may span different total numbers of chip enable regions.

[0058] Figure 7 FIG is a schematic diagram showing a method of establishing multiple virtual units across different chip enable regions according to an embodiment of the present invention. Figure 7 , the memory control circuit 23 can establish virtual cells VB1(1) to VB1(s), VB2(1) to VB2(s), and VB3(1) to VB3(s). Each of the virtual cells VB1(1) to VB1(s) spans chip enable regions CE(1) to CE(3). Each of the virtual cells VB2(1) and VB2(s) spans chip enable regions CE(4) to CE(6). In addition, each of the virtual cells VB3(1) and VB3(s) spans chip enable regions CE(7) and CE(8).

[0059] On the other hand, the memory control circuit 23 can establish idle groups 71-73. Virtual units VB1(1)-VB1(s) correspond to idle group 71. Virtual units VB2(1)-VB2(s) correspond to idle group 72. Virtual units VB3(1)-VB3(s) correspond to idle group 73. For other operational details, please refer to the description of the aforementioned embodiments and will not be elaborated on here.

[0060] In one embodiment, before determining the target idle group, the memory control circuit 23 may obtain the total number of virtual cells respectively included in the plurality of idle groups. Then, the memory control circuit 23 may determine the target idle group from the plurality of idle groups based on the total number. Figure 6 For example, before determining the target idle group, the memory control circuit 23 may obtain the total number of virtual cells included in each of the idle groups 61-64. The memory control circuit 23 may then determine the target idle group from among the idle groups 61-64 based on the total number. This prevents overuse of some virtual cells and effectively achieves the goal of distributing or balancing the use of virtual cells corresponding to different idle groups.

[0061] In one embodiment, based on the total number, the memory control circuit 23 may determine the idle group containing the most or relatively more virtual units among the plurality of idle groups as the target idle group. Figure 6 For example, assuming that the total number of virtual units included in the idle groups 61 to 64 is "20", "25", "60" and "10" respectively, the memory control circuit 23 can determine the idle group 63 that includes the largest or relatively more virtual units among the idle groups 61 to 64 as the target idle group.

[0062] In one embodiment, based on the total number, the memory control circuit 23 may further logically sort the plurality of idle groups and obtain a sorting result. Then, the memory control circuit 23 may determine a target idle group based on the sorted plurality of idle groups (i.e., the sorting result). Figure 6 For example, assuming that the total number of virtual units contained in idle groups 61 to 64 is "20", "25", "60" and "10" respectively, the memory control circuit 23 can logically sort the idle groups 61 to 64 according to the total number, for example, sorting the idle groups 61 to 64 into idle groups 63, 62, 61 and 64. The sorted idle groups 61 to 64 can synchronously reflect the total number of virtual units contained in the idle groups 61 to 64 respectively. Then, the memory control circuit 23 can determine the idle group 63 sorted at the endpoint position (indicating that the idle group 63 contains the most or relatively more virtual units) as the target idle group. Specifically, according to the sorting results of the total number from largest to smallest: "60", "25", "20", the idle group 63 is determined as the target idle group.

[0063] In one embodiment, the memory control circuit 23 may further compare the total number with a threshold value (also referred to as a first threshold value) and obtain a comparison result. Then, the memory control circuit 23 may determine a target idle group based on the comparison result. In one embodiment, if the comparison result shows that the total number of virtual units included in a specific idle group among the plurality of idle groups is less than the first threshold value, the memory control circuit 23 may not determine the specific idle group as the target idle group. Figure 6 For example, assume that the total number of virtual cells included in idle groups 61-64 is "20," "25," "60," and "10," respectively, and the first threshold is "15." In this example, the total number of virtual cells included in idle group 64 (i.e., "10") is less than the first threshold (i.e., "15"), indicating that the virtual cells in idle group 64 are overused compared to the virtual cells in the remaining idle groups 61-63. In this case, the memory control circuit 23 may not determine idle group 64 as a target idle group candidate. That is, after excluding idle group 64, the memory control circuit 23 may determine a target idle group from the remaining idle groups 61-63. For example, idle group 63, which contains the most or relatively more virtual cells among the idle groups 61-63, is determined as the target idle group.

[0064] In one embodiment, the memory control circuit 23 may further compare the total number with another threshold value (also referred to as a second threshold value) and obtain a comparison result. Then, the memory control circuit 23 may determine the target idle group based on the comparison result. In one embodiment, if the comparison result shows that the total number of virtual units included in a specific idle group among the plurality of idle groups is greater than the second threshold value, the memory control circuit 23 may determine the specific idle group as the target idle group. Figure 6 For example, assume that the total number of virtual cells included in idle groups 61-64 is "20," "25," "60," and "10," respectively, and the second threshold is "40." In this example, the total number of virtual cells included in idle group 63 (i.e., "60") is greater than the second threshold (i.e., "40"), indicating that the virtual cells in idle group 63 are less utilized than the virtual cells in the remaining idle groups 61, 62, and 64. In this case, the memory control circuit 23 may determine idle group 63 as the target idle group. That is, in this example, the memory control circuit 23 may also determine idle group 63, which contains the largest or relatively large number of virtual cells among idle groups 61-64, as the target idle group.

[0065] In one embodiment, the memory control circuit 23 may determine or adjust the threshold (eg, the first threshold and / or the second threshold) according to the total number of virtual cells in the plurality of idle groups (eg, idle groups 61-64). Figure 6 For example, the memory control circuit 23 may determine or adjust the thresholds (e.g., the first threshold and / or the second threshold) based on an average value of the total number of dummy cells in the idle groups 61-64. For example, the average value of the total number of dummy cells in the idle groups 61-64 may be positively correlated with the thresholds (e.g., the first threshold and / or the second threshold).

[0066] In one embodiment, before determining the target idle group, the memory control circuit 23 may further detect whether a data cleanup operation (such as a garbage collection operation, a wear leveling operation, or a bad block replacement operation) is currently being performed on the virtual units corresponding to a specific idle group among the plurality of idle groups. If a data cleanup operation is currently being performed on the virtual units corresponding to the specific idle group, the memory control circuit 23 may not determine the specific idle group as the target idle group. Figure 6For example, assuming that a garbage collection operation is currently being performed on virtual unit VB4(1), the memory control circuit 23 may not determine the idle group 64 corresponding to virtual unit VB4(1) as the target idle group. For example, after excluding idle group 64, the memory control circuit 23 may determine the target idle group from the remaining idle groups 61-63. In this way, overuse of some virtual units can be avoided, effectively achieving the purpose of distributing or balancing the use of virtual units corresponding to different idle groups.

[0067] In one embodiment, the memory control circuit 23 may further determine the type of at least one write instruction based on the data write event. The memory control circuit 23 may then determine a target idle group from the plurality of idle groups based on the type of the at least one write instruction and store the data (i.e., the first data) indicated by the at least one write instruction (or the data write event) into a virtual unit extracted from the target idle group. For example, based on different types of write instructions, the memory control circuit 23 may select one or more appropriate virtual units from the plurality of idle groups and then perform single-channel data write or multi-channel parallel data write on the selected virtual units. This effectively improves the data write performance of the storage device 12.

[0068] In one embodiment, the type of the at least one write instruction may reflect whether the data stored indicated by the data write event (i.e., the first data) includes sequential write data or random write data. For example, sequential write data is written to consecutive logical units (and / or consecutive physical units), while random write data is written to discontinuous logical units (and / or discontinuous physical units). Alternatively, in one embodiment, the type of the at least one write instruction may reflect the importance of the data stored indicated by the data write event (i.e., the first data). For example, system data used to manage the storage device 12 (e.g., a logical-to-physical mapping table or other management data used to manage the mapping relationship between logical units and physical units) may be more important than general user data. Alternatively, in one embodiment, the type of the at least one write instruction may reflect whether the data stored indicated by the data write event (i.e., the first data) includes cold data or hot data. For example, if the update frequency of data stored in a particular logical unit is higher than a preset frequency, the data may be determined to be hot data. However, if the update frequency of data stored in the particular logical unit is not higher than the preset frequency, the data may be determined to be cold data. It should be noted that the type of the at least one write instruction may also reflect other types of data to be stored, as long as it helps improve the data writing performance of the storage device 12 , and the present invention is not limited thereto.

[0069] In one embodiment, the memory control circuit 23 may further adjust the order of at least one write command. The memory control circuit 23 may then select one or more appropriate virtual units from the plurality of idle groups based on the adjusted order of the at least one write command, and then perform single-channel data writing or multi-channel parallel data writing on the selected virtual units. For example, by adjusting the order of some write commands, the memory control circuit 23 may instruct the memory module 12 to continuously write previously dispersed data to one or more specially selected virtual units, thereby improving the data writing performance of the storage device 12.

[0070] In one embodiment, by determining the target idle group through the various screening mechanisms described above, the virtual units corresponding to each idle group can be used as evenly as possible (equivalent to preventing the virtual units belonging to a particular idle group from being overused). This effectively improves the operating performance of the storage device 12 and / or extends the service life of the storage device 12. It should be noted that the above-mentioned target idle group selection mechanism can also be adjusted according to practical needs and is not limited by the present invention.

[0071] Figure 8 This is a flow chart of a data writing method according to an embodiment of the present invention. Figure 8 In step S801, a plurality of virtual units are established, wherein the plurality of virtual units respectively span a portion of the chip enable region in the memory module. In step S802, a plurality of idle groups are established, wherein the plurality of idle groups respectively correspond to at least one of the plurality of virtual units. In step S803, a data write event is detected. In step S804, a target idle group is determined from the plurality of idle groups based on the data write event. In step S805, a target virtual unit is extracted from the target idle group, and a data write operation is performed on the target virtual unit. In step S806, it is determined whether the target virtual unit meets a preset condition. If the target virtual unit meets the preset condition (for example, the target virtual unit does not store valid data), then in step S807, the target virtual unit is returned to the target idle group. However, if the target virtual unit does not meet the preset condition, step S806 may be repeated until it is determined that the target virtual unit meets the preset condition.

[0072] However, Figure 8 The steps have been described in detail above and will not be repeated here. Figure 8 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 8 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0073] In summary, the data writing method and storage device proposed in the embodiment of the present invention can improve the flexibility of using virtual units by establishing multiple virtual units across different chip enable regions and the idle groups corresponding to the multiple virtual units, and can improve the efficiency of extraction and return between the multiple virtual units and the idle groups corresponding to them. In addition, by determining the target idle group through a special screening mechanism, the virtual units corresponding to each idle group can be used as evenly as possible (equivalent to avoiding the excessive use of virtual units belonging to a specific idle group). Thus, the working efficiency of the storage device can be effectively improved, and / or the service life of the storage device can be extended. Thus, under the operating strategy of managing the memory module by using virtual units across chip enable regions, the overall operating efficiency of the storage device can be effectively improved.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data writing method, characterized in that: For a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of chip enable regions, and the data writing method includes: Establishing a plurality of virtual units, wherein the plurality of virtual units respectively span a portion of the chip enable regions among the plurality of chip enable regions, and the chip enable regions spanned by the virtual units do not overlap with each other; establishing a plurality of idle groups, wherein the plurality of idle groups respectively correspond to at least one of the plurality of virtual units; Detect data write events; determining a target idle group from the plurality of idle groups according to the data writing event; extracting a target virtual unit from the target idle group and performing a data write operation on the target virtual unit; and If the target virtual unit meets a preset condition, the target virtual unit is returned to the target idle group.

2. The data writing method according to claim 1 , wherein the step of determining the target idle group from the plurality of idle groups comprises: Obtaining the total number of virtual units respectively included in the plurality of idle groups; as well as The target idle group is determined from the plurality of idle groups according to the total number.

3. The data writing method according to claim 2 , wherein the step of determining the target idle group from the plurality of idle groups according to the total number comprises: sorting the plurality of idle groups according to the total number to obtain a sorting result; as well as The target idle group is determined from the plurality of idle groups according to the sorting result.

4. The data writing method according to claim 2 , wherein the step of determining the target idle group from the plurality of idle groups according to the total number comprises: comparing the total with a critical value to obtain a comparison result; as well as The target idle group is determined from the plurality of idle groups according to the comparison result.

5. The data writing method according to claim 4 , wherein the step of determining the target idle group from the plurality of idle groups according to the comparison result comprises: If the total number of virtual units included in a specific idle group among the plurality of idle groups is smaller than a first threshold, the specific idle group is not determined as the target idle group.

6. The data writing method according to claim 4 , wherein the step of determining the target idle group according to the comparison result comprises: If the total number of virtual units included in a specific idle group among the plurality of idle groups is greater than a second threshold, the specific idle group is determined as the target idle group.

7. The data writing method according to claim 1 , wherein the step of determining the target idle group from the plurality of idle groups comprises: If a data arrangement operation for a virtual unit corresponding to a specific idle group among the plurality of idle groups is currently being executed, the specific idle group is not determined as the target idle group.

8. The data writing method according to claim 1 , further comprising: If the target virtual unit does not store valid data, it is determined that the target virtual unit meets the preset condition.

9. The data writing method according to claim 1 , wherein the step of determining the target idle group from the plurality of idle groups according to the data writing event comprises: determining a type of at least one write instruction according to the data write event; as well as The target idle group is determined from the plurality of idle groups according to the type.

10. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of chip enable regions, and the memory controller is configured to: Establishing a plurality of virtual units, wherein the plurality of virtual units respectively span a portion of the chip enable regions among the plurality of chip enable regions, and the chip enable regions spanned by the virtual units do not overlap with each other; establishing a plurality of idle groups, wherein the plurality of idle groups respectively correspond to at least one of the plurality of virtual units; Detect data write events; determining a target idle group from the plurality of idle groups according to the data writing event; extracting a target virtual unit from the target idle group, and performing a data writing operation on the target virtual unit; as well as If the target virtual unit meets a preset condition, the target virtual unit is returned to the target idle group.

11. The storage device according to claim 10 , wherein the operation of the memory controller determining the target idle group from the plurality of idle groups comprises: Obtaining the total number of virtual units respectively included in the plurality of idle groups; as well as The target idle group is determined from the plurality of idle groups according to the total number.

12. The storage device according to claim 11 , wherein the memory controller determines the target idle group from the plurality of idle groups according to the total number, comprising: sorting the plurality of idle groups according to the total number to obtain a sorting result; as well as The target idle group is determined from the plurality of idle groups according to the sorting result.

13. The storage device according to claim 11 , wherein the memory controller determines the target idle group from the plurality of idle groups according to the total number, comprising: comparing the total with a critical value to obtain a comparison result; as well as The target idle group is determined from the plurality of idle groups according to the comparison result.

14. The storage device according to claim 13 , wherein the memory controller determines the target idle group from the plurality of idle groups according to the comparison result, comprising: If the total number of virtual units included in a specific idle group among the plurality of idle groups is smaller than a first threshold, the specific idle group is not determined as the target idle group.

15. The storage device according to claim 13 , wherein the memory controller determines the target idle group according to the comparison result, comprising: If the total number of virtual units included in a specific idle group among the plurality of idle groups is greater than a second threshold, the specific idle group is determined as the target idle group.

16. The storage device according to claim 10, wherein the operation of the memory controller determining the target idle group from the plurality of idle groups comprises: If a data arrangement operation for a virtual unit corresponding to a specific idle group among the plurality of idle groups is currently being executed, the specific idle group is not determined as the target idle group.

17. The storage device according to claim 10, wherein the memory controller is further configured to: If the target virtual unit does not store valid data, it is determined that the target virtual unit meets the preset condition.

18. The storage device according to claim 10, wherein the operation of the memory controller determining the target idle group from the plurality of idle groups according to the data write event comprises: determining a type of at least one write instruction according to the data write event; as well as The target idle group is determined from the plurality of idle groups according to the type.

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