Test method, test circuit, device and readable storage medium

Abstract

The embodiment of the invention provides a test method, a test circuit, a test device and a readable storage medium. The testing method comprises the steps that a target data stream is provided for a data receiving circuit of the storage system, the target data stream comprises a first value and a second value which alternately appear and are different from each other, and the data receiving circuit has a decision feedback equalization mode; the data receiving circuit receives the target data stream and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode; generating a corresponding eye pattern based on the output signal; and obtaining a test value for representing the performance of the decision feedback equalization mode based on the eye pattern.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a testing method, a testing circuit, a device, and a readable storage medium. Background Art

[0002] The operating rates of memory devices, including the data rates of memory devices, have increased over time. As a side effect of the increased speed of memory devices, data errors due to distortion may increase. For example, inter-symbol interference between transmitted data may occur so that previously received data affects currently received data (e.g., previously received data affects and interferes with subsequently received data). One way to correct for this interference is by using a decision feedback equalizer (DFE) circuit that can be programmed to counteract (i.e., cancel, mitigate, or cancel) the effects of the channel on the transmitted data. Summary of the invention

[0003] The embodiments of the present disclosure provide a testing method, a testing circuit, a device, and a readable storage medium, which can at least test the performance of a decision feedback mode.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a testing method applied to a storage system, comprising: providing a target data stream to a data receiving circuit of the storage system, the target data stream comprising a first value and a second value that appear alternately and are different from each other, the data receiving circuit having a decision feedback equalization mode; the data receiving circuit receives the target data stream, and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode; generating a corresponding eye diagram based on the output signal; and obtaining a test value for characterizing the performance of the decision feedback equalization mode based on the eye diagram.

[0005] In some embodiments, the output signal corresponding to the target data stream and the decision feedback equalization function includes: the data receiving circuit does not enable the decision feedback equalization mode, and outputs the original output signal corresponding to the target data stream; the data receiving circuit enables the decision feedback equalization mode, and outputs the corrected output signal corresponding to the target data stream; the generating a corresponding eye diagram based on the output signal includes: generating an original eye diagram based on the original output signal; generating a corrected eye diagram based on the corrected output signal; and obtaining a test value for characterizing the performance of the decision feedback equalization mode includes: obtaining the test value based on the difference between the corrected eye diagram and the original eye diagram.

[0006] In some embodiments, obtaining the test value based on the difference between the corrected eye diagram and the original eye diagram includes: obtaining a first difference between a maximum reference voltage corresponding to the corrected eye diagram and a maximum reference voltage corresponding to the original eye diagram, and using the first difference as the test value.

[0007] In some embodiments, obtaining the test value based on the corrected eye diagram and the original eye diagram includes: obtaining a second difference between a minimum reference voltage corresponding to the corrected eye diagram and a minimum reference voltage corresponding to the original eye diagram, and using the absolute value of the second difference as the test value.

[0008] In some embodiments, the decision feedback equalization mode has different gears; the testing method further includes: obtaining a plurality of the corrected output signals, and the corrected output signals correspond one-to-one to each gear; based on the original eye diagram and the corrected eye diagram corresponding to any gear, obtaining a test value corresponding to the gear.

[0009] In some embodiments, the test method further includes: obtaining a characterization curve based on the test values ​​corresponding to different gears, wherein the abscissa of the characterization curve represents the gear, and the ordinate of the characterization curve represents the test value.

[0010] In some embodiments, the target data stream includes a binary data stream 0101010101 or a binary data stream 1010101010.

[0011] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure provides a test circuit, which is applied to a storage system, including: a data stream input circuit, configured to provide a target data stream to a data receiving circuit of the storage system, the target data stream including a first value and a second value that appear alternately and are different from each other, the data receiving circuit having a decision feedback equalization mode, the data receiving circuit receiving the target data stream, and outputting an output signal corresponding to the target data stream and the decision feedback equalization mode; an eye diagram generating circuit, configured to generate a corresponding eye diagram based on the output signal; and a processing circuit, configured to obtain a test value for characterizing the performance of the decision feedback equalization mode based on the eye diagram.

[0012] In some embodiments, it also includes: a control circuit configured to control whether the data receiving circuit enables the decision feedback equalization mode; the eye diagram generating circuit is configured to generate an original eye diagram based on an original output signal, and the original output signal is an output signal that the data receiving circuit does not enable the decision feedback equalization mode, receives the target data stream and outputs; the eye diagram generating circuit is also configured to generate a corrected eye diagram based on a corrected output signal, and the corrected output signal is an output signal that the data receiving circuit enables the decision feedback equalization mode, receives the target data stream and outputs.

[0013] In some embodiments, the processing circuit is further configured to obtain the test value based on a difference between the corrected eye diagram and the original eye diagram.

[0014] In some embodiments, the decision feedback equalization mode has different gears; the control circuit is further configured to control the data receiving circuit to enable the decision feedback equalization mode at different gears.

[0015] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a device, including a storage system and a test circuit provided by any of the above embodiments.

[0016] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure provides a readable storage medium, including: a program stored in the readable storage medium, the program is used to enable a processor to perform the following operations: generate a target data stream, the target data stream includes suppression and second values ​​that appear alternately and are different from each other; provide the target data stream to a data receiving circuit of a storage system, the data receiving circuit has a decision feedback equalization mode, the data receiving circuit receives the target data stream, and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode; generate a corresponding eye diagram based on the output signal; based on the eye diagram, obtain a test value for characterizing the performance of the decision feedback equalization mode.

[0017] In some embodiments, the program is also used to instruct the processor to perform the following operations: control the data receiving circuit to not enable the decision feedback equalization mode to output the original output signal corresponding to the target data stream; control the data receiving circuit to enable the decision feedback equalization mode to output the corrected output signal corresponding to the target data stream; generate an original eye diagram based on the original output signal; generate a corrected eye diagram based on the corrected output signal; and obtain the test value based on the difference between the corrected eye diagram and the original eye diagram.

[0018] In some embodiments, the program is also used to instruct the processor to perform the following operations: obtain a first difference between a maximum reference voltage corresponding to the corrected eye diagram and a maximum reference voltage corresponding to the original eye diagram, and use the first difference as the test value.

[0019] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0020] In the disclosed embodiment, since the target data stream is a first value and a second value that appear alternately and are different from each other, that is, the target data stream is 0 and 1 that appear alternately or 1 and 0 that appear alternately, in this case, the amount of inter-symbol interference is minimal, and the degree of decision feedback equalization processing performed by the data receiving circuit can best reflect the equalization performance. Therefore, the test value obtained by testing based on this target data stream can best reflect the actual performance value, and can more accurately reflect the performance of the decision feedback equalization mode, effectively avoiding the problem of underestimating the performance of the decision feedback equalization mode, thereby improving the test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 is a block diagram of a data receiving circuit;

[0023] Figure 2 A flow chart of a testing method provided in an embodiment of the present disclosure;

[0024] Figure 3 The eye diagram obtained in the test method;

[0025] Figure 4 It is a characterization curve obtained in the test method;

[0026] Figure 5 A block diagram of a test circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Currently, there is still no good definition of simulation or test methods for the balance amount in DFE performance. The balance amount in DFE performance is difficult to measure using a direct current (DC) method, and there is currently no clear specification to define the test of the balance amount of DFE, which makes it difficult to compare the DFE performance of memory devices horizontally.

[0028] Based on the above requirements, an embodiment of the present disclosure provides a testing method, which uses a test value to measure the performance of a decision feedback equalization mode, and the test accuracy is high.

[0029] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0030] The test method provided by the embodiment of the present disclosure can be applied to a storage system, and the data receiving circuit of the storage system has a decision feedback equalization mode. That is, the data receiving circuit includes a decision feedback equalization circuit (hereinafter referred to as a DFE circuit).

[0031] The storage system may be DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). In some embodiments, the storage system may be SDRAM (Synchronous Dynamic Random Access Memory), which may be DDR (Double Data Rate) SDRAM, such as DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory or LPDDR6 memory.

[0032] Testing the DFE circuit of the storage system can, on the one hand, confirm whether the compensation value generated by the DFE circuit can correctly compensate for the distortion in the received data to ensure that the accurate value is stored in or read from the storage system. On the other hand, the equalization amount of the DFE circuit can be learned. The size of the equalization amount based on different storage systems can be used as one of the indicators for evaluating the difference in decision feedback equalization effects of different storage systems.

[0033] According to the number of bits of input data participating in DFE in the previously transmitted input data, the DFE circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap and 4-tap equalization circuits. The DFE circuit can even have more (that is, the number of taps can be greater than 4) taps. Tap means taps. It can be understood that the DFE circuit can include multiple tap adjustment circuits, each of which corresponds to a tap signal, and a tap signal corresponds to a bit of data. The currently transmitted input data is adjusted according to the tap signal. Among them, 1-tap means that the previously transmitted 1-bit data participates in DFE; 2-tap means that the previously transmitted 2-bit data participates in DFE; 3-tap means that the previously transmitted 3-bit data participates in DFE; 4-tap means that the previously transmitted 4-bit data participates in DFE.

[0034] It should be noted that, if specifically stated, in the disclosed embodiments, n-tap refers to the n-bit data previously transmitted participating in DFE, and Tap-n refers to the n-th bit data previously transmitted participating in DFE. For example, Tap-1 refers to the 1st bit data previously transmitted participating in DFE, and Tap-2 refers to the 2nd bit data previously transmitted participating in DFE.

[0035] Figure 1 Figure 1 is a block diagram of a data receiving circuit. Figure 1 , taking the data receiving circuit including 4 data paths as an example, each data path includes an adder and a sampler (or called a limiter), wherein the adders in the 4 data paths are represented by Summer#1, Summer#2, Summer#3, and Summer#4 respectively, and the corresponding samplers are represented by Slicer#1, Slicer#2, Slicer#3, and Slicer#4 respectively, and the target data output by the corresponding data paths are represented by OUT_I, OUT_Q, OUT_IB, and OUT_QB respectively. The data receiving path may also include a DQ pin 11 for providing input data and an amplifier 12 connected to the DQ pin 11, and the amplifier 12 is connected to the adder. Among them, multiple data paths can share the amplifier 12. Among them, the phases of the sampling clocks received by the data paths that output the target data OUT_I, OUT_Q, OUT_IB, OUT_QB, can be 0°, 90°, 180°, and 270° respectively.

[0036] For the data path of the output target data OUT_I: adder Summer#1 receives the feedback signal from the output of sampler Slicer#4 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#3 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#2 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#1 as Tap-4 participating in DFE.

[0037] For the data path of the output target data OUT_Q: adder Summer#2 receives the feedback signal from the output of sampler Slicer#1 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#4 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#3 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#2 as Tap-4 participating in DFE.

[0038] For the data path of the output target data OUT_IB: adder Summer#3 receives the feedback signal from the output of sampler Slicer#2 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#1 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#4 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#3 as Tap-4 participating in DFE.

[0039] For the data path of the output target data OUT_QB: adder Summer#4 receives the feedback signal from the output of sampler Slicer#3 as Tap-1 participating in DFE; receives the feedback signal from the output of sampler Slicer#2 as Tap-2 participating in DFE; receives the feedback signal from the output of sampler Slicer#11 as Tap-3 participating in DFE; receives the feedback signal from the output of sampler Slicer#4 as Tap-4 participating in DFE.

[0040] The DFE circuit includes the adder described above.

[0041] Figure 2 A flowchart of a testing method provided in an embodiment of the present disclosure.

[0042] Step S1: providing a target data stream to a data receiving circuit of a storage system. The target data stream includes a first value and a second value that appear alternately and are different from each other, and the data receiving circuit has a decision feedback equalization mode.

[0043] In some examples, a target data stream can be provided to the DQ pins.

[0044] For a target data stream that is a random data stream, there are usually long "0" or long "1" situations. For example, the long "1" situation is: a long string of "1" appears first in the random data stream "11111101", followed by a "01" signal. When the long "1" signal switches to the "01" signal, there will be an inter-symbol interference problem, or even an inter-symbol interference saturation problem, which will cause the DFE circuit to be over-equalized. If the test value representing the performance of the decision feedback equalization mode is obtained based on the output signal generated by the random data stream, this test value will be lower than the actual performance value (that is, the actual performance value of the decision feedback equalization module), which leads to an underestimation of the performance of the decision feedback equalization mode. In addition, the data of the random data stream is random. When the number of consecutive "1" or consecutive "0" in the random data stream is uncertain, this will also cause the amount by which the obtained test value is lower than the actual performance value to be uncertain. In addition, the more consecutive "1" or "0" appears, the greater the degree to which the test value is lower than the actual performance value, and the poor stability of the test result.

[0045] In the disclosed embodiment, the target data stream is a binary data stream, the first value is 0, and the second value is 1. Since the target data stream is a first value and a second value that appear alternately and are different from each other, that is, the target data stream is 0 and 1 that appear alternately or 1 and 0 that appear alternately, in this case, the amount of inter-symbol interference is minimal, and the degree of equalization processing performed by the DFE circuit can most effectively reflect the equalization performance of the DFE circuit. Therefore, the test value obtained by testing based on this target data stream can best reflect the actual performance value, and can more accurately reflect the performance of the decision feedback equalization mode, effectively avoiding the problem of underestimating the performance of the decision feedback equalization mode, thereby improving the test accuracy.

[0046] In some examples, the target data stream may be a binary data stream 0101010101.

[0047] In other examples, the target data stream may be a binary data stream 1010101010.

[0048] In addition, it can be known from the above analysis that the decision feedback equalization mode may include an n-tap mode, where n is any natural number greater than or equal to 1, and n refers to the number of bits previously transmitted that participate in the decision feedback equalization.

[0049] In addition, the decision feedback equalization mode may also have different gears. Each gear corresponds to a different decision feedback equalization degree. For example, the decision feedback equalization degree of the mth gear is less than the decision feedback equalization degree of the m+1th gear, where m is any natural number greater than or equal to 1.

[0050] The gear position of the decision feedback equalization mode can be adjusted by a control code in the mode register.

[0051] Step S2: The data receiving circuit receives the target data stream and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode.

[0052] Ideally, the output signal is consistent with the target data stream. In some examples, the DQ pin receives the target data stream, compares and amplifies the voltage difference between the reference voltage and each bit in the target data stream through the amplifier, and the DFE circuit performs decision feedback equalization on the output node of the amplifier. The signal at the output node of the amplifier is transmitted to the sampler, and the sampler outputs the output signal after sampling.

[0053] Among them, the output signal corresponding to the target data stream and the decision feedback equalization function is output, including: the data receiving circuit does not enable the decision feedback equalization mode, and outputs the original output signal corresponding to the target bit stream data stream; the data receiving circuit enables the decision feedback equalization mode, and outputs the corrected output signal corresponding to the target bit stream data stream.

[0054] The original output signal is a signal that has not been subjected to decision feedback equalization, and the calibrated output signal is a signal that has been subjected to decision feedback equalization, which can reflect the degree of decision feedback equalization.

[0055] In some examples, the decision feedback equalization mode has different gears, and accordingly, a plurality of correction output signals need to be obtained, and the correction output signals correspond to each gear one by one.

[0056] Step S3: Generate a corresponding eye diagram based on the output signal.

[0057] An oscilloscope can be connected to the output of the sampler, and the scanning period of the oscilloscope can be adjusted to synchronize the horizontal scanning period of the oscilloscope with the period of the target data stream. The image seen on the oscilloscope screen looks like a human eye, so it is called an "eye diagram". The oscilloscope can be set to observe the voltage of the output signal reaching the oscilloscope, and "trigger" based on the delay of the output signal compared to the data clock signal, that is, start capturing the waveform of the output signal on the oscilloscope.

[0058] Figure 3 From left to right, the eye diagrams corresponding to the decision feedback equalization mode not turned on, the first gear, the third gear, the fifth gear, and the seventh gear are shown in sequence. The eye diagram is formed by the curve of the waveform observed by the oscilloscope. It should be noted that Figure 3 Only the shamoo plots part of the eye diagram is shown in the figure, that is, only the "eye" part of the eye diagram is shown.

[0059] The ordinate of the eye diagram is the reference voltage, the reference voltage corresponding to the highest point of the eye diagram is the maximum reference voltage, and the reference voltage corresponding to the lowest point of the eye diagram is the minimum reference voltage.

[0060] In one example, a method for obtaining an eye diagram may include: an oscilloscope receives an output signal, and compares the output signal with different reference voltages and performs sampling, wherein the horizontal axis of the eye diagram is the sampling time; the different reference voltages include a first reference voltage VH (not shown) and a second reference voltage VL (not shown). Wherein, if the voltage of the output signal is lower than the second reference voltage VL, it is identified as being sampled as "0", and if the voltage of the output signal is too much lower than the second reference voltage VL, the sampling fails and is therefore not reflected in the eye diagram. If the voltage of the output signal is higher than the first reference voltage VH, it is identified as being sampled as "1", and if the voltage of the output signal is too much higher than the first reference voltage VH, the sampling fails and is therefore not reflected in the eye diagram.

[0061] Therefore, the maximum value of the reference voltage corresponding to the eye diagram is the maximum value of the reference voltage corresponding to when the output signal can be sampled as "1". If the reference voltage is greater than the maximum value of the reference voltage, the sampling fails; the minimum value of the reference voltage corresponding to the eye diagram is the minimum value of the reference voltage corresponding to when the output signal can be sampled as "0". If the reference voltage is less than the minimum value of the reference voltage, the sampling fails.

[0062] In some examples, reference Figure 3 , generating a corresponding eye diagram based on the output signal, including: generating an original eye diagram EYE0 based on the original output signal; and generating a corrected eye diagram EYER based on the corrected output signal.

[0063] In the case where the correction output signal includes multiple ones and each correction output signal corresponds to each gear position one by one, the calibration eye diagram EYER also includes multiple ones accordingly. Figure 4 In the figure, DFE1, DFE3, DFE5, and DFE7 are used to represent the corrected eye diagram corresponding to the first gear, the corrected eye diagram of the second gear, the corrected eye diagram of the fifth gear, and the corrected eye diagram of the seventh gear, respectively.

[0064] Step S4: Based on the eye diagram, a test value for characterizing the performance of the decision feedback equalization mode is obtained.

[0065] Among them, the test value can be obtained based on the difference between the corrected eye diagram and the original eye diagram. The test value can be understood as the compensation amount in the decision feedback equalization mode, or the degree of elimination of inter-symbol interference. The larger the test value, the better the effect of decision feedback equalization.

[0066] Specifically, in some examples, the method for obtaining the test value may be: obtaining a first difference between a maximum reference voltage corresponding to the corrected eye diagram and a maximum reference voltage corresponding to the original eye diagram, the first difference being the test value.

[0067] From the above analysis, it can be seen that since the target data stream is composed of the first value and the second value that appear alternately, the test value obtained by the test can more truly reflect the performance of the decision feedback equalization mode, avoiding the problem of underestimation or overestimation.

[0068] In the case where the decision feedback equalization mode has different gears, a test value corresponding to the gear is obtained based on the original eye diagram and the corrected eye diagram corresponding to any gear.

[0069] refer to Figure 3 , corresponding to the first gear, the test value VQ can be V1H-V0H, where V1H is the maximum reference voltage of the corrected eye diagram corresponding to the first gear, and V0H is the maximum reference voltage of the original eye diagram. For the third gear, the test value can be V3H-V0H, where V3H is the maximum reference voltage of the corrected eye diagram corresponding to the third gear. For the fifth gear, the test value can be V5H-V0H, where V5H is the maximum reference voltage of the corrected eye diagram corresponding to the fifth gear. For the seventh gear, the test value can be V7H-V0H, where V7H is the maximum reference voltage of the corrected eye diagram corresponding to the seventh gear.

[0070] In other examples, the method for obtaining the test value may also be: obtaining a second difference between the minimum reference voltage corresponding to the corrected eye diagram and the minimum reference voltage corresponding to the original eye diagram, and using the absolute value of the second difference as the test value.

[0071] Continue to refer Figure 3 , corresponding to the first gear, the test value VQ can be the absolute value of V1L-V0L, wherein V1L (not marked) is the minimum reference voltage of the corrected eye diagram corresponding to the first gear, and V0L (not marked) is the minimum reference voltage of the original eye diagram. For the third gear, the test value can be the absolute value of V3L-V0L, and V3L (not marked) is the minimum reference voltage of the corrected eye diagram corresponding to the third gear. For the fifth gear, the test value can be the absolute value of V5L-V0L, and V5L (not marked) is the minimum reference voltage of the corrected eye diagram corresponding to the fifth gear. For the seventh gear, the test value can be the absolute value of V7L-V0L, and V7L (not marked) is the minimum reference voltage of the corrected eye diagram corresponding to the seventh gear.

[0072] Figure 4 It is a characterization curve obtained in the test method. Among them, line 1 is a characterization curve obtained based on the random data stream test, and line 2 is a standard curve obtained in the embodiment of the present disclosure.

[0073] The test method may further include: obtaining a characterization curve based on the test values ​​corresponding to different gears, wherein the abscissa of the characterization curve represents the gear, and the ordinate represents the test value.

[0074] from Figure 4 It can be found that when the gear position is higher, the test value obtained by using the random data stream test corresponds to a greater underestimation of the decision feedback equalization performance, that is, when the gear position is higher, the difference between the test value obtained by using the random data stream test and the test value in the embodiment of the present disclosure is greater.

[0075] The test method provided in the above embodiment uses a simple target data stream, which is conducive to shortening the test simulation time, and can also avoid the over-equalization problem caused by inter-symbol interference saturation. The test result is stable and not easily interfered with, making the test value obtained by the test more accurate. The test value can be used to characterize the performance of the decision feedback equalization mode, that is, the test value is used to characterize the degree of elimination of inter-symbol interference or the degree of decision feedback equalization. At the same time, the test value can also be used as one of the indicators for horizontally comparing the DFE capabilities of different storage systems.

[0076] Accordingly, the embodiment of the present disclosure also provides a test circuit, which is applied to a storage system, and the test circuit can be used to perform the test method provided in any of the above embodiments. The test circuit provided in the embodiment of the present disclosure will be described in detail below. It should be noted that the description in the above embodiments is also applicable to the embodiments of the test circuit.

[0077] Figure 5 A block diagram of a test circuit provided in an embodiment of the present disclosure.

[0078] refer to Figure 5 The test circuit includes a data stream input circuit 201, an eye diagram generating circuit 202 and a processing circuit 203.

[0079] The bitstream data stream input circuit 201 is configured to provide a target data stream to a data receiving circuit of the storage system, wherein the target data stream includes a first value and a second value that appear alternately and are different from each other, and the data receiving circuit has a decision feedback equalization mode. The data receiving circuit receives the target data stream and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode.

[0080] The eye pattern generation circuit 202 is configured to generate a corresponding eye pattern based on the output signal.

[0081] The processing circuit 203 is configured to obtain a test value for characterizing the performance of the decision feedback equalization mode based on the eye diagram.

[0082] For detailed descriptions of the target data stream, output signal, eye diagram and test value, reference may be made to the detailed descriptions of the aforementioned embodiments.

[0083] The processing circuit 203 is further configured to obtain a test value based on the difference between the corrected eye diagram and the original eye diagram.

[0084] The eye diagram generating circuit 202 can also be configured to generate an original eye diagram based on the original output signal, where the original output signal is an output signal when the data receiving circuit does not enable the decision feedback equalization mode, receives the target data stream and outputs it; and generate a corrected eye diagram based on the corrected output signal, where the corrected output signal is an output signal when the data receiving circuit enables the decision feedback equalization mode, receives the target data stream and outputs it.

[0085] Continue to refer Figure 5 The test circuit may further include a control circuit 204. The control circuit 204 is configured to control whether the data receiving circuit enables a decision feedback equalization mode.

[0086] The decision feedback equalization mode has different gears. The control circuit 204 can also be configured to control the data receiving circuit to enable the decision feedback equalization mode at different gears. Accordingly, the eye diagram generation circuit 202 generates corrected eye diagrams corresponding to different gears.

[0087] Accordingly, the present disclosure also provides a device, including a storage system and a test circuit provided by any of the above embodiments. It should be noted that the contents of the above embodiments are also applicable to the device embodiments, and in order to avoid repetition, the device will not be described in detail below.

[0088] The storage system may be a DRAM or an SRAM. The DRAM may be an SDRAM, and the SDRAM may be a DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6. In some embodiments, the storage system may be a storage chip, and the storage chip may be a DRAM chip or an SRAM chip.

[0089] Accordingly, the embodiment of the present disclosure also provides a storable medium having a program stored in a readable storage medium, the program being used to enable a processor to execute the above-mentioned test method. It should be noted that the contents of the above-mentioned embodiments are also applicable to the storable medium embodiment.

[0090] Specifically, the readable storage medium includes: a program stored in the readable storage medium, the program is used to enable the processor to perform the following operations: generate a target data stream, the target data stream includes suppression and second values ​​that appear alternately and are different from each other; provide the target data stream to a data receiving circuit of the storage system, the data receiving circuit has a decision feedback equalization mode, the data receiving circuit receives the target data stream, and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode; generate a corresponding eye diagram based on the output signal; based on the eye diagram, obtain a test value for characterizing the performance of the decision feedback equalization mode.

[0091] In some examples, the program is also used to provide instructions for the processor to perform the following operations: control the data receiving circuit to not enable the decision feedback equalization mode to output the original output signal corresponding to the target data stream; control the data receiving circuit to enable the decision feedback equalization mode to output the corrected output signal corresponding to the target data stream; generate an original eye diagram based on the original output signal; generate a corrected eye diagram based on the corrected output signal; and obtain a test value based on the difference between the corrected eye diagram and the original eye diagram.

[0092] In some examples, the program is further used to instruct the processor to perform the following operations: obtain a first difference between a maximum value of a reference voltage corresponding to the corrected eye diagram and a maximum value of a reference voltage corresponding to the original eye diagram, and use the first difference as a test value.

[0093] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a readable storage medium, including several programs for making a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0094] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A testing method applied to a storage system, characterized in that: include: Providing a target data stream to a data receiving circuit of a storage system, the target data stream comprising a first value and a second value that appear alternately and are different from each other, the data receiving circuit having a decision feedback equalization mode; The data receiving circuit receives the target data stream and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode; generating a corresponding eye diagram based on the output signal; Based on the eye diagram, a test value for characterizing the performance of the decision feedback equalization mode is obtained.

2. The testing method according to claim 1, characterized in that: The outputting an output signal corresponding to the target data stream and the decision feedback equalization function comprises: The data receiving circuit does not enable the decision feedback equalization mode and outputs an original output signal corresponding to the target data stream; The data receiving circuit enables the decision feedback equalization mode and outputs a correction output signal corresponding to the target data stream; The generating a corresponding eye diagram based on the output signal comprises: generating an original eye diagram based on the original output signal; generating a corrected eye diagram based on the corrected output signal; The obtaining of a test value for characterizing the performance of the decision feedback equalization mode includes: The test value is obtained based on the difference between the corrected eye diagram and the original eye diagram.

3. The testing method according to claim 2, characterized in that: The obtaining the test value based on the difference between the corrected eye diagram and the original eye diagram comprises: A first difference between a maximum value of a reference voltage corresponding to the corrected eye diagram and a maximum value of a reference voltage corresponding to the original eye diagram is obtained, and the first difference is used as the test value.

4. The testing method according to claim 2, characterized in that: The obtaining the test value based on the corrected eye diagram and the original eye diagram includes: A second difference between a minimum reference voltage value corresponding to the corrected eye diagram and a minimum reference voltage value corresponding to the original eye diagram is obtained, and an absolute value of the second difference is used as the test value.

5. The testing method according to any one of claims 2 to 4, characterized in that: The decision feedback equalization mode has different gears; the testing method also includes: Acquire a plurality of the corrected output signals, wherein the corrected output signals correspond one to one to each gear position; Based on the original eye diagram and the corrected eye diagram corresponding to any gear position, a test value corresponding to the gear position is acquired.

6. The testing method according to claim 5, characterized in that: The test method also includes: Based on the test values ​​corresponding to different gears, a characterization curve is obtained, wherein the abscissa of the characterization curve represents the gear, and the ordinate of the characterization curve represents the test value.

7. The testing method according to claim 1, characterized in that: The target data stream includes a binary data stream 0101010101 or a binary data stream 1010101010.

8. A test circuit, applied to a storage system, characterized in that: include: A data stream input circuit is configured to provide a target data stream to a data receiving circuit of the storage system, wherein the target data stream includes a first value and a second value that appear alternately and are different from each other, and the data receiving circuit has a decision feedback equalization mode. The data receiving circuit receives the target data stream and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode. An eye diagram generating circuit is configured to generate a corresponding eye diagram based on the output signal; The processing circuit is configured to obtain a test value for characterizing the performance of the decision feedback equalization mode based on the eye diagram.

9. The test circuit according to claim 8, characterized in that: Also includes: A control circuit configured to control whether the data receiving circuit enables the decision feedback equalization mode; The eye diagram generating circuit is configured to generate an original eye diagram based on an original output signal, wherein the original output signal is an output signal when the data receiving circuit receives and outputs the target data stream without enabling the decision feedback equalization mode; The eye diagram generation circuit is further configured to generate a corrected eye diagram based on a corrected output signal, wherein the corrected output signal is an output signal outputted by the data receiving circuit when the decision feedback equalization mode is enabled and the target data stream is received.

10. The test circuit according to claim 9, characterized in that: The processing circuit is further configured to obtain the test value based on a difference between the corrected eye diagram and the original eye diagram.

11. The test circuit according to claim 9, characterized in that: The decision feedback equalization mode has different gears; the control circuit is further configured to control the data receiving circuit to enable the decision feedback equalization mode at different gears.

12. A device, characterized in that: include: Storage systems; A test circuit as claimed in any one of claims 8 to 11.

13. A readable storage medium, characterized in that: include: A program is stored in the readable storage medium, and the program is used to cause the processor to perform the following operations: generating a target data stream, the target data stream comprising suppression and second values ​​that appear alternately and are different from each other; Providing the target data stream to a data receiving circuit of a storage system, wherein the data receiving circuit has a decision feedback equalization mode, the data receiving circuit receives the target data stream, and outputs an output signal corresponding to the target data stream and the decision feedback equalization mode; generating a corresponding eye diagram based on the output signal; Based on the eye diagram, a test value for characterizing the performance of the decision feedback equalization mode is obtained.

14. The readable storage medium according to claim 13, characterized in that: The program also provides instructions for the processor to perform the following operations: Controlling the data receiving circuit to not enable the decision feedback equalization mode to output an original output signal corresponding to the target data stream; Controlling the data receiving circuit to enable a decision feedback equalization mode to output a correction output signal corresponding to the target data stream; generating an original eye diagram based on the original output signal; generating a corrected eye diagram based on the corrected output signal; The test value is obtained based on the difference between the corrected eye diagram and the original eye diagram.

15. The readable storage medium according to claim 14, characterized in that: The program also provides instructions for the processor to perform the following operations: A first difference between a maximum value of a reference voltage corresponding to the corrected eye diagram and a maximum value of a reference voltage corresponding to the original eye diagram is obtained, and the first difference is used as the test value.

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