Semiconductor device
By designing side by side transistor cells and cover metal layers in a semiconductor device, gate-drain parasitic capacitance is suppressed, and the characteristic degradation caused by electrode extension in the prior art is solved, and high-frequency characteristics are improved.
Patent Information
- Application Number
- CN202410759567.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-30
- Filing Date
- 2024-06-13
- Publication Date
- 2024-12-31
AI Technical Summary
In a field effect transistor with a finger-like source electrode, gate electrode and drain electrode, configuring a plurality of unit FETs in the extension direction of the electrode causes a shortening of the gate resistance, but also increases the parasitic capacitance between the gate pad and the drain. , resulting in deterioration of characteristics.
A semiconductor device is designed in which the first and second transistor units are arranged side by side along the source electrode and are electrically connected to the source electrode and the drain electrode through gate wiring, and the gate-drain parasitic capacitance is suppressed by a cover metal layer to ensure characteristics No deterioration.
The gate-drain parasitic capacitance is effectively suppressed, and the characteristics are deteriorated, and the high-frequency characteristics of the semiconductor device are improved.
Smart Images
Figure CN119230547A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device. Background Art
[0002] It is known that in a field effect transistor (FET) having a finger-shaped source electrode, a gate electrode, and a drain electrode, a plurality of unit FETs having a source electrode, a gate electrode, and a drain electrode are arranged in the extending direction of the electrodes (for example, Patent Document 1).
[0003] Prior art literature
[0004] Patent Literature
[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351
[0006] In Patent Document 1, by configuring a plurality of unit FETs in the extending direction of the electrode, the width of the gate electrode in the unit FET can be shortened. Thus, the gate resistance can be suppressed. However, the parasitic capacitance between the gate wiring that electrically connects the gate pad to the gate electrode away from the gate pad and the drain electrode increases, and the characteristics deteriorate. Summary of the invention
[0007] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics.
[0008] One embodiment of the present disclosure is a semiconductor device, comprising: a substrate; a first transistor unit, on which a first drain electrode, a first gate electrode, and a first source electrode are sequentially provided; a second transistor unit, on which a second source electrode, a second gate electrode, and a second drain electrode, which are arranged side by side along the first source electrode and electrically connected to the first source electrode, a second gate electrode, and a second drain electrode, which are electrically connected to the first drain electrode, are sequentially provided on the substrate, the second transistor unit being located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring, which is provided on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first covering metal layer, which is electrically provided on the first source electrode, at least an upper portion of which protrudes toward the gate wiring side more than the first source electrode; and a second covering metal layer, which is electrically provided on the second source electrode, at least an upper portion of which protrudes toward the gate wiring side more than the second source electrode.
[0009] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit, on which a first drain electrode, a first gate electrode, and a first source electrode are sequentially provided; a second transistor unit, on which a second source electrode, a second gate electrode, and a second drain electrode electrically connected to the first drain electrode, are sequentially provided along the first source electrode, and are arranged side by side, and are arranged in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; and a gate wiring, between the first source electrode and the second source electrode, and connected to the first The source electrode and the second source electrode are adjacently arranged on the substrate, and the gate wiring is electrically connected to the first gate electrode and the second gate electrode; a first source wiring is arranged on the first source electrode in an electrically contacting manner; a second source wiring is arranged on the second source electrode in an electrically contacting manner; a first drain wiring is arranged on the first drain electrode in an electrically contacting manner, and the height of the upper surface of the first drain wiring from the substrate is less than the height of the upper surface of the first source wiring from the substrate; and a second drain wiring is arranged on the second drain electrode in an electrically contacting manner, and the height of the upper surface of the second drain wiring from the substrate is less than the height of the upper surface of the second source wiring from the substrate.
[0010] Effects of the Invention
[0011] According to the present disclosure, degradation of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 1 is a top view of the semiconductor device of Example 1.
[0013] Figure 2 yes Figure 1 An enlarged view of range D.
[0014] Figure 3 yes Figure 1 and Figure 2 A-A section view.
[0015] Figure 4 yes Figure 1 and Figure 2 B-B section view.
[0016] Figure 5 yes Figure 1 C-C section view.
[0017] Figure 6 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0018] Figure 7It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0019] Figure 8 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0020] Fig. 9 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0021] Fig. 10A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0022] Fig. 10B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0023] Fig. 10C It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0024] Fig.11A It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0025] Fig. 11B It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0026] Fig. 11C It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0027] Fig.12 is a cross-sectional view of a semiconductor device according to Comparative Example 1.
[0028] Fig.13 This is an enlarged top view of a semiconductor device according to Modification 1 of Embodiment 1.
[0029] Fig.14 yes Fig.13 A-A section view.
[0030] Fig.15 yes Fig.13 B-B section view.
[0031] Fig.16 This is an enlarged top view of a semiconductor device according to a second variation of the first embodiment.
[0032] Fig.17 yes Fig.16 A-A section view.
[0033] Fig.18 This is an enlarged top view of a semiconductor device according to a third variation of the first embodiment.
[0034] Fig.19 yes Fig.18A-A section view.
[0035] Fig. 20 It is a top view of the semiconductor device of Example 2.
[0036] Fig.21 is a graph showing the K factor of semiconductor devices A and B versus frequency.
[0037] Fig. 22 Graph showing |S12| of semiconductor devices A and B with respect to frequency.
[0038] Description of Reference Numerals
[0039] 10, 10a: substrate;
[0040] 10b: semiconductor layer;
[0041] 11a, 11b, 11c: active area;
[0042] 12, 12a, 12b, 12c: source electrodes;
[0043] 13a, 13b: passive area;
[0044] 14, 14a, 14b, 14c, 14d: gate electrodes;
[0045] 16a, 16b, 16c, 16d: drain electrodes;
[0046] 18, 23: Gate wiring;
[0047] 18a, 25a: gate metal layer;
[0048] 20: vias;
[0049] 22, 22a, 22b, 22c: source wiring;
[0050] 24: drain bus;
[0051] 25: Gate busbar;
[0052] 26a, 26c: drain wiring;
[0053] 28, 28a, 30a, 30b, 30c, 30d: metal layer;
[0054] 30: Covering metal layer;
[0055] 32, 32a: insulation layer;
[0056] 34a, 34b: location;
[0057] 35, 35a, 35b, 35c, 35d: unit FET (transistor unit);
[0058] 36a, 36b, 36c, 36d: FET group;
[0059] 38: gap;
[0060] 50, 53b: solid arrows;
[0061] 51, 52, 53a: dotted arrows;
[0062] 100 , 102 , 104 , 106 , 108 , 110 : semiconductor devices. DETAILED DESCRIPTION
[0063] [Description of Embodiments of the Present Disclosure]
[0064] First, the contents of the embodiments of the present disclosure will be listed and described.
[0065] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit, on which a first drain electrode, a first gate electrode, and a first source electrode are sequentially provided; a second transistor unit, on which a second source electrode, a second gate electrode, and a second drain electrode, arranged side by side along the first source electrode and electrically connected to the first source electrode, are sequentially provided on the substrate, wherein the second transistor unit is located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring, between the first source electrode and the second source electrode, provided on the substrate adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first covering metal layer, electrically provided on the first source electrode, at least an upper portion of the first covering metal layer protruding toward the gate wiring side relative to the first source electrode; and a second covering metal layer, electrically provided on the second source electrode, at least an upper portion of the second covering metal layer protruding toward the gate wiring side relative to the second source electrode. Thus, gate-drain parasitic capacitance can be suppressed, and degradation of characteristics can be suppressed.
[0066] (2) In the above (1), at least a portion of the first cover metal layer and at least a portion of the second cover metal layer may overlap the gate wiring in a non-contact manner when viewed from above. This can further suppress gate-drain parasitic capacitance and further suppress degradation of characteristics.
[0067] (3) In the above (1) or (2), the first cover metal layer and the second cover metal layer may be in contact with each other above the gate wiring. This can further suppress gate-drain parasitic capacitance and further suppress degradation of characteristics.
[0068] (4) In the above (3), the portion where the first covering metal layer and the second covering metal layer are in contact above the gate wiring and the portion where the first covering metal layer and the second covering metal layer are not provided above the gate wiring may be alternately provided along the gate wiring. In this way, the gate-drain parasitic capacitance and the gate-source parasitic capacitance can be made to have desired values, and the degradation of characteristics can be further suppressed.
[0069] (5) In the above (1) or (2), the first cover metal layer and the second cover metal layer may not be in contact with each other above the gate wiring. This can suppress gate-source parasitic capacitance and further suppress degradation of characteristics.
[0070] (6) In the above (5), the end of the first covering metal layer may overlap with the gate wiring when viewed from above, and the end of the second covering metal layer may overlap with the gate wiring when viewed from above. In this way, gate-drain parasitic capacitance and gate-source parasitic capacitance can be suppressed, and degradation of characteristics can be further suppressed.
[0071] (7) In any one of the above (1) to (6), the semiconductor device may include a third transistor unit, wherein a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode are sequentially provided on the substrate, and the third transistor unit is located in the direction in which the first gate electrode extends relative to the first transistor unit. In this way, the gate-drain parasitic capacitance can be further suppressed, and the degradation of characteristics can be further suppressed.
[0072] (8) In the above (7), the semiconductor device may include a connection wiring that electrically connects the third gate electrode to the gate wiring between the first transistor unit and the third transistor unit, and a portion of the first cover metal layer overlaps with at least a portion of the connection wiring when viewed from above. This can further suppress gate-drain parasitic capacitance and further suppress degradation of characteristics.
[0073] (9) In any one of the above (1) to (8), the semiconductor device may include: a first drain wiring provided on the first drain electrode in an electrically contacting manner, wherein the height from the substrate to the upper surface of the first drain wiring is smaller than the height from the substrate to the upper surface of the first cover metal layer; and a second drain wiring provided on the second drain electrode in an electrically contacting manner, wherein the height from the substrate to the upper surface of the second drain wiring is smaller than the height from the substrate to the upper surface of the second cover metal layer. Thus, gate-drain parasitic capacitance and gate-source parasitic capacitance can be suppressed, and degradation of characteristics can be suppressed.
[0074] (10) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a first transistor unit, on which a first drain electrode, a first gate electrode, and a first source electrode are sequentially provided; a second transistor unit, on which a second source electrode, a second gate electrode, and a second drain electrode electrically connected to the first drain electrode, are sequentially provided along the first source electrode, and are arranged side by side, respectively, along the first source electrode; the second transistor unit is located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; and a gate wiring is provided between the first source electrode and the second source electrode and connected to the The first source electrode and the second source electrode are adjacently arranged on the substrate, the gate wiring is electrically connected to the first gate electrode and the second gate electrode; the first source wiring is arranged on the first source electrode in an electrically contacting manner; the second source wiring is arranged on the second source electrode in an electrically contacting manner; the first drain wiring is arranged on the first drain electrode in an electrically contacting manner, the height of the upper surface of the first drain wiring from the substrate is less than the height of the upper surface of the first source wiring from the substrate; and the second drain wiring is arranged on the second drain electrode in an electrically contacting manner, the height of the upper surface of the second drain wiring from the substrate is less than the height of the upper surface of the second source wiring from the substrate. Thus, gate-drain parasitic capacitance and gate-source parasitic capacitance can be suppressed, and degradation of characteristics can be suppressed.
[0075] (11) In the above (10), the semiconductor device may include a third transistor unit, wherein a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode are sequentially provided on the substrate, and the third transistor unit is located in the direction in which the first gate electrode extends relative to the first transistor unit. In this way, the gate-drain parasitic capacitance can be further suppressed, and the degradation of characteristics can be further suppressed.
[0076] [Details of the embodiments of the present disclosure]
[0077] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.
[0078] [Example 1]
[0079] A semiconductor device of an amplifier used for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station for mobile communications will be described as an example. Figure 1 1 is a top view of the semiconductor device of Example 1.
[0080] Figure 2 yes Figure 1 The enlarged view of the range D, Figures 3 to 5 They are Figure 1 or Figure 2 The thickness direction of the substrate 10 is set to the Z direction, the extension direction of each finger-shaped electrode is set to the Y direction (first direction), and the arrangement direction of each electrode is set to the X direction (second direction intersecting the first direction). It should be noted that Figure 1 and Figure 2 In the top view, if the cover metal layer 30 overlaps with the source wiring 22a to the source wiring 22c, it is difficult to read the figure. Therefore, the cover metal layer 30 is transparent, and only the thick dotted line indicating the outer periphery is shown inside the source wiring 22a to the source wiring 22c.
[0081] In each figure, the source electrode 12, the gate electrode 14, the source wiring 22, and the unit FET 35 represent general elements, and the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the source wiring 22a to 22c, and the unit FETs 35a to 35d represent specific elements included in the general elements. Hereinafter, the unit FETs 35a to 35d will be described mainly using the source electrodes 12a to 12c, the gate electrodes 14a to 14d, the drain electrode 16a, the drain electrode 16b, the source wiring 22a to 22c, the drain wiring 26a, and the drain wiring 26c.
[0082] like Figures 1 to 5 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the regions deactivated by ion implantation or the like of the semiconductor layer 10b are the inactive regions 13a and 13b, and the regions not deactivated are the active regions 11a to 11c.
[0083] The active region 11a and the active region 11b are arranged in the X direction. The active region 11c is provided in a region closer to the + direction in the Y direction than the active region 11a and the active region 11b. The region between the active region 11a and the active region 11b is the inactive region 13a. The region between the active region 11a and the active region 11b and the active region 11c is the inactive region 13b. A FET group 36a including a plurality of unit FETs 35a and 35c arranged in the X direction is provided on the active region 11a and the active region 11b. A FET group 36b including a plurality of unit FETs 35b and 35d arranged in the X direction is provided on the active region 11c. The gate bus 25 and the FET group 36b are separated by the FET group 36a. The drain bus 24 and the FET group 36a are separated by the FET group 36b.
[0084] The unit FET 35a (first transistor unit) has a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode) extending in the Y direction and respectively disposed on the substrate 10. The drain electrode 16a, the gate electrode 14a, and the source electrode 12a are disposed in sequence. The unit FET 35c (second transistor unit) is located in the direction in which the drain electrode 16a, the gate electrode 14a, and the source electrode 12a are arranged relative to the unit FET 35a. The unit FET 35c has a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode) extending in the Y direction and respectively disposed on the substrate 10. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are disposed in sequence. The source electrode 12c is disposed side by side along the source electrode 12a, and is electrically connected to the source electrode 12a via the source electrode 12b. The gate electrode 14c is electrically connected to the gate electrode 14a via the gate bus 25. The drain electrode 16 c is electrically connected to the drain electrode 16 a via a drain bus bar 24 .
[0085] A gate wiring 23 extending in the Y direction is provided on the region of the substrate 10 located in the +X direction of the unit FET 35a. The gate wiring 23 is provided adjacent to the source electrode 12a and the source electrode 12c on the inactive region 13a between the unit FET 35a and the unit FET 35c. That is, in the unit FET 35a, the source electrode 12a is closer to the gate wiring 23 than the drain electrode 16a. In the unit FET 35c, the source electrode 12c is closer to the gate wiring 23 than the drain electrode 16c. A gate metal layer 18a is provided between the gate wiring 23 and the substrate 10. The gate metal layer 18a may not be provided.
[0086] The unit FET 35b (third transistor unit) and the unit FET 35d are respectively provided in the region on the substrate 10 located in the direction in which the gate electrode 14a extends relative to the unit FET 35a and the unit FET 35c. The unit FET 35b has a source electrode 12b (third source electrode), a gate electrode 14b (third gate electrode), and a drain electrode 16b (third drain electrode) which extend in the Y direction and are respectively provided on the substrate 10. The drain electrode 16b, the gate electrode 14b, and the source electrode 12b are provided in sequence. The drain electrode 16b is electrically connected to the drain electrode 16a. The gate electrode 14b is electrically connected to the gate wiring 23. The source electrode 12b is electrically connected to the source electrode 12a. The unit FET 35d has a source electrode 12b, a gate electrode 14d, and a drain electrode 16d which extend in the Y direction and are respectively provided on the substrate 10. The unit FET 35b and the unit FET 35d share the source electrode 12b. When viewed from the Y direction, the source electrode 12 a , the source electrode 12 c , and the gate wiring 23 are provided so as to overlap with the source electrode 12 b and fall within the range where the source electrode 12 b is provided.
[0087] The gate wiring 18 extending in the X direction is provided on the inactive region 13 b. The gate wiring 18 electrically connects the gate wiring 23 and the gate electrodes 14 b and 14 d to short-circuit them. The gate wiring 23 and the gate electrodes 14 a and 14 c are connected to a gate bus 25 .
[0088] The source wiring 22a (first source wiring), the source wiring 22b, and the source wiring 22c (second source wiring) are provided on the source electrode 12a, the source electrode 12b, and the source electrode 12c, respectively, in a contacting manner. The source wiring 22a and the source wiring 22c cross the gate wiring 18 in a non-contact manner via the insulating layer 32a, thereby connecting to the source electrode 12b. The drain wiring 26a (first drain wiring) is provided on the drain electrode 16a and the drain electrode 16b in a contacting manner, and the drain electrode 16a and the drain electrode 16b are electrically connected to the drain bus 24. The drain wiring 26c (second drain wiring) is provided on the drain electrode 16c and the drain electrode 16d in a contacting manner, and the drain electrode 16c and the drain electrode 16d are electrically connected to the drain bus 24.
[0089] The cover metal layer 30 is provided on the source wiring 22a to the source wiring 22c in a contacting manner. An insulating layer 32 is provided on the substrate 10 in a manner covering the source electrodes 12a to the source electrodes 12c, the gate electrodes 14a to the gate electrodes 14d, the drain electrodes 16a to the drain electrodes 16d, the source wiring 22a to the source wiring 22c, the drain wiring 26a, the drain wiring 26c, and the cover metal layer 30. When viewed from the Z direction, the cover metal layer 30 is provided to overlap a portion of the gate wiring 18 and a portion of the gate wiring 23. Figure 3Thus, in the FET group 36a, the cover metal layer 30 includes the metal layer 30a and the metal layer 30c provided on the source wiring 22a and the source wiring 22c respectively, and the metal layer 30b connecting the metal layer 30a and the metal layer 30c. The metal layers 30a to 30c are provided continuously in one piece.
[0090] The via hole 20 penetrates the substrate 10 and is connected to the source electrode 12b. A metal layer 28 is provided on the lower surface of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20. Thus, the metal layer 28 is electrically connected to the source electrode 12b via the via hole 20 to form a short circuit.
[0091] The source potential (for example, a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrode 12b via the metal layer 28a in the via 20. Furthermore, the source potential is supplied to the source electrode 12a, the source electrode 12c, and the cover metal layer 30 via the source wiring 22a to the source wiring 22c. The gate potential (for example, a high-frequency signal and a gate bias voltage) is supplied from the gate bus 25 to the gate electrode 14a and the gate electrode 14c. In addition, the gate potential is supplied from the gate bus 25 to the gate electrode 14b and the gate electrode 14d via the gate wiring 23 and the gate wiring 18. The drain bias voltage is supplied from the drain bus 24 to the drain electrode 16a to the drain electrode 16d via the drain wiring 26a and the drain wiring 26c. The high-frequency signal amplified in each unit FET 35a to the unit FET 35d is output from the drain wiring 26a and the drain wiring 26c to the drain bus 24.
[0092] In the unit FET 35a and the unit FET 35c, a high-frequency signal is input from the - end in the Y direction of the gate electrode 14a and the gate electrode 14c. In the unit FET 35b and the unit FET 35d, a high-frequency signal is input from the - end in the Y direction of the gate electrode 14b and the gate electrode 14d. If a high-frequency signal is input to the gate electrode 14a and the gate electrode 14c from both ends of the + end and the - end in the Y direction of the gate electrode 14a and the gate electrode 14c, the high-frequency characteristics of the unit FET 35a and the unit FET 35c will deteriorate due to a phase difference, etc. In the first embodiment, the + end in the Y direction of the gate electrode 14a and the gate electrode 14c is not connected to the - end in the Y direction of the gate electrode 14b and the gate electrode 14d, so that the degradation of the high-frequency characteristics of the unit FET 35a and the unit FET 35c can be suppressed.
[0093] In the case where the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. In the case where the unit FETs 35a to 35d are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. In the case where the semiconductor device 100 is, for example, a gallium arsenide (GaAs)-based semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as a LDMOS (Laterally Diffused Metal Oxide Semiconductor).
[0094] The source electrodes 12a to 12c and the drain electrodes 16a to 16d are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14d and the gate metal layer 18a are metal films, for example, nickel films and gold films from the substrate 10 side. The source wirings 22a to 22c, the drain wirings 26a, the drain wirings 26c, the gate wirings 23, and the cover metal layer 30 are, for example, gold layers, copper layers, or aluminum layers. The insulating layer 32a is, for example, an inorganic insulating layer such as a silicon nitride layer. The insulating layer 32 is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.
[0095] The width of the source electrode 12a and the source electrode 12c in the X direction is, for example, 5 μm to 20 μm. The width of the source electrode 12b in the X direction is, for example, 50 μm to 150 μm. The gate length of the gate electrodes 14a to 14d in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a and 16c in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 23 in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 18 in the Y direction is, for example, 3 μm to 20 μm. The gate width of the unit FETs 35a to 35d in the Y direction is, for example, 100 μm to 400 μm. The width of the via 20 in the X direction is, for example, 10 μm to 60 μm.
[0096] The widths of the source wirings 22a to 22c, the drain wirings 26a and 26c in the X direction are the same as or slightly smaller than the widths of the source electrodes 12a to 12c, the drain electrodes 16a and 16c in the X direction, respectively. The thicknesses of the source wirings 22a to 22c, the drain wirings 26a and 26c are, for example, 1 μm to 20 μm. The thickness of the gate wiring 23 is, for example, 0.5 μm to 5 μm. The thickness of the gate wiring 23 may be the same as the thickness of the source wirings 22a to 22c, the drain wirings 26a and 26c, or may be thinner than the thicknesses of the source wirings 22a to 22c, the drain wirings 26a and 26c. The thickness of the cover metal layer 30 is, for example, 1 μm to 5 μm.
[0097] [Manufacturing method of Example 1]
[0098] Figures 6 to 9 It is a top view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10A to FIG. 11C is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1, which is equivalent to Figures 6 to 9 A-A section.
[0099] like Figure 6 and Fig. 10A As shown, by performing ion implantation into the semiconductor layer 10b, an inactive region 13a and an inactive region 13b are formed in the semiconductor layer 10b. The region where the inactive region 13a and the inactive region 13b are not formed is the active region 11a to the active region 11c. The inactive region 13a is formed between the active region 11a and the active region 11b, and the inactive region 13b is formed between the active region 11a and the active region 11b and the active region 11c.
[0100] like Figure 6 and Fig. 10B As shown, a source electrode 12a and a drain electrode 16a are formed on the active region 11a. A source electrode 12c and a drain electrode 16c are formed on the active region 11b. A source electrode 12b, a drain electrode 16b, and a drain electrode 16d are formed on the active region 11c. In the formation of the source electrodes 12a to 12c and the drain electrodes 16a to 16d, for example, a vacuum evaporation method and a lift-off method are used. Thereafter, a heat treatment is performed. Thus, the source electrodes 12a to 12c and the drain electrodes 16a to 16d are in ohmic contact with the active regions 11a, 11b, and 11c.
[0101] like Figure 7 and Fig. 10CAs shown, gate electrodes 14a to 14d, gate wiring 18, gate metal layer 18a and gate metal layer 25a are formed on substrate 10. For example, vacuum evaporation method and lift-off method are used to form gate electrodes 14a to 14d, gate wiring 18, gate metal layer 18a and gate metal layer 25a.
[0102] like Fig.11A As shown, an insulating layer 32a is formed on the substrate 10 to cover the source electrodes 12a to 12c, the drain electrodes 16a and 16c, the gate electrodes 14a to 14d, the gate wiring 18, the gate metal layer 18a and the gate metal layer 25a. The insulating layer 32a is formed by, for example, using a CVD (Chemical Vapor Deposition) method.
[0103] like Figure 8 and Fig.11A As shown, an opening is formed in a desired region of the insulating layer 32a by etching. Source wirings 22a to 22c, drain wirings 26a and 26c are formed on the source electrodes 12a to 12c, the drain electrodes 16a and 16c, respectively. A gate wiring 23 is formed on the gate metal layer 18a. A gate bus 25 and a drain bus 24 are formed. For example, a plating method is used to form the source wirings 22a to 22c, the drain wirings 26a, the drain wirings 26c, the gate wirings 23, the gate bus 25 and the drain bus 24.
[0104] like Fig. 9 and Fig. 11B As shown in FIG. 1 , a cover metal layer 30 is formed on the source wiring 22a to the source wiring 22c. For example, a plating method is used to form the cover metal layer 30. The space between the source wirings 22a and 22c is covered by the cover metal layer 30. Fig. 11C As shown, an insulating layer 32 is formed on the substrate 10 in a manner covering the source wiring 22a to the source wiring 22c, the drain wiring 26a, the drain wiring 26c, the gate wiring 23 and the covering metal layer 30. The insulating layer 32 is formed in a space surrounded by the source wiring 22a, the source wiring 22c and the covering metal layer 30. The insulating layer 32 includes, for example, an inorganic insulator layer and an organic insulator layer formed on the inorganic insulator layer. The inorganic insulator layer is formed, for example, using a CVD method. The organic insulator layer is formed by applying a solvent containing a resin and performing a heat treatment. An opening (not shown) is formed in the insulating layer 32 to expose the gate bus 25 and the drain bus 24.
[0105] Then, the lower surface of the substrate 10 is ground or polished to make the substrate 10 thinner, and a via hole 20 is formed to penetrate the substrate 10. The metal layer 28 and the metal layer 28a are formed on the lower surface of the substrate 10 and the inner surface of the via hole 20. Thus, the semiconductor device of Example 1 is manufactured.
[0106] [Comparative Example 1]
[0107] Fig.12 is a cross-sectional view of a semiconductor device of Comparative Example 1. Fig.12 As shown, in the semiconductor device 110 of the comparative example 1, the cover metal layer 30 is not provided. The other structures are the same as those of the first embodiment.
[0108] The gate wiring 23 and the gate wiring 18 electrically connect the gate electrode 14b and the gate electrode 14d to the gate bus 25. As a result, the gate resistance of the unit FET 35b and the unit FET 35d can be reduced. However, as shown by the solid arrow 50, the gate wiring 23 and the drain wiring 26a and the drain wiring 26c are capacitively coupled due to the electric lines passing through the source wiring 22a and the source wiring 22c. As a result, the gate-drain parasitic capacitance increases. If the gate-drain parasitic capacitance increases, the gain decreases. In addition, the K factor, which is a stability factor, decreases. In this way, the high-frequency characteristics of the semiconductor device 110 deteriorate.
[0109] [Description of Example 1]
[0110] like Figure 3 As such, according to Embodiment 1, a covering metal layer 30 is provided, and the covering metal layer 30 is provided on the source wiring 22a and the source wiring 22c, and covers the entire area between the source wiring 22a and the source wiring 22c. Thus, as shown by the dotted arrow 52, the covering metal layer 30 shields the electric lines between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c. Thus, the capacitive coupling between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c is suppressed. Thus, the gate-drain parasitic capacitance can be suppressed, and the degradation of the high-frequency characteristics of the semiconductor device 100 can be suppressed. It should be noted that in Embodiment 1, the gate-source parasitic capacitance and the drain-source parasitic capacitance increase. However, the gate-source capacitance and the drain-source capacitance are larger than the gate-drain capacitance. Therefore, the influence of the gate-source parasitic capacitance and the drain-source parasitic capacitance is small.
[0111] like Figure 4In this way, in the inactive region 13b, the cover metal layer 30 is provided on the gate wiring 18 via the insulating layer 32a. As a result, as shown by the dotted arrow 51, the cover metal layer 30 shields a part of the gate wiring 18 and the electric lines of force between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c, thereby suppressing capacitive coupling. As a result, the gate-drain parasitic capacitance can be suppressed, and the degradation of the high-frequency characteristics of the semiconductor device 100 can be suppressed.
[0112] [Variation 1 of Example 1]
[0113] Fig.13 This is an enlarged top view of a semiconductor device according to Modification 1 of Embodiment 1. Fig.14 and Fig.15 They are Fig.13 The A-A section view and the B-B section view. Figures 13 to 15 As shown, in the semiconductor device 102 of the first modification of the first embodiment, the portions 34a provided with the metal layer 30b and the portions 34b not provided with the metal layer 30b are alternately provided in the Y direction. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.
[0114] like Fig.14 In this way, at the portion 34a where the metal layer 30b is provided, the metal layer 30b shields the electric lines of force between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c as indicated by the dotted arrow 52, thereby suppressing capacitive coupling. As a result, the gate-drain parasitic capacitance is suppressed. However, the gate-source parasitic capacitance between the gate wiring 23 and the metal layer 30b increases.
[0115] like Fig.15 As shown in FIG. 5 , at the portion 34b where the metal layer 30b is not provided, as shown by the dotted arrow 53a, the metal layer 30a and the metal layer 30c shield a portion of the electric lines between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c. As shown by the solid arrow 53b, a portion of the electric lines between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c is not shielded. As a result, the gate-drain parasitic capacitance is increased compared to the first embodiment. However, at the portion 34b, the metal layer 30b does not cover the top of the gate wiring 23, so the gate-source parasitic capacitance is reduced. As a result, the gate-source parasitic capacitance can be suppressed compared to the first embodiment.
[0116] The number of parts 34a and parts 34b, and the widths W1 and W2 of parts 34a and parts 34b in the Y direction can be appropriately set according to whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is emphasized. When the suppression of the gate-drain parasitic capacitance is emphasized, the total width W1 of the part 34a in the Y direction can be set to be greater than 0.5 times the gate width Wg in the Y direction of the unit FET 35a and the unit FET 35c (the width of the active area 11a and the active area 11b in the Y direction), and can be set to be greater than 0.7 times. When the suppression of the gate-source parasitic capacitance is emphasized, the total width W1 can be set to be less than 0.5 times the gate width Wg, and can be set to be less than 0.3 times. The width W1 and the width W2 are, for example, greater than 1 μm and less than 100 μm, respectively.
[0117] In Example 1, Fig. 11C When the insulating layer 32 is provided in the embodiment 1, the solvent containing the resin may not bypass the metal layer 30b, and a void may be formed. In the modification 1 of the embodiment 1, the metal layer 30b is not provided at the portion 34b. Therefore, the solvent containing the resin bypasses the metal layer 30b at the portion 34a. Thus, the formation of a void in the insulating layer 32 can be suppressed.
[0118] [Variation 2 of Example 1]
[0119] Fig.16 This is an enlarged top view of a semiconductor device according to a second variation of the first embodiment. Fig.17 yes Fig.16 A-A section view. Fig.16 and Fig.17 As shown, in the semiconductor device 104 of the second variation of the first embodiment, the cover metal layer 30 has metal layers 30a to 30d. The metal layer 30a and the metal layer 30c are provided on the source wiring 22a and the source wiring 22c, respectively, in a contacting manner. The metal layer 30b protrudes from the metal layer 30a to the source wiring 22c side. The metal layer 30d protrudes from the metal layer 30c to the source wiring 22a side. A gap 38 is provided between the metal layer 30b and the metal layer 30d. When viewed from the Z direction, the + side of the metal layer 30b in the X direction overlaps with the gate wiring 23, and the - side of the metal layer 30d in the X direction overlaps with the gate wiring 23. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.
[0120] like Fig.17As shown by the dotted arrow 54, most of the electric force lines between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c are shielded by the cover metal layer 30. There are not many electric force lines passing through the gap 38. Thus, the gate-drain parasitic capacitance can be suppressed. On the other hand, a part of the area closest to the gate wiring 23 in the cover metal layer 30 is the gap 38. Thus, the gate-source parasitic capacitance can be suppressed.
[0121] The width W3 of the metal layer 30b and the metal layer 30d in the X direction can be appropriately set according to whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is emphasized. When the suppression of the gate-drain parasitic capacitance is emphasized, the width W3 of each metal layer 30b and the metal layer 30d in the X direction can be set to be greater than 0.25 times the interval W4 between the source wiring 22a and the source wiring 22c in the X direction, and can be set to be greater than 0.4 times. When the suppression of the gate-source parasitic capacitance is emphasized, each width W3 can be set to be less than 0.4 times the interval W4, and can be set to be less than 0.25 times.
[0122] The width W5 of the gap 38 in the X direction can be appropriately set depending on whether the gate-drain parasitic capacitance or the gate-source parasitic capacitance is emphasized. When the suppression of the gate-drain parasitic capacitance is emphasized, the width W5 can be set to be less than 0.8 times the width W6 of the gate wiring 23 in the X direction, and can be set to be less than 0.5 times. When the suppression of the gate-source parasitic capacitance is emphasized, the width W5 can be set to be more than 0.5 times the width W6, and can be set to be more than 0.8 times. It is also possible that when viewed from the Z direction, the + side of the metal layer 30b in the X direction does not overlap with the gate wiring 23, and the - side of the metal layer 30d in the X direction does not overlap with the gate wiring 23.
[0123] In addition, Fig. 11C When the insulating layer 32 is provided in the insulating layer 32, the solvent containing the resin passes through the gap 38 and goes around under the metal layer 30b and the metal layer 30d. Thus, the formation of voids in the insulating layer 32 can be suppressed.
[0124] In the first embodiment and its first and second modifications, the cover metal layer 30 is flat, but the center portion of the cover metal layer 30 in the X direction may be in an arch shape that bulges upward.
[0125] [Variation 3 of Example 1]
[0126] Fig.18 This is an enlarged top view of a semiconductor device according to a third variation of the first embodiment. Fig.19 yes Fig.18 A-A section view. Fig.18 and Fig.19As shown, in the semiconductor device 106 of the third variation of the first embodiment, the cover metal layer 30 includes a metal layer 30a and a metal layer 30c. The metal layer 30a and the metal layer 30c are provided on the source wiring 22a and the source wiring 22c, respectively, in a contact manner. The cover metal layer 30 is not provided between the source wiring 22a and the source wiring 22c. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.
[0127] like Fig.19 As shown in the embodiment 1, the metal layer 30a and the metal layer 30c shield a part of the electric force lines between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c, as shown by the dotted arrow 53a. As shown by the solid arrow 53b, a part of the electric force lines between the gate wiring 23 and the drain wiring 26a and the drain wiring 26c is not shielded. As a result, the gate-drain parasitic capacitance is increased compared with the embodiment 1, and the gate-source parasitic capacitance is reduced.
[0128] From the perspective of suppressing gate-drain parasitic capacitance, the height H1 of the upper surface of the metal layer 30a and the metal layer 30c from the upper surface of the substrate 10 can be set to be 1.5 times or more, 2.5 times or more, or 3 times or more of the height H2 of the upper surface of the drain wiring 26a and the drain wiring 26c from the upper surface of the substrate 10. From the perspective of the manufacturing process, the height H1 can be set to be 10 times or less of the height H2. In Example 1 and its Modification 1 and Modification 2, the height H1 can also be greater than the height H2, and can be set to be 1.5 times or more, 2.5 times or more, or 3 times or more of the height H2.
[0129] According to Embodiment 1 and its Modification 1 and Modification 2, as Figure 3 , Fig.14 as well as Fig.17 In this way, the metal layers 30a and 30b (first cover metal layer) in the cover metal layer 30 are provided on the source wiring 22a in a contacting manner, and are electrically connected to the source electrode 12a via the source wiring 22a. The metal layer 30b protrudes toward the gate wiring 23 side from the source electrode 12a. Thus, the protruding metal layer 30b suppresses the capacitive coupling between the gate wiring 23 and the drain wiring 26a. Thus, the gate-drain parasitic capacitance can be suppressed, and the degradation of the characteristics of the semiconductor device can be suppressed.
[0130] The metal layers 30c and 30d (second covering metal layers) of the covering metal layer 30 are provided on the source wiring 22c in a contacting manner, and are electrically connected to the source electrode 12c via the source wiring 22c. The metal layer 30d protrudes toward the gate wiring 23 side more than the source electrode 12c. Thus, the protruding metal layer 30d suppresses the capacitive coupling between the gate wiring 23 and the drain wiring 26c. Thus, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed. At least the upper portion of the covering metal layer 30 protrudes toward the gate wiring 23 side more than the source electrodes 12a and 12c.
[0131] Furthermore, at least a portion of the cover metal layer 30 overlaps the gate wiring 23 in a non-contact manner when viewed from the Z direction (ie, in a plan view). This further reduces gate-drain parasitic capacitance and further reduces degradation of characteristics of the semiconductor device.
[0132] According to Embodiment 1 and its variation 1, Figure 3 and Fig.14 Thus, the metal layer 30b and the metal layer 30c are in contact with each other above the gate wiring 23. Thus, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0133] As in Example 1 Figure 2 and Figure 3 In this way, the metal layer 30b may be provided in the entire region between the metal layer 30a and the metal layer 30c when viewed from the Z direction. This can suppress the gate-drain parasitic capacitance and further suppress the degradation of the characteristics of the semiconductor device.
[0134] As in the variant 1 of the embodiment 1 Fig.13 In this way, the portion 34a where the metal layer 30b and the metal layer 30c are in contact above the gate wiring 23 and the portion 34b where the metal layer 30b and the metal layer 30c are not provided above the gate wiring 23 are alternately provided in the Y direction along the gate wiring 23. Thus, the gate-drain parasitic capacitance and the gate-source parasitic capacitance can be made into desired values, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0135] As in the variation 2 of the embodiment 1 Fig.16 and Fig.17 Thus, the metal layer 30b and the metal layer 30d are not in contact with each other above the gate wiring 23. Thus, the gate-source parasitic capacitance can be suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0136] Furthermore, the ends of the metal layers 30b and 30d in the X direction overlap the gate wiring 23 when viewed from the Z direction. This can suppress gate-drain parasitic capacitance and gate-source parasitic capacitance, and further suppress degradation of the characteristics of the semiconductor device.
[0137] As in Example 1 Figure 4 In this way, between the unit FET 35a and the unit FET 35b, the gate wiring 18 (connection wiring) extends in the X direction to electrically connect the gate electrode 14b and the gate wiring 23. A portion of the cover metal layer 30 overlaps with at least a portion of the gate wiring 18 when viewed from the Z direction. Thus, the capacitive coupling between the gate wiring 23 and the drain wiring 26a is suppressed. Thus, the gate-drain parasitic capacitance can be further suppressed, and the degradation of the characteristics of the semiconductor device can be further suppressed.
[0138] As in the variant 3 of the embodiment 1 Fig.19 Thus, the height H2 of the drain wiring 26a from the substrate 10 is smaller than the height of the source wiring 22a and the metal layer 30a from the substrate 10. This can suppress the gate-drain parasitic capacitance and the gate-source parasitic capacitance, and can suppress the degradation of the characteristics of the semiconductor device.
[0139] The height H2 of the drain wiring 26c from the substrate 10 is smaller than the height H1 of the source wiring 22c and the metal layer 30c from the substrate 10. This can further suppress the gate-drain parasitic capacitance and the gate-source parasitic capacitance, and can further suppress the degradation of the characteristics of the semiconductor device.
[0140] In the first embodiment and its modified example, the cover metal layer 30 is provided on the source wiring 22b, but the cover metal layer 30 may not be provided on the source wiring 22b. Figure 8 and Fig. 9 In this way, the source wiring 22a, the source wiring 22c, and the cover metal layer 30 are formed by different steps, but the source wiring 22a, the source wiring 22c, and the cover metal layer 30 may be formed integrally at the same time.
[0141] [Example 2]
[0142] Fig. 20 FIG. 2 is a top view of the semiconductor device of Example 2. Fig. 20As shown, in the semiconductor device 108 of the second embodiment, a FET group 36c and a FET group 36d are provided between the FET group 36a and the FET group 36b. The source wiring 22a and the source wiring 22c are electrically connected to the source electrodes of the FET group 36a, the FET group 36c, and the FET group 36d. The drain wiring 26a and the drain wiring 26c are electrically connected to the drain electrodes of the FET group 36a to the FET group 36d. The gate wiring 18 and the gate wiring 23 are electrically connected to the gate electrodes 14 of the FET group 36b to the FET group 36d. A covering metal layer 30 is provided in the region between the source wiring 22a and the source wiring 22c of the FET group 36a, the FET group 36c, and the FET group 36d. The other configurations are the same as those of the first embodiment, and the description thereof is omitted.
[0143] As in Example 2, the number of FET groups arranged in the Y direction may be four. In Example 1 and its variants, the number of FET groups arranged in the Y direction may be appropriately set. In Example 1, Example 2 and its variants, an example in which four unit FETs 35 are arranged in the X direction is described, but the number of unit FETs 35 in the X direction may be any one of one to three, five or more, and may be appropriately set.
[0144] [Measurement results]
[0145] GaN HEMTs having the structures of Comparative Example 1 and Modification Example 1 of Example 1 were fabricated, and high frequency characteristics were measured. A high frequency signal was input to the gate bus 25 , and an amplified high frequency signal was output from the drain bus 24 . Fig.21 is a graph showing K factors of semiconductor device A and semiconductor device B with respect to frequency. Fig. 22 Graph showing |S12| of semiconductor device A and semiconductor device B with respect to frequency. Fig.21 The horizontal axis is the frequency, and the vertical axis is the K factor, which is the stability factor. The smaller the K factor, the less likely it is to oscillate, and the more stable it is. Fig. 22 The horizontal axis is frequency, and the vertical axis is |S12|. |S12| is the absolute value of the S parameter S12 when the gate is set as port 1 and the drain is set as port 2. |S12| represents the power fed back from the drain to the gate. Semiconductor device A corresponds to Modification 1 of Example 1, and semiconductor device B corresponds to Comparative Example 1.
[0146] like Fig.21 and Fig. 22 As shown in the figure, when the frequency increases, both the K factor and |S12| increase. Compared with semiconductor device B, semiconductor device A has smaller K factor and |S12|. The gate-drain capacitance is a feedback capacitance, and when the gate-drain capacitance increases, both the K factor and |S12| increase. Compared with semiconductor device B, semiconductor device A can reduce the gate-drain capacitance and suppress the K factor and |S12|.
[0147] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.
Claims
1. A semiconductor device comprising: substrate; A first transistor unit, wherein a first drain electrode, a first gate electrode and a first source electrode are sequentially provided on the substrate; a second transistor unit, wherein a second source electrode, a second gate electrode, and a second drain electrode are arranged in parallel along the first source electrode and electrically connected to the first source electrode, respectively, on the substrate, and the second transistor unit is located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring disposed on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first cover metal layer, which is electrically connected to the first source electrode, and at least an upper portion of the first cover metal layer protrudes toward the gate wiring side beyond the first source electrode; as well as The second cover metal layer is provided on the second source electrode so as to be electrically connected thereto, and at least an upper portion of the second cover metal layer protrudes toward the gate wiring side beyond the second source electrode.
2. The semiconductor device according to claim 1, wherein At least a portion of the first cover metal layer and at least a portion of the second cover metal layer overlap the gate wiring in a non-contact manner in a plan view.
3. The semiconductor device according to claim 1 or 2, wherein: The first cover metal layer and the second cover metal layer are in contact with each other above the gate wiring.
4. The semiconductor device according to claim 3, wherein: Portions where the first cover metal layer and the second cover metal layer are in contact with each other above the gate wiring and portions where the first cover metal layer and the second cover metal layer are not provided above the gate wiring are alternately provided along the gate wiring.
5. The semiconductor device according to claim 1 or 2, wherein: The first cover metal layer and the second cover metal layer are not in contact with each other above the gate wiring.
6. The semiconductor device according to claim 5, wherein: The end of the first cover metal layer overlaps with the gate wiring when viewed from above, An end portion of the second cover metal layer overlaps with the gate wiring in a plan view.
7. The semiconductor device according to claim 1 or 2, comprising: A third transistor unit, which is provided with a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode in sequence on the substrate, and the third transistor unit is located in the direction in which the first gate electrode extends relative to the first transistor unit.
8. The semiconductor device according to claim 7, wherein: A connection wiring electrically connecting the third gate electrode and the gate wiring is provided between the first transistor unit and the third transistor unit, A portion of the first cover metal layer overlaps with at least a portion of the connection wiring in a plan view.
9. The semiconductor device according to claim 1 or 2, comprising: a first drain wiring disposed on the first drain electrode in an electrically contacting manner, wherein a height from the substrate to an upper surface of the first drain wiring is smaller than a height from the substrate to an upper surface of the first cover metal layer; and The second drain wiring is provided on the second drain electrode in an electrically contacting manner, and the height from the substrate to the upper surface of the second drain wiring is smaller than the height from the substrate to the upper surface of the second cover metal layer.
10. A semiconductor device comprising: substrate; A first transistor unit, wherein a first drain electrode, a first gate electrode and a first source electrode are sequentially provided on the substrate; a second transistor unit, wherein a second source electrode, a second gate electrode, and a second drain electrode are arranged in parallel along the first source electrode and electrically connected to the first source electrode, respectively, on the substrate, and the second transistor unit is located in a direction in which the first drain electrode, the first gate electrode, and the first source electrode are arranged relative to the first transistor unit; a gate wiring disposed on the substrate between the first source electrode and the second source electrode and adjacent to the first source electrode and the second source electrode, the gate wiring being electrically connected to the first gate electrode and the second gate electrode; a first source wiring, provided on the first source electrode in an electrically contacting manner; a second source wiring, provided on the second source electrode in an electrically contacting manner; A first drain wiring is disposed on the first drain electrode in an electrically contacting manner, wherein a height of an upper surface of the first drain wiring from the substrate is less than a height of an upper surface of the first source wiring from the substrate; as well as The second drain wiring is disposed on the second drain electrode in an electrically contacting manner, and a height of an upper surface of the second drain wiring from the substrate is smaller than a height of an upper surface of the second source wiring from the substrate.
11. The semiconductor device according to claim 10, comprising: A third transistor unit, which is provided with a third drain electrode electrically connected to the first drain electrode, a third gate electrode electrically connected to the gate wiring, and a third source electrode electrically connected to the first source electrode in sequence on the substrate, and the third transistor unit is located in the direction in which the first gate electrode extends relative to the first transistor unit.