Image sensor and forming method of image sensor

Abstract

The embodiment of the invention relates to the field of image sensors, and provides an image sensor, which comprises a substrate; the first transistor and the second transistor share a source electrode or a drain electrode, and at least the first transistor is a junction transistor; the first transistor comprises a first doped region and a second doped region; the first channel region is located between the first doped region and the second doped region; the third doped region surrounds the first channel region; the first channel region extends in a first direction parallel to the substrate surface or a second direction perpendicular to the substrate surface.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and more particularly to an image sensor and a method for forming the image sensor. Background Art

[0002] The source follower in current CMOS image sensors is usually a metal-oxide semiconductor field effect transistor (MOSFET: metal-oxide semiconductor FET). In this structure, changes in gate voltage will affect changes in source voltage or current. By detecting this change, the amount of photogenerated charge in the photodiode can be known. This process is often accompanied by noise, among which transient noise plays a major role at low frequencies. Transient noise is caused by the capture and release of electrons and holes in the channel by the Si and SiO2 interface. Transient noise will weaken the gate control ability and reduce the conversion gain. Summary of the invention

[0003] The embodiments of the present disclosure provide an image sensor and a method for forming the image sensor, which are at least beneficial for reducing transient noise and solving the problem of weakened gate control capability and reduced conversion gain caused by transient noise.

[0004] According to some embodiments of the present disclosure, an image sensor is provided on one hand, including: a substrate;

[0005] A first transistor and a second transistor, the first transistor and the second transistor share a source or a drain, and at least the first transistor is a junction transistor;

[0006] The first transistor includes: a first doping region and a second doping region; a first channel region located between the first doping region and the second doping region, and a third doping region surrounding the first channel region;

[0007] The first channel region extends along a first direction or a second direction, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

[0008] In some embodiments, it is characterized in that the first channel region extends along the second direction, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, and the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region.

[0009] In some embodiments, a first isolation structure is provided between the second sub-doping region and the third doping region, and the first isolation structure includes a first sub-isolation structure and a second sub-isolation structure; a first pad is provided between the first sub-isolation structure and the second sub-isolation structure, the first sub-isolation structure extends from the top of the substrate to below the first doping region, and the second sub-isolation structure extends from the top of the substrate to the first sub-doping region; a depth of the first sub-isolation structure along the second direction is greater than a depth of the first doping region along the second direction and is less than a depth of the second sub-isolation structure along the second direction.

[0010] In some embodiments, the first doping region and the second doping region have the same doping type, the first channel region has the same doping type as the first doping region and the second doping region, and the third doping region has a doping type opposite to that of the first channel region; the doping concentration of the first channel region is less than the doping concentration of the first doping region and the second doping region.

[0011] In some embodiments, the second transistor is a metal oxide semiconductor field effect transistor, and the second transistor also includes a gate and a fourth doping region, the gate is located on the substrate and is adjacent to the first doping region, the fourth doping region is located on a side of the gate away from the first doping region, and the doping depth of the fourth doping region is less than the doping depth of the first doping region.

[0012] In some embodiments, the second transistor is a junction transistor, and the second transistor also includes a fourth doping region and a second channel region, the second channel region is located between the first doping region and the fourth doping region, the fifth doping region is arranged around the second channel region, and the second channel region extends along the first direction or the second direction.

[0013] In some embodiments, the second channel region extends along the second direction, the fourth doping region includes a third sub-doping region and a fourth sub-doping region, the third sub-doping region is located below the first doping region and parallel to the substrate surface, and the fourth sub-doping region extends along the second direction and is electrically connected to the third sub-doping region.

[0014] In some embodiments, a second isolation structure is provided between the fourth sub-doping region and the fifth doping region, and the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure; a second pad is provided between the third sub-isolation structure and the fourth sub-isolation structure, the third sub-isolation structure extends from the top of the substrate to below the first doping region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doping region; a depth of the third sub-isolation structure along the second direction is greater than a depth of the first doping region along the second direction and is less than a depth of the fourth sub-isolation structure along the second direction.

[0015] In some embodiments, a third isolation structure is further provided between the fifth doping region and the third doping region, and a depth of the third isolation structure is not less than a depth of the first channel region or the second channel.

[0016] Another aspect of the present disclosure provides a method for forming an image sensor, including:

[0017] providing a substrate;

[0018] forming a first transistor and a second transistor, wherein the first transistor and the second transistor share a source or a drain, and at least the first transistor is a junction transistor;

[0019] The first transistor includes: a first doping region and a second doping region; a first channel region located between the first doping region and the second doping region, and a third doping region surrounding the first channel region;

[0020] The first channel region extends along a first direction or a second direction, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

[0021] In some embodiments, the first channel region extends along a first direction, and the method for forming the first transistor includes at least: performing first doping and second doping on the substrate to form a first doping region and a second doping region, forming a first channel region between the first doping region and the second doping region, and performing third doping around the first channel region to form a third doping region.

[0022] In some embodiments, the first channel region extends along a first direction, and the method for forming the first transistor at least includes: forming a first initial doping region, the top surface of the first initial doping region has a first distance from the top surface of the substrate, forming a second initial doping region on the first initial doping region, forming a third initial doping region on the top of the second initial doping region, and forming a fourth initial doping region on the side of the second initial doping region, the first initial doping region, the third initial doping region and the fourth initial doping region together constitute a third doping region, the third doping region surrounds the second initial doping region, the doping type of the third doping region is opposite to the doping type of the second initial doping region, and the second initial doping region serves as a first channel region; forming a first doping region and a second doping region at both ends of the third doping region.

[0023] In some embodiments, the first channel region extends along a first direction, and the method for forming the first transistor at least includes: forming a fifth initial doping region, the fifth initial doping region extends from the surface of the substrate to the substrate, and the bottom of the fifth initial doping region has a second distance from the surface of the substrate; forming a sixth initial doping region in the fifth initial doping region, the doping type of the fifth initial doping region is opposite to that of the sixth initial doping region, the sixth initial doping region serves as the first channel region, the remaining fifth initial doping region surrounds the first channel region, the remaining fifth initial doping region serves as the third doping region, and the first doping region and the second doping region are formed at both ends of the third doping region.

[0024] In some embodiments, the first channel region extends along the second direction, and the method for forming the first transistor at least includes: forming a second doping region, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, and the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region; forming a seventh initial doping region on the first sub-doping region, the seventh initial doping region serves as the first channel region, and doping is performed around the first channel region to form a third doping region; forming a first doping region on the third doping region and the first channel region; a first isolation structure is formed between the second sub-doping region and the third doping region, the first isolation structure includes a first sub-isolation structure and a second sub-isolation structure; a first pad is formed between the first sub-isolation structure and the second sub-isolation structure, the first sub-isolation structure extends from the top of the substrate to below the first doping region, and the second sub-isolation structure extends from the top of the substrate to the first sub-doping region; the depth of the first sub-isolation structure along the second direction is greater than the depth of the first doping region along the second direction and less than the depth of the second sub-isolation structure along the second direction.

[0025] In some embodiments, the first channel region extends along the second direction, and the method for forming the first transistor at least includes: forming a second doping region, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region; forming an eighth initial doping region on the first sub-doping region, the eighth initial doping region extends from the top surface of the substrate to the first sub-doping region, and a ninth initial doping region is formed in the eighth initial doping region, the eighth initial doping is opposite to the doping type of the ninth initial doping region, the ninth initial doping region serves as the first channel region, the remaining eighth initial doping region surrounds the first channel region, the remaining eighth initial doping region serves as the third doping region, and the first doping region is formed on the top of the third doping region.

[0026] In some embodiments, the second transistor is a metal oxide semiconductor field effect transistor, and the method for forming the second transistor also includes forming a gate, the gate is located on the substrate, and the gate is adjacent to the first doped region; a fourth doped region is formed on the side of the gate away from the first doped region, and the doping depth of the fourth doped region is less than the doping depth of the first doped region.

[0027] In some embodiments, the second transistor is a junction transistor, and the second transistor also includes a fourth doping region and a second channel region, the second channel region is located between the first doping region and the fourth doping region, the fifth doping region is arranged around the second channel region, and the second channel region extends along the first direction or the second direction.

[0028] In some embodiments, the second channel region extends along the second direction, the fourth doping region includes a third sub-doping region and a fourth sub-doping region, the third sub-doping region is located below the first doping region and parallel to the substrate surface, and the fourth sub-doping region extends along the second direction and is electrically connected to the third sub-doping region.

[0029] In some embodiments, a second isolation structure is formed between the fourth sub-doping region and the fifth doping region, and the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure; a second pad is provided between the third sub-isolation structure and the fourth sub-isolation structure, the third sub-isolation structure extends from the top of the substrate to below the first doping region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doping region; the depth of the third sub-isolation structure along the second direction is greater than the depth of the first doping region along the second direction and is less than the depth of the fourth sub-isolation structure along the second direction.

[0030] In some embodiments, a third isolation structure is further formed between the fifth doping region and the third doping region, and a depth of the third isolation structure is not less than a depth of the first channel region or the second channel.

[0031] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the source follower transistor is changed from a MOSFET transistor to a JFET transistor, and the conduction of the JFET requires the field effect of PN but not the field effect of the oxide. Therefore, the transient noise originally generated by the capture and release of carriers at the Si and / SiO2 interface can be removed, thereby enhancing the gate control capability of the source follower transistor and increasing the conversion gain. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of an image sensor provided by an embodiment of the present disclosure;

[0034] Figure 1a , Figure 1b For along Figure 1 Sectional view in X-X' direction;

[0035] Figure 2 for Figure 1 A top view of

[0036] Figure 3 A schematic diagram of circuit connections of an image sensor provided by an embodiment of the present disclosure;

[0037] Figure 4 A schematic diagram of an image sensor provided by another embodiment of the present disclosure;

[0038] Figure 5 for Figure 4 A top view of

[0039] Figure 6 A circuit connection diagram of an image sensor provided by another embodiment of the present disclosure;

[0040] Figure 7 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure;

[0041] Figure 7a , Figure 7b For along Figure 7 Sectional view in Y-Y' direction;

[0042] Figure 8 for Figure 7 A top view of

[0043] Fig. 9 A circuit connection diagram of an image sensor provided by yet another embodiment of the present disclosure;

[0044] Fig.10 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure;

[0045] Fig.11 for Fig.10 A top view of

[0046] Fig.12 A circuit connection diagram of an image sensor provided by yet another embodiment of the present disclosure;

[0047] Fig.13 is a circuit diagram of the image sensor disclosed herein;

[0048] Figures 14a to 14c A process flow chart of a method for preparing an image sensor provided in one embodiment of the present disclosure, Fig.14d for Fig.14c Cross-sectional view in Z-Z' direction;

[0049] Figures 15a to 15d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure, Fig.15e for Fig.14d Cross-sectional view in Z-Z' direction;

[0050] Figures 16a to 16d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure, Fig.16e for Fig.14d Cross-sectional view in Z-Z' direction;

[0051] Figures 17a to 17e A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure;

[0052] Figures 18a to 18d A process flow chart of a method for preparing an image sensor provided by yet another embodiment of the present disclosure; DETAILED DESCRIPTION

[0053] As can be seen from the background technology, the source follower in the current CMOS image sensor is usually a MOSFET. In this structure, the change of the gate voltage will affect the change of the source voltage or current. By detecting this change, the amount of photogenerated charge of the photodiode can be known. This process is often accompanied by noise, among which transient noise plays a major role at low frequencies. Transient noise is caused by the capture and release of electrons and holes in the channel by the Si and SiO2 interface. Transient noise will weaken the gate control ability and reduce the conversion gain.

[0054] The disclosed implementation changes the source follower transistor from a MOSFET transistor to a JFET transistor. The conduction of the JFET requires the field effect of PN but not the field effect of oxide. Therefore, the transient noise originally generated by the capture and release of carriers at the interface of Si and SiO2 can be removed, thereby enhancing the gate control capability of the source follower transistor and improving the conversion gain.

[0055] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0056] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0057] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0058] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0059] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0060] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0061] Figure 1 A schematic diagram of an image sensor provided by an embodiment of the present disclosure; Figure 1a , Figure 1b For along Figure 1 Sectional view in X-X' direction; Figure 2 for Figure 1 A top view of Figure 3 A schematic diagram of circuit connections of an image sensor provided by an embodiment of the present disclosure;

[0062] Figure 4 A schematic diagram of an image sensor provided by another embodiment of the present disclosure; Figure 5 for Figure 4 A top view of Figure 6 A circuit connection diagram of an image sensor provided by another embodiment of the present disclosure; Figure 7 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure; Figure 7a , Figure 7b For along Figure 7 Sectional view in Y-Y' direction; Figure 8 for Figure 7 A top view of Fig. 9 A circuit connection diagram of an image sensor provided by yet another embodiment of the present disclosure; Fig.10 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure; Fig.11 for Fig.10 A top view of Fig.12 A circuit connection diagram of an image sensor provided by yet another embodiment of the present disclosure; Fig.13 is a circuit diagram of the image sensor disclosed herein; Figures 14a to 14c A process flow chart of a method for preparing an image sensor provided in one embodiment of the present disclosure, Fig.14d for Fig.14cCross-sectional view in Z-Z' direction; Figures 15a to 15d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure, Fig.15e for Fig.14d Cross-sectional view in Z-Z' direction;

[0063] Figures 16a to 16d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure, Fig.16e for Fig.14d Cross-sectional view in Z-Z' direction; Figures 17a to 17e A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure; Figures 18a to 18d A process flow chart of a method for preparing an image sensor provided by yet another embodiment of the present disclosure;

[0064] Figures 1 to 3 For the first embodiment; Figure 1 The image sensor includes: a substrate 10, the substrate 10 has a well region 20; a first transistor 1 and a second transistor 2, the first transistor 1 and the second transistor 2 share a source or drain, and at least the first transistor 1 is a junction transistor (JFET); the first transistor 1 includes: a first doping region 101 and a second doping region 102; a first channel region 201 located between the first doping region 101 and the second doping region 102, and a third doping region 103 surrounding the first channel region 201; the first channel region 201 extends along a first direction or a second direction, the first direction is parallel to the surface of the substrate 10, and the second direction is perpendicular to the surface of the substrate 10. The first doping region 101 and the second doping region 102 serve as the source and drain of the first transistor 1, the first doping region 101 and the fourth doping region 104 serve as the source and drain of the second transistor 2, and the first doping region 101 serves as a common source or drain of the first transistor 1 and the second transistor 2. The first transistor 1 can be a source follower transistor (SF: SourceFollower), and the second transistor 2 can be a select transistor (SEL: Selector).

[0065] The second transistor 2 may be a junction transistor or a metal oxide semiconductor field effect transistor (MOSFET), Figure 1 The first transistor 1 shown is a junction transistor, and the second transistor 2 is a metal oxide semiconductor field effect transistor; the second transistor 2 also includes a gate 301 and a fourth doping region 104, the gate 301 is located on the substrate 10 and is adjacent to the first doping region 101, the fourth doping region 104 is located on the side of the gate 301 away from the first doping region 101, and the doping depth of the fourth doping region 104 is less than the doping depth of the first doping region 101.

[0066] Figure 1a , Figure 1b For along Figure 1Cross-sectional view along the XX' direction; the third doped region 103 is arranged around the first channel region 201, and the cross-section of the first channel region 201 can be circular or square, and the corresponding third doped region 103 can also be circular or square. This is only an example and is not limited here. For example, the third doped region 103 and the first channel region 201 can also be elliptical or rectangular.

[0067] Figure 2 for Figure 1 A top view of Figure 2 The dotted line schematically indicates the position of the first channel region 201 , which is located between the first doping region 101 and the second doping region 102 . The first transistor 1 and the second transistor 2 share the first doping region 101 , and the second transistor 2 has a gate 301 .

[0068] In the present embodiment, the first transistor 1 is a junction transistor (JFET), the second transistor 2 is a metal oxide semiconductor field effect transistor (MOSFET), the first transistor 1 in the present embodiment can be a P-type junction transistor, wherein the well region 20 is N-type doped, that is, an N-well, the first doping region 101 and the second doping region 102 are P-type doped, the first channel region 201 is also P-type doped, the doping concentrations of the first doping region 101 and the second doping region 102 are greater than the doping concentration of the first channel region 201, and the third doping region 103 is N-type doped; since the doping type of the third doping region 103 is the same as that of the first channel region 201, On the contrary, a PN junction is formed between the third doping region 103 and the first channel region 201. By applying a voltage to the third doping region 103 to change the width of the PN junction barrier, and thus changing the thickness of the conductive channel, i.e., the first channel region 201, the JFET is turned on or off, and the conductivity of the conductive channel is adjusted to achieve control of the output current. The thickness of the first channel region 201 mentioned here refers to the width from top to bottom of the first channel region 201. When the cross-section of the first channel region 201 is circular, its thickness refers to the diameter of the circle. When the cross-section of the first channel region 201 is square, its thickness refers to the side length of the square.

[0069] The first transistor 1 may be a source follower transistor (SF), which is used in a CMOS image sensor (CIS) to amplify and read out a signal output from a floating diffusion region (FD). In the prior art, a SF transistor is generally a MOSFET, and there are interface defects between Si and SiO2 of the MOSFET. When the SF transistor in the CMOS image sensor is in operation, carriers in the channel continuously undergo a binding and dissociation process with the bound states of the Si and SiO2 interfaces, causing the source output voltage to experience random transient fluctuations over time, generating transient noise, thereby affecting the stability of the output voltage. In the present embodiment, the first transistor 1 is a junction transistor, and a voltage is applied to the third doping region 103 to change the width of the PN junction barrier, thereby changing the thickness of the first channel region 201, so that the JFET is turned on or off; since the third doping region 103 and the first channel region 201 in the JFET are both made of silicon, there is no interface between Si and SiO2, that is, there is no interface defect between Si and SiO2, that is, in the present embodiment, when the SF transistor in the CMOS image sensor is working, there is no binding and dissociation process between the carriers in the channel and the bound states at the Si and SiO2 interface, which prevents the generation of transient noise, thereby making the output voltage more stable.

[0070] Figure 3 A circuit connection diagram of an image sensor provided by an embodiment of the present disclosure; and Figure 2 What is different from the top view is that in this embodiment, a first pad M1, a second pad M2, a third pad M3 and a fourth pad M4 are also included. The first pad M1 is electrically connected to the third doping region 103, and is used to apply a voltage to the third doping region 103; the second pad M2 is electrically connected to the gate 301, and is used to apply a voltage to the gate 301; the third pad M3 is used to lead out the signal, and the fourth pad M4 is used to apply a power supply voltage VDD to the first transistor 1. In addition, the image sensor also includes a photodiode (PD: Photo diode) 401, and the photodiode 401 is used to collect and store charges induced by photons; a transfer transistor 402 (TG: Transfer gate), and the transfer transistor 402 is used to control the conduction and cutoff of FD, and a fifth pad M5 is also included in the transfer transistor 402, and the fifth pad M5 is used to input a voltage to the transfer transistor 402; a floating diffusion region (FD: Floating diffusion) is also included between the multiple photodiodes 401, and FD is used to store electrons transferred from PD, Figure 3FD is not shown in the figure, and there is a sixth pad M6 on FD, which is used to lead out the signal of FD; the first pad M1 and the sixth pad M6 are connected by a wire 403; the source follower transistor SF can amplify the potential change of the floating diffusion area FD, and can output the amplified signal.

[0071] Figures 4 to 6 This is the second embodiment; the difference from the previous embodiment is that the second transistor 2 and the first transistor 1 are both junction transistors (JFET). Figure 4 and Figure 5 , Figure 4 A schematic diagram of an image sensor provided by another embodiment of the present disclosure, Figure 5 for Figure 4 The image sensor comprises: a substrate 10, the substrate 10 having a well region 20; a first transistor 1 and a second transistor 2, the first transistor 1 and the second transistor 2 share a source or a drain, and the first transistor 1 and the second transistor 2 are both JFETs; the first transistor 1 comprises: a first doping region 101 and a second doping region 102; a first channel region 201 located between the first doping region 101 and the second doping region 102, and a third doping region 103 surrounding the first channel region 201; the first channel region 201 extends along a first direction, the first direction is parallel to the surface of the substrate 10, wherein the first doping region 101 is a doping region of the first doping region 102; the first channel region 201 extends along a first direction, the first direction is parallel to the surface of the substrate 10, and the first doping region 103 is a doping region of the first doping region 101. The doped region 101 and the second doped region 102 serve as the source and drain of the first transistor 1; the second transistor 2 includes the first doped region 101 and the fourth doped region 104, the second channel region 202 located between the first doped region 101 and the fourth doped region 104, and the fifth doped region 105 surrounding the second channel region 202. The second channel region 202 extends along a first direction, and the first direction is parallel to the surface of the substrate 10. The first doped region 101 and the fourth doped region 104 serve as the source and drain of the second transistor 2, and the first doped region 101 serves as a common source or drain of the first transistor 1 and the second transistor 2. The first transistor 1 may be a source follower transistor (SF: Source Follower), and the second transistor 2 may be a select transistor (SEL: Selector). Figure 5 The dotted lines in FIG. 2 respectively show the positions of the first channel region 201 and the second channel region 202 .

[0072] Figure 6A circuit connection diagram of an image sensor provided in another embodiment of the present disclosure, the same parts as those in the circuit connection diagram in the previous embodiment are not repeated here, and the difference from the circuit connection diagram in the previous embodiment is that, in this embodiment, the second pad M2 is connected to the fifth doping region 105 instead of the gate 301, and a voltage is applied to the fifth doping region 105 through the second pad M2 to change the width of the PN junction barrier in the second transistor 2, thereby changing the thickness of the second channel region 202, so that the JFET is turned on or off.

[0073] Figures 7 to 9 This is the third embodiment; Figure 7 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure; Figure 7a , Figure 7b For along Figure 7 Sectional view in Y-Y' direction; Figure 8 for Figure 7 A top view of Fig. 9 This is a circuit connection diagram of an image sensor provided by another embodiment of the present disclosure. Figure 7The image sensor includes: a substrate 10, the substrate 10 has a well region 20; a first transistor 1 and a second transistor 2, the first transistor 1 and the second transistor 2 share a source or a drain; the first transistor 1 includes: a first doping region 101 and a second doping region 102, the second doping region 102 includes a first sub-doping region 1021 and a second sub-doping region 1022, the first sub-doping region 1021 is located below the first doping region 101 and is parallel to the surface of the substrate 10, the second sub-doping region 1022 extends along a second direction and is electrically connected to the first sub-doping region 1021, the second direction is perpendicular to the surface of the substrate 10, it should be noted that the first sub-doping region 1021 is inside the substrate 10 and has a certain distance from the top surface of the substrate 10, and the lateral length of the first doping region 101 is less than the lateral length of the first sub-doping region. A first channel region 201 is further provided between the first doping region 101 and the first sub-doping region 1021. The first channel region 201 extends along a second direction, and the second direction is perpendicular to the direction of the substrate 10. A third doping region 103 is arranged around the first channel region 201. One end of the third doping region 103 is connected to the first doping region 101, and the other end of the third doping region 103 is connected to the first sub-doping region 1021. A first isolation structure 50 is provided between the second sub-doping region 1022 and the third doping region 103. The first isolation structure 50 The first isolation structure 501 includes a first pad M1 and a second isolation structure 502; the first isolation structure 501 and the second isolation structure 502 have a first pad M1 between them; the first isolation structure 501 extends from the top of the substrate 10 to below the first doping region 101; the second isolation structure 502 extends from the top of the substrate 10 to the first sub-doping region 1021; the depth of the first isolation structure 501 along the second direction is greater than the depth of the first doping region 101 along the second direction and less than the depth of the second isolation structure 502 along the second direction. The second transistor 2 is a metal oxide semiconductor field effect transistor (MOSFET), with reference to Figure 7 The second transistor 2 further includes a gate 301 and a fourth doping region 104 . The gate 301 is located on the substrate 10 and is adjacent to the first doping region 101 . The fourth doping region 104 is located on a side of the gate 301 away from the first doping region 101 .

[0074] Figure 7a , Figure 7b For along Figure 7 Cross-sectional view along the Y-Y' direction; the third doped region 103 is arranged around the first channel region 201, and the cross-section of the first channel region 201 can be circular or square, and the corresponding third doped region 103 can also be circular or square. This is only an example and is not limited here. For example, the third doped region 103 and the first channel region 201 can also be elliptical or rectangular.

[0075] Figure 8 for Figure 7 A top view of Figure 8 The dotted line schematically indicates the position of the first channel region 201 , which is located between the first doped region 101 and the gate 301 ; the first transistor 1 and the second transistor 2 share the first doped region 101 ; and a first pad M1 is provided between the first sub-isolation structure 501 and the second sub-isolation structure 502 .

[0076] In this embodiment, by setting the first transistor 1 as a JFET and the first channel region 201 extending along the second direction, the channel length of the first channel region 201 is lengthened, so that the control capability of the first transistor 1 is improved, the voltage output is more stable, and the performance of the first transistor 1 is further improved. In this embodiment, the first transistor 1 is a junction transistor (JFET), the second transistor 2 is a metal oxide semiconductor field effect transistor (MOSFET), the first transistor 1 is a P-type junction transistor, wherein the well region 20 is N-type doped, that is, an N-well, the first doping region 101 and the second doping region 102 are P-type doped, the first channel region 201 is also P-type doped, the doping concentrations of the first doping region 101 and the second doping region 102 are both greater than the doping concentration of the first channel region 201, and the third doping region 103 is N-type doped; the doping type of the third doping region 103 is the same as the doping type of the well region 20, and the third doping region 103 is N-type doped. 3 is opposite to the doping type of the first channel region 201; since the doping type of the third doping region 103 is opposite to that of the first channel region 201, a PN junction is formed between the third doping region 103 and the first channel region 201. Since the first channel region 201 extends along the second direction, its extension depth becomes deeper, so that the channel length of the first channel region 201 is lengthened. When a voltage is applied to the third doping region 103 through the first pad M1, the thickness of the conductive channel, i.e., the first channel region 201, is changed, so that the JFET is turned on or off. The first channel region 201 disposed vertically on the substrate 10 improves the control capability of the first transistor. It should also be noted that the doping type of the third doping region 103 is the same as the doping type of the well region 20. When a voltage is applied to the first pad M1, the voltage will be transmitted to the third doping region 103 through the well region 20 between the third doping region 103 and the second sub-doping region 1022, thereby changing the width of the PN junction barrier of the first transistor 1, so that the JFET is turned on or off, and the output current is controlled by adjusting the conductivity of the conductive channel. In order to prevent the first pad M1 from affecting the first doping region 101 and the second sub-doping region 1022 when a voltage is applied thereto, a first sub-isolation structure 501 and a second sub-isolation structure 502 are arranged on both sides of the first pad. The first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doping region 101, thereby preventing the first pad M1 from affecting the first doping region 101. The second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doping region 1021 to further prevent the first pad M1 from affecting the second sub-doping region 1022. Since the first sub-doping region 1021 is far away from the first pad M1, the first sub-doping region 1021 will basically not be affected by the voltage applied by the first pad M1. Therefore, the first sub-doping region 1021 may not be provided with an isolation structure. Of course, in other embodiments, in order to maintain a better isolation effect, other isolation structures may also be arranged on the first sub-doping region 1021.

[0077] Fig. 9 A circuit connection diagram of an image sensor provided in another embodiment of the present disclosure. In this embodiment, the image sensor further includes a first pad M1, a second pad M2, a third pad M3, and a fourth pad M4. The first pad M1 is located between the first sub-isolation structure 501 and the second sub-isolation structure 502, and the first pad is used to apply a voltage to the third doping region 103; the second pad M2 is electrically connected to the gate 301, and is used to apply a voltage to the gate 301; the third pad M3 is located in the fourth doping region 104 for leading out a signal, and the fourth pad M4 is located in the second sub-doping region 1022 for applying a power supply voltage VDD to the first transistor 1. In addition, the image sensor further includes a photodiode (PD) 401, which is used to collect and store charges induced by photons; a transfer transistor 402 (TG), which is used to control the on and off of FD, and the transfer transistor 402 also includes a fifth pad M5, which is used to input voltage to the transfer transistor 402; and a floating diffusion region (FD) is also included between the multiple photodiodes 401, and the FD is used to store electrons transferred from the PD. Figure 3 FD is not shown in the figure, and there is also a sixth pad M6 on FD, which is used to lead out the signal of FD; the first pad M1 and the sixth pad M6 are connected by a wire 403; the source follower transistor SF can amplify the potential change of the floating diffusion area FD that receives charges from the photodiode PD, and can output the amplified change to the output line.

[0078] Figures 10 to 12 This is the fourth embodiment; Fig.10 A schematic diagram of an image sensor provided in yet another embodiment of the present disclosure; Fig.11 for Fig.10 A top view of Fig.12A circuit connection diagram of an image sensor provided for another embodiment of the present disclosure; different from the previous embodiment, in this embodiment, the second transistor 2 and the first transistor 1 are both junction transistors, the first channel region 201 and the second channel region 202 both extend along the second direction, the first transistor 1 and the second transistor 2 share a first doping region 101, the second transistor 2 also includes a fourth doping region 104 and a second channel region 202, the second channel region 202 is located between the first doping region 101 and the fourth doping region 104, the fifth doping region 105 is arranged around the second channel region 202, and the second channel region 202 extends along the second direction. The fourth doping 104 includes a third sub-doping region 1041 and a fourth sub-doping region 1042, the third sub-doping region 1041 is located below the first doping region 101 and parallel to the surface of the substrate 10, and the fourth sub-doping region 1042 extends along the second direction and is electrically connected to the third sub-doping region 1041; a second isolation structure 60 is provided between the fourth sub-doping region 1042 and the fifth doping region 105, and the second isolation structure 60 includes a third sub-isolation structure 601 and a fourth sub-isolation structure 602; a second pad M2 is provided between the third sub-isolation structure 601 and the fourth sub-isolation structure 602, the third sub-isolation structure 601 extends from the top of the substrate 10 to below the first doping region 101, and the fourth sub-isolation structure 602 extends from the top of the substrate 10 to the third sub-doping region 1041; the depth of the third sub-isolation structure 601 along the second direction is greater than the depth of the first doping region 101 along the second direction and is less than the depth of the fourth sub-isolation structure 602 along the second direction. A third isolation structure 70 is further provided between the fifth doping region 105 and the third doping region. The depth of the third isolation structure 70 is not less than the depth of the first channel region 201 or the second channel 202 .

[0079] Fig.11 for Fig.10 A top view of Fig.11 The dotted line position schematically indicates the position of the first channel region 201 and the second channel region 202, and a third isolation structure 70 is provided between the first channel region 201 and the second channel region 202; the first transistor 1 and the second transistor 2 share the first doped region 101; a first pad M1 is provided between the first sub-isolation structure 501 and the second sub-isolation structure 502, and a second pad M2 is provided between the third sub-isolation structure 601 and the fourth sub-isolation structure 602.

[0080] In this embodiment, by setting the first transistor 1 and the second transistor 2 as JFETs and the first channel region 201 and the second channel region 202 both extending along the second direction, the channel lengths of the first channel region 201 and the second channel region 202 are lengthened, so that the control capability of the first transistor 1 and the second transistor 2 is improved, the voltage output is more stable, and the performance of the first transistor 1 and the second transistor 2 is further improved. In the present embodiment, the first transistor 1 and the second transistor 2 are both P-type junction transistors, wherein the well region 20 is N-type doped, i.e., an N-well, the first doping region 101 and the second doping region 102 are P-type doped, the first channel region 201 and the second channel region 202 are also P-type doped, the doping concentrations of the first doping region 101 and the second doping region 102 are both greater than the doping concentration of the first channel region 201, the doping concentrations of the first doping region 101 and the fourth doping region 104 are both greater than the doping concentration of the second channel region 202, and the third doping region 103 and the fifth doping region 105 are both N-type doped; the doping type of the third doping region 103 and the doping type of the fifth doping region 105 are the same as the doping type of the well region 20, the doping type of the third doping region 103 is opposite to that of the first channel region 201, and the doping type of the fifth doping region 105 is opposite to that of the second channel region 202.

[0081] Since the doping type of the third doping region 103 is opposite to that of the first channel region 201, a PN junction is formed between the third doping region 103 and the first channel region 201. Since the first channel region 201 extends along the second direction, its extension depth becomes deeper, so that the channel length of the first channel region 201 is lengthened. When a voltage is applied to the third doping region 103 through the first pad M1, the thickness of the conductive channel, i.e., the first channel region 201, is changed, so that the JFET is turned on or off. The first channel region 201 arranged vertically on the substrate 10 improves the control capability of the first transistor. It should also be noted that the doping type of the third doping region 103 is the same as the doping type of the well region 20. When a voltage is applied to the first pad M1, the voltage is transmitted to the third doping region 103 through the well region 20 between the third doping region 103 and the second sub-doping region 1022, changing the width of the PN junction barrier of the first transistor 1, so that the JFET is turned on or off, and then the output current is controlled by adjusting the conductivity of the conductive channel. In order to prevent the first pad M1 from affecting the first doping region 101 and the second sub-doping region 1022 when a voltage is applied thereto, a first sub-isolation structure 501 and a second sub-isolation structure 502 are arranged on both sides of the first pad. The first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doping region 101, thereby preventing the first pad M1 from affecting the first doping region 101. The second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doping region 1021 to further prevent the first pad M1 from affecting the second sub-doping region 1022. Since the first sub-doping region 1021 is far away from the first pad M1, the first sub-doping region 1021 will basically not be affected by the voltage applied by the first pad M1. Therefore, the first sub-doping region 1021 may not be provided with an isolation structure. Of course, in other embodiments, in order to maintain a better isolation effect, other isolation structures may also be arranged on the first sub-doping region 1021. Since the doping type of the fifth doping region 105 is opposite to that of the second channel region 202, a PN junction is formed between the fifth doping region 105 and the second channel region 202. Since the second channel region 202 extends along the second direction, its extension depth becomes deeper, so that the channel length of the second channel region 202 is lengthened. When a voltage is applied to the fifth doping region 105 through the second pad M2, the thickness of the conductive channel, i.e., the second channel region 202, is changed, so that the JFET is turned on or off. The second channel region 202 arranged vertically on the substrate 10 improves the control capability of the second transistor. It should also be noted that the doping type of the fifth doping region 105 is the same as the doping type of the well region 20. When a voltage is applied to the second pad M2, the voltage is transmitted to the fifth doping region 105 through the well region 20 between the fifth doping region 105 and the fourth sub-doping region 1042, changing the width of the PN junction barrier of the second transistor 2, so that the JFET is turned on or off, and then the output current is controlled by adjusting the conductivity of the conductive channel.In order to prevent the second pad M2 from affecting the first doping region 101 and the fourth sub-doping region 1042 when a voltage is applied, a third sub-isolation structure 601 and a fourth sub-isolation structure 602 are set on both sides of the second pad M2. The third sub-isolation structure 601 extends from the top of the substrate 10 to below the first doping region 101, thereby preventing the second pad M2 from affecting the first doping region 101. The fourth sub-isolation structure 602 extends from the top of the substrate 10 to the third sub-doping region 1041 to further prevent the second pad M2 from affecting the fourth sub-doping region 1042. Since the third sub-doping region 1041 is far away from the second pad M2, the third sub-doping region 1041 will basically not be affected by the voltage applied by the second pad M2. Therefore, the third sub-doping region 1041 may not be set with an isolation structure. Of course, in other embodiments, in order to maintain a better isolation effect, other isolation structures may also be set on the third sub-doping region 1041.

[0082] Fig.12 A circuit connection diagram of an image sensor provided for another embodiment of the present disclosure. In this embodiment, the image sensor further includes a first pad M1, a second pad M2, a third pad M3, and a fourth pad M4. The first pad M1 is located between the first sub-isolation structure 501 and the second sub-isolation structure 502, and the first pad is used to apply a voltage to the third doping region 103; the second pad M2 is located between the third sub-isolation structure 601 and the fourth sub-isolation structure 602, and the second pad M2 is used to apply a voltage to the fifth doping region 105; the third pad M3 is located in the fourth sub-doping region 1042 for leading out the signal, and the fourth pad M4 is located in the second sub-doping region 1022 for applying a power supply voltage VDD to the first transistor 1. In addition, the image sensor further includes a photodiode (PD) 401, which is used to collect and store charges induced by photons; a transfer transistor 402 (TG), which is used to control the on and off of FD, and the transfer transistor 402 also includes a fifth pad M5, which is used to input voltage to the transfer transistor 402; and a floating diffusion region (FD) is also included between the multiple photodiodes 401, and the FD is used to store electrons transferred from the PD. Figure 3 FD is not shown in the figure, and there is also a sixth pad M6 on FD, which is used to lead out the signal of FD; the first pad M1 and the sixth pad M6 are connected by a wire 403; the source follower transistor SF can amplify the potential change of the floating diffusion area FD that receives charges from the photodiode PD, and can output the amplified change to the output line.

[0083] Fig.131 is a circuit diagram of an image sensor disclosed in the present invention; the image sensor includes a photodiode PD, a transfer transistor TG, a floating diffusion area FD, a reset transistor RST, a source follower transistor SF, and a selection transistor SEL. The photodiode PD can generate charges proportional to the amount of light incident from the outside, the photodiode PD can be coupled to the transfer transistor TG, the charges generated and accumulated by the photodiode PD are transferred to the floating diffusion area FD through the transfer transistor TG, and the floating diffusion area FD can accumulate and store the charges. One end of the transfer transistor TG is connected to the photodiode PD, and the other end of the transfer transistor TG can be connected to the floating diffusion area FD. The transfer transistor TG can transfer the charge generated by the photodiode PD to the floating diffusion area FD according to the transfer signal TX. The source follower transistor SF can amplify the potential change of the floating diffusion area FD and can output the amplified signal; when the source follower transistor SF is turned on, the power supply voltage VDD provided to the drain of the source follower transistor SF can be transferred to the drain area of ​​the selection transistor SEL, and the selection transistor SEL can select the unit pixel to be read row by row. The selection transistor SEL can be a transistor driven by the selection line of the row selection signal RS; the reset transistor RST can periodically reset the floating diffusion area FD, and the reset transistor RST can be driven by the reset line of the reset signal RX. When the reset signal RX turns on the reset transistor RST, the power supply voltage VDD is provided to the drain of the reset transistor RST, and the power supply voltage VDD can be transferred to the floating diffusion area FD. The circuit operation process of the image sensor in this embodiment is roughly as follows: first, RST and TG are turned on at the same time to clear the PD, and then the RST transistor is turned on to reset the FD voltage; the photodiode PD generates electron holes under light, and the TG transistor is turned on, so that the electrons generated by the PD are transmitted to the FD (the voltages of the FD and SF transistors are equal), the gate of the SF transistor obtains electrons, and the gate voltage of the SF transistor decreases (the potential increases). As the potential of the FD fluctuates, the output signal Vout fluctuates.

[0084] The following is an explanation of a method for forming an image sensor. A method for forming an image sensor includes: providing a substrate, and doping the substrate to form a well region; forming a first transistor and a second transistor in the substrate, wherein the first transistor and the second transistor share a source or a drain, and at least the first transistor is a junction transistor; the first transistor includes: a first doping region and a second doping region; a first channel region located between the first doping region and the second doping region, and a third doping region surrounding the first channel region; the first channel region extends along a first direction or a second direction, wherein the first direction is parallel to a surface of the substrate, and the second direction is perpendicular to the surface of the substrate. Figure 14a-Figure 18d Only the method for forming the first transistor 1 is described, and the formation process of the second transistor 2 can refer to the formation process of the first transistor 1 .

[0085] Figures 14a to 14c The process flow chart of the image sensor preparation method provided in one embodiment of the present disclosure, the first channel region 201 extends along the first direction, and the method for forming the first transistor at least includes: providing a substrate 10, doping the substrate 10 to form a well region 20; performing first doping and second doping on the well region 20 to form a first doping region 101 and a second doping region 102, forming a first channel region 201 between the first doping region 101 and the second doping region 102, and performing third doping around the first channel region 201 to form a third doping region 103. Fig.14d for Fig.14c In the cross-sectional view along the ZZ′ direction, the first channel region 201 may be circular, the third doped region 103 surrounds the first channel region 201 , and the third doped region 103 and the first channel region 201 may be concentric circles.

[0086] Figures 15a to 15d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure, Fig.15e for Fig.14d In the Z-Z' direction cross-sectional view; in the present embodiment, the first channel region extends along the first direction, and the method for forming the first transistor at least comprises: forming a first initial doping region 1031, the top surface of the first initial doping region 1031 has a first distance D1 from the top surface of the substrate 10, forming a second initial doping region 1032 on the first initial doping region 1031, forming a third initial doping region 1033 on the top of the second initial doping region 1032, and forming a fourth initial doping region 1034 on the side of the second initial doping region 1032, as shown in FIG. Fig.15e The fourth initial doping region 1034 shown is located between the first initial doping region 1031 and the second initial doping region 1032 and on both sides of the second initial doping region 1032; the first initial doping region 1031, the third initial doping region 1033 and the fourth initial doping region 1034 together constitute the third doping region 103, the third doping region 103 surrounds the second initial doping region 1032, the doping type of the third doping region 103 is opposite to the doping type of the second initial doping region 1032, and the second initial doping region 1032 serves as the first channel region 201; the first doping region 101 and the second doping region 102 are formed at both ends of the third doping region.

[0087] Figures 16a to 16d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure, Fig.16e for Fig.14dThe Z-Z' direction cross-sectional view; the first channel region extends along the first direction, and the method for forming the first transistor at least includes: forming a fifth initial doping region 1035, the fifth initial doping region 1035 extends from the surface of the substrate 10 to the inside of the substrate 10, and the bottom of the fifth initial doping region 1035 has a second distance D2 from the surface of the substrate 10; forming a sixth initial doping region 1036 in the fifth initial doping region 1035, the doping type of the fifth initial doping region 1035 is opposite to that of the sixth initial doping region 1036, the sixth initial doping region 1036 serves as the first channel region 201, the remaining fifth initial doping region 1035 surrounds the first channel region 201, and the remaining fifth initial doping region serves as the third doping region 103, and the first doping region 101 and the second doping region 102 are formed at both ends of the third doping region 103. Fig.16e As shown, the sixth initial doping region 1036 may be circular, the remaining fifth initial doping region 1035 surrounds the sixth initial doping region 1036 , and the remaining fifth initial doping region 1035 and the sixth initial doping region 1036 may be concentric circles.

[0088] Figures 17a to 17e A process flow chart of an image sensor manufacturing method provided by another embodiment of the present disclosure; the first channel region 201 extends along the second direction, and the forming method of the first transistor 1 at least includes: forming a second doping region 102, the second doping region 102 includes a first sub-doping region 1021 and a second sub-doping region 1022, the first sub-doping region 1021 is located below the surface of the substrate 10, and the second sub-doping region 1022 extends along the second direction and is electrically connected to the first sub-doping region 1021; forming a seventh initial doping region 1037 on the first sub-doping region 1021, the seventh initial doping region 1037 serves as the first channel region 201, and is doped around the first channel region 201 to form a third doping region 103; between the third doping region 103 and A first doping region 101 is formed on the seventh initial doping region 1037; a first isolation structure 50 is formed between the second sub-doping region 102 and the third doping region 103, and the first isolation structure 50 includes a first sub-isolation structure 501 and a second sub-isolation structure 502; a first pad M1 is formed between the first sub-isolation structure 501 and the second sub-isolation structure 502, the first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doping region 101, and the second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doping region 1021; the depth of the first sub-isolation structure 1021 along the second direction is greater than the depth of the first doping region 101 along the second direction and is less than the depth of the second sub-isolation structure 1022 along the second direction.

[0089] Figures 18a to 18d A process flow chart of a method for preparing an image sensor provided by another embodiment of the present disclosure; the structure of the first transistor 1 formed in this embodiment is similar to Fig.17e Same, so see Figures 18a to 18das well as Fig.17e For illustration, the first channel region 201 extends along the second direction, and the method for forming the first transistor 1 at least includes: forming a second doping region 102, the second doping region 102 includes a first sub-doping region 1021 and a second sub-doping region 1022, the first sub-doping region 1021 is located below the surface of the substrate 10, the second sub-doping region 1022 extends along the second direction and is electrically connected to the first sub-doping region 1021; forming an eighth initial doping region 1038 on the first sub-doping region 1021, the eighth initial doping region 1038 is formed on the first sub-doping region 1021, and the eighth initial doping region 1038 is formed on the first sub-doping region 1021. The top surface of the substrate 10 extends to the first sub-doping region 1021, and a ninth initial doping region 1039 is formed in the eighth initial doping region 1038. The doping type of the eighth initial doping region 1038 is opposite to that of the ninth initial doping region 1039. The ninth initial doping region 1039 serves as the first channel region 201. The remaining eighth initial doping region 1038 surrounds the first channel region 201. The remaining eighth initial doping region 1038 serves as the third doping region 103. The first doping region 101 is formed on the top of the third doping region 103. A first isolation structure 50 is formed between the second sub-doping region 102 and the third doping region 103, and the first isolation structure 50 includes a first sub-isolation structure 501 and a second sub-isolation structure 502; a first pad M1 is formed between the first sub-isolation structure 501 and the second sub-isolation structure 502, the first sub-isolation structure 501 extends from the top of the substrate 10 to below the first doping region 101, and the second sub-isolation structure 502 extends from the top of the substrate 10 to the first sub-doping region 1021; the depth of the first sub-isolation structure 1021 along the second direction is greater than the depth of the first doping region 101 along the second direction and is less than the depth of the second sub-isolation structure 1022 along the second direction.

[0090] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. An image sensor, characterized in that: include: substrate; A first transistor and a second transistor, wherein the first transistor and the second transistor share a source or a drain, and at least the first transistor is a junction transistor; The first transistor includes: a first doping region and a second doping region; a first channel region located between the first doping region and the second doping region, and a third doping region surrounding the first channel region; The first channel region extends along a first direction or a second direction, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

2. The image sensor according to claim 1, characterized in that The first channel region extends along a second direction, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, and the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region.

3. The image sensor according to claim 2, characterized in that A first isolation structure is provided between the second sub-doping region and the third doping region, the first isolation structure comprising a first sub-isolation structure and a second sub-isolation structure; a first pad is provided between the first sub-isolation structure and the second sub-isolation structure, the first sub-isolation structure extends from the top of the substrate to below the first doping region, and the second sub-isolation structure extends from the top of the substrate to the first sub-doping region; a depth of the first sub-isolation structure along the second direction is greater than a depth of the first doping region along the second direction and is less than a depth of the second sub-isolation structure along the second direction.

4. The image sensor according to claim 1, characterized in that The first doping region and the second doping region have the same doping type, the first channel region has the same doping type as the first doping region and the second doping region, and the third doping region has a doping type opposite to that of the first channel region; the doping concentration of the first channel region is less than the doping concentration of the first doping region and the second doping region.

5. The image sensor according to any one of claims 1 to 4, characterized in that: The second transistor is a metal oxide semiconductor field effect transistor, and the second transistor also includes a gate and a fourth doping region, the gate is located on the substrate and is adjacent to the first doping region, the fourth doping region is located on a side of the gate away from the first doping region, and the doping depth of the fourth doping region is less than the doping depth of the first doping region.

6. The image sensor according to any one of claims 1 to 4, characterized in that: The second transistor is a junction transistor, and the second transistor also includes a fourth doping region and a second channel region, the second channel region is located between the first doping region and the fourth doping region, the fifth doping region is arranged around the second channel region, and the second channel region extends along the first direction or the second direction.

7. The image sensor according to claim 6, characterized in that: The second channel region extends along the second direction, the fourth doping region includes a third sub-doping region and a fourth sub-doping region, the third sub-doping region is located below the first doping region and parallel to the substrate surface, and the fourth sub-doping region extends along the second direction and is electrically connected to the third sub-doping region.

8. The image sensor according to claim 6, characterized in that A second isolation structure is provided between the fourth sub-doping region and the fifth doping region, and the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure; a second pad is provided between the third sub-isolation structure and the fourth sub-isolation structure, the third sub-isolation structure extends from the top of the substrate to below the first doping region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doping region; a depth of the third sub-isolation structure along the second direction is greater than a depth of the first doping region along the second direction and is less than a depth of the fourth sub-isolation structure along the second direction.

9. The image sensor according to claim 6, characterized in that: A third isolation structure is further provided between the fifth doping region and the third doping region, and a depth of the third isolation structure is not less than a depth of the first channel region or the second channel.

10. A method for forming an image sensor, characterized in that: include: providing a substrate; forming a first transistor and a second transistor, wherein the first transistor and the second transistor share a source or a drain, At least the first transistor is a junction transistor; The first transistor includes: a first doping region and a second doping region; a first channel region located between the first doping region and the second doping region, and a third doping region surrounding the first channel region; The first channel region extends along a first direction or a second direction, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

11. The method for forming an image sensor according to claim 10, wherein: The first channel region extends along the first direction, and the method for forming the first transistor at least includes: performing first doping and second doping on the substrate to form a first doping region and a second doping region, forming a first channel region between the first doping region and the second doping region, and performing third doping around the first channel region to form a third doping region.

12. The method for forming an image sensor according to claim 10, wherein: The first channel region extends along the first direction, and the method for forming the first transistor at least includes: forming a first initial doping region, the top surface of the first initial doping region has a first distance from the top surface of the substrate, forming a second initial doping region on the first initial doping region, forming a third initial doping region on the top of the second initial doping region, and forming a fourth initial doping region on the side of the second initial doping region, the first initial doping region, the third initial doping region and the fourth initial doping region together constitute the third doping region, the third doping region surrounds the second initial doping region, the doping type of the third doping region is opposite to the doping type of the second initial doping region, and the second initial doping region serves as the first channel region; forming the first doping region and the second doping region at both ends of the third doping region.

13. The method for forming an image sensor according to claim 10, wherein: The first channel region extends along the first direction, and the method for forming the first transistor at least includes: forming a fifth initial doping region, the fifth initial doping region extends from the substrate surface to the substrate, and the bottom of the fifth initial doping region has a second distance from the substrate surface; forming a sixth initial doping region in the fifth initial doping region, the fifth initial doping is opposite to the doping type of the sixth initial doping region, the sixth initial doping region serves as the first channel region, the remaining fifth initial doping region surrounds the first channel region, the remaining fifth initial doping region serves as the third doping region, and the first doping region and the second doping region are formed at both ends of the third doping region.

14. The method for forming an image sensor according to claim 10, wherein: The first channel region extends along the second direction, and the method for forming the first transistor at least includes: forming the second doping region, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region; forming a seventh initial doping region on the first sub-doping region, the seventh initial doping region serves as the first channel region, and is doped around the first channel region to form the third doping region; forming the first doping region on the third doping region and the first channel region; a first isolation structure is formed between the second sub-doping region and the third doping region, the first isolation structure includes a first sub-isolation structure and a second sub-isolation structure; a first pad is formed between the first sub-isolation structure and the second sub-isolation structure, the first sub-isolation structure extends from the top of the substrate to below the first doping region, and the second sub-isolation structure extends from the top of the substrate to the first sub-doping region; the depth of the first sub-isolation structure along the second direction is greater than the depth of the first doping region along the second direction and less than the depth of the second sub-isolation structure along the second direction.

15. The method for forming an image sensor according to claim 10, wherein: The first channel region extends along the second direction, and the method for forming the first transistor at least includes: forming the second doping region, the second doping region includes a first sub-doping region and a second sub-doping region, the first sub-doping region is located below the first doping region and parallel to the substrate surface, the second sub-doping region extends along the second direction and is electrically connected to the first sub-doping region; forming an eighth initial doping region on the first sub-doping region, the eighth initial doping region extends from the top surface of the substrate to the first sub-doping region, and a ninth initial doping region is formed in the eighth initial doping region, the eighth initial doping is opposite to the doping type of the ninth initial doping region, the ninth initial doping region serves as the first channel region, the remaining eighth initial doping region surrounds the first channel region, the remaining eighth initial doping region serves as the third doping region, and the first doping region is formed on the top of the third doping region.

16. The method for forming an image sensor according to any one of claims 10 to 15, characterized in that: The second transistor is a metal oxide semiconductor field effect transistor, and the method for forming the second transistor also includes forming a gate, the gate is located on the substrate, and the gate is adjacent to the first doping region; a fourth doping region is formed on a side of the gate away from the first doping region, and the doping depth of the fourth doping region is less than the doping depth of the first doping region.

17. The method for forming an image sensor according to any one of claims 10 to 15, characterized in that: The second transistor is a junction transistor, and the second transistor also includes a fourth doping region and a second channel region, the second channel region is located between the first doping region and the fourth doping region, the fifth doping region is arranged around the second channel region, and the second channel region extends along the first direction or the second direction.

18. The method for forming an image sensor according to claim 17, wherein: The second channel region extends along the second direction, the fourth doping region includes a third sub-doping region and a fourth sub-doping region, the third sub-doping region is located below the first doping region and parallel to the substrate surface, and the fourth sub-doping region extends along the second direction and is electrically connected to the third sub-doping region.

19. The method for forming an image sensor according to claim 17, wherein: A second isolation structure is formed between the fourth sub-doping region and the fifth doping region, and the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure; a second pad is provided between the third sub-isolation structure and the fourth sub-isolation structure, the third sub-isolation structure extends from the top of the substrate to below the first doping region, and the fourth sub-isolation structure extends from the top of the substrate to the third sub-doping region; the depth of the third sub-isolation structure along the second direction is greater than the depth of the first doping region along the second direction and is less than the depth of the fourth sub-isolation structure along the second direction.

20. The method for forming an image sensor according to claim 17, wherein: A third isolation structure is further formed between the fifth doping region and the third doping region, and a depth of the third isolation structure is not less than a depth of the first channel region or the second channel.

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