Semiconductor device and memory system
By using a second electron capture material with a larger dielectric constant and higher trap density in the electron capture layer, the problem of poor maintenance characteristics of memory cells in the 3D NAND memory is solved, and programming speed and charge capture performance are improved.
Patent Information
- Application Number
- CN202310805000.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2024-12-31
AI Technical Summary
As the number of device stacking layers increases, the retention characteristics of memory cells become worse, limiting the performance improvement of 3D NAND memory.
The electron-trapping layer is added with a second electron-trapping material with a larger dielectric constant and a higher trap density to reduce the voltage division, improve programming speed, and enhance charge trapping and retention performance.
By increasing the dielectric constant and trap density of the electron trapping layer, the voltage division is reduced, the programming speed and charge trapping and retention performance of the semiconductor device are improved, and the charge loss is suppressed.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a memory system. Background Art
[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.
[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by stacking memory cells three-dimensionally on a substrate.
[0004] However, as the number of device stacking layers increases, the retention characteristics of memory cells have always been a problem that needs to be solved urgently. Summary of the invention
[0005] The present application provides a semiconductor device and a memory system, which can effectively solve the problem of deterioration of retention characteristics existing in the memory system in the related art.
[0006] In a first aspect, the present application provides a semiconductor device, comprising a first semiconductor structure, wherein the first semiconductor structure comprises: a gate stack structure; a channel structure located within the gate stack structure, wherein the channel structure comprises an electron capture layer; wherein the electron capture layer comprises a first electron capture material and a second electron capture material, wherein the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material.
[0007] In some embodiments, the conduction band energy level of the second electron capture material is less than the conduction band energy level of the first electron capture material.
[0008] In some embodiments, the electron capture layer includes at least one electron capture sublayer, and the electron capture sublayer is a mixture of the first electron capture material and the second electron capture material.
[0009] In some embodiments, the electron capture layer includes at least one first electron capture layer and at least one second electron capture layer, wherein the first electron capture layer includes the first electron capture material and does not include the second electron capture material; the second electron capture layer includes the second electron capture material and does not include the first electron capture material.
[0010] In some embodiments, the electron capture layer includes: a plurality of first electron capture layers, wherein a second electron capture layer is disposed between any two adjacent first electron capture layers.
[0011] In some embodiments, there are multiple second electron capture layers.
[0012] In some embodiments, the channel structure further includes: a channel layer, a tunneling layer and an electron blocking layer, wherein the channel layer, the tunneling layer, the electron capture layer and the electron blocking layer are arranged sequentially in a first direction, and the first direction is a radial direction from the center of the channel structure toward the outer surface of the channel structure; wherein the tunneling layer and the second electron capture layer are adjacently arranged on both sides of one of the first electron capture layers.
[0013] In some embodiments, the electron blocking layer is disposed adjacent to the second electron capturing layer.
[0014] In some embodiments, the channel structure further includes: a dielectric layer, the dielectric layer being disposed on a side of the electron blocking layer away from the electron capture layer, wherein the dielectric layer includes the second electron capture material.
[0015] In some embodiments, the second electron capture layer consists of the second electron capture material.
[0016] In some embodiments, the second electron capture layer includes a second electron capture material and a doping material.
[0017] In some embodiments, the first electron-capturing material comprises silicon nitride and the second electron-capturing material comprises hafnium dioxide.
[0018] In some embodiments, the semiconductor device further includes: a second semiconductor structure, wherein the first semiconductor structure is hybrid-bonded to the second semiconductor structure.
[0019] In a second aspect, the present application provides a memory system, the memory system comprising any one of the semiconductor devices described above; and a controller, the controller being configured to control the semiconductor device.
[0020] The present application provides a semiconductor device and a memory system, the semiconductor device includes a first semiconductor structure, the first semiconductor structure includes: a gate stack structure and a channel structure, the channel structure is located in the gate stack structure, the channel structure includes an electron capture layer, wherein the electron capture layer includes a first electron capture material and a second electron capture material, the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material. The semiconductor device and the memory system provided by the present application can reduce the partial pressure of the electron capture layer and improve the programming speed of the semiconductor device by adding a second electron capture material with a larger dielectric constant and a higher trap density to the electron capture layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0022] Figure 1 A schematic cross-sectional view of a semiconductor device provided for some embodiments of the present application.
[0023] Figure 2 A schematic cross-sectional view of an electron capture layer provided in some embodiments of the present application.
[0024] Figure 3 A module schematic diagram of a memory system provided for some embodiments of the present application.
[0025] Figure 4a Another schematic cross-sectional view of an electron capture layer provided in some embodiments of the present application.
[0026] Figure 4b Another schematic cross-sectional view of an electron capture layer provided in some embodiments of the present application.
[0027] Figure 4c Another cross-sectional schematic diagram of the electron capture layer provided in some embodiments of the present application.
[0028] Figure 5a A cross-sectional schematic diagram of a tunneling layer, an electron capture layer and an electron blocking layer in a channel structure provided in some embodiments of the present application.
[0029] Figure 5b Another cross-sectional schematic diagram of the tunneling layer, the electron capture layer and the electron blocking layer in the channel structure provided in some embodiments of the present application.
[0030] Figure 5c Another cross-sectional schematic diagram of the tunneling layer, the electron capture layer and the electron blocking layer in the channel structure provided in some embodiments of the present application.
[0031] Figure 6 A schematic cross-sectional view of a channel structure provided for some embodiments of the present application.
[0032] Reference numerals:
[0033] Semiconductor device 1; gate stack structure 10; gate insulating layer 11; gate conductive layer 12; gate dielectric layer 121; metal barrier layer 122; gate conductor layer 123; channel structure 20, 20'; channel layer 21; tunneling layer 22; electron capture layer 23, 23'; electron capture sublayer 230; first electron capture layer 231; second electron capture layer 232; electron blocking layer 24; dielectric layer 25; first electron capture material A1; second electron capture material A2; controller 2; memory system 3; first direction X; DETAILED DESCRIPTION
[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0035] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.
[0036] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0037] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.
[0038] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.
[0039] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0040] Figure 1 A schematic cross-sectional view of a semiconductor device provided in some embodiments of the present application; Figure 2 A schematic cross-sectional view of an electron capture layer provided in some embodiments of the present application. Figure 1 and Figure 2 As shown, in the first aspect, embodiment 1 of the present application provides a semiconductor device 1, wherein the semiconductor device 1 includes a first semiconductor structure, wherein the first semiconductor structure includes: a gate stack structure 10 and a channel structure 20, wherein the channel structure 20 is located within the gate stack structure 10, and the channel structure 20 includes an electron capture layer 23, wherein the electron capture layer 23 includes a first electron capture material A1 and a second electron capture material A2, wherein the dielectric constant of the second electron capture material A2 is greater than the dielectric constant of the first electron capture material A1, and the trap density of the second electron capture material A2 is greater than the trap density of the first electron capture material A1.
[0041] In the semiconductor device 1 provided in the present application, since the electron capture layer 23 includes two electron capture materials, and the dielectric constant of the second electron capture material A2 is greater than the dielectric constant of the first electron capture material A1, and the trap density of the second electron capture material A2 is greater than the trap density of the first electron capture material A1, the partial pressure of the electron capture layer 23 can be reduced and the programming speed of the semiconductor device 1 can be improved by adding the second electron capture material A2 with a larger dielectric constant and a higher trap density to the electron capture layer 23.
[0042] In some embodiments of the present application, the conduction band energy level of the second electron capture material A2 is smaller than the conduction band energy level of the first electron capture material A1.
[0043] In the semiconductor device 1 provided in the present application, since the electron capture layer 23 includes two electron capture materials, and the conduction band energy level of the second electron capture material A2 is lower than the conduction band energy level of the first electron capture material A1, the charge capture and retention performance of the electron capture layer 23 can be improved and the charge retention loss can be suppressed by adding the second electron capture material A2 with a lower conduction band energy level into the electron capture layer 23.
[0044] In some embodiments of the present application, the electron capture layer 23 includes at least one electron capture sublayer 230 , and the electron capture sublayer 230 is formed by mixing the first electron capture material A1 and the second electron capture material A2 .
[0045] In the semiconductor device 1 provided in the present application, since the second electron capture material A2 distributed in the electron capture sublayer 230 has a higher dielectric constant, a higher trap density and a lower conduction band energy level than the first electron capture material A1, it is possible to reduce the partial pressure of the electron capture layer 23, increase the programming speed of the semiconductor device 1, reduce the probability of electron tunneling, improve the charge capture and retention performance of the electron capture layer 23, and suppress the loss of retained charge.
[0046] In some embodiments of the present application, the first electron capture material A1 includes silicon nitride, and the second electron capture material A2 includes hafnium dioxide.
[0047] In some embodiments of the present application, the gate stack structure 10 includes a gate insulating layer 11 and a gate conductive layer 12 that are alternately stacked, wherein the gate insulating layer 11 may include a dielectric material, which includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination of the above, but is not limited thereto; the gate conductive layer 12 includes a gate dielectric layer 121, a metal barrier layer 122, and a gate conductor layer 123, wherein the material of the gate dielectric layer 121 includes, for example, titanium nitride (TiN); the material of the metal barrier layer 122 includes, for example, aluminum oxide (Al2O3); the material of the gate conductor layer 123 includes, for example, tungsten (W).
[0048] Continue to refer to Figure 1 In some embodiments of the present application, the channel structure 20 further includes: a channel layer 21, a tunneling layer 22 and an electron blocking layer 24, and the channel layer 21, the tunneling layer 22, the electron capture layer 23 and the electron blocking layer 24 are arranged in sequence in a first direction X, and the first direction X is a radial direction from the center of the channel structure 20 toward the outer surface of the channel structure 20.
[0049] In some embodiments of the present application, the semiconductor device 1 further includes: a second semiconductor structure, and the first semiconductor structure is connected to the second semiconductor structure by hybrid bonding.
[0050] In some embodiments of the present application, the second semiconductor structure includes a peripheral circuit device, and the semiconductor device includes, for example, a three-dimensional NAND flash memory device (NAND Flash memory device), and the first semiconductor structure and the second semiconductor structure constitute the three-dimensional NAND flash memory device.
[0051] Figure 3 This is a module diagram of the memory system 3 provided in the first embodiment of the present application. Figure 3 As shown, in a second aspect, the present application further provides a memory system 3 , wherein the memory system 3 comprises the semiconductor device 1 and a controller 2 as described above, and the controller 2 is configured to control the semiconductor device 1 .
[0052] The memory system 3 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. The controller 2 may be configured to control operations of the semiconductor device 1, such as read, erase, and program operations.
[0053] In some embodiments of the present application, the controller 2 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.
[0054] In some embodiments of the present application, the controller 2 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), where the SSD or eMMC is used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.
[0055] Figure 4a Another cross-sectional schematic diagram of an electron capture layer provided in some embodiments of the present application; Figure 4b Another cross-sectional schematic diagram of an electron capture layer provided in some embodiments of the present application; Figure 4c Another cross-sectional schematic diagram of an electron capture layer provided in some embodiments of the present application. Figure 1 , Figure 4a-4c As shown, in the first aspect, some embodiments of the present application provide a semiconductor device 1, wherein the semiconductor device 1 includes a first semiconductor structure, wherein the first semiconductor structure includes: a gate stack structure 10 and a channel structure 20, wherein the channel structure 20 is located within the gate stack structure 10, and the channel structure 20 includes an electron capture layer 23', wherein the electron capture layer 23' includes a first electron capture material and a second electron capture material, wherein the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material.
[0056] It should be noted that if Figure 4a-4c The structure of the semiconductor device 1 shown is similar to that of the semiconductor device 1 provided in some embodiments described above in the present application, and the same parts will not be described again.
[0057] The difference is that the electron capture layer 23' includes at least one first electron capture layer 231 and at least one second electron capture layer 232, wherein the first electron capture layer 231 includes the first electron capture material and does not include the second electron capture material; the second electron capture layer 232 includes the second electron capture material and does not include the first electron capture material.
[0058] In the semiconductor device 1 provided in the present application, since the first electron capture layer 231 includes the first electron capture material and does not include the second electron capture material; the second electron capture layer 232 includes the second electron capture material and does not include the first electron capture material, that is, the first electron capture material and the second electron capture material are independently arranged in different film layers, thereby further reducing the partial pressure of the electron capture layer 23', improving the programming speed of the semiconductor device 1, and improving the charge capture and retention performance of the electron capture layer 23', thereby suppressing the loss of retained charge.
[0059] Continue to refer to Figure 4a-4c In some embodiments of the present application, the electron capture layer 23 ′ includes: a plurality of first electron capture layers 231 , wherein a second electron capture layer 232 is disposed between any two adjacent first electron capture layers 231 .
[0060] In the semiconductor device 1 provided in the present application, since a second electron capture layer 232 is arranged between any two adjacent first electron capture layers 231, the second electron capture layer 232 can form a sandwich structure with the two adjacent first electron capture layers 231 on both sides thereof, thereby utilizing the characteristic that the conduction band energy level of the second electron capture material is smaller than the conduction band energy level of the first electron capture material to form an electron potential well between the two adjacent first electron capture layers 231, thereby further improving the charge capture and retention performance of the electron capture layer 23 and suppressing the loss of retained charge.
[0061] Continue to refer to Figure 4b and Figure 4c In some embodiments of the present application, the number of the second electron capture layer 232 is multiple.
[0062] In the semiconductor device 1 provided in the present application, since the number of the second electron capture layers 232 is multiple, the number of electron potential wells in the electron capture layer 23' can be increased, thereby further improving the charge capture and retention performance of the electron capture layer 23' and suppressing charge loss.
[0063] In some embodiments of the present application, the second electron capture layer 232 is composed of the second electron capture material.
[0064] In the semiconductor device 1 provided in the present application, since the second electron capture layer 232 is composed of the second electron capture material, that is, the second electron capture layer 232 only contains the second electron capture material, the trap density of the second electron capture layer 232 can be increased, thereby further reducing the partial pressure of the electron capture layer 23', and improving the programming speed of the semiconductor device 1.
[0065] In some embodiments of the present application, the second electrode capture layer includes a second electron capture material and a doping material.
[0066] In the semiconductor device 1 provided in the present application, since the second electron capture layer 232 includes a second electron capture material and a doping material, that is, the second electron capture layer 232 includes a doping material other than the second electron capture material, the crystallization difficulty of the second electron capture layer 232 can be increased, thereby improving the device retention performance.
[0067] Optionally, the second electron capture layer 232 includes a substrate and a doping material, the substrate includes the second electron capture material, the doping material is doped into the substrate, and the doping material includes at least one of zirconium, silicon, and aluminum.
[0068] Continue to refer to Figure 3 In a second aspect, the present application further provides a memory system 3 , wherein the memory system 3 comprises the semiconductor device 1 and a controller 2 as described above, and the controller 2 is configured to control the semiconductor device 1 .
[0069] Figure 5a A cross-sectional schematic diagram of a tunneling layer, an electron capture layer and an electron blocking layer in a channel structure provided in some embodiments of the present application; Figure 5b Another cross-sectional schematic diagram of a tunneling layer, an electron capture layer, and an electron blocking layer in a channel structure provided in some embodiments of the present application; Figure 5c Another cross-sectional schematic diagram of a tunneling layer, an electron capture layer, and an electron blocking layer in a channel structure provided in some embodiments of the present application. Figure 1 , Figure 5a-5c As shown, in the first aspect, some embodiments of the present application provide a semiconductor device 1, wherein the semiconductor device 1 includes a first semiconductor structure, wherein the first semiconductor structure includes: a gate stack structure 10 and a channel structure 20, wherein the channel structure 20 is located within the gate stack structure 10, and the channel structure 20 includes an electron capture layer 23', wherein the electron capture layer 23' includes a first electron capture material and a second electron capture material, wherein the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material.
[0070] It should be noted that Figure 5a-5c The structure of the semiconductor device 1 shown is similar to that of the semiconductor device 1 provided in some embodiments described above in the present application, and the same parts will not be repeated here.
[0071] The difference is that the channel structure 20 also includes: a channel layer 21, a tunneling layer 22 and an electron blocking layer 24, and the channel layer 21, the tunneling layer 22, the electron capture layer 23' and the electron blocking layer 24 are arranged in sequence in a first direction X, and the first direction X is a radial direction from the center of the channel structure 20 toward the outer surface of the channel structure 20; wherein the tunneling layer 22 and the second electron capture layer 232 are adjacently arranged on both sides of one of the first electron capture layers 231.
[0072] In the semiconductor device 1 provided in the present application, since the tunneling layer 22 and the second electron capture layer 232 are adjacently arranged on both sides of one of the first electron capture layers 231, that is, the tunneling layer 22 and the second electron capture layer 232 are not in direct contact, and the second electron capture layer 232 adjacent to the tunneling layer 22 is separated by the first electron capture layer 231, and since the conduction band energy level of the second electron capture material is lower than the conduction band energy level of the first electron capture material, therefore, in order for the electrons in the second electron capture layer 232 to be excited to the conduction band, it is necessary to overcome the obstruction of the first electron capture layer 231 with a higher conduction band energy level, which increases the difficulty of tunneling, thereby reducing the probability of electron tunneling, improving the charge capture and retention performance of the electron capture layer 23`, and suppressing the loss of retained charge.
[0073] Continue to refer to Figure 5a-5c In some embodiments of the present application, the electron blocking layer 24 is disposed adjacent to the second electron capture layer 232 .
[0074] In the semiconductor device 1 provided in the present application, the second electron capture layer 232 is arranged adjacent to the electron blocking layer 24, that is, the first electron capture layer 231 and the electron blocking layer 24 are separated by the second electron capture layer 232, so that the first electron capture material with a higher conduction band energy level and the electron blocking layer 24 are not in direct contact, which is beneficial to improving the charge capture and retention performance of the electron capture layer 23' and suppressing the loss of retained charge.
[0075] Continue to refer to Figure 3 In a second aspect, the present application further provides a memory system 3 , wherein the memory system 3 comprises the semiconductor device 1 and a controller 2 as described above, and the controller 2 is configured to control the semiconductor device 1 .
[0076] Figure 6 A cross-sectional schematic diagram of a channel structure provided in some embodiments of the present application. Figure 1-Figure 6As shown, in the first aspect, some embodiments of the present application provide a semiconductor device 1, wherein the semiconductor device 1 includes a first semiconductor structure, wherein the first semiconductor structure includes: a gate stack structure 10 and a channel structure 20', wherein the channel structure 20' is located within the gate stack structure 10, and the channel structure 20 includes an electron capture layer 23 (23'), wherein the electron capture layer 23 (23') includes a first electron capture material and a second electron capture material, wherein the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material.
[0077] It should be noted that if Figure 6 The structure of the semiconductor device 1 is similar to that of the semiconductor device 1 provided in the aforementioned embodiment of the present application, and the structure of the electron capture layer thereof may be the same, and the same parts will not be described in detail herein.
[0078] The difference is that the channel structure 20 ′ further includes: a dielectric layer 25 , and the dielectric layer 25 is arranged on a side of the electron blocking layer 24 away from the electron capture layer 23 ( 23 ′), wherein the dielectric layer 25 includes the second electron capture material.
[0079] In the semiconductor device 1 provided in the present application, since the dielectric layer 25 includes the second electron capture material, the blocking ability of the dielectric layer 25 can be improved, thereby improving the performance of the semiconductor device 1. Optionally, the dielectric layer 25 includes a high dielectric constant layer and the second electron capture material doped in the high dielectric constant layer, the high dielectric constant layer can be formed of aluminum oxide, and the dielectric constant of the second electron capture material is greater than the dielectric constant of the aluminum oxide in the high dielectric constant layer.
[0080] Continue to refer to Figure 3 In a second aspect, the present application further provides a memory system 3 , wherein the memory system 3 comprises the semiconductor device 1 and a controller 2 as described above, and the controller 2 is configured to control the semiconductor device 1 .
[0081] In summary, the present application provides a semiconductor device and a memory system, wherein the semiconductor device includes a first semiconductor structure, wherein the first semiconductor structure includes: a gate stack structure and a channel structure, wherein the channel structure is located within the gate stack structure, and wherein the channel structure includes an electron capture layer, wherein the electron capture layer includes a first electron capture material and a second electron capture material, wherein the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material. The semiconductor device and the memory system provided by the present application can reduce the partial pressure of the electron capture layer and improve the programming speed of the semiconductor device by adding a second electron capture material with a larger dielectric constant and a higher trap density to the electron capture layer.
[0082] The semiconductor device and its memory system provided by the embodiments of the present application are introduced in detail above. The principles and implementation methods of the present application are explained in this article using specific examples. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure comprises: Gate stack structure; A channel structure, located in the gate stack structure, the channel structure comprising an electron capture layer; The electron capture layer includes a first electron capture material and a second electron capture material, the dielectric constant of the second electron capture material is greater than the dielectric constant of the first electron capture material, and the trap density of the second electron capture material is greater than the trap density of the first electron capture material.
2. The semiconductor device according to claim 1, wherein: The conduction band energy level of the second electron capture material is smaller than the conduction band energy level of the first electron capture material.
3. The semiconductor device according to claim 2, characterized in that The electron capture layer includes at least one electron capture sublayer, and the electron capture sublayer is formed by mixing the first electron capture material and the second electron capture material.
4. The semiconductor device according to claim 2, characterized in that The electron capture layer comprises at least one first electron capture layer and at least one second electron capture layer, wherein The first electron capture layer includes the first electron capture material and does not include the second electron capture material; The second electron capture layer includes the second electron capture material and does not include the first electron capture material.
5. The semiconductor device according to claim 4, characterized in that The electron capture layer includes: a plurality of first electron capture layers, wherein a second electron capture layer is disposed between any two adjacent first electron capture layers.
6. The semiconductor device according to claim 5, characterized in that The number of the second electron capture layers is plural.
7. The semiconductor device according to claim 4, characterized in that The channel structure further includes: a channel layer, a tunneling layer and an electron blocking layer, wherein the channel layer, the tunneling layer, the electron capture layer and the electron blocking layer are sequentially arranged in a first direction, and the first direction is a radial direction from the center of the channel structure toward the outer surface of the channel structure; Wherein, the tunneling layer and the second electron capture layer are adjacently arranged on both sides of one of the first electron capture layers.
8. The semiconductor device according to claim 7, characterized in that The electron blocking layer is disposed adjacent to the second electron capturing layer.
9. The semiconductor device according to claim 7, characterized in that The channel structure further includes: a dielectric layer, which is disposed on a side of the electron blocking layer away from the electron capture layer, wherein the dielectric layer includes the second electron capture material.
10. The semiconductor device according to claim 4, characterized in that The second electron-trapping layer is composed of the second electron-trapping material.
11. The semiconductor device according to claim 4, characterized in that The second electron capture layer includes a second electron capture material and a doping material.
12. The semiconductor device according to claim 1, wherein: The first electron-capturing material includes silicon nitride, and the second electron-capturing material includes hafnium dioxide.
13. The semiconductor device according to any one of claims 1 to 12, characterized in that: The semiconductor device further includes: a second semiconductor structure, the first semiconductor structure and the second semiconductor structure are connected by hybrid bonding.
14. A memory system, characterized in that: include: The semiconductor device according to any one of claims 1 to 13; and A controller is configured to control the semiconductor device.