Multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing

Abstract

The invention relates to a multichannel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing. The interface circuit comprises a frequency modulator module, a first-stage integrator, a second-stage proportional integrator, a successive approximation quantizer, a dynamic weighted average unit and a current digital-to-analog converter. According to the direct digital conversion architecture of the interface circuit, a special physiological signal amplification circuit is omitted, and collected signals are directly converted into digital signals to be processed, so that the interface circuit has remarkable advantages in area and power consumption; in addition, the interface circuit integrates the advantages of a frequency division multiplexing technology and a direct digital conversion architecture, and an efficient and innovative solution is provided for a multi-channel physiological signal acquisition system.

Description

Technical Field

[0001] The present application relates to the technical field of analog integrated circuits, and in particular to a multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing. Background Art

[0002] Nowadays, people want to keep up to date with the latest health data, which has promoted the popularity of wearable devices such as smart bracelets and smart watches. These devices integrate a variety of sensors, which can monitor heart rate, blood pressure, sleep and other data in real time, and can be seamlessly connected with mobile phones and other devices to facilitate viewing and sharing of information. The development of semiconductor technology has enabled the integration of biosignal acquisition and processing systems on small chips, providing technical support for low-power, small-sized wearable devices. The bioelectric signal acquisition system mainly includes analog front-end, analog-to-digital converter, digital signal processing, wireless transmission and power management modules. Among them, the analog front-end and analog-to-digital converter are key interfaces that determine the overall performance of the system. As demand grows, ultra-low power multi-channel sensor interface circuits have become a future development trend.

[0003] In multi-channel design, the traditional "one-to-one" architecture is more common, but as the number of channels increases, power consumption and area increase sharply. Therefore, the "many-to-one" multiplexing circuit has gradually attracted attention. Common multiplexing structures such as Figure 1 As shown, (a) is voltage domain time division multiplexing, (b) is current domain time division multiplexing, (c) is voltage domain frequency division multiplexing, and (d) is current domain frequency division multiplexing. Voltage domain time division multiplexing uses N independent amplifiers and a multiplexer to select the signal input of different channels to share the analog-to-digital converter for processing. Although it is easy to integrate, as the number of channels N increases, the size of the multiplexer increases by N², and the driving power consumption also increases accordingly. Current domain time division multiplexing drives low impedance loads through variable gain transconductance amplifiers, alleviating the impact of load capacitance. However, as N increases, the time period allocated to each channel is shortened, resulting in incomplete or distorted signal processing, and it is impossible to sample multiple channels simultaneously. In contrast, frequency division multiplexing modulates the signal of each channel to different frequencies to achieve parallel signal processing. However, as N increases, in order to avoid noise folding and signal interference, it is necessary to increase the maximum carrier frequency, increase bandwidth requirements, and expand the -3 dB bandwidth of the amplifier. Voltage domain frequency division multiplexing usually uses a closed-loop instrumentation amplifier, whose feedback factor is inversely proportional to N, resulting in power consumption increasing with N². Current domain frequency division multiplexing replaces the closed-loop instrument amplifier with an open-loop transconductance unit, which greatly reduces the power consumption caused by the feedback current. The total power consumption of the system increases linearly with the number of channels, and the average power consumption of a single channel is relatively stable. This innovative design effectively solves the power consumption bottleneck in multi-channel multiplexing and provides a new solution for high-channel-count, low-power applications. However, the traditional analog front-end and analog-to-digital converter cascade architecture face challenges in achieving high dynamic range. Summary of the invention

[0004] Based on this, it is necessary to provide a multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing to address the above technical problems.

[0005] A multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing, the multi-channel direct digital conversion sensing interface circuit comprising: The frequency modulator module is used to modulate the N-channel low-frequency input signal into N non-overlapping high-frequency bands to generate N-channel high-frequency band signals; N is an integer greater than 0; and the high-frequency band signal is a voltage domain signal.

[0006] The first stage integrator is used to convert the received N-channel high-frequency band signal into a current domain signal, add the signals, subtract the addition result from the feedback current output by the current digital-to-analog converter, and then perform integration processing to obtain a first integration result.

[0007] The second-stage proportional integrator is used to perform integration and feedforward superposition processing on the first integration result to obtain a second integration result.

[0008] The successive approximation quantizer is used to sample the second integration result and generate a corresponding binary digital code.

[0009] The dynamic weighted average unit is used to convert the binary digital code into a thermometer code, and process the thermometer code through a round-robin control strategy to obtain a thermometer code after dynamic weighted average.

[0010] The current digital-to-analog converter is used to generate a corresponding feedback current according to the thermometer code after dynamic weighted averaging, and feed the feedback current back to the first-stage integrator.

[0011] In one embodiment, the frequency modulator module includes N frequency modulation units, each frequency modulation unit is used to modulate a low-frequency channel input signal through a square wave carrier, and the spectrum of each low-frequency channel input signal is up-converted to a preset range of N different high-frequency fundamental carrier frequencies and odd harmonic frequencies.

[0012] In one embodiment, the first stage integrator includes: N transconductance units, two common mode resistors, an operational amplifier and two integrating capacitors.

[0013] The positive ends of all transconductance units are connected to the first end of the first common-mode resistor, the second end of the first common-mode resistor is connected to the first end of the second common-mode resistor, the negative ends of all transconductance units are connected to the second end of the second common-mode resistor, the first end of the first common-mode resistor is connected to the positive input terminal of the operational amplifier, the second end of the second common-mode resistor is connected to the negative input terminal of the operational amplifier, the positive end of the operational amplifier is connected to one end of the first integrating capacitor, the other end of the first integrating capacitor is connected to the negative output terminal of the operational amplifier, the negative end of the operational amplifier is connected to one end of the second integrating capacitor, and the other end of the second integrating capacitor is connected to the positive output terminal of the operational amplifier.

[0014] The transconductance unit is used to convert the high-frequency band signal generated by the frequency modulator module into a current signal, and perform current superposition at the output node to achieve linear conversion from voltage to current.

[0015] In one embodiment, the second-stage proportional integrator includes: two integral resistors, two proportional resistors, a first operational amplifier, and two first integral capacitors.

[0016] One end of the first integrating resistor is connected to the first output end of the first-stage integrator, the other end of the first integrating resistor is connected to the positive input end of the first operational amplifier, one end of the first proportional resistor is connected to the positive input end of the first operational amplifier, the other end of the first proportional resistor is connected to one end of the first first integrating capacitor, and the other end of the first first integrating capacitor is connected to the negative output end of the first operational amplifier; one end of the second integrating resistor is connected to the second output end of the first-stage integrator, the other end of the second integrating resistor is connected to the negative input end of the first operational amplifier, one end of the second proportional resistor is connected to the negative input end of the first operational amplifier, the other end of the second proportional resistor is connected to one end of the second first integrating capacitor, and the other end of the second first integrating capacitor is connected to the positive output end of the first operational amplifier.

[0017] In one embodiment, the successive approximation quantizer is a three-bit quantizer controlled by asynchronous logic, which is used to sample the second integration result output by the second-stage proportional integrator, convert it into a three-bit binary digital code through successive approximation logic, and output the binary digital code.

[0018] In one embodiment, the dynamic weighted averaging unit includes: a binary code to thermometer code unit, a pointer register, and a barrel shifter.

[0019] The binary code to thermometer code unit is used to convert the binary digital code into a thermometer code.

[0020] A pointer register is used to record the first unused unit current unit each time through a pointer as a starting point for the next selection; The barrel shifter is used for shifting the thermometer code according to the starting point recorded by the pointer register and outputting the shifted code to the current digital-to-analog converter.

[0021] In one embodiment, a current digital-to-analog converter includes: a register, a low cross-point control circuit, and a digital-to-analog converter unit.

[0022] The register and the low cross point control circuit form a switch driving circuit, and the switch driving circuit is connected to the digital-to-analog converter unit; the digital-to-analog converter unit outputs a feedback current to the first-stage integrator.

[0023] In one embodiment, the digital-to-analog converter unit adopts a bipolar architecture.

[0024] The above-mentioned multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing includes: a frequency modulator module, a first-stage integrator, a second-stage proportional integrator, a successive approximation quantizer, a dynamic weighted average unit, and a current digital-to-analog converter. The direct digital conversion architecture of the interface circuit eliminates the need for a dedicated physiological signal amplification circuit and directly converts the collected signal into a digital signal for processing, thereby showing significant advantages in area and power consumption; in addition, the interface circuit combines the advantages of frequency division multiplexing technology and direct digital conversion architecture, providing an efficient and innovative solution for multi-channel physiological signal acquisition systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the existing multi-channel multiplexing circuit structure, wherein (a) is a schematic diagram of the voltage domain time division multiplexing circuit structure, (b) is a schematic diagram of the current domain time division multiplexing circuit structure, (c) is a schematic diagram of the voltage domain frequency division multiplexing circuit structure, and (d) is a schematic diagram of the current domain frequency division multiplexing circuit structure; Figure 2 A schematic diagram of a multi-channel direct digital conversion sensing interface circuit structure based on current domain frequency division multiplexing in one embodiment; Figure 3 is a schematic diagram of the structure of a first-stage integrator in another embodiment; Figure 4 A schematic diagram of the structure of a second-stage proportional integrator in another embodiment; Figure 5 A schematic diagram of a dynamic weighted average unit structure in another embodiment; Figure 6 FIG. 4 is a schematic diagram of the structure of a current digital-to-analog converter in another embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] In one embodiment, Figure 2 As shown, a multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing is provided, and the multi-channel direct digital conversion sensing interface circuit includes: The frequency modulator module 1 is used to modulate N-channel low-frequency input signals into N non-overlapping high-frequency bands to generate N-channel high-frequency band signals; N is an integer greater than 0; and the high-frequency band signals are voltage domain signals.

[0028] Specifically, the N-channel low-frequency input signal is composed of N channels of high-frequency carriers (f ch1 、f ch2、 …、f chN ) is moved to high frequency, and the high frequency carrier (f ch1 、f ch2 ,…,f chN ) are equally spaced, and f ch1 The higher harmonics are far away from f chN Among them, f ch1 、f ch2 、f chN They are the frequencies of the first, second, and Nth high-frequency carrier waves respectively.

[0029] The first stage integrator 2 is used to convert the received N-channel high-frequency band signal into a current domain signal, add it, subtract the addition result from the feedback current output by the current digital-to-analog converter, and then perform integration processing to obtain a first integration result.

[0030] Specifically, the first-stage integrator 2 converts the voltage domain signal into a current domain signal through the coordinated work of N transconductance units, two common-mode resistors, an operational amplifier and an integrating capacitor, and performs addition and integration processing.

[0031] The second-stage proportional integrator 3 is used to perform integration and feedforward superposition processing on the first integration result to obtain a second integration result.

[0032] Specifically, the second-stage proportional integrator 3 performs further integration and feedforward superposition processing on the output signal of the first-stage integrator 2 to optimize the signal quality.

[0033] The successive approximation quantizer 4 is used to sample the second integration result and generate a corresponding binary digital code.

[0034] Specifically, the successive approximation quantizer 4 is a three-bit quantizer controlled by asynchronous logic, which can convert the output result of the second-stage proportional integrator 3 into a three-bit binary digital code for output.

[0035] The dynamic weighted averaging unit 5 is used to convert the binary digital code into a thermometer code, and process the thermometer code through a round-robin control strategy to obtain a thermometer code after dynamic weighted averaging.

[0036] Specifically, the dynamic weighted averaging unit 5 receives these three-bit binary digital codes, converts them into seven-bit thermometer codes, and further processes them through a round-robin control strategy to control the digital-to-analog converter to reduce noise and distortion.

[0037] The current digital-to-analog converter 6 is used to generate a corresponding feedback current according to the thermometer code after dynamic weighted averaging, and feed the feedback current back to the first-stage integrator 2 .

[0038] Specifically, the current digital-to-analog converter 6 generates corresponding currents according to the thermometer code generated by the dynamic weighted average unit, and feeds back the currents to the output nodes of the transconductance unit in the first-stage integrator to form a closed-loop control.

[0039] The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing combines the advantages of frequency division multiplexing technology and direct digital conversion architecture, and proposes a Gm-C based continuous-time Delta-Sigma modulator composed of a first-stage integrator 2, a second-stage proportional integrator 3, a successive approximation quantizer 4, a dynamic weighted average unit 5 and a current digital-to-analog converter 6 as a core module, which provides an efficient and innovative solution for the multi-channel physiological signal acquisition system.

[0040] In the above-mentioned multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing, the interface circuit includes: a frequency modulator module, a first-stage integrator, a second-stage proportional integrator, a successive approximation quantizer, a dynamic weighted average unit and a current digital-to-analog converter. The direct digital conversion architecture of the interface circuit eliminates the need for a dedicated physiological signal amplification circuit and directly converts the collected signal into a digital signal for processing, thereby showing significant advantages in area and power consumption; in addition, the interface circuit combines the advantages of frequency division multiplexing technology and direct digital conversion architecture, providing an efficient and innovative solution for multi-channel physiological signal acquisition systems.

[0041] In one embodiment, the frequency modulator module 1 includes N frequency modulation units, each frequency modulation unit is used to modulate a low-frequency channel input signal through a square wave carrier, and the spectrum of each low-frequency channel input signal is up-converted to a preset range of N different high-frequency fundamental carrier frequencies and odd harmonic frequencies.

[0042] Specifically, the input signals of the N channels in the frequency modulator module 1 are modulated by square wave carriers. The spectrum of the low-frequency input signal of the N channels is up-converted to N different high-frequency fundamental carrier frequencies (f ch1 、f ch2 …f chN ) and odd harmonic frequencies. To ensure effective separation of the signal and harmonic components, the frequency of each channel needs to be carefully selected. In addition, a guard band needs to be added. To prevent interference between adjacent channels. In an N-channel frequency division multiplexing system, to ensure that the modulated signal frequency domain does not contain high-frequency interference, it is necessary to ensure that the high-order harmonic components are far away from the frequency of each channel. At the same time, to avoid signal overlap between adjacent channels, the channel spacing Need to be consistent.

[0043] In one embodiment, the circuit structure of the first stage integrator is as follows: Figure 3 As shown, the first stage integrator 2 includes: N transconductance units 21 , two common mode resistors 22 , an operational amplifier 23 and two integrating capacitors 24 .

[0044] The positive ends of all transconductance units 21 are connected to the first end of the first common-mode resistor 22, the second end of the first common-mode resistor 22 is connected to the first end of the second common-mode resistor 22, the negative ends of all transconductance units 21 are connected to the second end of the second common-mode resistor 22, the first end of the first common-mode resistor 22 is connected to the positive input end of the operational amplifier 23, the second end of the second common-mode resistor 22 is connected to the negative input end of the operational amplifier 23, the positive end of the operational amplifier 23 is connected to one end of the first integrating capacitor 24, the other end of the first integrating capacitor 24 is connected to the negative output end of the operational amplifier 23, the negative end of the operational amplifier 23 is connected to one end of the second integrating capacitor 24, and the other end of the second integrating capacitor 24 is connected to the positive output end of the operational amplifier 23.

[0045] The transconductance unit 21 is used to convert the high-frequency band signal generated by the frequency modulator module 1 into a current signal, and perform current superposition at the output node to achieve linear conversion from voltage to current.

[0046] Specifically, Figure 3As shown, the first-stage integrator 2 is composed of N transconductance units 21, two common-mode resistors 22, an operational amplifier 23 and an integrating capacitor 24. The transconductance unit 21 converts the input voltage signal modulated to a high frequency into a current signal and performs current superposition at the output node. In order to achieve efficient linear conversion from voltage to current, the transconductance unit 21 has a wide linear input range. In order to stabilize the common-mode voltage, the positive and negative output ends of the transconductance unit 21 are each connected to a common-mode resistor 22 to the common-mode level. At the same time, the introduction of the operational amplifier 23 improves the driving capability of the system and ensures the stable performance of the subsequent cascade circuit. Integration is achieved through the integrating capacitor 24.

[0047] The transconductance unit 21 converts the N-channel high-frequency band signal from the voltage domain to the current domain and performs current superposition at the output node. One end of the two common-mode resistors 22 is connected to the positive and negative output terminals respectively, and the other end is connected to the common-mode level to achieve the stability of the common-mode voltage. The current and signal are integrated through the integration capacitor 24, and the operational amplifier 23 ensures the stability of the output common mode.

[0048] Compared with voltage domain frequency division multiplexing technology, current domain frequency division multiplexing technology significantly reduces power consumption by using open-loop transconductance units instead of closed-loop instrument amplifiers. Although the total power consumption of the system increases linearly with the number of channels, the average power consumption of a single channel remains relatively stable. In addition, the direct digital conversion architecture eliminates the need for dedicated physiological signal amplification circuits and directly converts the collected signals into digital signals for processing, thus showing significant advantages in area and power consumption.

[0049] In one embodiment, the circuit structure of the second-stage proportional integrator is as follows: Figure 4 As shown, the second-stage proportional integrator 3 includes: two integrating resistors 31 , two proportional resistors 32 , a first operational amplifier 33 and two first integrating capacitors 34 .

[0050] One end of the first integrating resistor 31 is connected to the first output end of the first-stage integrator 2, the other end of the first integrating resistor 31 is connected to the positive input end of the first operational amplifier 33, one end of the first proportional resistor 32 is connected to the positive input end of the first operational amplifier 33, the other end of the first proportional resistor 32 is connected to one end of the first first integrating capacitor 34, and the other end of the first first integrating capacitor 34 is connected to the negative output end of the first operational amplifier 33; one end of the second integrating resistor 31 is connected to the second output end of the first-stage integrator 2, the other end of the second integrating resistor 31 is connected to the negative input end of the first operational amplifier 33, one end of the second proportional resistor 32 is connected to the negative input end of the first operational amplifier 33, the other end of the second proportional resistor 32 is connected to one end of the second first integrating capacitor 34, and the other end of the second first integrating capacitor 34 is connected to the positive output end of the first operational amplifier 33.

[0051] Specifically, Figure 4 As shown. The second-stage proportional integrator 3 includes: an integral resistor 31, a proportional resistor 32, a first operational amplifier 33, and a first integral capacitor 34 connected across the first operational amplifier 33. There are two signal paths in the second-stage proportional integrator 3, namely, an integral path and a proportional path. The proportional path is realized by connecting the integral capacitor 34 and the proportional resistor 32 in series. The unit gain bandwidth and DC gain of the first operational amplifier 33 affect the overall performance. The ratio of the proportional resistor 32 to the integral resistor 31 determines the forward proportional coefficient (feedforward coefficient), while the integral resistor 31 and the first integral capacitor 34 jointly determine the integral coefficient. The first operational amplifier 33 also ensures the stability of the input and output common modes. In order to reduce the change of the proportional coefficient, the mismatch between the proportional resistor 32 and the integral resistor 31 needs to be minimized, which can be achieved by selecting resistors of the same process and type.

[0052] In one embodiment, the successive approximation quantizer is a three-bit quantizer controlled by asynchronous logic, which is used to sample the second integration result output by the second-stage proportional integrator, convert it into a three-bit binary digital code through successive approximation logic, and output the binary digital code.

[0053] In one embodiment, the circuit structure of the dynamic weighted average unit is as follows: Figure 5 As shown, the dynamic weighted averaging unit 5 includes: a binary code to thermometer code unit 51 , a pointer register 52 and a barrel shifter 53 .

[0054] The binary code to thermometer code unit 51 is used to convert the binary digital code into a thermometer code.

[0055] The pointer register 52 is used to record the first unused unit current unit each time through a pointer as the starting point for the next selection. The barrel shifter 53 is used to shift the thermometer code according to the starting point recorded in the pointer register and output it to the current digital-to-analog converter.

[0056] Specifically, Figure 5 As shown. The dynamic weighted average unit 5 is composed of a binary code to thermometer code unit 51, a pointer register 52 (pointer register P[2:0]) and a barrel shifter 53, and generates a control signal S[6:0]. Under the operation of the dynamic weighted average unit 5, all the unit current units of the digital-to-analog converter are used in sequence. The algorithm records the first unused unit current unit each time through the pointer, and uses it as the starting point for the next selection, thereby effectively converting the noise and distortion generated by the mismatch of the current digital-to-analog converter 6 into a first-order high-pass noise error.

[0057] In one embodiment, the circuit structure of the current digital-to-analog converter 6 is as follows: Figure 6As shown, the current digital-to-analog converter 6 includes: a register 61 , a low cross point control circuit 62 and a digital-to-analog converter unit 63 .

[0058] The register 61 and the low cross point control circuit 62 form a switch driving circuit, and the switch driving circuit is connected to the digital-to-analog converter unit 63; the digital-to-analog converter unit 63 outputs a feedback current to the first-stage integrator.

[0059] In one embodiment, the DAC unit 63 adopts a bipolar architecture.

[0060] Specifically, Figure 6 As shown. The current digital-to-analog converter 6 is composed of a register 61, a low cross-point control circuit 62 and a digital-to-analog converter unit 63. The current digital-to-analog converter 6 is controlled by a seven-bit thermometer code. The register 61 and the low cross-point control circuit 62 form a switch drive circuit to generate a control switch signal, thereby controlling the output current of the seven digital-to-analog converter units 63, so as to avoid the two current sources being turned off at the same time when the cross-point voltage of the complementary control signal is Vctrl / 2 to generate a peak current, thereby affecting the dynamic performance. This design not only speeds up the high and low level switching speed of the signal, but also further alleviates the influence of the clock feedthrough effect by reducing the high level voltage. Since the feedback point is set at the output end of the transconductance unit 21, the four-channel signal is transmitted by current superposition, so the current digital-to-analog converter 6 is selected. The digital-to-analog converter unit 63 adopts a bipolar architecture, which can achieve the same output range with only half the total current compared to the unipolar type.

[0061] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing, characterized in that: The multi-channel direct digital conversion sensor interface circuit comprises: A frequency modulator module, used for modulating N-channel low-frequency input signals into N non-overlapping high-frequency bands to generate N-channel high-frequency band signals; N is an integer greater than 0; and the high-frequency band signals are voltage domain signals; The first stage integrator is used to convert the received N-channel high-frequency band signal into a current domain signal, add the signals, subtract the addition result from the feedback current output by the current digital-to-analog converter, and then perform integration processing to obtain a first integration result; A second-stage proportional integrator is used to perform integration and feedforward superposition processing on the first integration result to obtain a second integration result; A successive approximation quantizer, used for sampling the second integration result and generating a corresponding binary digital code; A dynamic weighted averaging unit, used to convert the binary digital code into a thermometer code, and process the thermometer code through a round-robin control strategy to obtain a thermometer code after dynamic weighted averaging; The current digital-to-analog converter is used to generate a corresponding feedback current according to the thermometer code after dynamic weighted averaging, and feed the feedback current back to the first-stage integrator.

2. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The frequency modulator module includes N frequency modulation units, each frequency modulation unit is used to modulate a low-frequency channel input signal through a square wave carrier, and the spectrum of each low-frequency channel input signal is up-converted to a preset range of N different high-frequency fundamental carrier frequencies and odd harmonic frequencies.

3. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The first-stage integrator includes: N transconductance units, two common-mode resistors, an operational amplifier, and two integrating capacitors; The positive ends of all transconductance units are connected to the first end of the first common-mode resistor, the second end of the first common-mode resistor is connected to the first end of the second common-mode resistor, the negative ends of all transconductance units are connected to the second end of the second common-mode resistor, the first end of the first common-mode resistor is connected to the positive input terminal of the operational amplifier, the second end of the second common-mode resistor is connected to the negative input terminal of the operational amplifier, the positive end of the operational amplifier is connected to one end of the first integrating capacitor, the other end of the first integrating capacitor is connected to the negative output terminal of the operational amplifier, the negative end of the operational amplifier is connected to one end of the second integrating capacitor, and the other end of the second integrating capacitor is connected to the positive output terminal of the operational amplifier; The transconductance unit is used to convert the high-frequency band signal generated by the frequency modulator module into a current signal, and perform current superposition at the output node to achieve linear conversion from voltage to current.

4. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The second-stage proportional integrator includes: two integral resistors, two proportional resistors, a first operational amplifier and two first integral capacitors; One end of the first integrating resistor is connected to the first output end of the first-stage integrator, the other end of the first integrating resistor is connected to the positive input end of the first operational amplifier, one end of the first proportional resistor is connected to the positive input end of the first operational amplifier, the other end of the first proportional resistor is connected to one end of the first first integrating capacitor, and the other end of the first first integrating capacitor is connected to the negative output end of the first operational amplifier; one end of the second integrating resistor is connected to the second output end of the first-stage integrator, the other end of the second integrating resistor is connected to the negative input end of the first operational amplifier, one end of the second proportional resistor is connected to the negative input end of the first operational amplifier, the other end of the second proportional resistor is connected to one end of the second first integrating capacitor, and the other end of the second first integrating capacitor is connected to the positive output end of the first operational amplifier.

5. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The successive approximation quantizer is a three-bit quantizer controlled by asynchronous logic, which is used to convert the second integration result output by the second-stage proportional integrator into a three-bit binary digital code through successive approximation logic after sampling, and output the binary digital code.

6. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The dynamic weighted average unit includes: a binary code to thermometer code unit, a pointer register and a barrel shifter; The binary code to thermometer code unit is used to convert the binary digital code into a thermometer code; The pointer register is used to record the first unused unit current unit each time through a pointer as the starting point for the next selection; The barrel shifter is used to shift the thermometer code according to the starting point recorded in the pointer register and output it to the current digital-to-analog converter.

7. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The current digital-to-analog converter comprises: a register, a low cross-point control circuit and a digital-to-analog converter unit; The register and the low cross point control circuit form a switch driving circuit, and the switch driving circuit is connected to the digital-to-analog converter unit; the digital-to-analog converter unit outputs a feedback current to the first-stage integrator.

8. The multi-channel direct digital conversion sensor interface circuit based on current domain frequency division multiplexing according to claim 7, characterized in that: The digital-to-analog converter unit adopts a bipolar architecture.

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