Control module, display device and electronic equipment

Abstract

The invention provides a control module, a display device and electronic equipment, and relates to the technical field of touch control. The control module comprises a controller; the controller comprises a read time sequence controller and a flash memory; the control module is provided with a time sequence circuit, and the time sequence circuit is used for providing a read time sequence for the read time sequence controller; the flash memory is used for working under the control of a read time sequence; the sequential circuit at least comprises an external crystal oscillator located outside the controller; and in at least partial working modes, the time sequence circuit determines a read time sequence according to a clock signal provided by the external crystal oscillator. The performance of the touch chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of touch technology, and in particular to a control module, a display device and an electronic device. Background Art

[0002] In touch technology, the transmitted data is integrated through the internal oscillator (OSC) and transmitted to the analog front end (AFE), and at the same time transmitted to the micro control unit (Micro Controller Unit, MCU) through timing division to read the firmware data in the flash memory to ensure the validity of the touch signal.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a control module, a display device and an electronic device to improve the performance of a touch chip.

[0005] According to a first aspect of the present disclosure, there is provided a control module, comprising a controller; the controller comprises a read timing controller and a flash memory;

[0006] The control module has a timing circuit, and the timing circuit is used to provide a read timing to the read timing controller; the flash memory is used to work under the control of the read timing;

[0007] The timing circuit includes at least an external crystal oscillator located outside the controller; in at least part of the working mode, the timing circuit determines the read timing according to the clock signal provided by the external crystal oscillator.

[0008] In one embodiment of the present disclosure, the sequential circuit includes a first clock unit and a second clock unit;

[0009] Wherein, the first clock unit comprises an internal oscillator located inside the controller;

[0010] The second clock unit includes the external crystal oscillator;

[0011] The accuracy of the clock signal provided by the external crystal oscillator is greater than the accuracy of the clock signal provided by the internal oscillator;

[0012] The timing circuit can determine the read timing according to one of the clock signal provided by the internal oscillator and the clock signal provided by the external crystal oscillator.

[0013] In one embodiment of the present disclosure, the first clock unit further includes a first read timing generation subunit, and the first read timing generation subunit is used to generate a first read timing according to a clock signal provided by the internal oscillator;

[0014] The second clock unit further includes a second read timing generation subunit, and the second read timing generation subunit is used to generate a second read timing according to the clock signal provided by the external crystal oscillator;

[0015] The control module also includes a gating unit;

[0016] In a first working mode, the gating unit sends the first read timing to the read timing controller;

[0017] In the second working mode, the gating unit sends the second read timing to the read timing controller.

[0018] In one implementation of the present disclosure, the second read timing generation subunit is located in the controller.

[0019] In one embodiment of the present disclosure, the read timing controller is configured to be able to issue a strobe signal;

[0020] The gating unit is used for determining whether to send the first read timing or the second read timing to the read timing controller according to a gating signal sent by the read timing controller.

[0021] In one embodiment of the present disclosure, the first clock unit is not provided in the controller;

[0022] The second clock unit further includes a second read timing generation subunit, and the second read timing generation subunit is used to generate a second read timing according to a clock signal provided by the external crystal oscillator.

[0023] In one embodiment of the present disclosure, the controller is one of a micro control unit, a touch control chip, and a touch display driver integrated chip.

[0024] In one embodiment of the present disclosure, the accuracy of the clock signal provided by the external crystal oscillator is ±10 PPM of the external crystal oscillator frequency.

[0025] According to a second aspect of the present disclosure, a display device is provided, comprising the above-mentioned control module.

[0026] According to a third aspect of the present disclosure, there is provided an electronic device, comprising the above-mentioned display device and an active pen;

[0027] The active pen is used to interact with the display device.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 FIG. 1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0031] Figure 2 FIG. 1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0032] Figure 3 The figure is a schematic diagram of signal interaction of a control module in the related art.

[0033] Figure 4 The present invention is a schematic diagram of signal interaction among an internal oscillator, a read timing production unit, a read timing controller, and a flash memory in the related art.

[0034] Figure 5 The figure is a schematic diagram of signal interaction in a control module in one embodiment of the present disclosure.

[0035] Figure 6 The figure is a schematic diagram of signal interaction in a control module in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0037] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0038] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0039] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as the structure layer A being formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, part of the structure layer A may also be located at the same physical height as the structure layer B or lower than the physical height of the structure layer B, wherein the substrate is a height reference.

[0040] The disclosed embodiment provides an electronic device, which includes a display device and an active pen. The display device may be a display device with a touch function, such as a mobile phone, a tablet computer, a laptop computer, a television, etc. The active pen is used to interact with the display device. For example, when the display device is a mobile phone, the active pen is used to touch the screen of the mobile phone so that the active pen shakes hands with the mobile phone to realize the touch function of the mobile phone. For another example, when the display device is a tablet computer, the active pen is used to touch the screen of the tablet computer so that the active pen shakes hands with the tablet computer to realize the touch function of the tablet computer.

[0041] Of course, the display device may be a display device that uses a human fingerprint to implement a touch function; in other words, the display device may implement a touch function without using an active pen.

[0042] In one embodiment of the present disclosure, the display device may include a display panel and a control module. Figure 1, the display panel includes a display area AA and a peripheral area BB located at least on one side of the display area AA. The display area AA of the display panel includes display units distributed in an array. The display unit includes a sub-pixel PIX and a pixel driving circuit PDC driving the sub-pixel PIX. Among them, the display panel has a plurality of scan lines GL arranged along the row direction DH in the display area AA, and each scan line GL is arranged in a one-to-one correspondence with each display unit row; the scan line GL is connected to each pixel driving circuit PDC of the corresponding display unit row. The display panel has a plurality of data lines DL arranged along the column direction DV in the display area AA, and each data line DL is arranged in a one-to-one correspondence with each display unit column; the data line DL is connected to each pixel driving circuit PDC of the corresponding display unit column. In this way, the pixel driving circuit PDC of each display unit is connected to one scan line GL and one data line DL. When the scan line GL is loaded with a selection signal, the data voltage loaded on the data line DL can be loaded to the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0043] Optionally, the sub-pixel PIX may be a current-driven self-luminous element, for example, any one of OLED, PLED, QLED, Micro LED, Mini LED and other light-emitting elements. In this embodiment, the sub-pixel PIX may include sub-pixels PIX of multiple different colors, for example, red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It is understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0044] In one embodiment of the present disclosure, see Figure 2 , the display panel may include a substrate BP, a driving layer DRL and a pixel layer PIXL stacked in sequence. The pixel layer PIXL is provided with sub-pixels PIX, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixels PIX; each sub-pixel PIX can emit light to display a picture under the drive of the pixel driving circuit PDC. Furthermore, the display panel also includes a thin film encapsulation layer TFE located on the side of the pixel layer PIXL away from the substrate BP, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0045] Optionally, the substrate BP may be a substrate of an inorganic material, or a substrate of an organic material; of course, it may also be a composite substrate formed by stacking a substrate of an inorganic material and a substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate BP may be a glass material such as soda-lime glass, quartz glass, or sapphire glass. In some other embodiments of the present disclosure, the material of the substrate BP may be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate BP may also be a flexible substrate, for example, the material of the substrate BP may include polyimide.

[0046] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT may be selected from a top gate thin film transistor, a bottom gate thin film transistor or a double gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0047] It is understandable that, among the transistors in the pixel driving circuit PDC, the types of any two transistors may be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit PDC, some transistors may be N-type transistors and some transistors may be P-type transistors. Again exemplarily, in other embodiments, in a pixel driving circuit PDC, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0048] Optionally, the driving layer DRL may include a semiconductor layer SCOL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate BP and the pixel layer PIXL. Each thin film transistor and storage capacitor may be located in a film layer such as the semiconductor layer SCOL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source-drain metal layer SD, etc. Among them, the positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCOL may be used to form the channel region of the transistor, and may also be formed into a partial wiring or conductive structure by conductorization when necessary. The gate layer GT may be used to form one or more of the gate layer GT wirings such as the write control wiring, the reset control wiring, and the light emitting control wiring, and may also be used to form the gate of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor. The source-drain metal layer SD may be used to form source-drain metal layer wirings such as data wirings and driving power supply voltage wirings, and may also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer located between the semiconductor layer SCOL and the substrate BP. As needed, any of the above-mentioned film layers such as the semiconductor layer SCOL, the gate layer GT, the source-drain metal layer SD, etc. may also be multilayered. For example, the driving layer DRL may include two different semiconductor layers SCOL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0049] Optionally, the driving layer DRL may further include a passivation layer. The passivation layer may be disposed on a surface of the source-drain metal layer SD away from the substrate BP so as to protect the source-drain metal layer SD.

[0050] As an example, see Figure 2 The driving layer DRL may include a buffer layer Buff, a semiconductor layer SCOL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD and a planarization layer PLN which are stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor.

[0051] In one embodiment of the present disclosure, the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional unit sandwiched between the two electrodes. Figure 2The pixel layer PIXL may include a light emitting element layer PEL, a light emitting function layer EFL and a common electrode layer COML which are stacked in sequence. The light emitting element layer PEL has a plurality of light emitting elements PE in the display area of ​​the display panel; the portion where the light emitting function layer EFL is connected to the light emitting element PE serves as a light emitting function unit of the sub-pixel PIX, and the common electrode layer COML serves as a common electrode and is electrically connected to the light emitting function units of each sub-pixel PIX.

[0052] Further, the pixel layer PIXL may also include a pixel definition layer PDL located between the light emitting element layer PEL and the light emitting function layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in one-to-one correspondence with the plurality of light emitting elements PE, and any one of the pixel openings exposes at least a portion of the corresponding light emitting element. For example, the pixel definition layer PDL covers the edge of the light emitting element PE and exposes at least a portion of the internal area of ​​the light emitting element PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the light emitting element PE (the area directly connected to the light emitting function unit), thereby defining the light emitting area and light emitting area of ​​the sub-pixel PIX. The light emitting function layer EFL at least covers the light emitting element PE exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light emitting function layer EFL in the display area. The light emitting element PE and the common electrode layer COML provide carriers such as electrons and holes to the light emitting function layer EFL, so that the light emitting function layer EFL emits light. The portion of the light emitting function layer EFL located between the light emitting element layer PEL and the common electrode layer COML may serve as a light emitting function unit. The light emitting element PE, the common electrode layer COML, and the light emitting functional unit form a sub-pixel PIX, wherein one of the light emitting element PE and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.

[0053] In an example, the light emitting element PE serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0054] It is understandable that the type of light-emitting element is different, and the material and film layer of the light-emitting functional unit are different. For example, when the light-emitting element is an OLED, the light-emitting functional unit may include an organic electroluminescent material layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer.

[0055] See also Figure 2, the thin film encapsulation layer TFE can be arranged on the surface of the pixel layer PIXL away from the substrate BP, which may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PIXL and causing aging of the material in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 stacked sequentially on the side of the pixel layer PIXL away from the substrate BP. The first inorganic encapsulation layer CVD1 covers the display area and extends to the outside of the retaining wall; the organic encapsulation layer covers the display area and extends to the inside of the retaining wall; the second inorganic encapsulation layer CVD2 covers the organic encapsulation layer IJP and extends to the outside of the retaining wall. Outside the retaining wall, the second inorganic encapsulation layer CVD2 contacts the first inorganic encapsulation layer CVD1. In this way, the organic encapsulation layer IJP is sealed by the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, balancing the stress of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 seal the organic encapsulation layer IJP, isolating the organic encapsulation layer IJP from contact with water and oxygen.

[0056] In some embodiments of the present disclosure, see Figure 2 The display panel may further include a touch function layer TSL. The touch function layer TSL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel has a touch function.

[0057] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor and a storage capacitor, and the gate of the driving transistor can be electrically connected to an electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the gate of the data writing transistor can be electrically connected to the scan line GL. The pixel driving circuit PDC is configured so that when the scan signal is loaded on the scan line GL, the data writing transistor is turned on, so that the driving voltage on the data line DL is written into the gate and storage capacitor of the driving transistor. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiment of the present disclosure can also include other transistors or capacitors so that the pixel driving circuit PDC has better driving performance. For example, the pixel driving circuit PDC can be a pixel driving circuit of 7T1C (7 thin film transistors and a storage capacitor), 8T1C (8 thin film transistors and a storage capacitor) or other architectures.

[0058] In the related art, see Figure 3 , the control module includes a touch chip TIC and a microcontroller unit MCU. The touch chip TIC may include an analog front end AFE, a power converter DC-DC, an analog-to-digital converter ADC, a power manager PMIC, a low voltage dropout stabilizer LDO, and a low voltage resetter BOR. The analog front end AFE is used to receive a first touch signal RX from the display panel, and to send a second touch signal TX to the display panel, and is also used to convert the first touch signal RX and the second touch signal TX into digital signals and send them to the microcontroller unit MCU. The power converter DC-DC is provided on the analog front end AFE, and is used to convert one DC signal into another DC signal. The analog-to-digital converter ADC is used to convert an analog voltage (for example) from a terminal AP (not shown in the drawings of the present disclosure) into a digital signal. Figure 3 The analog voltage of AVDD in the power supply (in one example, the voltage of AVDD is 3V) is converted into a digital voltage, and the converted digital voltage is sent to the micro control unit MCU. The power manager PMIC is used to receive the voltage from the terminal AP. The low voltage dropout stabilizer LDO is arranged on the power manager PMIC to stabilize the received voltage, and the low voltage dropout stabilizer LDO is used to provide the micro control unit MCU with an operating voltage. The low voltage resetter BOR is used to restart the micro control unit MCU to reset the micro control unit MCU.

[0059] See also Figure 3The microcontroller unit MCU includes an analog front-end control unit AFEC, a buffer Buffer, a processing core, an internal oscillator OSC, a flash memory FLASH, a static random access memory SRAM, a read timing controller TIMER, a debugging unit Debug, a serial interface I2C, a hardware accelerator HW Accel, a general interface GPIOS, and an interface configuration information unit IOCONFIG. Among them, the analog front-end control unit AFEC is used to process the digital signal provided by the analog front-end AFE and send the processed digital signal to the processing core. The buffer Buffer is used to amplify the digital signal from the analog front-end control unit AFEC and send the amplified digital signal to the processing core. The internal oscillator OSC is used to provide a clock signal. The flash memory FLASH is used to store and read firmware data. The static random access memory SRAM is used to store data. The read timing controller TIMER is used to control the flash memory FLASH to read firmware data. The interface configuration information unit IOCONFIG is used to receive a reset signal RESETB, an interrupt signal TINTX, a synchronization signal (including a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC), a data signal SDA, and an external clock signal SCL from the terminal AP. The debugging unit Debug is used to send the signal from the interface configuration information unit IOCONFIG to the processing core. The serial interface I2C is used to connect the processing core with the interface configuration information unit IOCONFIG so that the data signal SDA and the external clock signal SCL are sent to the processing core. The general interface GPIOS is used to connect the processing core with the interface configuration information unit IOCONFIG so that the interrupt signal TINTX, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC are sent to the processing core. The processing core is used to process the received signal. For example, the type of the processing core can be Cortex M3.

[0060] See also Figure 4 In the control module of the related technology, the clock signal generated by the internal oscillator OSC is sent to the read timing generation unit TU. The read timing generation unit TU generates a read timing with reference to the clock signal, and sends the read timing to the read timing controller TIMER. After receiving the read timing, the read timing controller TIMER controls the flash memory FLASH to read the firmware data to ensure the validity of the touch signal.

[0061] In the related art, when the clock signal generated by the internal oscillator OSC is sent to the read timing controller TIMER, it passes through multiple control circuits (such as RC circuits), which makes the impedance of the clock signal larger; on the one hand, RC delay (capacitor resistance delay) will be generated, and the transmission rate of the clock signal will be slower than other signals, which may cause insufficient data retention time and data sampling errors, thereby causing abnormal function of the flash memory FLASH. On the other hand, when the resistance of the clock signal is large, the rising and falling edge times of the clock signal input end are longer. If abnormal power supply jitter occurs, clock signal glitches may be generated inside the flash memory FLASH, causing abnormal function of the flash memory FLASH. Therefore, when the accuracy of the clock signal generated by the internal oscillator OSC is not calibrated or the accuracy is not high (for example, the accuracy of the internal oscillator OSC is 5%), there will be errors in reading the firmware data of the flash memory FLASH, causing the touch chip to fail.

[0062] It should be noted that the internal read logic of the flash memory FLASH is designed based on the clock signal. If there is a glitch in the clock signal, it will cause the internal logic of the flash memory FLASH to be abnormal, thereby causing the flash memory FLASH to output abnormally. As long as the input and output ports of other signals are used as data signal inputs and the signals are normal when sampling at the rising edge of the clock signal, there will be no problem. When used as data signal output, it will not affect the internal logic function of the flash memory FLASH.

[0063] In order to solve the above problems, in one embodiment of the present disclosure, see Figure 5 , the control module includes a controller CON. The controller CON includes a read timing controller TIMER and a flash memory FLASH. The control module has a timing circuit SC, the timing circuit SC is used to provide a read timing to the read timing controller TIMER; the flash memory FLASH is used to work under the control of the read timing. The timing circuit SC at least includes an external crystal oscillator CRY located outside the controller CON. In at least part of the working mode, the timing circuit SC determines the read timing according to the clock signal provided by the external crystal oscillator CRY.

[0064] In this way, after the timing circuit SC determines the read timing by the clock signal generated by the external crystal oscillator CRY, the determined read timing is sent to the read timing controller TIMER, and the read timing controller TIMER controls the flash memory FLASH to read the firmware data according to the received read timing. Since the external crystal oscillator CRY is located outside the controller CON, the accuracy of the clock signal provided by the external crystal oscillator CRY is higher than the accuracy of the clock signal provided by the internal oscillator OSC, thereby improving the accuracy of the read timing determined by the timing circuit SC, reducing the influence of the clock signal impedance, and helping to reduce the error of reading the flash memory FLASH firmware data, reducing the risk of failure of the touch chip, and improving the effectiveness of the touch function of the touch chip, thereby improving the reliability of the product.

[0065] In one embodiment of the present disclosure, the external crystal oscillator CRY can be arranged on a flexible circuit board or on a terminal AP, so as to realize the handshake function between the external crystal oscillator CRY and the active pen, thereby starting the alignment frequency.

[0066] In one embodiment of the present disclosure, see Figure 5 , the timing circuit SC includes a first clock unit CU1 and a second clock unit CU2. Among them, the first clock unit CU1 includes an internal oscillator OSC located inside the controller CON. The second clock unit CU2 includes the above-mentioned external crystal oscillator CRY. The accuracy of the clock signal provided by the external crystal oscillator CRY is greater than the accuracy of the clock signal provided by the internal oscillator OSC; the timing circuit SC can determine the read timing according to one of the clock signals provided by the internal oscillator OSC or the external crystal oscillator CRY. In this way, the clock signal is generated by the internal oscillator OSC and the external crystal oscillator CRY together, so that the control module is compatible with a new working mode on the original working mode, so as to improve the flexibility of the product and increase the versatility of the application scenario. For example, when the internal oscillator OSC fails, the external crystal oscillator CRY can be used to replace the internal oscillator OSC to generate the clock signal. For another example, when the external crystal oscillator CRY fails, the internal oscillator OSC can be used to replace the external crystal oscillator CRY to generate the clock signal. For another example, when both the internal oscillator OSC and the external crystal oscillator CRY are normal, one of the oscillators can be selected to provide a clock signal as required.

[0067] In one embodiment of the present disclosure, see Figure 5, the first clock unit CU1 also includes a first read timing generation subunit TU1, the first read timing generation subunit TU1 is used to generate a first read timing according to the clock signal provided by the internal oscillator OSC. The second clock unit CU2 also includes a second read timing generation subunit TU2, the second read timing generation subunit TU2 is used to generate a second read timing according to the clock signal provided by the external crystal oscillator CRY. The control module also includes a gating unit MUX. In the first working mode, the gating unit MUX sends the first read timing to the read timing controller TIMER. In the second working mode, the gating unit MUX sends the second read timing to the read timing controller TIMER. In an example, in the first working mode, the first read timing generation subunit TU1 generates the first read timing according to the clock signal generated by the internal oscillator OSC, and then sends the first read timing to the gating unit MUX. After receiving the first read timing, the gating unit MUX sends the first read timing to the read timing controller TIMER, and the read timing controller TIMER controls the flash memory FLASH to read firmware data according to the first read timing. In another example, in the second working mode, the second read timing generation subunit TU2 generates the second read timing according to the clock signal generated by the external crystal oscillator CRY, and then sends the second read timing to the gating unit MUX. After receiving the second read timing, the gating unit MUX sends the second read timing to the read timing controller TIMER, and the read timing controller TIMER controls the flash memory FLASH to read the firmware data according to the second read timing. In this way, if the accuracy requirement of the clock signal is low, the first working mode can be adopted, and the internal oscillator OSC, the first read timing generation subunit TU1, and the gating unit MUX work to provide the first read timing for the read timing controller TIMER; if the accuracy requirement of the clock signal is high, the second working mode can be adopted, and the external crystal oscillator CRY, the second read timing generation subunit TU2, and the gating unit MUX work to provide the second read timing for the read timing controller TIMER. On the one hand, since the accuracy of the clock signal generated by the external crystal oscillator CRY is higher than that of the clock signal generated by the internal oscillator OSC, correspondingly, the accuracy of the second read timing is higher than that of the first read timing, so that the read timing controller TIMER can more accurately control the flash memory FLASH to read the firmware data, so as to improve the accuracy of the read data and improve the effectiveness of the touch function. On the other hand, the first working mode and the second working mode can be switched through the selection unit MUX, so that the control module has two signal paths for generating clock signals, which improves the compatibility of the control module, so as to be applied to different working scenarios, and the timing circuit SC selects a working mode to reduce system power consumption.

[0068] It can be understood that in one embodiment of the present disclosure, the control module has two working modes, namely the first working mode and the second working mode. In the first working mode, the internal oscillator OSC, the first read timing generation subunit TU1, and the gating unit MUX work to provide the first read timing for the read timing controller TIMER. In the second working mode, the external crystal oscillator CRY, the second read timing generation subunit TU2, and the gating unit MUX work to provide the second read timing for the read timing controller TIMER. When it is necessary to use an active pen for touch control, the control module needs to work in the second working mode to realize the handshake between the active pen and the display device and realize the function of using the active pen for touch control.

[0069] In one embodiment of the present disclosure, see Figure 5 , the second read timing generation subunit TU2 and the gating unit MUX are located in the controller CON. The external crystal oscillator CRY is located outside the controller CON. In this way, the clock signal generated by the external crystal oscillator CRY is sent to the second read timing generation subunit TU2, and the second read timing generation subunit TU2 generates a second read timing according to the clock signal and sends it to the gating unit MUX.

[0070] In one embodiment of the present disclosure, see Figure 5 , the read timing controller TIMER is configured to be able to send a strobe signal. The strobe unit MUX is used to determine whether to send the first read timing or the second read timing to the read timing controller TIMER according to the strobe signal sent by the read timing controller TIMER. In one example, when the read timing controller TIMER sends a strobe signal to select the first working mode to the strobe unit MUX, the strobe unit MUX sends the first read timing to the read timing controller TIMER. In another example, when the read timing controller TIMER sends a strobe signal to select the second working mode to the strobe unit MUX, the strobe unit MUX sends the second read timing to the read timing controller TIMER. In other words, the read timing controller TIMER controls the strobe unit MUX to send the first read timing or the second read timing to the read timing controller TIMER through the strobe signal. In this way, the read timing controller TIMER can control the strobe unit MUX to switch between the first working mode and the second working mode through the strobe signal.

[0071] In one embodiment of the present disclosure, see Figure 6, the first clock unit CU1 is not set in the controller CON. The second clock unit CU2 also includes a second read timing generation subunit TU2, and the second read timing generation subunit TU2 is used to generate a second read timing according to the clock signal provided by the external crystal oscillator CRY. In other words, the control module only sets the second clock unit CU2 to provide the second read timing for the read timing controller TIMER, and does not provide the first read timing. In this way, only the second clock unit CU2 is used to provide the second read timing for the read timing controller TIMER to improve the accuracy of the read timing provided to the read timing controller TIMER.

[0072] In one embodiment of the present disclosure, the controller CON is any one of a microcontroller unit MCU, a touch chip TIC, and a touch display driver integrated chip TDDI. In one example, the controller CON is a microcontroller unit MCU, and the control module needs to be additionally configured with a touch chip TIC to provide a touch signal for the microcontroller unit MCU. In another example, the controller CON is a touch chip TIC, so that the microcontroller unit MCU is integrated on the touch chip TIC. In other examples, the controller CON is a touch display driver integrated chip TDDI, so that the touch chip TIC, the microcontroller unit MCU, and the display driver are integrated into one.

[0073] In one embodiment of the present disclosure, the accuracy of the clock signal provided by the external crystal oscillator CRY is the external crystal oscillator frequency ±10PPM. In one example, the accuracy of the clock signal provided by the external crystal oscillator CRY is the external crystal oscillator frequency +10PPM. In another example, the accuracy of the clock signal provided by the external crystal oscillator CRY is the external crystal oscillator frequency -10PPM. In this way, the accuracy of the clock signal is improved from the internal oscillator frequency +5% to the external crystal oscillator frequency ±10PPM, so that the flash memory FLASH can read the firmware data more accurately, reduce the risk of failure of the touch chip, improve the effectiveness of the touch function of the touch chip, and thus improve the reliability of the product.

[0074] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A control module, characterized in that: A controller is included; the controller includes a read timing controller and a flash memory; The control module has a timing circuit, and the timing circuit is used to provide a read timing to the read timing controller; The flash memory is used to work under the control of read timing; The timing circuit includes at least an external crystal oscillator located outside the controller; in at least part of the working mode, the timing circuit determines the read timing according to the clock signal provided by the external crystal oscillator.

2. The control module according to claim 1, characterized in that: The sequential circuit comprises a first clock unit and a second clock unit; Wherein, the first clock unit comprises an internal oscillator located inside the controller; The second clock unit includes the external crystal oscillator; The accuracy of the clock signal provided by the external crystal oscillator is greater than the accuracy of the clock signal provided by the internal oscillator; The timing circuit can determine the read timing according to one of the clock signal provided by the internal oscillator and the clock signal provided by the external crystal oscillator.

3. The control module according to claim 2, characterized in that: The first clock unit further comprises a first read timing generation subunit, the first read timing generation subunit being used to generate a first read timing according to a clock signal provided by the internal oscillator; The second clock unit further includes a second read timing generation subunit, and the second read timing generation subunit is used to generate a second read timing according to the clock signal provided by the external crystal oscillator; The control module also includes a gating unit; In a first working mode, the gating unit sends the first read timing to the read timing controller; In the second working mode, the gating unit sends the second read timing to the read timing controller.

4. The control module according to claim 3, characterized in that: The second read timing generation subunit is located in the controller.

5. The control module according to claim 3, characterized in that: The read timing controller is configured to be able to issue a strobe signal; The gating unit is used for determining whether to send the first read timing or the second read timing to the read timing controller according to a gating signal sent by the read timing controller.

6. The control module according to claim 2, characterized in that: The first clock unit is not provided in the controller; The second clock unit further includes a second read timing generation subunit, and the second read timing generation subunit is used to generate a second read timing according to a clock signal provided by the external crystal oscillator.

7. The control module according to claim 1, characterized in that: The controller is one of a micro control unit, a touch chip, and a touch display driver integrated chip.

8. The control module according to any one of claims 1 to 7, characterized in that: The accuracy of the clock signal provided by the external crystal oscillator is ±10PPM of the external crystal oscillator frequency.

9. A display device, comprising the control module according to any one of claims 1 to 8.

10. An electronic device comprising the display device according to claim 9 and an active pen; The active pen is used to interact with the display device.

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