Method and system for online upgrading of configuration data of ARINC818 digital video card

Abstract

The present invention provides a method and system for online upgrading of configuration data of an ARINC818 digital video card, the system comprising an airborne mission machine and an ARINC818 digital video card, wherein the ARINC818 digital video card comprises an FPGA, a DDR and a FLASH. The FPGA comprises an 818 interface IP core. The airborne mission machine divides the configuration file into data blocks of a predetermined size, and assembles each data block into an FC-based 818 data frame and sends it to the FPGA via an optical fiber line; the FPGA receives the 818 data frame via the 818 interface IP core, and realizes the ARINC818 optical fiber data communication between the airborne mission machine and the FPGA of the ARINC818 video card; the FPGA is configured with an embedded soft core module, which is used to read the received 818 data frame from the FPGA, and after extracting the configuration file information therefrom, realizes the read and write operation of the FLASH through the SPI interface, and completes the online upgrade function.

Description

Technical Field

[0001] The present invention relates to the technical field of airborne data communication, and is applicable to configuration file upgrade of an airborne 818 video card, and in particular to a configuration data online upgrade method and system for an ARINC818 digital video card. Background Art

[0002] Currently, a common problem faced by airborne equipment is the sealing of the debugging interface. If you want to upgrade the software of the airborne equipment, you need to open the sealed cover of the equipment, connect the serial port or network port cable to upgrade the configuration file of the ARINC818 digital video card. The upgrade process is complicated and inconvenient to operate. Summary of the invention

[0003] In view of the problem of online upgrade of airborne ARINC818 digital video card in the prior art, the purpose of the present invention is to propose an online upgrade method of configuration file based on 818 video frame data stream transmission, by cutting the configuration file and assembling it into 818 data frames based on FC fiber channel, and transmitting it to ARINC818 digital video card through optical fiber in the form of video data stream by airborne mission machine, parsing the video frame and performing online upgrade processing of configuration file through FPGA in ARINC818 digital video card, so as to solve the problem of prior upgrade of software version of airborne ARINC818 digital video card.

[0004] According to a first aspect of the present invention, a configuration data online upgrade system for an ARINC818 digital video card is provided, comprising an airborne mission machine and an ARINC818 digital video card, wherein the ARINC818 digital video card comprises an FPGA, a DDR and a FLASH;

[0005] The FPGA includes an 818 interface IP core, and the airborne mission machine is connected to the ARINC818 video card via an optical fiber line; the airborne mission machine divides the configuration file into data blocks of a predetermined size, and assembles each data block into an FC-based 818 data frame and sends it to the FPGA via the optical fiber line;

[0006] The FPGA receives FC-based 818 data frames via the 818 interface IP core to implement ARINC818 optical fiber data communication between the airborne mission machine and the FPGA of the ARINC818 video card;

[0007] The FPGA is configured with an embedded soft core module, which is used to read the received 818 data frame from the FPGA, extract the configuration file information therefrom, and then implement the read and write operations on the FLASH through the SPI interface to complete the upgrade function.

[0008] According to a second aspect of the present invention, a method for online upgrading of configuration data of an ARINC818 digital video card based on the aforementioned online upgrading system for configuration data of an ARINC818 digital video card is also provided, comprising the following steps:

[0009] Step 1: The onboard mission machine divides the configuration file to be upgraded into data blocks of fixed size, and puts each data block into the Payload field of the FC-based 818 data frame, adds the frame header, frame footer and CRC check field, assembles them into FC-based 818 data frames, and then sends them to the FPGA via the optical fiber line;

[0010] Step 2: After receiving and parsing the FC-based 818 data frame via the 818 interface IP core, the FPGA removes the frame header and frame tail, removes the Payload field data, stores it, and then notifies the embedded soft core module to perform reading processing;

[0011] Step 3, the embedded soft core module reads the frame data and the Payload field from the dual-port BRAM of the FPGA through the AXI bus, performs a reception check, and sends a data notification to the FPGA to notify the FPGA to retransmit the current data frame when the reception check fails; if the check passes, the data block of the Payload field is stored in the DDR;

[0012] Step 4: The embedded soft core module performs erasing, writing, and writing verification processing on the FLASH through the SPI interface, writes each fixed-size data block into the FLASH, and completes the update of the configuration file stored in the FLASH.

[0013] As an optional embodiment, in step 4, updating the configuration file stored in FLASH includes:

[0014] (1) The airborne mission machine sends FC-based 818 data frames in parallel, and the embedded soft core module synchronously implements reception verification and FLASH erasing, writing, and writing verification processing in the FPGA of the receiving end, and updates the configuration file stored in the FLASH; or

[0015] (2) In the FPGA at the receiving end, the embedded soft core module reorganizes all received data blocks according to the total number of frames, and then performs space erasing, writing, and writing verification processing on the FLASH through the SPI bus to update the configuration file stored in the FLASH.

[0016] It should be understood that all combinations of the aforementioned concepts and the additional concepts described in more detail below can be considered as part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of the claimed subject matter are considered as part of the inventive subject matter of the present disclosure.

[0017] The foregoing and other aspects, embodiments and features of the present invention can be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the present invention, such as the features and / or beneficial effects of the exemplary embodiments, will be apparent from the following description or learned from the practice of the specific embodiments according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are not intended to be drawn to scale. In the accompanying drawings, each identical or nearly identical component shown in each figure may be represented by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the present invention will now be described by way of example and with reference to the accompanying drawings.

[0019] Figure 1 4 is a schematic diagram of an online configuration data upgrade system for an ARINC818 digital video card according to an embodiment of the present invention.

[0020] Figure 2 The present invention is a flowchart of an online configuration data upgrade system for an ARINC818 digital video card according to an embodiment of the present invention for updating a FLASH configuration file in a digital video card.

[0021] Figure 3 4 is a schematic diagram of a frame structure of an FC-based ARINC818 data frame according to an embodiment of the present invention.

[0022] Figure 4 It is a schematic diagram of the sending process of the ARINC818 data frame according to an embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram of the receiving process of the ARINC818 data frame according to an embodiment of the present invention.

[0024] Figure 6 It is a schematic diagram of a data processing flow according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0026] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed by the present invention are not limited to any implementation. In addition, some aspects disclosed by the present invention can be used alone or in any appropriate combination with other aspects disclosed by the present invention.

[0027] {Example 1}

[0028] Combination Figure 1 to Figure 6 As shown, the configuration data online upgrade system for the ARINC818 digital video card according to an embodiment of the present invention includes an airborne mission machine and an ARINC818 digital video card, and the ARINC818 digital video card includes FPGA, DDR and FLASH.

[0029] Combination Figure 1 As shown, the FPGA includes 818 interface IP cores.

[0030] Combination Figure 1 The onboard mission machine is connected to the ARINC818 video card via an optical fiber line. The onboard mission machine divides the configuration file into data blocks of a predetermined size, and assembles each data block into an FC-based 818 data frame and sends it to the FPGA via the optical fiber line.

[0031] The FPGA receives the FC-based 818 data frame via the 818 interface IP core, realizing ARINC818 optical fiber data communication between the airborne mission machine and the FPGA of the ARINC818 video card.

[0032] The FPGA is configured with an embedded soft core module, which is used to read the received 818 data frame from the FPGA, extract the configuration file information from it, and then realize the read and write operations of the FLASH through the SPI interface to complete the upgrade function.

[0033] As an optional implementation, the airborne mission machine divides the configuration file into multiple data blocks according to a fixed size, and stores each data block as upgrade file data in the FC-based 818 data frame using the Payload field. The 818 stream data consisting of the FC-based 818 data frames is sent to the ARINC818 digital video card through the optical fiber line, where the complete 818 stream data constitutes an FC optical fiber communication sequence, which is composed of multiple consecutive FC-based 818 data frames.

[0034] As an optional implementation, after receiving the FC-based 818 data frame, the FPGA parses the frame data and the Payload field through the 818 interface IP core, stores the frame data and the Payload field in the FPGA's dual-port BRAM, and notifies the embedded soft core module to perform read processing.

[0035] As an optional implementation, the embedded soft core module reads the frame data and the Payload field from the dual-port BRAM of the FPGA through the AXI bus, performs a reception check, and sends a notification to the FPGA when the reception check fails, informing the FPGA to retransmit the current data frame.

[0036] As an optional implementation, the frame data and Payload field read from the dual-port BRAM of the FPGA at least include the following field information: frame header, current frame number, total number of frames, data area, data check and frame tail.

[0037] As an optional implementation, the embedded soft core module performs erasing, writing, and writing verification processing on the FLASH through the SPI interface, writes each fixed-size data block into the FLASH, and completes the update of the configuration file stored in the FLASH.

[0038] As an optional implementation, the airborne mission machine sends FC-based 818 data frames in parallel, and the embedded soft-core module in the FPGA at the receiving end synchronously implements reception verification and FLASH erasure, writing, and write verification processing to update the configuration file stored in the FLASH.

[0039] As an optional implementation, in the FPGA of the receiving end, the embedded soft core module reorganizes all received data blocks according to the total number of frames, and then erases, writes, and verifies the FLASH space through the SPI bus to update the configuration file stored in the FLASH.

[0040] Combination Figure 1 , Figure 4 , Figure 5 , Figure 6 As shown, in combination with the above embodiment of the online upgrade system design for the configuration data of the ARINC818 digital video card, the online upgrade method of the configuration data of the ARINC818 digital video card implemented by the system includes the following process:

[0041] Step 1: The onboard mission machine divides the configuration file to be upgraded into data blocks of fixed size, and puts each data block into the Payload field of the FC-based 818 data frame, adds the frame header, frame footer and CRC check field, assembles them into FC-based 818 data frames, and then sends them to the FPGA via the optical fiber line;

[0042] Step 2: After receiving and parsing the FC-based 818 data frame via the 818 interface IP core, the FPGA removes the frame header and frame tail, removes the Payload field data, stores it, and then notifies the embedded soft core module to read and process it;

[0043] Step 3: After the embedded soft core module reads the frame data and the Payload field from the dual-port BRAM of the FPGA through the AXI bus, it performs a reception check and sends a data notification to the FPGA to notify the FPGA to retransmit the current data frame if the reception check fails. If the check passes, the data block of the Payload field is stored in the DDR.

[0044] Step 4: The embedded soft core module performs erasing, writing, and writing verification processing on the FLASH through the SPI interface, writes each fixed-size data block into the FLASH, and completes the update of the configuration file stored in the FLASH.

[0045] Furthermore, in step 4, updating the configuration file stored in FLASH includes:

[0046] (1) The airborne mission machine sends FC-based 818 data frames in parallel, and the embedded soft core module in the FPGA at the receiving end synchronously implements the reception verification and the erasing, writing, and writing verification processing of the FLASH, and updates the configuration file stored in the FLASH; or

[0047] (2) In the FPGA at the receiving end, the embedded soft core module reorganizes all received data blocks according to the total number of frames, and then performs space erasing, writing, and writing verification on the FLASH through the SPI bus to update the configuration file stored in the FLASH.

[0048] {Example 2}

[0049] In this embodiment, we further elaborate and illustrate the implementation of the above-mentioned configuration data online upgrade system for ARINC818 digital video card in conjunction with the accompanying drawings.

[0050] Combination Figure 1 ,In this example, the entire ARINC818 digital video card configuration file online ,upgrade system is composed of the ARINC818 video card and the airborne mission machine.

[0051] ARINC818 video card includes FPGA, DDR, and FLASH.

[0052] The FPGA includes an 818 interface IP core, an embedded soft core module and a dual-port BRAM. The airborne mission machine is connected to the ARINC818 video card via an optical fiber line to achieve ARINC818 optical fiber data communication between the airborne mission machine and the ARINC818 video card.

[0053] As an example, the embedded soft core module uses a MicroBlaze soft core, hereinafter referred to as the soft core for simplicity of description.

[0054] In the embodiment of the present invention, the soft core includes an FPGA-specific embedded MicroBlaze soft core processor launched by Xilinx and peripheral modules, such as AXI bus, Clock, MDM, LocalMemory, AXI Interrupt Controller, etc.

[0055] The MicroBlaze embedded soft core is a reduced instruction set processor optimized for FPGA provided by Xilinx. It has the advantages of fast running speed, small resource occupation and strong configurability.

[0056] AXI bus, as an interactive XI bus, the soft core reads and writes data to different offset addresses of the AXI bus to complete reading and writing driver registers, reading and writing logic registers, sending data, and receiving data.

[0057] Clock: Provides working clock.

[0058] MDM: Debug module, which can display the soft core serial port print information.

[0059] LocalMemory: This module is the memory resource provided by the logic to the soft core.

[0060] AXI Interrupt Controller (INTC): This module is used to receive the interrupt signal generated by the timer, convert it into an interrupt interface and send it to the soft core.

[0061] The 818 data transmission function is realized through the 818 interface IP core of FPGA, and the soft core realizes the reading and writing of FLASH device through the SPI interface to complete the upgrade function.

[0062] Figure 1 In the example shown, three ARINC818 digital video cards are taken as an example, and we only exemplarily show the internal design structure of one of them.

[0063] Combination Figure 1 , Figure 2As shown, the debugging machine sends the configuration file to be upgraded to the airborne mission machine through the network port. The airborne mission machine selects the ARINC818 digital video card and sends the ARINC818 streaming data to the FPGA board through the optical fiber. Figure 3 The figure shows the format of the ARINC818 data frame. The ARINC818 stream data uses a container to transmit a data frame (ie, a video frame), and each frame of video is defined as a container. In the example of the present invention, the Payload field ADVB container is used to store the file data to be upgraded.

[0064] It should be understood that a complete ARINC 818 container is mapped to a single FC sequence, consisting of multiple consecutive FC frames, each with a maximum payload of 2112 bytes.

[0065] After receiving the video frame via its 818 interface IP core, the FPGA parses the frame data and the Payload field, stores the frame data and the Payload field in the FPGA's dual-port BRAM, and notifies the embedded soft core module to read and process, for example, notifying the soft core to fetch data through an interrupt.

[0066] After receiving the interrupt, the soft core reads the frame data and the Payload field from the dual-port BRAM of the FPGA through the AXI bus, performs a reception check, and sends a notification to the FPGA when the reception check fails, requesting the FPGA to retransmit the current data frame.

[0067] As an optional embodiment, a data verification module is set in the soft core to verify the data read from the FPGA, including frame header and frame tail checks and frame data verification; when the CRC check fails, the sending module will be called to notify the FPGA to retransmit the current data frame.

[0068] The data frame consisting of frame data and Payload field is read from the dual-port BRAM of FPGA. The format includes: 2 bytes for frame header (starting with 0x7e7e), 2 bytes for frame tail (ending with 0x0d0d), 2 bytes for current frame number, 2 bytes for total number of frames, 1 byte for CRC check, and 1024 bytes for data area. The data receiving frame is 1033 bytes in total.

[0069] As shown in the accompanying drawings, the soft core is provided with a data sending module, a data receiving module and a data processing module.

[0070] The data sending module is used to send a message to the FPGA to request it to retransmit the current frame when a data frame data check error occurs; and print out the received frame data through the MDM serial port for debugging.

[0071] The data receiving module is used to fetch data from the BRAM in the FPGA through the AXI bus after receiving an interrupt. After fetching the data from the BRAM, it is put into the memory, and the interrupt of the interrupt controller is cleared, waiting for the next notification to fetch data.

[0072] The data processing module is used to fetch data from DDR and drive the erasing, writing and writing verification of FLASH through the SPI bus between the soft core and FLASH, so as to realize the prior upgrade of the configuration file stored in FLASH.

[0073] Combination Figure 4 As shown, the data sending process includes:

[0074] Step 1: The configuration file to be upgraded is sent to the onboard mission machine through the network, and the onboard mission machine stores it in the memory after receiving it;

[0075] Step 2: The onboard task machine starts the sending task, cuts the file into fixed-size data blocks (for example, 1KB), and finally sends the data blocks that are less than 1KB according to their actual size;

[0076] Step 3: The airborne mission machine sending module puts the cut data into the Payload field of the ARINC 818 frame, adds the frame header, frame footer, and CRC check field, and assembles them into FC-based ARINC 818 frames;

[0077] Step 4: After receiving the ARINC 818 frame, the 818 IP core in the ARINC818 video card 1 splits the frame data, removes the frame header and frame tail, extracts the Payload field data, and notifies the soft core to obtain the data;

[0078] Step 5: After receiving the data, the soft core will verify the data. If the verification fails, the 818 IP core will be notified that the current frame needs to be retransmitted.

[0079] Combination Figure 5 As shown, the data receiving process includes:

[0080] Step 1: Enable interrupts in the soft core and wait for interrupts to be triggered;

[0081] Step 2: The FPGA module in the video card 1 notifies the soft core to fetch data through an interrupt;

[0082] Step 3: After receiving the interrupt, the soft core goes to the BRAM in the FPGA module to fetch data through the AXI bus;

[0083] Step 4: After taking the data from BRAM, perform verification. If the verification fails, notify FPGA to resend it. The data that passes the verification is placed in DDR.

[0084] Step 5: Clear the interrupt controller and wait for the next notification to fetch data.

[0085] like Figure 6 As shown, the data processing flow is as follows:

[0086] Step 1: The data processing module in the soft core fetches data (assuming 1KB) from the memory start address (assuming 0x80000000) and puts it into temporary array 1;

[0087] Step 2: The SPI driver uses the erase function to erase the 64KB space;

[0088] Step 3: The SPI driver uses the programming function to write 1KB of data in temporary array 1 to the flash, assuming the starting address is 0xa0000000;

[0089] Step 4: The SPI driver uses the read function to read the data with a size of 1KB from the flash address 0xa0000000 and put it into temporary array 2;

[0090] Step 5: Compare the contents of temporary arrays 1 and 2. If they are equal, the data verification succeeds; if they are not equal, the data verification fails and the online upgrade fails.

[0091] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A configuration data online upgrade system for ARINC818 digital video card, characterized in that: It includes an airborne mission machine and an ARINC818 digital video card, wherein the ARINC818 digital video card includes FPGA, DDR and FLASH; The FPGA includes an 818 interface IP core, and the airborne mission machine is connected to the ARINC818 video card via an optical fiber line; the airborne mission machine divides the configuration file into data blocks of a predetermined size, and assembles each data block into an FC-based 818 data frame and sends it to the FPGA via the optical fiber line; The FPGA receives FC-based 818 data frames via the 818 interface IP core to implement ARINC818 optical fiber data communication between the airborne mission machine and the FPGA of the ARINC818 video card; The FPGA is configured with an embedded soft core module, which is used to read the received 818 data frame from the FPGA, extract the configuration file information therefrom, and then implement the read and write operations on the FLASH through the SPI interface to complete the upgrade function.

2. The configuration data online upgrade system for ARINC818 digital video card according to claim 1, characterized in that: The airborne mission machine divides the configuration file into multiple data blocks according to a fixed size, and stores each data block as upgrade file data in the FC-based 818 data frame using the Payload field. The 818 stream data consisting of the FC-based 818 data frames is sent to the ARINC818 digital video card through the optical fiber line, wherein the complete 818 stream data constitutes an FC optical fiber communication sequence, which is composed of multiple consecutive FC-based 818 data frames.

3. The configuration data online upgrade system for ARINC818 digital video card according to claim 1, characterized in that: After receiving the FC-based 818 data frame, the FPGA parses the frame data and the Payload field through the 818 interface IP core, stores the frame data and the Payload field in the dual-port BRAM of the FPGA, and notifies the embedded soft core module to perform reading processing.

4. The configuration data online upgrade system for ARINC818 digital video card according to claim 1, characterized in that: The embedded soft core module reads the frame data and the Payload field from the dual-port BRAM of the FPGA through the AXI bus, performs a reception check, and sends a notification to the FPGA to request the FPGA to retransmit the current data frame when the reception check fails.

5. The configuration data online upgrade system for ARINC818 digital video card according to claim 4, characterized in that: The frame data and Payload fields read from the dual-port BRAM of the FPGA include at least the following field information: frame header, current frame number, total number of frames, data area, data check, and frame tail.

6. The configuration data online upgrade system for ARINC818 digital video card according to claim 4, characterized in that: The embedded soft core module performs erasing, writing, and writing verification processing on the FLASH through the SPI interface, writes each fixed-size data block into the FLASH, and completes the update of the configuration file stored in the FLASH.

7. The configuration data online upgrade system for ARINC818 digital video card according to any one of claims 1 to 6, characterized in that: The airborne mission machine sends FC-based 818 data frames in parallel, and the embedded soft core module synchronously implements reception verification and FLASH erasing, writing, and writing verification processing in the FPGA of the receiving end, and updates the configuration file stored in the FLASH.

8. The configuration data online upgrade system for ARINC818 digital video card according to any one of claims 1 to 6, characterized in that: In the FPGA at the receiving end, the embedded soft core module reorganizes all received data blocks according to the total number of frames, and performs space erasing, writing, and writing verification processing on the FLASH through the SPI bus to update the configuration file stored in the FLASH.

9. The method for online upgrading of configuration data of an ARINC818 digital video card of the system for online upgrading of configuration data of an ARINC818 digital video card according to claim 1, characterized in that: The following steps are involved: Step 1: The onboard mission machine divides the configuration file to be upgraded into data blocks of fixed size, and puts each data block into the Payload field of the FC-based 818 data frame, adds the frame header, frame footer and CRC check field, assembles them into FC-based 818 data frames, and then sends them to the FPGA via the optical fiber line; Step 2: After receiving and parsing the FC-based 818 data frame via the 818 interface IP core, the FPGA removes the frame header and frame tail, removes the Payload field data, stores it, and then notifies the embedded soft core module to perform reading processing; Step 3, the embedded soft core module reads the frame data and the Payload field from the dual-port BRAM of the FPGA through the AXI bus, performs a reception check, and sends data to the FPGA to notify the FPGA to retransmit the current data frame when the reception check fails; If the verification passes, the data block in the Payload field is stored in DDR; Step 4: The embedded soft core module performs erasing, writing, and writing verification processing on the FLASH through the SPI interface, writes each fixed-size data block into the FLASH, and completes the update of the configuration file stored in the FLASH.

10. The method for online upgrading of configuration data for ARINC818 digital video card according to claim 9, characterized in that: In step 4, updating the configuration file stored in FLASH includes: (1) The airborne mission machine sends FC-based 818 data frames in parallel, and the embedded soft core module synchronously implements reception verification and FLASH erasing, writing, and writing verification processing in the FPGA of the receiving end, and updates the configuration file stored in the FLASH; or (2) In the FPGA at the receiving end, the embedded soft core module reorganizes all received data blocks according to the total number of frames, and performs space erasing, writing, and writing verification processing on the FLASH through the SPI bus to update the configuration file stored in the FLASH.

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