Chip power consumption evaluation method, system and storage medium based on artificial intelligence

Abstract

The present invention belongs to the field of chip power consumption detection and relates to data analysis technology, which is used to solve the problem that the prior art cannot perform optimization decision analysis based on test data when the power consumption of the chip is abnormal. Specifically, it is a chip power consumption evaluation method, system and storage medium based on artificial intelligence, including a static test module, a static analysis module, a dynamic test module, a dynamic analysis module and a database; the static test module is used to perform static testing on the chip power consumption; the static analysis module is used to analyze the static test results of the chip and mark the static test object i as a static normal object or a static abnormal object; the present invention can test the basic power consumption performance of the chip in a static operating environment, and then perform data processing on the static test results to obtain a static coefficient, and then differentiate the static test objects according to the static coefficient, so as to provide data support for the performance evaluation and analysis process.

Description

Technical Field

[0001] The present invention belongs to the field of chip power consumption detection and relates to data analysis technology, specifically to a chip power consumption evaluation method, system and storage medium based on artificial intelligence. Background Art

[0002] The power consumption of a chip mainly comes from the working state of its internal circuits; when the chip performs calculations, processes or transmits data, its internal transistors perform switching operations, which generates current and voltage in the process, resulting in energy consumption.

[0003] The invention patent with announcement number CN116755993B discloses a chip power consumption evaluation method, device, electronic device and storage medium; the application obtains at least two waveform files of the chip to be tested, and calculates the average power consumption corresponding to each of the waveform files; obtains the proportion information of each of the waveform files; according to the proportion information corresponding to each of the waveform files and the average power consumption corresponding to each of the waveform files, calculates the average power consumption evaluation result of the chip to be tested, so that when the percentage of the waveform file is adjusted, there is no need to recalculate the chip average power consumption, thereby effectively saving the time of calculating the chip average power consumption; however, the chip power consumption evaluation method cannot perform optimization decision analysis based on test data when the chip power consumption is abnormal, resulting in low optimization efficiency when the chip power consumption performance is abnormal.

[0004] In view of the above technical problems, this application proposes a solution. Summary of the invention

[0005] The purpose of the present invention is to provide a chip power consumption evaluation method, system and storage medium based on artificial intelligence, which is used to solve the problem that the prior art cannot perform optimization decision analysis based on test data when the power consumption of the chip is abnormal;

[0006] The technical problem to be solved by the present invention is: how to provide a chip power consumption evaluation method, system and storage medium based on artificial intelligence that can perform optimization decision analysis according to test data when the power consumption of the chip is abnormal.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] An artificial intelligence-based chip power consumption evaluation system, including a static test module, a static analysis module, a dynamic test module, a dynamic analysis module, and a database;

[0009] The static test module is used to perform a static test on the chip power consumption: the chip to be tested is marked as a static test object i, i=1, 2, ..., n, where n is a positive integer, and the static coefficient JTi of the static test object is obtained through the static test, and after all the static test objects i have completed the static test, the static coefficient JTi of all the static test objects i are sent to the static analysis module;

[0010] The static analysis module is used to analyze the static test results of the chip and mark the static test object i as a static normal object or a static abnormal object;

[0011] The dynamic test module is used to perform dynamic test on the chip power consumption: mark the static normal object as dynamic test object k, k=1, 2, ..., m, m is a positive integer, and m≤n; assign dynamic test parameters [JF+H1 k , JG+H1 m+1-k ], JF+H1 k is the data volume of the processing task set for the dynamic test object k during the dynamic test, JG+H1 m+1-k It is the interval between the completion of a processing task and the start of the next processing task in the dynamic test process; the dynamic coefficient DTk of the dynamic test object k is obtained through dynamic testing;

[0012] The dynamic analysis module is used to analyze the dynamic test results of the chip and mark the dynamic test object as a dynamic normal object or a dynamic abnormal object.

[0013] Furthermore, the process of obtaining the static coefficient JTi of the static test object i includes: setting a basic load value JF and a basic interval value JG for the static test object i, the basic load value JF being the data amount of the processing task set for the static test object i during the static test process; the static test is terminated when the static test object i completes the processing task, and the surface temperature value of the static test object i is obtained in real time during the static test process and marked as the temperature measurement value i, the difference between the value of the temperature measurement value i at the end of the static test and the value at the start of the static test is marked as the temperature rise value i, and the ratio of the temperature rise value i to the duration of the static test process is marked as the static coefficient JTi of the static test object i.

[0014] Furthermore, the specific process of the static analysis module analyzing the static test results of the chip includes: retrieving the static threshold JTmax through the database, and comparing the static coefficient JTi of the static test object i with the static threshold JTmax: if the static coefficient JTi is less than the static threshold JTmax, it is determined that the static power consumption performance of the static test object i meets the requirements, and the corresponding static test object i is marked as a static normal object; if the static coefficient JTi is greater than or equal to the static threshold JTmax, it is determined that the static power consumption performance of the static test object i does not meet the requirements, and the corresponding static test object i is marked as a static abnormal object.

[0015] Furthermore, the process of obtaining the dynamic coefficient DTk of the dynamic object k includes: obtaining the surface temperature value of the dynamic test object k in real time during the dynamic test process and marking it as the actual temperature value k; when the actual temperature value k reaches a preset temperature threshold, the dynamic test process is terminated; and the execution time of the dynamic test process corresponding to the dynamic test object k is recorded and marked as the dynamic coefficient DTk.

[0016] Furthermore, the specific process of the dynamic analysis module analyzing the dynamic test results of the chip includes: retrieving the dynamic threshold DTmin through the database, and comparing the dynamic coefficient DTk of the dynamic test object k with the dynamic threshold DTmin: if the dynamic coefficient DT is greater than the dynamic threshold DTmin, it is determined that the dynamic power consumption performance of the dynamic test object k meets the requirements, and the corresponding dynamic test object k is marked as a dynamic normal object; if the dynamic coefficient DT is less than or equal to the dynamic threshold DTmin, it is determined that the dynamic power consumption performance of the dynamic test object k does not meet the requirements, and the corresponding dynamic test object k is marked as a dynamic abnormal object.

[0017] Furthermore, it also includes a performance evaluation module and an optimization analysis module;

[0018] The performance evaluation module is used to evaluate and analyze the power consumption performance of the chip: the number of static abnormal objects and the number of dynamic abnormal objects are marked as static abnormal data JY and dynamic abnormal data DY respectively; the evaluation coefficient PG of the chip is obtained by the formula PG=(t1*JY+t2*DY) / n, wherein t1 and t2 are both proportional coefficients, and t1>t2>1; the evaluation threshold PGmax is retrieved through the database, and the evaluation coefficient PG is compared with the evaluation threshold PGmax: if the evaluation coefficient PG is less than the evaluation threshold PGmax, it is determined that the overall power consumption performance of the chip meets the requirements; if the evaluation coefficient PG is greater than or equal to the evaluation threshold PGmax, it is determined that the overall power consumption performance of the chip does not meet the requirements, and an optimization analysis signal is generated and sent to the optimization analysis module.

[0019] Furthermore, the optimization analysis module is used to optimize and analyze the power consumption performance of the chip: a dynamic analysis set is formed by the serial numbers corresponding to the dynamic abnormal objects in the dynamic test object k, the variance of the dynamic analysis set is calculated to obtain the dynamic concentration value DJ, and the optimization coefficient YH is obtained by the formula YH=u1*DJ+u2*JY / n, where u1 and u2 are both proportional coefficients, and u1>u2>1; the optimization threshold YHmax is retrieved from the database, and the optimization coefficient YH is compared with the optimization threshold YHmax: if the optimization coefficient YH is greater than or equal to the optimization threshold YHmax, a circuit optimization signal is generated and sent to the mobile phone terminal of the administrator; if the optimization coefficient YH is less than the optimization threshold YHmax, a distribution analysis is performed on the dynamic analysis set:

[0020] The distribution performance value is obtained by summing up all elements of the dynamic analysis set and taking the average value, and the distribution performance value is compared with m / 2: if the distribution performance value is less than m / 2, a frequency optimization signal is generated and sent to the mobile phone terminal of the administrator; if the distribution performance value is greater than or equal to m / 2, a load optimization signal is generated and sent to the mobile phone terminal of the administrator.

[0021] Furthermore, the chip power consumption evaluation method based on artificial intelligence includes the following steps:

[0022] Step 1: Perform static testing on chip power consumption: After all static test objects i have completed static testing, the static coefficients JTi of all static test objects i are sent to the static analysis module;

[0023] Step 2: Analyze the static test results of the chip and mark the static test object i as a static normal object or a static abnormal object, then send the static normal object to the dynamic test module and send the static abnormal object to the evaluation and optimization subsystem;

[0024] Step 3: Perform a dynamic test on the chip power consumption and obtain the dynamic coefficient DTk of the dynamic test object k, and send the dynamic coefficient DTk of all dynamic test objects k to the dynamic analysis module;

[0025] Step 4: Analyze the dynamic test results of the chip and mark the dynamic test object k as a dynamic normal object or a dynamic abnormal object, and send the dynamic abnormal object to the evaluation and optimization subsystem;

[0026] Step 5: Evaluate and analyze the power consumption performance of the chip and obtain the evaluation coefficient PG. Use the evaluation coefficient PG to determine whether the overall power consumption performance of the chip meets the requirements. If it does not meet the requirements, execute step 6.

[0027] Step 6: Optimize and analyze the power consumption performance of the chip and send a circuit optimization signal, a load optimization signal or a frequency optimization signal to the mobile phone terminal of the manager.

[0028] Furthermore, a computer storage medium stores a computer program, which, when executed by a processor, implements a chip power consumption evaluation method based on artificial intelligence.

[0029] Furthermore, a computer device includes: a processor and a memory; the memory stores a computer program, and the processor executes the computer program stored in the memory, so that the computer device executes a chip power consumption evaluation method based on artificial intelligence.

[0030] The present invention has the following beneficial effects:

[0031] The static test module can be used to test the basic power consumption performance of the chip in a static operating environment, and then the static test results are processed to obtain the static coefficient. Then, the static test objects are differentiated and marked according to the static coefficient, providing data support for the performance evaluation and analysis process.

[0032] The dynamic test module can be used to test the adaptability of the chip power consumption performance in a dynamic operating environment, and to assign corresponding dynamic test parameters to a group of dynamic test objects. Based on the dynamic test parameters, not only can the power consumption performance of the dynamic test objects be analyzed, but also data support can be provided for the optimization analysis process when the overall abnormal performance is abnormal;

[0033] The performance evaluation module can evaluate and analyze the power consumption performance of the chip. The evaluation coefficient is obtained by numerical calculation based on the analysis results of the static analysis process and the dynamic analysis process. The evaluation coefficient is used to provide feedback on the overall power consumption performance of a batch of chips, and timely early warning and optimization analysis can be performed when the overall power consumption performance is abnormal.

[0034] 4. The optimization analysis module can process the test parameters of the chip during static testing and dynamic testing, generate corresponding optimization processing signals based on the processing results, and then directly generate optimization directions when the overall performance is abnormal, thereby improving the efficiency of exception processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1A system block diagram of the present invention as a whole;

[0037] Figure 2 is a system block diagram of Embodiment 1 of the present invention;

[0038] Figure 3 is a system block diagram of Embodiment 2 of the present invention;

[0039] Figure 4 This is a method flow chart of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0040] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] like Figure 1 As shown, the chip power consumption evaluation system based on artificial intelligence includes a test and analysis subsystem, an evaluation and optimization subsystem, and a database.

[0042] Embodiment 1: Figure 2 As shown, the test and analysis subsystem includes a static test module, a static analysis module, a dynamic test module and a dynamic analysis module.

[0043] The static test module is used to perform static testing on chip power consumption: the chip to be tested is marked as static test object i, i=1, 2, ..., n, where n is a positive integer, and a basic load value JF and a basic interval value JG are set for the static test object i, where the basic load value JF is the data volume of the processing task set for the static test object i during the static test; the static test is terminated when the static test object i completes the processing task, and the surface temperature value of the static test object i is obtained in real time during the static test and marked as the temperature measurement value i, and the difference between the temperature measurement value i at the end of the static test and the start of the static test is marked as the temperature rise value i, and the ratio of the temperature rise value i to the duration of the static test process is marked as the static coefficient JTi of the static test object i, and after all static test objects i have completed the static test, the static coefficients JTi of all static test objects i are sent to the static analysis module.

[0044] The static analysis module is used to analyze the static test results of the chip: the static threshold JTmax is retrieved through the database, and the static coefficient JTi of the static test object i is compared with the static threshold JTmax: if the static coefficient JTi is less than the static threshold JTmax, it is determined that the static power consumption performance of the static test object i meets the requirements, and the corresponding static test object i is marked as a static normal object; if the static coefficient JTi is greater than or equal to the static threshold JTmax, it is determined that the static power consumption performance of the static test object i does not meet the requirements, and the corresponding static test object i is marked as a static abnormal object; then the static normal object is sent to the dynamic test module, and the static abnormal object is sent to the evaluation and optimization subsystem; the basic power consumption performance of the chip under the static operating environment is tested, and then the static test results are processed to obtain the static coefficient, and then the static test objects are differentiated according to the static coefficient to provide data support for the performance evaluation and analysis process.

[0045] The dynamic test module is used to perform dynamic testing on the chip power consumption: mark the static normal object as the dynamic test object k, k = 1, 2, ..., m, m is a positive integer, and m ≤ n; assign dynamic test parameters [JF + H1 k , JG+H1 m +1-k ], JF+H1 k is the data volume of the processing task set for the dynamic test object k during the dynamic test, JG+H1 m+1-k It is the interval between the completion of a processing task and the start of the next processing task in the dynamic test process; H1 is a numerical constant, and the value range of H1 is (1.01, 1.03); during the dynamic test process, the surface temperature value of the dynamic test object k is obtained in real time and marked as the actual temperature value k. When the actual temperature value k reaches the preset temperature threshold, the dynamic test process is terminated, and the execution time of the dynamic test process corresponding to the dynamic test object k is recorded and marked as the dynamic coefficient DTk; the dynamic coefficient DTk of all dynamic test objects k is sent to the dynamic analysis module.

[0046] The dynamic analysis module is used to analyze the dynamic test results of the chip: the dynamic threshold DTmin is retrieved through the database, and the dynamic coefficient DTk of the dynamic test object k is compared with the dynamic threshold DTmin: if the dynamic coefficient DT is greater than the dynamic threshold DTmin, the dynamic power consumption performance of the dynamic test object k is determined to meet the requirements, and the corresponding dynamic test object k is marked as a dynamic normal object; if the dynamic coefficient DT is less than or equal to the dynamic threshold DTmin, the dynamic power consumption performance of the dynamic test object k is determined to not meet the requirements, and the corresponding dynamic test object k is marked as a dynamic abnormal object, and the dynamic abnormal object is sent to the evaluation and optimization subsystem; the adaptability of the chip power consumption performance in the dynamic operating environment is tested, and corresponding dynamic test parameters are assigned to a group of dynamic test objects. According to the dynamic test parameters, not only the power consumption performance of the dynamic test object can be analyzed, but also data support can be provided for the optimization analysis process when the overall abnormal performance is abnormal.

[0047] Embodiment 2: Figure 3 As shown, the evaluation and optimization subsystem includes a performance evaluation module and an optimization analysis module.

[0048] The performance evaluation module is used to evaluate and analyze the power consumption performance of the chip: the number of static abnormal objects and the number of dynamic abnormal objects are marked as static abnormal data JY and dynamic abnormal data DY respectively; the evaluation coefficient PG of the chip is obtained by the formula PG=(t1*JY+t2*DY) / n, where t1 and t2 are both proportional coefficients, and t1>t2>1; the evaluation threshold PGmax is retrieved from the database, and the evaluation coefficient PG is compared with the evaluation threshold PGmax: if the evaluation coefficient PG is less than the evaluation threshold PGmax, it is determined that the overall power consumption performance of the chip meets the requirements; if the evaluation coefficient PG is greater than or equal to the evaluation threshold PGmax, it is determined that the overall power consumption performance of the chip does not meet the requirements, and an optimization analysis signal is generated and sent to the optimization analysis module; the analysis results of the static analysis process and the dynamic analysis process are combined to perform numerical calculations to obtain the evaluation coefficient, and the overall power consumption performance of a batch of chips is fed back through the evaluation coefficient, so as to timely perform early warning and optimization analysis when the overall power consumption performance is abnormal.

[0049] The optimization analysis module is used to optimize the power consumption performance of the chip: the dynamic analysis set is composed of the serial numbers corresponding to the dynamic abnormal objects in the dynamic test object k, the variance of the dynamic analysis set is calculated to obtain the dynamic concentration value DJ, and the optimization coefficient YH is obtained by the formula YH=u1*DJ+u2*JY / n, where u1 and u2 are both proportional coefficients, and u1>u2>1; the optimization threshold YHmax is retrieved from the database, and the optimization coefficient YH is compared with the optimization threshold YHmax: if the optimization coefficient YH is greater than or equal to the optimization threshold YHmax, a circuit optimization signal is generated and sent to the mobile terminal of the administrator; if the optimization coefficient YH is less than If the threshold YHmax is optimized, a distribution analysis is performed on the dynamic analysis set: the distribution performance value is obtained by summing up and averaging all elements of the dynamic analysis set, and the distribution performance value is compared with m / 2: if the distribution performance value is less than m / 2, a frequency optimization signal is generated and sent to the administrator's mobile terminal; if the distribution performance value is greater than or equal to m / 2, a load optimization signal is generated and sent to the administrator's mobile terminal; the test parameters of the chip during the static test process and the dynamic test process are processed, and the corresponding optimization processing signal is generated according to the processing results, and then the optimization direction is directly generated when the overall performance is abnormal, thereby improving the efficiency of abnormal processing.

[0050] Embodiment 3: Figure 4 As shown, the chip power consumption evaluation method based on artificial intelligence includes the following steps:

[0051] Step 1: Perform static testing on chip power consumption: After all static test objects i have completed static testing, the static coefficients JTi of all static test objects i are sent to the static analysis module;

[0052] Step 2: Analyze the static test results of the chip and mark the static test object i as a static normal object or a static abnormal object, then send the static normal object to the dynamic test module and send the static abnormal object to the evaluation and optimization subsystem;

[0053] Step 3: Perform a dynamic test on the chip power consumption and obtain the dynamic coefficient DTk of the dynamic test object k, and send the dynamic coefficient DTk of all dynamic test objects k to the dynamic analysis module;

[0054] Step 4: Analyze the dynamic test results of the chip and mark the dynamic test object k as a dynamic normal object or a dynamic abnormal object, and send the dynamic abnormal object to the evaluation and optimization subsystem;

[0055] Step 5: Evaluate and analyze the power consumption performance of the chip and obtain the evaluation coefficient PG. Use the evaluation coefficient PG to determine whether the overall power consumption performance of the chip meets the requirements. If it does not meet the requirements, execute step 6.

[0056] Step 6: Optimize and analyze the power consumption performance of the chip and send a circuit optimization signal, a load optimization signal or a frequency optimization signal to the mobile phone terminal of the manager.

[0057] The present invention also includes a readable storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned chip power consumption evaluation method based on artificial intelligence is implemented. A person of ordinary skill in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0058] The terminal of the present invention includes: a processor and a memory; the memory is used to store a computer program; the processor is connected to the memory and is used to execute the computer program stored in the memory, so that the terminal executes any chip power consumption evaluation method based on artificial intelligence. Specifically, the memory includes: ROM, RAM, disk, U disk, memory card or CD and other media that can store program codes.

[0059] Preferably, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0060] The chip power consumption evaluation system based on artificial intelligence, when working, sends the static coefficients JTi of all static test objects i to the static analysis module after all static test objects i have completed the static test; analyzes the static test results of the chip and marks the static test object i as a static normal object or a static abnormal object, then sends the static normal object to the dynamic test module, and sends the static abnormal object to the evaluation and optimization subsystem; performs dynamic testing on the chip power consumption and obtains the dynamic coefficient DTk of the dynamic test object k, and sends the dynamic coefficient DTk of all dynamic test objects k to the dynamic analysis module; analyzes the dynamic test results of the chip and marks the dynamic test object k as a dynamic normal object or a dynamic abnormal object, and sends the dynamic abnormal object to the evaluation and optimization subsystem; evaluates and analyzes the power consumption performance of the chip and obtains the evaluation coefficient PG, determines whether the overall power consumption performance of the chip meets the requirements through the evaluation coefficient PG, optimizes and analyzes the power consumption performance of the chip when it does not meet the requirements, and sends a circuit optimization signal, a load optimization signal or a frequency optimization signal to the mobile phone terminal of the manager.

[0061] The above contents are merely examples and explanations of the structure of the present invention. The technicians in this technical field may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the structure of the invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

[0062] The above formulas are obtained by collecting a large amount of data for software simulation and selecting a formula close to the real value. The coefficients in the formula are set by technicians in this field according to the actual situation; for example: formula PG= (t1*JY+t2*DY) / n; technicians in this field collect multiple groups of sample data and set corresponding evaluation coefficients for each group of sample data; substitute the set evaluation coefficients and the collected sample data into the formula, any two formulas constitute a set of two-variable linear equations, screen the calculated coefficients and take the average, and obtain the values ​​of t1 and t2 as 3.25 and 2.86 respectively;

[0063] The size of the coefficient is to quantify each parameter to obtain a specific value for subsequent comparison. The size of the coefficient depends on the amount of sample data and the preliminary setting of the corresponding evaluation coefficient for each group of sample data by technical personnel in this field; as long as it does not affect the proportional relationship between the parameter and the quantized value, such as the evaluation coefficient is proportional to the value of the static difference data.

[0064] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0065] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. The chip power consumption evaluation system based on artificial intelligence is characterized by: It includes static test module, static analysis module, dynamic test module, dynamic analysis module and database; The static test module is used to perform a static test on the power consumption of the chip: the chip to be tested is marked as a static test object i, i=1, 2, ..., n, n is a positive integer, and the static coefficient JTi of i is obtained through the static test, including: setting a basic load value JF and a basic interval value JG for i, JF is the data volume of the processing task set for i during the static test; when i completes the processing task, the static test is terminated, and the surface temperature value of i is obtained in real time during the static test and marked as the temperature measurement value, and the difference between the value of the temperature measurement value at the end of the static test and the value at the start of the static test is marked as the temperature rise value, and the ratio of the temperature rise value to the duration of the static test process is marked as JTi; after all i have completed the static test, the JTi of all i is sent to the static analysis module; The static analysis module is used to analyze the static test results of the chip and mark i as a static normal object or a static abnormal object, including: calling the static threshold JTmax through the database, comparing JTi with JTmax: if JTi is less than JTmax, it is determined that the static power consumption performance of i meets the requirements, and the corresponding i is marked as a static normal object; if JTi is greater than or equal to JTmax, it is determined that the static power consumption performance of i does not meet the requirements, and the corresponding i is marked as a static abnormal object; The dynamic test module is used to perform dynamic test on the chip power consumption: mark the static normal object as dynamic test object k, k=1, 2, ..., m, m is a positive integer, and m≤n; assign dynamic test parameters [JF+H1 k , JG+H1 m+1-k ], JF+H1 k is the data volume of the processing task set for k during the dynamic test, JG+H1 m+1-k It is the interval time between the completion of a processing task and the start of the next processing task in the dynamic test process; the dynamic coefficient DTk of k is obtained through dynamic testing, including: the surface temperature value of k is obtained in real time during the dynamic test process and marked as the actual temperature value, when the actual temperature value reaches the preset temperature threshold, the dynamic test process is terminated, and the execution time of the dynamic test process corresponding to k is recorded and marked as DTk; The dynamic analysis module is used to analyze the dynamic test results of the chip and mark k as a dynamic normal object or a dynamic abnormal object, including: retrieving the dynamic threshold DTmin through the database, and comparing DTk with DTmin: if DTk is greater than DTmin, it is determined that the dynamic power consumption performance of k meets the requirements, and the corresponding k is marked as a dynamic normal object; if DTk is less than or equal to DTmin, it is determined that the dynamic power consumption performance of k does not meet the requirements, and the corresponding k is marked as a dynamic abnormal object.

2. The chip power consumption evaluation system based on artificial intelligence according to claim 1 is characterized in that: It also includes performance evaluation module and optimization analysis module; The performance evaluation module is used to evaluate and analyze the power consumption performance of the chip: the number of static abnormal objects and the number of dynamic abnormal objects are marked as static abnormal data JY and dynamic abnormal data DY respectively; the evaluation coefficient PG of the chip is obtained by the formula PG=(t1*JY+t2*DY) / n, where t1 and t2 are both proportional coefficients, and t1>t2>1; the evaluation threshold PGmax is retrieved from the database, and the evaluation coefficient PG is compared with the evaluation threshold PGmax: if the evaluation coefficient PG is less than the evaluation threshold PGmax, it is determined that the overall power consumption performance of the chip meets the requirements; If the evaluation coefficient PG is greater than or equal to the evaluation threshold PGmax, it is determined that the overall power consumption performance of the chip does not meet the requirements, an optimization analysis signal is generated and sent to the optimization analysis module.

3. The chip power consumption evaluation system based on artificial intelligence according to claim 2 is characterized in that: The optimization analysis module is used to optimize and analyze the power consumption performance of the chip: a dynamic analysis set is formed by the serial numbers corresponding to the dynamic abnormal objects in the dynamic test object k, the variance of the dynamic analysis set is calculated to obtain the dynamic concentration value DJ, and the optimization coefficient YH is obtained by the formula YH=u1*DJ+u2*JY / n, where u1 and u2 are both proportional coefficients, and u1>u2>1; the optimization threshold YHmax is retrieved from the database, and the optimization coefficient YH is compared with the optimization threshold YHmax: if the optimization coefficient YH is greater than or equal to the optimization threshold YHmax, a circuit optimization signal is generated and sent to the mobile phone terminal of the administrator; if the optimization coefficient YH is less than the optimization threshold YHmax, a distribution analysis is performed on the dynamic analysis set: The distribution performance value is obtained by summing up all elements of the dynamic analysis set and taking the average value, and the distribution performance value is compared with m / 2: if the distribution performance value is less than m / 2, a frequency optimization signal is generated and sent to the mobile phone terminal of the administrator; if the distribution performance value is greater than or equal to m / 2, a load optimization signal is generated and sent to the mobile phone terminal of the administrator.

4. The chip power consumption evaluation method based on artificial intelligence is characterized by: The chip power consumption evaluation system based on artificial intelligence as claimed in claim 1 comprises the following steps: Step 1: Perform static testing on chip power consumption: After all static test objects i have completed static testing, the static coefficients JTi of all static test objects i are sent to the static analysis module; Step 2: Mark the static test object i as a static normal object or a static abnormal object through the static coefficient JTi; Step 3: Perform dynamic testing on the chip power consumption and obtain the dynamic coefficient DTk of the dynamic test object k; Step 4: Mark the dynamic test object k as a dynamic normal object or a dynamic abnormal object through the dynamic coefficient DTk; Step 5: Evaluate and analyze the power consumption performance of the chip and determine whether the overall power consumption performance of the chip meets the requirements. If it does not meet the requirements, execute step 6. Step 6: Optimize and analyze the power consumption performance of the chip and send a circuit optimization signal, a load optimization signal or a frequency optimization signal to the mobile phone terminal of the manager.

5. A computer storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the chip power consumption evaluation method based on artificial intelligence described in claim 4 is implemented.

6. A computer device, characterized in that: include: Processor and memory; The memory stores a computer program, and the processor executes the computer program stored in the memory so that the computer device executes the chip power consumption evaluation method based on artificial intelligence as claimed in claim 4.

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