A three-dimensional storage-computing integrated system and an operation method thereof

Abstract

The application belongs to the technical field of memory computing integration, and specifically discloses a three-dimensional memory computing integration system and an operation method thereof. The system comprises: an input module, an input end of which is connected to an output end of a main processor, and which is used for converting to-be-processed data into an analog voltage signal; a memristor array, an input end of which is connected to an output end of the input module, and which is used for performing matrix-vector multiplication operation or matching operation on pre-stored operation data and the analog voltage signal, and outputting a first operation result of the to-be-processed data; a perception module, an input end of which is connected to an output end of the memristor array, and which is used for converting the first operation result into a corresponding digital signal based on a signal form of the first operation result; and the main processor, which is used for analyzing the digital signal and determining a second operation result of the to-be-processed data. Through the application, the storage area and power consumption of the system can be effectively reduced, and the operation speed and efficiency of the system can be improved.

Description

Technical Field

[0001] This application belongs to the field of in-memory computing technology, and more specifically, relates to a three-dimensional in-memory computing system and its computing method. Background Technology

[0002] Matrix multiplication and exact matching are both crucial computational methods in machine learning. Matrix multiplication is primarily used to implement convolutional and fully connected layers in machine learning neural networks, while exact matching is used to implement decision trees and random forest algorithms. Often, these two methods are combined in machine learning algorithms to achieve higher predictive performance.

[0003] However, the current computing architecture used in the systems that implement the two machine learning algorithms mentioned above is the traditional von Neumann architecture. During the data processing, because the computing module and the storage module are separate, data is constantly transferred between the computing module and the storage module. The amount of data computation is huge, resulting in large system storage area and power consumption. At the same time, it also leads to slow system speed and low computing efficiency. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, this application aims to solve the problems of large system storage area and resource consumption, slow system operation speed and low operation efficiency of traditional fusion matrix multiplication and exact matching algorithms.

[0005] To achieve the above objectives, this application provides a three-dimensional in-memory computing system, comprising:

[0006] The input module, whose input terminal is connected to the output terminal of the main processor, is used to convert the data to be processed into an analog voltage signal;

[0007] A memristor array, whose input terminal is connected to the output terminal of the input module, is used to perform matrix-vector multiplication or matching operations on the pre-stored computation data and the analog voltage signal, and output the first computation result of the data to be processed;

[0008] The sensing module, whose input is connected to the output of the memristor array, is used to convert the first calculation result into a corresponding digital signal based on the signal form of the first calculation result.

[0009] The main processor has a first input terminal for receiving the data to be processed and a second input terminal connected to the output terminal of the sensing module for analyzing the digital signal and determining the second operation result of the data to be processed.

[0010] Optionally, the memristor array includes multiple layers of memristor subarrays, with each column of memristors in each layer of the memristor subarray connected by bit lines and each row of memristors in each layer of the memristor subarray connected by word lines;

[0011] The memristor subarrays in each layer are connected by word lines; the number of bit lines and word lines are determined according to the size of the memristor subarray.

[0012] The bit lines are used to input the analog voltage signal; the word lines are used to output the first calculation result of the data to be processed.

[0013] Optionally, a discharge transistor is connected to each word line; the discharge transistor is used to perform data initialization operations before matrix-vector multiplication or matching operations are performed on the memristor array.

[0014] Optionally, the multilayer memristor subarray includes a first memristor subarray and a second memristor subarray;

[0015] The first memristor subarray is used to store the multiplicative data matrix so that the multiplicative data matrix can be used to perform matrix-vector multiplication with the analog voltage signal;

[0016] The second memristor subarray is used to store the data matrix to be searched, so that the data matrix to be searched can be matched with the analog voltage signal; the operation data includes the multiplicated data matrix and the data matrix to be searched.

[0017] Optionally, the data to be processed includes first data for performing matrix-vector multiplication or second data for performing matching operations; correspondingly, the analog voltage signal includes a first analog voltage signal corresponding to the first data or a second analog voltage signal corresponding to the second data.

[0018] The bit line includes a first bit line disposed in the first memristor subarray and a second bit line disposed in the second memristor subarray; the first bit line is used to input the first analog voltage signal, and the second bit line is used to input the second analog voltage signal;

[0019] The first memristor subarray is used to perform matrix-vector multiplication on the first analog voltage signal and the multiplied data matrix; the second memristor subarray is used to perform matching operation on the second analog voltage signal and the search data matrix.

[0020] The word line is used to output the calculation result corresponding to the first data or the calculation result corresponding to the second data; the first calculation result includes the calculation result corresponding to the first data or the calculation result corresponding to the second data.

[0021] Optionally, each column of stored data in the multiplied data matrix is ​​represented by a column of memristors in the first memristor subarray, wherein the high resistance state of the memristor represents the stored data as "0" and the low resistance state of the memristor represents the stored data as "1".

[0022] When the data input to one column of memristors in the first memristor subarray is "0", the corresponding input analog voltage signal is defined as signal GND; when the data input to one column of memristors is "1", the corresponding input analog voltage signal is defined as signal Vs.

[0023] Among them, signal Vs is used to indicate the voltage signal of the memristor, and signal GND is used to indicate that the memristor is grounded.

[0024] Optionally, each column of stored data in the data matrix to be searched is represented by two columns of memristors in the second memristor subarray. In the two columns of memristors, the high resistance state of any memristor and its corresponding low resistance state represent stored data as "0", the low resistance state of any memristor and its corresponding high resistance state represent stored data as "1", and the high resistance state of any memristor and its corresponding high resistance state represent stored data as "X". The stored data as "X" is used to characterize the state of not being of interest.

[0025] When the data input to the two columns of memristors in the second memristor subarray is "0", the two corresponding analog voltage signals are defined as a sequential combination of signal GND and signal Vs; when the data input to the two columns of memristors is "1", the two corresponding analog voltage signals are defined as a sequential combination of signal Vs and signal GND; when the data input to the two columns of memristors is "X", the two corresponding analog voltage signals are defined as a combination of signal GND and signal GND.

[0026] Optionally, the memristor array includes a resistive random access memory array, a ferroelectric memory array, a phase change memory array, a magnetic random access memory array, or a non-volatile flash memory array.

[0027] Optionally, the spatial arrangement structure of the memristor array includes a three-dimensional horizontal stacking structure or a three-dimensional vertical stacking structure.

[0028] This application also provides a computing method applied to any of the three-dimensional in-memory computing systems described above, including:

[0029] Convert the data to be processed into an analog voltage signal;

[0030] Perform matrix-vector multiplication or matching operations on the pre-stored computation data and the analog voltage signal, and output the first computation result of the data to be processed;

[0031] Based on the signal form of the first calculation result, the first calculation result is converted into a corresponding digital signal;

[0032] The digital signal is analyzed to determine the second operation result of the data to be processed.

[0033] Overall, the technical solutions conceived in this application have at least the following beneficial effects compared with the prior art:

[0034] This application provides a three-dimensional in-memory computing system and its computing method. The system uses an input module to convert the input data to be processed into an analog voltage signal. A memristor array performs matrix-vector multiplication or matching operations on the stored computing data and the analog voltage signal. Combined with the processing and analysis of the operation results by the sensing module and the main processor, both precise lookup and matrix multiplication functions can be realized in the same memristor array. This can effectively reduce the system's storage area and power consumption, improve the system's computing speed and efficiency, and also achieve system reconfigurability without introducing additional arrays and circuits. It can adapt to the functional requirements of precise matching operations or matrix multiplication operations, and is conducive to improving the integration density of the system circuit and the array size. Attached Figure Description

[0035] Figure 1 This is one of the structural schematic diagrams of the three-dimensional in-memory computing system provided in the embodiments of this application;

[0036] Figure 2 This is the second schematic diagram of the structure of the three-dimensional in-memory computing system provided in the embodiments of this application;

[0037] Figure 3 This is one of the structural schematic diagrams of the three-dimensional self-rectified memristor array provided in the embodiments of this application;

[0038] Figure 4 This is the second schematic diagram of the structure of the three-dimensional self-rectified memristor array provided in the embodiments of this application;

[0039] Figure 5 This is a schematic diagram of the process of performing matrix-vector multiplication on a memristor array according to an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the process of performing a matching operation on a memristor array according to an embodiment of this application;

[0041] Figure 7 This is a schematic diagram showing the result of matrix-vector multiplication operation implemented by a three-dimensional self-rectified memristor array provided in the embodiments of this application;

[0042] Figure 8This is a schematic diagram showing the result of precise matching operation achieved by the three-dimensional self-rectified memristor array provided in the embodiments of this application;

[0043] Figure 9 This is a flowchart illustrating the computation method of the three-dimensional in-memory computing system provided in the embodiments of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first operation result" and "second operation result" are used to distinguish different operation results, not to describe a specific order of operation results; "first memristor subarray" and "second memristor subarray" are used to distinguish memristor subarrays with different functions, not to describe a specific order of memristor subarrays.

[0046] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0047] In the description of the embodiments of this application, unless otherwise stated, "multilayer" means two or more layers. For example, a multilayer memristor subarray means a memristor subarray with two or more layers.

[0048] The embodiments of this application are described below with reference to the accompanying drawings.

[0049] Figure 1 This is one of the structural schematic diagrams of the three-dimensional in-memory computing system provided in the embodiments of this application, such as... Figure 1 As shown, the system includes:

[0050] The input module, whose input terminal is connected to the output terminal of the main processor, is used to convert the data to be processed into an analog voltage signal;

[0051] A memristor array, whose input is connected to the output of the input module, is used to perform matrix-vector multiplication or matching operations on the pre-stored computational data and the analog voltage signal, and output the first computational result of the data to be processed.

[0052] The sensing module, whose input is connected to the output of the memristor array, is used to convert the first calculation result into a corresponding digital signal based on the signal form of the first calculation result;

[0053] The main processor has a first input terminal for receiving data to be processed and a second input terminal connected to the output terminal of the sensing module for analyzing digital signals and determining the second operation result of the data to be processed.

[0054] Specifically, the computational data described in the embodiments of this application is used to perform matrix-vector multiplication or matching operations with analog voltage signals. The matching operation can be a fuzzy matching operation or a precise matching operation.

[0055] In embodiments of this application, the input module is used to convert the data to be processed forwarded by the main processor into an analog voltage signal, which can also be described as an "input voltage driving module". Specifically, it can consist of multiple 1-bit digital-to-analog converters to use the converted analog voltage signal as the voltage input of the memristor array for calculation.

[0056] In the embodiments of this application, the memristor array can pre-map each data point in the computational data to a corresponding conductance value for data storage. Specifically, the memristor array can be a three-dimensional self-rectifying memristor array, i.e., a self-rectifying memristor array fabricated using three-dimensional chip stacking technology. By utilizing the reverse rectification characteristics of the self-rectifying memristor, the self-rectifying memristor array can effectively suppress array leakage current.

[0057] It should be noted that the memristor array can also use other memristors that can perform matrix-vector multiplication and matching operations, and this application does not make any specific restrictions on this.

[0058] Due to the self-rectifying characteristics of memristor devices, when reading in the forward direction, the high and low resistance states of the device can be read, while when reading in the reverse direction, the resistance read is much higher than the high resistance of the device. This self-rectifying characteristic of forward conduction and reverse cutoff can further help memristor arrays achieve precise matching and reconfigurable operations of matrix-vector multiplication.

[0059] The first calculation result described in this application refers to the original calculation result obtained after the analog voltage signal corresponding to the data to be processed is processed by a memristor array. Specifically, it may include the memristor array processing result corresponding to matrix-vector multiplication operation, or the memristor array processing result corresponding to matching operation. The signal form of the first calculation result may include both current signal and voltage signal forms.

[0060] In the embodiments of this application, the sensing module can be pre-configured with sensing modes, including voltage sensing mode and current sensing mode, and therefore it can also be described as a "configurable current / voltage sensing module". The principle of using the configurable current / voltage sensing module to implement matching and matrix-vector multiplication functions is as follows: the current sensing mode corresponds to the matrix-vector multiplication function. In this mode, the calculation result is positively linearly correlated with the current. Through the first calculation result output in the form of a current signal, the sensing module directly senses the corresponding current value, and then converts it into the corresponding multiplication result by the main processor. The voltage sensing mode corresponds to the matching function. Since the voltage difference between complete matching and non-matching is large and easily distinguishable, a reference voltage can be set between the two. Through the first calculation result output in the form of a voltage signal, the sensing module compares the first calculation result with the reference voltage to determine whether there is a complete match.

[0061] The second operation result described in this application refers to the final matrix-vector multiplication operation result or matching result corresponding to the data to be processed. When the second operation result is the final matrix-vector multiplication operation result, it specifically represents the data information obtained by performing matrix-vector multiplication calculation on the data to be processed; when the second operation result is the final matching operation result, it specifically represents the data information obtained by performing search and matching calculation on the data to be processed, indicating whether the data is successfully matched or not matched.

[0062] Furthermore, in the embodiments of this application, after the perception module converts the first calculation result into a corresponding digital signal, it inputs it into the main processor. The main processor analyzes the digital signal and finally determines the matrix-vector multiplication result or matching result corresponding to the data to be processed.

[0063] It should be noted that the main processor can be a processor commonly used in the art, such as a DSP chip or an FPGA chip, and this application embodiment does not impose specific limitations on it.

[0064] Figure 2 This is a second schematic diagram of the structure of the three-dimensional in-memory computing system provided in the embodiments of this application, as shown below. Figure 2 As shown in the embodiments of this application, the memristor array 2 adopts a three-dimensional self-rectified memristor array. The input voltage drive module 1 converts the data to be processed input by the main processor 4 into an analog voltage signal and transmits it to the three-dimensional self-rectified memristor array for matrix-vector multiplication or matching operation. The operation result is further output to the configurable current / voltage sensing module 3 for analog-to-digital conversion and converted into the corresponding digital signal. The main processor 4 performs digital signal analysis to obtain the final operation result of the data to be processed.

[0065] The configurable current / voltage sensing module can include multiple configurable current / voltage sensing units, each of which is connected to a matching line. Each configurable current / voltage sensing unit includes a transimpedance amplifier, two 2-to-1 switches respectively arranged at both ends of the transimpedance amplifier, and an analog-to-digital converter (ADC). The sensing mode of each configurable current / voltage sensing unit can be realized by the main processor controlling the switching of the two 2-to-1 switches in the configurable current / voltage sensing module.

[0066] When the main processor controls the two-to-one switch to switch so that the first calculation result is processed by the transimpedance amplifier and ADC, the sensing module is in current sensing mode. The transimpedance amplifier converts the current signal into a voltage signal during current sensing. When the two-to-one switch is controlled to switch so that the first calculation result is processed only by the ADC, the sensing module is in voltage sensing mode. The ADC is used to sense the voltage signal and output the corresponding digital signal.

[0067] The three-dimensional in-memory computing system of this application embodiment uses an input module to convert the input data to be processed into an analog voltage signal. The memristor array performs matrix-vector multiplication or matching operations on the stored computation data and the analog voltage signal. Combined with the processing and analysis of the operation results by the sensing module and the main processor, both precise lookup and matrix multiplication functions can be realized in the same memristor array. This can effectively reduce the storage area and power consumption of the system, improve the system's computing speed and efficiency, and at the same time, achieve system reconfigurability without introducing additional arrays and circuits. It can adapt to the functional requirements of precise matching operations or matrix multiplication operations, and is conducive to improving the integration density of system circuits and array size.

[0068] Based on the above embodiments, as an optional embodiment, the memristor array includes multiple memristor subarrays, each column of memristors in each memristor subarray is connected by bit lines, and each row of memristors in each memristor subarray is connected by word lines.

[0069] Each layer of memristor subarrays is connected by word lines; the number of bit lines and word lines is determined according to the size of the memristor subarray.

[0070] Bit lines are used to input analog voltage signals; word lines are used to output the first result of the data to be processed.

[0071] Specifically, in the embodiments of this application, the memristor array can be fabricated using three-dimensional chip stacking technology, including multiple layers of memristor subarrays. Each column of memristors in each layer of the memristor subarray is connected by bit lines, and each row of memristors in each layer of the memristor subarray is connected by word lines. The bit lines can be divided into three categories according to the type of input data, denoted as BL, SL, and SLb, respectively; the word lines can be denoted as WL.

[0072] In the embodiments of this application, the memristor subarrays are connected by word lines to form a three-dimensional large array. The number of bit lines and word lines is determined according to the size of the memristor subarray. For example, if the size of each memristor subarray is 4×8, then each memristor subarray has 8 bit lines and 4 word lines.

[0073] The bit lines are used to input the analog voltage signal corresponding to the data to be processed; the word lines are used to output the first operation result of the data to be processed.

[0074] The system in this application embodiment uses a hierarchical array structure design, employing word lines and bit lines to connect various memristor devices to form a multi-layer memristor sub-array. Word lines are used to connect the various memristor sub-arrays and stack them in three dimensions to form a complete three-dimensional memristor array. By controlling the input and output of data signals through bit lines and word lines, a matrix multiplication or matching array operation can be performed in a single array parallel read operation. This gives the system the advantages of low time complexity and high parallelism, as well as high integration density and large array size.

[0075] Based on the above embodiments, as an optional embodiment, a discharge transistor is connected to each word line; the discharge transistor is used to perform data initialization operations before the memristor array performs matrix-vector multiplication or matching operations.

[0076] It should be noted that during the operation of the memristor array, a certain amount of charge may accumulate on the word lines. These residual charges may affect the normal operation of the entire array circuit or cause data reading errors.

[0077] Specifically, in the embodiments of this application, a discharge transistor is connected to each word line in the memristor array structure. By controlling the conduction and cutoff of the discharge transistor, residual charge accumulated on the word line can be easily cleared, thereby realizing data initialization before the memristor array performs matrix-vector multiplication or matching operations.

[0078] At the same time, the discharge transistor can also be used to reset the circuit, restoring it to its initial state through a discharge operation.

[0079] In addition, when an abnormal situation occurs in the memristor array circuit (such as overcurrent or overvoltage), the discharge transistor can quickly turn on to divert the current or voltage to a safe path, thereby protecting other circuit components from damage.

[0080] The system of this application embodiment initializes the data before operation by connecting a discharge transistor to each word line in the memristor array. By discharging the discharge transistor, the charge or current on the word line can be effectively released, thereby clearing residual charge, resetting the circuit state, or protecting other circuit components, thus ensuring the stable operation and high efficiency of the memristor array.

[0081] Based on the above embodiments, as an optional embodiment, the multilayer memristor subarray includes a first memristor subarray and a second memristor subarray;

[0082] The first memristor subarray is used to store the multiplied data matrix so that the multiplied data matrix can be used to perform matrix-vector multiplication with the analog voltage signal;

[0083] The second memristor subarray is used to store the data matrix to be searched, so that the data matrix to be searched can be matched with the analog voltage signal; the operation data includes the multiplicand data matrix and the data matrix to be searched.

[0084] Specifically, the first memristor subarray described in the embodiments of this application refers to the memristor array portion in a multilayer memristor subarray used for performing matrix-vector multiplication operations.

[0085] The second memristor subarray described in the embodiments of this application refers to the memristor array portion in a multilayer memristor subarray used to perform matching operations.

[0086] In embodiments of this application, the computational data may specifically include a multiplicative data matrix and a searchable data matrix. It is understood that when performing matrix-vector multiplication, the computational data is the multiplicative data matrix; when performing a matching operation, the computational data is the searchable data matrix. The multiplicative data matrix is ​​pre-mapped and stored in a first memristor subarray, and the searchable data matrix is ​​pre-mapped and stored in a second memristor subarray.

[0087] It should be noted that when the result of the second operation is the final matrix-vector multiplication result, it specifically represents the data information obtained by calculating the data to be processed and the multiplied data matrix; when the result of the second operation is the final matching result, it specifically represents the data information of whether the data to be processed and the data matrix to be searched match successfully or not.

[0088] Based on the above embodiments, as an optional embodiment, the data to be processed includes first data for performing matrix-vector multiplication or second data for performing matching operations; correspondingly, the analog voltage signal includes a first analog voltage signal corresponding to the first data or a second analog voltage signal corresponding to the second data.

[0089] The bit lines include a first bit line disposed in the first memristor subarray and a second bit line disposed in the second memristor subarray; the first bit line is used to input a first analog voltage signal, and the second bit line is used to input a second analog voltage signal;

[0090] The first memristor subarray is used to perform matrix-vector multiplication on the first analog voltage signal and the multiplied data matrix; the second memristor subarray is used to perform matching operation on the second analog voltage signal and the data matrix to be searched.

[0091] The word line is used to output the operation result corresponding to the first data or the operation result corresponding to the second data; the first operation result includes the operation result corresponding to the first data or the operation result corresponding to the second data.

[0092] Specifically, in the embodiments of this application, the data to be processed includes first data used for matrix-vector multiplication or second data used for matching operations. After the first data or the second data is processed by the input voltage driving module, the corresponding analog voltage signal obtained includes the first analog voltage signal corresponding to the first data or the second analog voltage signal corresponding to the second data.

[0093] In embodiments of this application, the memristor array is controlled by bit lines (BL, SL, SLb) and word lines (WL). The bit lines include a first bit line (BL) disposed in a first memristor subarray and second bit lines (SL, SLb) disposed in a second memristor subarray. The first bit line (BL) consists of one bit line and is used to input a first analog voltage signal; the second bit lines (SL, SLb) consist of two bit lines and are used to input a second analog voltage signal. Thus, the first memristor subarray can perform matrix-vector multiplication on the first analog voltage signal and its stored multiplicand data matrix, and the second memristor subarray can perform data matching operations on the second analog voltage signal and its stored search data matrix.

[0094] Figure 3 This is one of the structural schematic diagrams of the three-dimensional self-rectified memristor array provided in the embodiments of this application, such as... Figure 3As shown in the embodiments of this application, the memristor array adopts a three-dimensional self-rectified memristor array with a total of t layers of memristor subarrays. Each layer of array is m×n in size, and the solid black dots in the array represent a memristor device. The three-dimensional self-rectified memristor array is directly interconnected via word lines WL to form a large array with an array size of m×N, where N=n×t. There are N bit lines and m word lines. The device on each bit line can be arbitrarily defined for matrix-vector multiplication operations, corresponding to the first bit line (BL); or it can be defined for exact matching operations, corresponding to the second bit line (SL, SLb).

[0095] The entire t-layer memristor subarray comprises two functional arrays: a first memristor subarray and a second memristor subarray. The first memristor subarray performs i-dimensional matrix-vector multiplication, with an array size of m×i. The first bit line corresponding to this i-dimensional matrix-vector multiplication has i bits, denoted as BL[0], BL[1], ..., BL[i-1]. The second memristor subarray performs j-dimensional exact matching operations, with an array size of m×2j. The second bit line corresponding to this j-dimensional exact matching operation has 2j bits, denoted as SL[0], SLb[0], SL[1], SLb[1], ..., SL[j-1], SLb[j-1]. Furthermore, m word lines are used to output the first operation result, denoted as WL[0], WL[1], ..., WL[m-1]. Here, i and j satisfy N = i + 2j.

[0096] In the embodiments of this application, the bit lines of the entire array are driven by an input voltage driving module to input analog voltage signals. The first bit lines BL[0], BL[1], ..., BL[i-1] respectively input the i-dimensional data corresponding to the first analog voltage signal, and the second bit lines SL[0], SLb[0], SL[1], SLb[1], ..., SL[j-1], SLb[j-1] respectively input the j-dimensional data corresponding to the second analog voltage signal. The word lines WL[0], WL[1], ..., WL[m-1] are used to output the calculation result corresponding to the first data in the form of current, or the calculation result corresponding to the second data in the form of voltage, and output them to a configurable current / voltage sensing module for analog-to-digital conversion.

[0097] The system in this application embodiment, by further subdividing the signal input of the memristor array and the allocation of bit lines and word lines, can make the memristor subarray that implements matrix-vector multiplication and the memristor subarray that implements matching operation more efficient, further improve the parallelism of system operation, reduce system time complexity, and improve system operation speed and efficiency.

[0098] Figure 4This is the second schematic diagram of the structure of the three-dimensional self-rectified memristor array provided in the embodiments of this application, as shown below. Figure 4 As shown, the memristor array has t = 2 layers of memristor subarrays. Each layer of memristor subarray has an array size of 4×8. The word lines of the two arrays are connected together vertically to form a 4×16 array, which has 4 word lines and 16 bit lines. The first memristor subarray stores a 6×4 multiplicative data matrix, and the second memristor subarray stores a 5×4 searchable data matrix.

[0099] Among them, 6 bit lines BL[0], BL[1], ..., BL[5] are used to input the first analog voltage signal of the 6-dimensional multiplication vector, and 10 bit lines SL[0], SLb[0], ..., SL[4], SLb[4] are used to input the second analog voltage signal of the 5-dimensional matching search vector.

[0100] The system in this application embodiment, by splitting the multilayer memristor subarray into a memristor array part for matrix-vector multiplication and a memristor array part for matching operations, with each array part used to store the multiplied data matrix and the search data matrix respectively, can efficiently realize both precise search and matrix-vector multiplication operations in the same memristor array, which is beneficial to further improve the efficiency and reliability of the system operation.

[0101] Figure 5 This is a schematic diagram illustrating the process of performing matrix-vector multiplication on a memristor array according to an embodiment of this application, as shown below. Figure 5 As shown, each column of stored data in the multiplied data matrix is ​​represented by a column of memristors in the first memristor subarray, where the high resistance state of the memristor represents the stored data as "0" and the low resistance state of the memristor represents the stored data as "1".

[0102] When the data input to one column of the first memristor subarray is "0", the corresponding analog voltage signal is defined as signal GND; when the data input to one column of the memristor is "1", the corresponding analog voltage signal is defined as signal Vs.

[0103] Among them, signal Vs is used to indicate the voltage signal of the memristor, and signal GND is used to indicate that the memristor is grounded.

[0104] Specifically, the embodiments in this application only illustrate an example of a single device storing binary data; in reality, multiple values ​​may be stored. The implementation of matrix-vector multiplication is as follows: Figure 5 As shown, the input multiplication vector can be represented as [a0, a1, ..., a...]. i-1The first analog voltage signal is input through the array bit lines of the first memristor subarray, namely the first bit lines BL[0], BL[1], ..., BL[i-1]. The first analog voltage signal can be represented as [V in[0] V in[1] , ..., V in[i-1] Among them, the second bit lines SL[0], SLb[0], ..., SL[j-1], and SLb[j-1] are all in a floating state.

[0105] Wherein, when the input first analog voltage signal is signal V S When the input is GND, it means the data a in the input multiplication vector is "1"; when the first input analog voltage signal is GND, it means the input data a is "0".

[0106] In the embodiments of this application, the multiplicative data matrix stored in the first memristor subarray can be represented as: {[b 0,0 b 0,1 , ..., b 0,i-1 ],[b 1,0 b 1,1 , ..., b 1,i-1 ],…,[b m-1,0 b m-1,1 , ..., b m-1,i-1 ]}, the i×m self-rectified memristor array, i.e., the first memristor subarray, can be mapped to a conductance matrix, which can be expressed as: {[R 0,0 R 0,1 , ..., R 0,i-1 ], [R 1,0 R 1,1 , ..., R 1,i-1 ],…,[R m-1,0 R m-1,1 , ..., R m-1,i-1 ]}.

[0107] Specifically, when the storage self-rectified memristor is in a high-resistance state (HRS), the corresponding stored data b is "0"; when the storage state is in a low-resistance state (LRS), the corresponding stored data b is "1"; the output result, i.e., the first operation result, can be represented as [c0, c1, ..., c m-1 The current is output from the array word line [I]. out[0] I out[1] , ..., I out[m-1] This indicates that the output current value is positively correlated with the matrix-vector multiplication result value c, which can be read out by the subsequent current sensing module.

[0108] The system in this application embodiment can effectively implement matrix-vector multiplication in the same memristor array by mapping the multiplicative data matrix stored in the memristor array with the memristor resistance state, thereby improving the speed and efficiency of the system in performing matrix-vector multiplication.

[0109] Figure 6 This is a schematic diagram of the process of performing a matching operation on a memristor array according to an embodiment of this application, as shown below. Figure 6 As shown, each column of stored data in the data matrix to be searched is represented by two columns of memristors in the second memristor subarray. In the two columns of memristors, the high resistance state of any memristor and its corresponding low resistance state represent the stored data as "0", the low resistance state of any memristor and its corresponding high resistance state represent the stored data as "1", and the high resistance state of any memristor and its corresponding high resistance state represent the stored data as "X". The stored data as "X" is used to characterize the state that is not of interest.

[0110] When the data input to the two columns of memristors in the second memristor subarray is "0", the two corresponding analog voltage signals are defined as a sequential combination of signals GND and Vs; when the data input to the two columns of memristors is "1", the two corresponding analog voltage signals are defined as a sequential combination of signals Vs and GND; when the data input to the two columns of memristors is "X", the two corresponding analog voltage signals are defined as a combination of signals GND and GND.

[0111] Specifically, in the embodiments of this application, the process of the second memristor subarray performing the matching operation is as follows: Figure 6 As shown, the binary input search vector can be represented as [q0, q1, ..., q]. j-1 The second analog voltage signal is input through the array bit lines of the second memristor subarray, namely the second bit lines SL[0], SLb[0], ..., SL[j-1], SLb[j-1]. This voltage signal can be represented as [V in[0] V inb[0] V in[1] V inb[1] , ..., V in[j-1] V inb[j-1] Among them, the first line BL[0], BL[1], ..., BL[i-1] are all in a floating state.

[0112] Among them, the input voltage (V) in V inb ) represents a one-dimensional binary input data q, when the corresponding second analog voltage signal is a sequential combination of signal Vs and signal GND (V S When GND is the input signal, it means the input data q is "1"; when the input second analog voltage signal is GND and V, it means the input data q is "1". SThe sequential combination (GND, V) S When the input voltage signal is GND, it means the input data q is "0"; when the input voltage signal is a combination of GND and GND (GND, GND), it means the input data q is "X", which means the state is not important.

[0113] In the embodiments of this application, the searchable data matrix stored in the second memristor subarray can be represented as {[d 0,0 d 0,1 , ...,d 0,j-1 ],[d 1,0 d 1,1 , ...,d 1,j-1 ],…,[d m-1,0 d m-1,1 , ...,d m-1,j-1 The second memristor subarray, with a size of 2j×m, can be mapped to a conductance matrix and expressed as: {[M 0,0 Mb 0,0 M 1,0 Mb 0,1 M 0,j-1 Mb 0,j-1 ], [M 1,0 Mb 1,0 M 1,1 Mb 1,1 M 1,j-1 Mb 1,j-1 ],…,[M m-1,0 Mb m-1,0 M m-1,1 Mb m-1,1 M m-1,j-1 Mb m-1,j-1 ]}.

[0114] In this context, the memory state (M, Mb) represents a binary stored data d. When it is (LRS, HRS), it means the stored data d of the memristor is "0"; when it is (HRS, LRS), it means the stored data d of the memristor is "1"; and when it is (HRS, HRS), it means the stored data d of the memristor is "X". The matching result, i.e., the first operation result, can be represented as [s0, s1, ..., s...]. m-1 The voltage output from the array word line is [V]. out[0] V out[1] , ..., V out[m-1] This indicates that when the output voltage is high, it represents "mismatch"; when the output voltage is low, it represents "successful match".

[0115] It should be noted that when performing voltage readout, due to the self-rectifying characteristics of the self-rectifying memristor, devices with an input voltage of GND are always reverse readout resistors, which are much higher than the device's high-resistance state, approximately equivalent to an open circuit. When mismatched, it is connected to V... S The device on the line is in a low-resistance state, which forms a charging circuit, causing the word line voltage to rise; while during matching, the device connected to V... S All the devices on the device are in a high-impedance state, so they are not charged and the word line voltage does not increase.

[0116] The system in this application embodiment can effectively perform matching operations in the same memristor array by mapping the search data matrix stored in the memristor array with the memristor resistance states, thereby improving the speed and efficiency of the system in performing matching operations.

[0117] Figure 7 This is a schematic diagram illustrating the result of matrix-vector multiplication operations implemented by a three-dimensional self-rectified memristor array according to an embodiment of this application, as shown below. Figure 7 As shown, the data stored in the 6×4 self-rectified memristor array is [100110,111010,001110,011011], where "1" corresponds to LRS with a resistance of 17.7MΩ; and "0" corresponds to HRS with a resistance of 294MΩ. When performing matrix-vector multiplication, the input data for the word line is [011011], at which point "1" corresponds to signal V. S This means a 2V input voltage; "0" corresponds to the signal GND, which is grounded. The output is in current form, and the word line output is essentially grounded. According to Ohm's law and Kirchhoff's current law, the output currents of the four word lines are 0.907μA, 2.705μA, 1.806μA, and 3.604μA, respectively. According to the correspondence table between output current and multiplication result (MACV), the output MACVs are 1, 3, 2, and 4, respectively, which matches the expectation.

[0118] Figure 8 This is a schematic diagram illustrating the result of precise matching operation achieved by the three-dimensional self-rectified memristor array provided in the embodiments of this application, as shown below. Figure 8 As shown, the 10×4 self-rectified memristor array stores 5×4 data of size [010X1, X0X10, 1X0X1, 10011], where each data is represented by two self-rectified memristors: "1" corresponds to (HRS, LRS), "0" corresponds to (LRS, HRS), and "X" corresponds to (HRS, HRS). When a search is performed, the input search data for the word line is [01X01], at which point "1" corresponds to (V... S "0" corresponds to (GND, V) S “X” corresponds to (GND, GND). The output result is output in voltage form, and at this time the word line output terminal is equivalent to an open circuit.

[0119] Since the word line voltage is between 0-2V, devices connected to GND are essentially in reverse read mode and have extremely high resistance. Therefore, the main resistance is V. S The word line is determined by the impedance state of the devices at the input and output terminals. When a low-impedance device is present, the word line is quickly charged to a high level; when all devices are in high-impedance state, the word line cannot be charged and remains low. The word line charging levels at certain moments are 0.01V, 1.98V, 1.87V, and 1.97V. A voltage comparison reference voltage of 1V can be set. When the word line voltage is higher than the reference voltage, the input vector does not match; when it is lower than the reference voltage, it matches. Based on the voltage results, the output results are "Match", "Mismatch", "Mismatch", and "Mismatch", which is as expected.

[0120] Based on the above embodiments, as an optional embodiment, the memristor array includes a resistive random access memory array, a ferroelectric memory array, a phase change memory array, a magnetic random access memory array, or a non-volatile flash memory device array.

[0121] Specifically, in the embodiments of this application, the memristor array can be a resistive random access memory array, a ferroelectric memory array, a phase-change memory array, a magnetic random access memory array, or a non-volatile flash memory array. The non-volatile flash memory array includes a NOR Flash memory array or a NAND Flash memory array.

[0122] The spatial arrangement structure of the memristor array includes a three-dimensional horizontal stacking structure similar to a 3D X-Point structure or a three-dimensional vertical stacking structure similar to a 3D V-NAND flash memory, and this application does not specifically limit it.

[0123] The system in this application embodiment utilizes different types of memory arrays and arrangement structures to construct memristor arrays, which can increase the diversity of memristor array fabrication methods, reduce the fabrication cost of memristor arrays, and thus reduce the fabrication cost of the entire in-memory computing circuit.

[0124] Figure 9 This is a flowchart illustrating the computation method of the three-dimensional in-memory computing system provided in this application embodiment, which can be applied to any of the aforementioned three-dimensional in-memory computing systems, such as... Figure 9 As shown, the method includes:

[0125] Step S1: Convert the input data to be processed into an analog voltage signal;

[0126] Step S2: Perform matrix-vector multiplication or matching operations on the pre-stored computation data and the analog voltage signal, and output the first computation result of the data to be processed.

[0127] Step S3: Based on the signal form of the first operation result, convert the first operation result into a corresponding digital signal;

[0128] Step S4: Analyze the digital signal to determine the second operation result of the data to be processed.

[0129] It should be understood that the method in the above embodiments is applied to the aforementioned three-dimensional in-memory computing system, and its implementation principle and technical effect are similar to those described in the above system. The detailed process of this method can be referred to the corresponding description process in the above system, and will not be repeated here.

[0130] The computational method of the three-dimensional in-memory computing system in this application embodiment uses an input module to convert the input data to be processed into an analog voltage signal. The memristor array performs matrix-vector multiplication or matching operations on the stored computation data and the analog voltage signal. Combined with the processing and analysis of the computation results by the sensing module and the main processor, both precise lookup and matrix multiplication functions can be realized in the same memristor array. This can effectively reduce the storage area and power consumption of the system, improve the system's computing speed and efficiency, and at the same time, achieve system reconfigurability without introducing additional arrays and circuits. It can adapt to the functional requirements of precise matching or matrix multiplication operations and is conducive to improving the integration density of the system circuit and the array size.

[0131] In another specific embodiment of this application, a parallel computing method for a three-dimensional in-memory computing system is also provided. In this method, the memristor array is a three-dimensional self-rectified memristor array, and the specific steps include:

[0132] Step 110: Determine which operational function the three-dimensional self-rectified memristor array needs to implement, and configure the sensing mode of the corresponding configurable current / voltage sensing module.

[0133] Step 120: Initialization operation, turn on all discharge transistors to discharge each word line to ground; after initialization is complete, turn off all discharge transistors.

[0134] Step 130: The main processor inputs the data to be processed, including multiplication data (i.e., the first data) or search data (i.e., the second data), into the input voltage drive module to convert it into the corresponding analog voltage signal and input it in parallel to each bit line of the three-dimensional self-rectified memristor array. The voltage or current signal is output in parallel according to the sensing mode to obtain the first calculation result.

[0135] Step 140: The configurable current / voltage sensing module converts the aforementioned current or voltage signals on the matching line into corresponding digital signal results according to the sensing mode. When sensing voltage, it outputs digital results "0" and "1" according to the voltage level, representing "matching successfully" and "mismatching" respectively; when sensing current, it directly outputs the digital result of the read current value.

[0136] Step 150: The main processor performs digital analysis based on the digital signal output by the configurable current / voltage sensing module to obtain the second calculation result, which is the final matching result or multiplication result corresponding to the data to be processed.

[0137] In summary, the technical solutions provided in this application, compared with the prior art, can achieve the following beneficial effects:

[0138] (1) The three-dimensional in-memory computing system provided in this application can perform one array operation in one array parallel read operation, which has the advantages of low time complexity and high parallelism;

[0139] (2) The three-dimensional in-memory computing system provided in this application can realize two operation functions, matrix-vector multiplication or precise search, by switching the sensing mode of the configurable current / voltage sensing module according to the operation requirements. This achieves the reconfigurability of the system without introducing additional arrays and circuits, reducing the area and power consumption of the system, and has versatility.

[0140] (3) The three-dimensional in-memory computing system provided in this application adopts a three-dimensional stacked structure, which has the characteristics of high integration density and large array size.

[0141] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0142] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0143] Furthermore, the mathematical concepts mentioned in the embodiments of this application, such as symmetry, equality, parallelism, and perpendicularity, are limitations specific to the current technological level, rather than absolute and strict mathematical definitions. Slight deviations are permissible; approximations of symmetry, equality, parallelism, and perpendicularity are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional in-memory computing system, characterized in that, include: The input module, whose input terminal is connected to the output terminal of the main processor, is used to convert the data to be processed into an analog voltage signal; A memristor array, whose input terminal is connected to the output terminal of the input module, is used to perform matrix-vector multiplication or matching operations on the pre-stored computation data and the analog voltage signal, and output the first computation result of the data to be processed; The sensing module, whose input is connected to the output of the memristor array, is used to convert the first calculation result into a corresponding digital signal based on the signal form of the first calculation result. And a main processor, whose first input terminal is used to receive the data to be processed, and whose second input terminal is connected to the output terminal of the sensing module, for analyzing the digital signal and determining the second operation result of the data to be processed; The memristor array includes multiple memristor subarrays, each column of memristors in each layer of the memristor subarray is connected by bit lines, and each row of memristors in each layer of the memristor subarray is vertically interconnected by word lines. The memristor subarrays in each layer are connected by word lines; the number of bit lines and word lines are determined according to the size of the memristor subarray. The bit lines are used to input the analog voltage signal; the word lines are used to output the first calculation result of the data to be processed. The multilayer memristor subarray includes a first memristor subarray and a second memristor subarray. The bit line includes a first bit line disposed in the first memristor subarray and a second bit line disposed in the second memristor subarray; the first bit line is used to input a first analog voltage signal, and the second bit line is used to input a second analog voltage signal; The first memristor subarray is used to store the multiplicand data matrix and perform matrix-vector multiplication on the first analog voltage signal and the multiplicand data matrix; the second memristor subarray is used to store the search data matrix and perform matching operation on the second analog voltage signal and the search data matrix; the operation data includes the multiplicand data matrix and the search data matrix.

2. The three-dimensional in-memory computing system according to claim 1, characterized in that, Each word line is connected to a discharge transistor; the discharge transistor is used to perform data initialization operations before matrix-vector multiplication or matching operations are performed on the memristor array.

3. The three-dimensional in-memory computing system according to claim 1, characterized in that, The data to be processed includes first data for matrix-vector multiplication or second data for matching operations; correspondingly, the analog voltage signal includes a first analog voltage signal corresponding to the first data or a second analog voltage signal corresponding to the second data. The word line is used to output the calculation result corresponding to the first data or the calculation result corresponding to the second data; the first calculation result includes the calculation result corresponding to the first data or the calculation result corresponding to the second data.

4. The three-dimensional in-memory computing system according to claim 1, characterized in that, Each column of stored data in the multiplied data matrix is ​​represented by a column of memristors in the first memristor subarray, wherein the high resistance state of the memristor represents the stored data as "0" and the low resistance state of the memristor represents the stored data as "1". When the data input to one column of memristors in the first memristor subarray is "0", the corresponding input analog voltage signal is defined as signal GND; when the data input to one column of memristors is "1", the corresponding input analog voltage signal is defined as signal Vs. Among them, signal Vs is used to indicate the voltage signal of the memristor, and signal GND is used to indicate that the memristor is grounded.

5. The three-dimensional in-memory computing system according to claim 3, characterized in that, Each column of stored data in the search data matrix is ​​represented by two columns of memristors in the second memristor subarray. Specifically, in the two memristors, the high-resistance state of any memristor and its corresponding low-resistance state represent stored data as "0", the low-resistance state of any memristor and its corresponding high-resistance state represent stored data as "1", and the high-resistance state of any memristor and its corresponding high-resistance state represent stored data as "X". The stored data "X" represents an indifferent state. When the data input to the two columns of memristors in the second memristor subarray is "0", the two corresponding analog voltage signals are defined as a sequential combination of signal GND and signal Vs. When the data input to the two columns of memristors is "1", the two corresponding analog voltage signals are defined as a sequential combination of signal Vs and signal GND. When the data input to the two columns of memristors is "X", the two corresponding analog voltage signals are defined as a combination of signal GND and signal GND.

6. The three-dimensional in-memory computing system according to any one of claims 1-5, characterized in that, The memristor array includes resistive random access memory arrays, ferroelectric memory arrays, phase change memory arrays, magnetic random access memory arrays, or non-volatile flash memory arrays.

7. The three-dimensional in-memory computing system according to any one of claims 1-5, characterized in that, The spatial arrangement structure of the memristor array includes a three-dimensional horizontal stacking structure or a three-dimensional vertical stacking structure.

8. A computational method applied to a three-dimensional in-memory computing system as described in any one of claims 1-7, characterized in that, include: Convert the input data to be processed into an analog voltage signal; Perform matrix-vector multiplication or matching operations on the pre-stored computation data and the analog voltage signal, and output the first computation result of the data to be processed; Based on the signal form of the first calculation result, the first calculation result is converted into a corresponding digital signal; The digital signal is analyzed to determine the second operation result of the data to be processed.

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