Method for preparing multi-bit quantum entangled state

Abstract

The application discloses a multi-bit quantum entangled state preparation method. The multi-bit quantum entangled state preparation method comprises the following steps: determining a candidate arc queue according to a physical topology structure of a target quantum computer and a starting bit, wherein the candidate arc queue comprises a plurality of candidate arcs; obtaining a preparation cost of each candidate arc according to the candidate arc queue and the physical topology structure; determining a target candidate arc according to the preparation cost; and obtaining a preparation circuit according to the target candidate arc, so as to prepare a multi-bit quantum entangled state according to the preparation circuit. In this way, the computer device can select the target candidate arc by using the preparation cost, so as to construct the preparation circuit by using quantum bits with relatively low noise and high quality corresponding to the target candidate arc, reduce the circuit depth of the preparation circuit, and make the multi-bit quantum entangled state prepared by the target quantum computer more reliable in actual application, thereby enhancing the practicability and performance of quantum computation based on the multi-bit quantum entangled state.

Description

Technical Field

[0001] This application relates to the field of quantum computing, and more specifically, to a method for preparing multi-qubit quantum entangled states. Background Technology

[0002] Multi-qubit entangled states are an important resource in quantum computing, widely used in quantum algorithms, quantum communication, and quantum cryptography. In related technologies, preparing multi-qubit entangled states is not only a prerequisite for many quantum algorithms but also an important metric for evaluating the performance of quantum computers. However, due to limitations imposed by the topological structure of quantum computers on multi-qubit entangled states, the prepared multi-qubit entangled states are often not stable enough. Summary of the Invention

[0003] This application provides a method for preparing multi-qubit quantum entangled states.

[0004] This application provides a method for preparing a multi-qubit quantum entangled state, the method comprising:

[0005] A candidate arc queue is determined based on the physical topology and starting bit of the target quantum computer, and the candidate arc queue includes multiple candidate arcs;

[0006] The preparation cost of each candidate arc is obtained based on the candidate arc queue and the physical topology.

[0007] The target candidate arc is determined based on the aforementioned preparation cost;

[0008] The preparation circuit is obtained based on the target candidate arc, so that the target quantum computer can prepare the multi-bit quantum entangled state based on the preparation circuit.

[0009] Thus, the computer device determines a queue of candidate arcs based on the physical topology of the target quantum computer and the starting bit. This queue comprises multiple candidate arcs. The physical topology describes how the qubits are interconnected and how their interactions occur; the candidate arc queue can be determined from the physical topology based on the determined starting bit. Next, the computer calculates the preparation cost for each candidate arc based on the queue and the physical topology. This preparation cost indicates the noise level of the qubits corresponding to different candidate arcs. Then, the computer determines the target candidate arc based on the preparation cost, selecting the qubit with relatively low noise and high quality corresponding to the target candidate arc. Finally, the computer obtains a preparation circuit based on the target candidate arc, enabling the target quantum computer to prepare a multi-qubit entangled state. In this way, the computer selects the target candidate arc based on the preparation cost, using the qubit with relatively low noise and high quality corresponding to the target candidate arc to construct the preparation circuit. This reduces the number of quantum gates and the circuit depth required for the preparation circuit, making the multi-qubit entangled state prepared by the preparation circuit more reliable in practical applications and enhancing the practicality and performance of quantum computing based on this multi-qubit entangled state. Furthermore, it can automatically adjust the GHZ state preparation circuit based on the connection relationship between qubits.

[0010] In some implementations, the starting bit is determined in response to user input.

[0011] In this way, the computer determines the starting bit in response to user input. Thus, the user can specify a qubit as the starting bit according to specific quantum algorithm requirements, obtain different fabrication circuits, and then obtain the final fabrication cost corresponding to each fabrication circuit. The fabrication circuit with the lowest final fabrication cost is selected as the fabrication circuit for fabricating multi-qubit quantum entangled states.

[0012] In some implementations, an arbitrary qubit in the physical topology is used as the starting bit.

[0013] In this way, the computer uses any qubit in the physical topology as the starting bit. The computer can then select any qubit in the physical topology as the starting bit to obtain different fabrication circuits, and then obtain the final fabrication cost corresponding to each fabrication circuit. The circuit with the lowest final fabrication cost is selected as the fabrication circuit for fabricating multi-qubit quantum entangled states.

[0014] In some implementations, determining the candidate arc queue based on the physical topology and starting bit of the target quantum computer includes:

[0015] All the qubits of the fabricated circuit are used together as the starting bit;

[0016] Determine all outgoing edges of the starting bit based on the physical topology;

[0017] The candidate arc queue is determined based on the outgoing edges.

[0018] In this way, the computer uses all the qubits of the fabricated circuit as the starting bit. Next, the computer determines all outgoing edges of the starting bit based on the physical topology. Finally, the computer determines a queue of candidate arcs based on these outgoing edges. This process of determining all outgoing edges of the starting bit and then using these outgoing edges to determine the queue of candidate arcs helps optimize the use of qubits, reduces unnecessary quantum gate operations, and thus improves the efficiency of circuit fabrication.

[0019] In some implementations, obtaining the preparation cost of each candidate arc based on the candidate arc queue and the physical topology includes:

[0020] Set the expected number of qubits;

[0021] If the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, calculate the current fabrication depth after the control NOT gate corresponding to the current candidate arc is added to the fabrication circuit.

[0022] The fabrication cost of the current candidate arc is obtained based on the current fabrication depth, the candidate arc queue, and the physical topology.

[0023] Thus, the computer sets the expected number of qubits, determined by the algorithm's requirements and computational complexity. Next, assuming the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, the computer calculates the current fabrication depth after adding the control NOT gate corresponding to the current candidate arc to the fabrication circuit. Finally, the computer obtains the fabrication cost of the current candidate arc based on the current fabrication depth, the candidate arc queue, and the physical topology. In this way, the computer obtains the current fabrication depth and can calculate the fabrication cost of the current candidate arc; the fabrication cost can be used to subsequently evaluate the quality of the fabrication circuit.

[0024] In some implementations, obtaining the fabrication cost of the current candidate arc based on the current fabrication depth, the candidate arc queue, and the physical topology includes:

[0025] The current single-bit gate error rate, current double-bit gate error rate, current read error, and current relaxation time are obtained based on the current starting bit of the current candidate arc, the current ending bit of the current candidate arc, and the physical topology substructure corresponding to the current candidate arc in the physical topology structure.

[0026] The fabrication cost of the current candidate arc is obtained based on the current single-bit gate error rate, the current double-bit gate error rate, the current read error, the current relaxation time, and the current fabrication depth.

[0027] Thus, the computer obtains the current single-qubit gate error rate, current two-qubit gate error rate, current read error, and current relaxation time based on the current starting bit, the current ending bit, and the corresponding physical topological substructure in the physical topology. These parameters reflect the reliability of the qubits and quantum logic gates. Next, the computer calculates the fabrication cost of the current candidate arc based on the current single-qubit gate error rate, current two-qubit gate error rate, current read error, current relaxation time, and current fabrication depth. This comprehensive evaluation of the fabrication cost of the current candidate arc provides a crucial basis for selecting target candidate arcs. This fabrication cost considers the reliability of the qubits, the complexity of the fabrication circuit, and the fidelity of quantum operations.

[0028] In some implementations, the preparation cost of the current candidate arc is calculated using the following formula: COST = W readout E readout +W single E single +W double E double +W depth D+(1-W time )T,

[0029] Among them, W readout To read the error weight, E readout For the current read error, W single E is the weight for the single-bit gate error rate. single W represents the current single-bit gate error rate. double E is the weight for the two-bit gate error rate. double Let W be the current two-bit gate error rate. depth The current fabrication depth is the weight, where D is the current fabrication depth, and W is the weight. time The relaxation time weight is T, where T is the current relaxation time. The read error weight, the single-bit gate error rate weight, the double-bit gate error rate weight, the current preparation depth weight, and the relaxation time weight are all preset.

[0030] Thus, the computer calculates according to the formula COST = W readout E readout +W single E single +W double E double +W depth D+(1-W time)T calculates the preparation cost of the current candidate arc, where W readout To read the error weight, E readout A read error has occurred. single E is the weight for the single-bit gate error rate. single Given the current single-bit gate error rate, W double E is the weight for the two-bit gate error rate. double Given the current two-bit gate error rate, W depth The current fabrication depth is the weight, D is the current fabrication depth, and W is the weight. time The relaxation time weight is T, where T is the current relaxation time. Read error weight, single-qubit gate error rate weight, two-qubit gate error rate weight, current fabrication depth weight, and relaxation time weight are all preset. In this way, the computer obtains the fabrication cost by comprehensively considering the reliability of the qubits, the complexity of the fabrication circuit, and the fidelity of quantum operations, providing an important basis for subsequent selection of target candidate arcs.

[0031] In some embodiments, determining the target candidate arc based on the preparation cost includes:

[0032] The candidate arc with the lowest preparation cost is determined as the target candidate arc.

[0033] In this way, the computer identifies the candidate arc with the lowest preparation cost as the target candidate arc. By identifying the candidate arc with the lowest preparation cost as the target candidate arc, the computer can subsequently construct a preparation circuit based on the corresponding qubits with relatively low noise and high quality, thereby improving the compatibility and efficiency of multi-qubit quantum entangled states prepared using the preparation circuit.

[0034] In some embodiments, obtaining the fabrication circuit based on the target candidate arc includes:

[0035] The fabrication circuit is obtained by adding a control NOT gate corresponding to the target candidate arc according to the physical topology.

[0036] Thus, the computer adds control NOT gates corresponding to the target candidate arcs according to the physical topology to obtain the fabrication circuit. By analyzing the physical topology, the computer determines the specific location and connection method of the target candidate arcs in the physical circuit, and then adds control NOT gates corresponding to the target candidate arcs at those specific locations on the corresponding fabrication circuit. This results in an optimal fabrication circuit that conforms to the physical topology of the target quantum computer, while also possessing a high degree of parallelism and shallow circuit depth. This makes the multi-qubit quantum entangled states fabricated based on this circuit more reliable in practical applications.

[0037] In some embodiments, the method further includes:

[0038] The state of the fabrication circuit is updated when a control NOT gate corresponding to the target candidate arc is added according to the physical topology.

[0039] Thus, by adding control NOT gates corresponding to the target candidate arc based on the physical topology, the computer updates the state of the fabrication circuit. In this way, by updating the state of the fabrication circuit, it is ensured that the selected target candidate arc always has the lowest fabrication cost within the same time period.

[0040] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0041] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0042] Figure 1 This is one of the flowcharts illustrating the method for preparing multi-bit quantum entangled states according to an embodiment of this application;

[0043] Figure 2 This is a second schematic flowchart of the method for preparing multi-bit quantum entangled states according to the embodiments of this application;

[0044] Figure 3 This is the third flowchart illustrating the method for preparing multi-qubit quantum entangled states according to the embodiments of this application;

[0045] Figure 4 This is the fourth flowchart illustrating the method for preparing multi-qubit quantum entangled states according to the embodiments of this application;

[0046] Figure 5 This is the fifth flowchart illustrating the method for preparing multi-qubit quantum entangled states according to the embodiments of this application;

[0047] Figure 6 This is the sixth flowchart illustrating the method for preparing multi-qubit quantum entangled states according to the embodiments of this application;

[0048] Figure 7 This is the seventh flowchart illustrating the method for preparing multi-bit quantum entangled states according to the embodiments of this application;

[0049] Figure 8 This is the eighth flowchart illustrating the method for preparing multi-bit quantum entangled states according to the embodiments of this application;

[0050] Figure 9 This is a schematic diagram of a conventional fabrication circuit for the multi-bit quantum entangled state fabrication method according to the embodiments of this application;

[0051] Figure 10 This is a schematic diagram of the physical topology of the quantum computer according to an embodiment of this application;

[0052] Figure 11 This is a schematic diagram of the fabrication circuit of the multi-bit quantum entangled state fabrication method according to the embodiments of this application;

[0053] Figure 12 This is a schematic diagram of the Hadamard gate for the multi-bit quantum entangled state preparation method according to the embodiments of this application;

[0054] Figure 13 This is a schematic diagram of the controlled NOT gate of the multi-bit quantum entangled state preparation method according to the embodiments of this application. Detailed Implementation

[0055] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application.

[0056] Multi-qubit entangled states, or GHz states, are an important resource in quantum computing, widely used in quantum algorithms, quantum communication, and quantum cryptography. In related technologies, preparing multi-qubit entangled states is not only a prerequisite for many quantum algorithms but also an important metric for evaluating the performance of quantum computers. However, due to limitations imposed by the topological structure of quantum computers on multi-qubit entangled states, the prepared multi-qubit entangled states are often not stable enough.

[0057] This is mainly reflected in the fact that, due to the limitations of the topological structure of quantum computers and the influence of decoherent factors such as single-qubit gate noise and double-qubit gate noise, GHZ states prepared in different qubit selection areas on the same quantum computer often have different performance characteristics. On the other hand, GHZ states prepared in the same qubit selection area are also affected by the depth of the preparation circuit. GHZ states prepared by circuits with greater circuit depth are often less stable.

[0058] Quantum decoherence refers to the phenomenon in quantum mechanics where the quantum coherence of an open quantum system is gradually lost over time due to quantum entanglement with its external environment.

[0059] Based on the above issues, please refer to Figure 1 This application provides a method for preparing multi-qubit quantum entangled states, the method comprising:

[0060] 011: Determine the candidate arc queue based on the physical topology and starting bit of the target quantum computer. The candidate arc queue includes multiple candidate arcs.

[0061] 012: The preparation cost of each candidate arc is obtained based on the candidate arc queue and physical topology;

[0062] 013: Determine the target candidate arc based on the preparation cost;

[0063] 014: Obtain the preparation circuit based on the target candidate arc so that the target quantum computer can prepare multi-bit quantum entangled states based on the preparation circuit.

[0064] This application also provides a computer device, including a memory and a processor. The method for preparing multi-qubit quantum entangled states according to this application can be implemented by the computer device described in this application. Specifically, the memory stores a computer program, and the processor is used to determine a candidate arc queue based on the physical topology of the target quantum computer and the starting qubit, the candidate arc queue including multiple candidate arcs. It also determines the preparation cost of each candidate arc based on the candidate arc queue and the physical topology. The processor is further used to determine a target candidate arc based on the preparation cost, and to obtain a preparation circuit based on the target candidate arc, so as to prepare a multi-qubit quantum entangled state according to the preparation circuit.

[0065] This application also provides a multi-qubit quantum entangled state preparation apparatus. The multi-qubit quantum entangled state preparation method of this application can be implemented by the multi-qubit quantum entangled state preparation apparatus of this application. Specifically, the multi-qubit quantum entangled state preparation apparatus includes a determining module and a processing module. The determining module is used to determine a candidate arc queue based on the physical topology of the target quantum computer and the starting qubit, the candidate arc queue including multiple candidate arcs. The processing module is used to obtain the preparation cost of each candidate arc based on the candidate arc queue and the physical topology. The determining module is used to determine the target candidate arc based on the preparation cost. The processing module is used to obtain a preparation circuit based on the target candidate arc, so as to prepare a multi-qubit quantum entangled state based on the preparation circuit.

[0066] Specifically, a multi-qubit quantum entanglement state (Greenberger-Horne-Zeilinger, CHZ) is a special type of quantum entanglement state involving two or more qubits. Its characteristic is that all qubits are in a quantum superposition of states 0 and 1. Multi-qubit quantum entanglement states are a key resource for quantum computing and form the basis of many quantum computing algorithms.

[0067] A quantum bit is the basic unit of quantum computing. It can represent both 0 and 1 states simultaneously, or a superposition of these two states, and is used to store and process quantum information.

[0068] A quantum state is a fundamental concept in quantum mechanics used to describe quantum systems. It is usually represented by a wave function or density matrix and is used to describe all possible states of a quantum system and their probabilities.

[0069] A quantum circuit consists of a series of quantum gates that describe how the gates operate on the state of a qubit. It is the foundation for realizing quantum algorithms and quantum information processing.

[0070] A quantum gate, also called a quantum logic gate, is the basic operational unit in quantum computing, similar to a logic gate in a circuit. By applying specific quantum algorithms, the rotation, flipping, or more complex operations on qubits can be achieved, thus realizing the basic functions of quantum computing.

[0071] The physical topological structure of a quantum computer refers to how multiple qubits are connected to form a computable system. Different physical topologies directly affect important factors such as the scalability, error correction capability, and computational speed of a quantum computer. The multi-qubit quantum entangled state preparation method of this application is applicable to various physical topologies of quantum computers, such as fully connected topologies, linear topologies, and other complex topologies.

[0072] The computer determines a queue of candidate arcs based on the physical topology of the target quantum computer and the starting bit. This queue comprises multiple candidate arcs. The physical topology describes how the qubits are interconnected and how their interactions occur; the candidate arc queue can be determined from the physical topology based on the given starting bit. Next, the computer calculates the fabrication cost for each candidate arc based on the queue and the physical topology. This cost indicates the noise level and other characteristics of the qubits corresponding to different candidate arcs. Then, the computer determines the target candidate arc based on the fabrication cost, selecting the qubit with relatively low noise and high quality. Finally, the computer obtains a fabrication circuit based on the target candidate arc to fabricate a multi-qubit entangled quantum state.

[0073] In summary, the multi-qubit quantum entangled state preparation method of this application enables the computer to select target candidate arcs based on preparation cost, and to construct preparation circuits using qubits with relatively low noise and high quality corresponding to the target candidate arcs. This significantly reduces the number of quantum gates and circuit depth required for the preparation circuits, making the multi-qubit quantum entangled states prepared by the preparation circuits more reliable in practical applications, and enhancing the practicality and performance of quantum computing based on the multi-qubit quantum entangled states.

[0074] Please see Figure 2In some implementations, the method further includes:

[0075] 015: In response to user input, determine the starting bit, or use any qubit in the physical topology as the starting bit.

[0076] In some implementations, the processing module is used to determine the starting bit in response to user input, or to use any qubit in the physical topology as the starting bit.

[0077] In some implementations, the processor is also configured to determine a starting bit in response to user input, or to use any qubit in the physical topology as the starting bit.

[0078] Specifically, the computer device determines the starting bit in response to user input, or uses any quantum bit in the physical topology as the starting bit.

[0079] In this way, users can specify a qubit as the starting bit according to the specific requirements of the quantum algorithm. Alternatively, the computer device can select any qubit in the physical topology as the starting bit to obtain different fabrication circuits, then obtain the final fabrication cost corresponding to each fabrication circuit, and select the fabrication circuit with the minimum final fabrication cost as the fabrication circuit for fabricating multi-qubit quantum entangled states.

[0080] Please see Figure 3 In some implementations, step 011 (determining the candidate arc queue based on the physical topology of the target quantum computer and the starting bit) includes:

[0081] 0111: Use all the qubits of the circuit as the starting bit;

[0082] 0112: Determine all outgoing edges of the starting bit based on the physical topology;

[0083] 0113: Determine the candidate arc queue based on the outgoing edges.

[0084] In some implementations, the processing module is used to take all the qubits of the fabricated circuit as the starting bit. The determination module is used to determine all outgoing edges of the starting bit based on the physical topology. The determination module is also used to determine a queue of candidate arcs based on the outgoing edges.

[0085] In some implementations, the processor is also used to use all the qubits of the fabricated circuit as a starting bit, and to determine all outgoing edges of the starting bit based on the physical topology. Furthermore, it determines a queue of candidate arcs based on the outgoing edges.

[0086] Specifically, an outgoing edge refers to an edge in a physical topology that originates from a certain vertex. In the embodiments of this application, it refers to all edges originating from the starting bit, except for the edges between the qubits of the fabrication circuit.

[0087] Candidate arcs refer to the links between the qubits corresponding to the outgoing edges.

[0088] The computer uses all the qubits of the fabricated circuit as the starting bit. Next, the computer determines all outgoing edges from the starting bit based on the physical topology. Finally, the computer determines a queue of candidate arcs based on the outgoing edges.

[0089] In this way, determining all outgoing edges of the starting bit and identifying candidate arc queues based on these outgoing edges helps optimize the use of qubits, reduce unnecessary quantum gate operations, and thus improve the efficiency of circuit fabrication.

[0090] Please see Figure 4 In some implementations, step 012 (obtaining the fabrication cost of each candidate arc based on the candidate arc queue and physical topology) includes:

[0091] 0121: Set the expected number of qubits;

[0092] 0122: If the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, calculate the current fabrication depth after the control NOT gate corresponding to the current candidate arc is added to the fabrication circuit;

[0093] 0123: The fabrication cost of the current candidate arc is obtained based on the current fabrication depth, candidate arc queue, and physical topology.

[0094] In some implementations, the setting module is used to set the expected number of qubits. The calculation module is used to calculate the current fabrication depth after the control NOT gate corresponding to the current candidate arc is added to the fabrication circuit, provided that the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits. The processing module is used to obtain the fabrication cost of the current candidate arc based on the current fabrication depth, the candidate arc queue, and the physical topology.

[0095] In some implementations, the processor is also used to set the expected number of qubits, and, if the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, to calculate the current fabrication depth after the control NOT gate corresponding to the current candidate arc is added to the fabrication circuit. And, based on the current fabrication depth, the candidate arc queue, and the physical topology, to obtain the fabrication cost of the current candidate arc.

[0096] Specifically, the expected number of qubits refers to the maximum number of qubits in the fabricated circuit obtained according to the multi-qubit quantum entangled state preparation method.

[0097] The controlled-NOT gate (CNOT) is a fundamental gate in quantum computing, playing a crucial role in the process. A CNOT gate is a two-qubit gate consisting of a control qubit and a target qubit.

[0098] The computer sets the expected number of qubits, determined by the algorithm's requirements and computational complexity. Next, assuming the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, the computer calculates the current fabrication depth after adding the control NOT gate corresponding to the current candidate arc to the fabrication circuit. Finally, the computer obtains the fabrication cost of the current candidate arc based on the current fabrication depth, the candidate arc queue, and the physical topology.

[0099] In this way, the computer obtains the current fabrication depth and can calculate the fabrication cost of the current candidate arc. The fabrication cost can be used to judge the quality of the fabricated circuit.

[0100] Please see Figure 5 In some implementations, step 0123 (obtaining the fabrication cost of the current candidate arc based on the current fabrication depth, candidate arc queue, and physical topology) includes:

[0101] 01231: Based on the current starting bit of the current candidate arc, the current ending bit of the current candidate arc, and the physical topology substructure corresponding to the current candidate arc in the physical topology structure, obtain the current single-bit gate error rate, the current double-bit gate error rate, the current read error, and the current relaxation time;

[0102] 01232: The preparation cost of the current candidate arc is obtained based on the current single-bit gate error rate, the current double-bit gate error rate, the current read error, the current relaxation time, and the current preparation depth.

[0103] In some implementations, the acquisition module is used to obtain the current single-bit gate error rate, the current double-bit gate error rate, the current read error, and the current relaxation time based on the current starting bit, the current ending bit, and the physical topology substructure corresponding to the current candidate arc in the physical topology. The calculation module is also used to obtain the fabrication cost of the current candidate arc based on the current single-bit gate error rate, the current double-bit gate error rate, the current read error, the current relaxation time, and the current fabrication depth.

[0104] In some implementations, the processor is further configured to obtain the current single-bit gate error rate, the current double-bit gate error rate, the current read error, and the current relaxation time based on the current starting bit of the current candidate arc, the current ending bit of the current candidate arc, and the physical topology substructure corresponding to the current candidate arc in the physical topology structure. It also determines the fabrication cost of the current candidate arc based on the current single-bit gate error rate, the current double-bit gate error rate, the current read error, the current relaxation time, and the current fabrication depth.

[0105] Specifically, the Single Qubit Gate Noise Model describes the various noise sources and error modes that a quantum computer may encounter when performing single-qubit operations. These noise sources can include the inherent decoherence of the qubit, environmental interference, and imprecision of the control signal.

[0106] The single-qubit gate error rate refers to the deviation between the result of a single-qubit operation and the ideal result. This deviation can be caused by various noise sources described in the single-qubit gate noise model. The single-qubit gate error rate can be regarded as the combined effect of various noise sources described in the single-qubit gate noise model.

[0107] The double-qubit gate noise model describes the various noise sources and error modes that a quantum computer may encounter when performing two-qubit operations. These noise sources can include coupling noise, environmental interference, inaccuracies in control signals, and inherent errors.

[0108] The two-qubit gate error rate refers to the deviation between the result of a two-qubit operation and the ideal result. This deviation can be caused by various noise sources described in the two-qubit gate noise model.

[0109] The Readout Noise Model refers to the deviation between the read quantum state and the actual quantum state caused by various types of errors introduced during the measurement process due to noise and instrument limitations in actual computer equipment.

[0110] Readout errors refer to deviations that occur when measuring the state of a qubit after a computer device has executed a quantum algorithm. This deviation can be considered as the combined effect of noise sources in a readout noise model.

[0111] Relaxation time describes the timescale by which a qubit loses its quantum state information during interaction with its environment. There are two main types of relaxation time: T1 time and T2 time. T1 time refers to the time required for a qubit to return from an excited state to its ground state. T2 time refers to the time required for a qubit to return from any non-zero superposition state to its initial state.

[0112] The computer sets the expected number of qubits, determined by the algorithm's requirements and computational complexity. Next, assuming the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, the computer calculates the current fabrication depth after adding the control NOT gate corresponding to the current candidate arc to the fabrication circuit. Then, based on the current starting bit, the current ending bit of the current candidate arc, and the physical topology substructure corresponding to the current candidate arc in the physical topology, the computer obtains the current single-qubit gate error rate, the current two-qubit gate error rate, the current read error, and the current relaxation time. These parameters reflect the reliability of the qubits and quantum logic gates. Finally, the computer calculates the fabrication cost of the current candidate arc based on the current single-qubit gate error rate, the current two-qubit gate error rate, the current read error, the current relaxation time, and the current fabrication depth.

[0113] Thus, the preparation cost of the current candidate arc is obtained through comprehensive evaluation, which provides an important basis for the subsequent selection of target candidate arcs. This preparation cost takes into account the reliability of the qubit, the complexity of the preparation circuit, and the fidelity of quantum operations.

[0114] In some implementations, the preparation cost of the current candidate arc is calculated using the following formula:

[0115] COST = W readout E readout +W single E single +W double E double +W depth D+(1-W time )T,

[0116] Among them, W readout To read the error weight, E readout A read error has occurred. single E is the weight for the single-bit gate error rate. single Given the current single-bit gate error rate, W double E is the weight for the two-bit gate error rate. double Given the current two-bit gate error rate, W depth The current fabrication depth is the weight, D is the current fabrication depth, and W is the weight. timeThe relaxation time weight is T, where T is the current relaxation time. The read error weight, single-bit gate error rate weight, double-bit gate error rate weight, current preparation depth weight, and relaxation time weight are all preset.

[0117] Thus, the computer calculates according to the formula COST = W readout E readout +W single E single +W double E double +W depth D+(1-W time The computer calculates the fabrication cost of the current candidate arc. By comprehensively considering the reliability of the qubits, the complexity of the fabrication circuit, and the fidelity of quantum operations, the computer obtains the fabrication cost, providing an important basis for selecting target candidate arcs.

[0118] Please see Figure 6 In some embodiments, step 013 (determining the target candidate arc based on the preparation cost) includes:

[0119] 0131: The candidate arc with the lowest preparation cost is selected as the target candidate arc.

[0120] In some implementations, the determination module is used to identify the candidate arc with the lowest preparation cost as the target candidate arc.

[0121] In some implementations, the processor is also used to identify the candidate arc with the lowest fabrication cost as the target candidate arc.

[0122] Specifically, after the computer obtains the preparation cost of each candidate arc in the candidate arc queue according to the above formula for calculating preparation cost, it determines the candidate arc with the lowest preparation cost as the target candidate arc.

[0123] Thus, by identifying the candidate arc with the lowest preparation cost as the target candidate arc, the computer can subsequently construct a preparation circuit based on the qubits with relatively low noise and high quality corresponding to the target candidate arc, thereby improving the compatibility and efficiency of the multi-qubit quantum entangled states prepared based on the preparation circuit.

[0124] Please see Figure 7 In some embodiments, step 014 (obtaining the fabrication circuit based on the target candidate arc) includes:

[0125] 0141: Add control NOT gates corresponding to the target candidate arcs according to the physical topology to obtain the fabrication circuit.

[0126] In some implementations, the addition module is used to add a control NOT gate corresponding to the target candidate arc according to the physical topology to obtain the fabrication circuit.

[0127] In some implementations, the processor is also used to add control NOT gates corresponding to the target candidate arcs according to the physical topology to obtain the fabrication circuit.

[0128] Specifically, the computer adds control NOT gate operations corresponding to the target candidate arc to the fabrication circuit according to the physical topology to obtain a new fabrication circuit.

[0129] In this way, the computer analyzes the physical topology to determine the specific location and connection method of the target candidate arc in the physical circuit. Then, according to the specific location, a control NOT gate corresponding to the target candidate arc is added to the corresponding preparation circuit. The resulting preparation circuit is the optimal preparation circuit, which conforms to the physical topology of the target quantum computer. At the same time, it has a high degree of parallelization and a shallow circuit depth, making the multi-bit quantum entangled state prepared according to this preparation circuit more reliable in practical applications.

[0130] Please see Figure 8 In some implementations, the method further includes:

[0131] 016: Update the state of the fabrication circuit by adding a control NOT gate corresponding to the target candidate arc according to the physical topology.

[0132] In some implementations, the update module is also used to update the state of the fabrication circuit when a control NOT gate corresponding to the target candidate arc is added according to the physical topology.

[0133] In some implementations, the processor is also used to update the state of the fabrication circuit when a control NOT gate corresponding to the target candidate arc is added according to the physical topology.

[0134] Specifically, after adding a control NOT gate corresponding to the target candidate arc to the fabrication circuit according to the physical topology, the computer device updates the state of the fabrication circuit. Updating the state of the fabrication circuit can update the parameters of the starting bit in the fabrication circuit and the quantum computer for a period of time, thereby enabling the acquisition of all outgoing edges and their parameters.

[0135] In this way, by updating the state of the fabrication circuit, it is ensured that the selected target candidate arc is fabricated at the lowest cost within the same time period.

[0136] The following example illustrates the method for preparing multi-qubit quantum entangled states according to embodiments of this application. Please refer to... Figure 9 , Figure 9 To fabricate a circuit for a CHZ state that does not consider the physical topology of a quantum computer. Figure 9This refers to the circuit used in the traditional GHZ state preparation process, which connects the individual bits sequentially using CNOT gates. A significant drawback of this traditional GHZ state preparation method is its large circuit depth. In practical quantum computers, due to decoherence effects, this large circuit depth can easily lead to the failure of the GHZ state. Decoherence effects cause the quantum state to deviate from its expected state over time, thereby reducing the fidelity of quantum entanglement.

[0137] It can be found. Please see. Figure 10 and Figure 11 . Figure 10 This diagram illustrates the physical topology of a quantum computer, where Q0, Q1…QN represent individual qubits. Links between qubits are called coupling bits, indicating that a two-qubit gate can be applied between two qubits. Each link between two qubits is a candidate arc, and the value in the candidate arc represents the two-qubit gate error E when applying the two-qubit gate. double The value marked on the qubit is the measured readout error E. readout . Figure 10 In this context, a deeper node indicates a smaller error, a darker link color indicates a smaller double-bit gate error, and a larger node indicates a longer relaxation time T1. Figure 11 This is a schematic diagram of the fabrication circuit obtained according to the fabrication method of the present application, where, for example, q24 represents a quantum bit. Please refer to [link / reference needed]. Figure 12 and Figure 13 , Figure 12 It means Hadamamen, Figure 13 This indicates a control NOT gate.

[0138] In response to user input, the expected number of qubits is set to 9, and the user selects... Figure 10 q24 is the starting bit. From Figure 10 We can observe that the candidate arc queue at this point consists of four candidate arcs: q24-q18, q24-q19, q24-q30, and q24-q31. First, we take q24-q18 as the current candidate arc, calculate the fabrication circuit depth D1 after adding the control NOT gates corresponding to q24-q18 to the fabrication circuit, and then... Figure 11 The single-bit gate error E of q24-q18 can be obtained from this. single -1 = 0, double-bit gate error E double -1 = 1.0, Reading error E readout -1 = 5.82 and relaxation time T1. Then, according to the formula for calculating preparation cost: COST = W readout E readout +W single E single +W double E double +W depthD+(1-W time The calculated preparation cost of q24-q18 is cost1 = 5.82W. readout +W double +W depth D1+(1-W time T1

[0139] Next, q24-q19 are selected as the current candidate arcs. The same processing as for q24-q18 is performed on q24-q19, which will not be repeated here. After processing q24-q19 to obtain the preparation cost cost2, the remaining candidate arcs in the candidate arc queue are processed in the same way to obtain the preparation costs cost3 for q24-q30 and cost4 for q24-q31. Comparing cost1, cost2, cost3, and cost4, cost4 is the smallest. Therefore, the control NOT gate corresponding to q24-q31 is selected and added to the preparation circuit. The state of the preparation circuit is then updated.

[0140] We can see that the starting bits are q24 and q31 at this point, so the candidate arc queue consists of all outgoing edges of q24 and q31, namely, q24-q18, q24-q19, q24-q30, q31-q25, q31-q36, and q31-q37. We then perform the aforementioned cost calculation on all candidate arcs in the queue, resulting in cost5, cost6, cost7, cost8, cost9, and cost10. We observe that candidate arc q24-q19 has the lowest cost. Therefore, we select the NOT gate corresponding to q24-q19 and add it to the fabrication circuit, updating the circuit's state.

[0141] Repeat the above steps until the number of qubits in the fabricated circuit reaches the expected number of 9, to obtain the following result. Figure 11 The fabrication circuit is shown.

[0142] This application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, it causes the one or more processors to perform the multi-bit quantum entangled state preparation method of this application.

[0143] It is understood that a computer program includes computer program code. Computer program code can be in the form of source code, object code, executable files, or some intermediate form. Computer-readable storage media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, external hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution media, etc.

[0144] In this specification, the terms "specifically," "furthermore," "particularly," "understandably," etc., refer to specific features, structures, materials, or characteristics described in connection with embodiments or examples that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0145] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0146] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for preparing multi-qubit quantum entangled states, characterized in that, The method includes: A candidate arc queue is determined based on the physical topology and starting bit of the target quantum computer, and the candidate arc queue includes multiple candidate arcs; The preparation cost of each candidate arc is obtained based on the candidate arc queue and the physical topology. The target candidate arc is determined based on the aforementioned preparation cost; A fabrication circuit is obtained based on the target candidate arc, so that the target quantum computer can fabricate the multi-bit quantum entangled state based on the fabrication circuit; The preparation cost of the candidate arc is calculated using the following formula: ； in, To read the error weight, The candidate arc was read incorrectly. For single-bit gate error rate weights, The single-bit gate error rate of the candidate arc. For the two-bit gate error rate weights, The two-bit gate error rate of the candidate arc. To prepare depth weights for the current process, The preparation depth of the candidate arc. As relaxation time weight, The relaxation time of the candidate arc, the read error weight, the single-bit gate error rate weight, the double-bit gate error rate weight, the current preparation depth weight, and the relaxation time weight are all preset.

2. The method for preparing multi-qubit quantum entangled states according to claim 1, characterized in that, The starting bit is determined in response to user input.

3. The method for preparing multi-qubit quantum entangled states according to claim 1, characterized in that, The starting bit is any qubit in the physical topology.

4. The method for preparing multi-qubit quantum entangled states according to claim 1, characterized in that, The step of determining the candidate arc queue based on the physical topology and starting bit of the target quantum computer includes: All the qubits of the fabricated circuit are used together as the starting bit; Determine all outgoing edges of the starting bit based on the physical topology; The candidate arc queue is determined based on the outgoing edges.

5. The method for preparing multi-qubit quantum entangled states according to claim 1, characterized in that, The step of obtaining the preparation cost of each candidate arc based on the candidate arc queue and the physical topology includes: Set the expected number of qubits; If the candidate arc queue is not empty and the number of qubits in the fabrication circuit is less than or equal to the expected number of qubits, calculate the current fabrication depth after the control NOT gate corresponding to the current candidate arc is added to the fabrication circuit. The fabrication cost of the current candidate arc is obtained based on the current fabrication depth, the candidate arc queue, and the physical topology.

6. The method for preparing multi-qubit quantum entangled states according to claim 5, characterized in that, The step of obtaining the fabrication cost of the current candidate arc based on the current fabrication depth, the candidate arc queue, and the physical topology includes: The current single-bit gate error rate, current double-bit gate error rate, current read error, and current relaxation time are obtained based on the current starting bit of the current candidate arc, the current ending bit of the current candidate arc, and the physical topology substructure corresponding to the current candidate arc in the physical topology structure. The fabrication cost of the current candidate arc is obtained based on the current single-bit gate error rate, the current double-bit gate error rate, the current read error, the current relaxation time, and the current fabrication depth.

7. The method for preparing multi-qubit quantum entangled states according to claim 6, characterized in that, The step of determining the target candidate arc based on the preparation cost includes: The candidate arc with the lowest preparation cost is determined as the target candidate arc.

8. The method for preparing multi-qubit quantum entangled states according to claim 1, characterized in that, The step of obtaining the circuit based on the target candidate arc includes: The fabrication circuit is obtained by adding a control NOT gate corresponding to the target candidate arc according to the physical topology.

9. The method for preparing multi-qubit quantum entangled states according to claim 8, characterized in that, The method further includes: The state of the fabrication circuit is updated when a control NOT gate corresponding to the target candidate arc is added according to the physical topology.

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