Method for optimizing quantum circuits based on timing alignment

Abstract

The application discloses a quantum circuit optimization method based on timing alignment. The quantum circuit optimization method comprises the following steps: determining a first quantum circuit according to the dependency relationship of quantum gates in the quantum circuit; processing a target quantum gate in the first quantum circuit to obtain a second quantum circuit; and performing delay processing on single-bit quantum gates in the second quantum circuit by using a barrier gate to obtain a first optimized quantum circuit, so as to realize optimization of the quantum circuit. In this way, the computer device inserts a timing alignment operation, delays the positions of part of the quantum gates in the quantum circuit, and ensures that the quantum gates will not run in advance by using the barrier gate, so that the quantum bits entering the quantum circuit only participate in the calculation when necessary, the quantum bits are prevented from entering the superposition state too early, the interference of noise on the quantum bits in the calculation process is reduced, and the stability and reliability of the quantum circuit operation are improved.

Description

Technical Field

[0001] This application relates to the field of quantum circuit optimization, and more specifically, to an optimization method for quantum circuits based on timing alignment. Background Technology

[0002] Quantum circuits, used to implement quantum algorithms and quantum information processing, consist of a series of quantum logic gates and are a fundamental component of quantum computers. By manipulating the states of qubits, quantum circuits can implement quantum algorithms and simulate the behavior of quantum systems. However, qubits in a superposition state are susceptible to noise such as quantum gate noise, decoherence of the qubit itself, and bit flipping, leading to quantum state decay and errors, which in turn affect the stability of quantum circuit operation. Summary of the Invention

[0003] This application provides an optimization method for quantum circuits based on timing alignment.

[0004] This application provides an optimization method for time-aligned quantum circuits, the method comprising:

[0005] The first quantum circuit is determined based on the quantum gate dependencies in the quantum circuit;

[0006] The target quantum gate in the first quantum circuit is processed to obtain the second quantum circuit;

[0007] A first optimized quantum circuit is obtained by delaying the single-bit quantum gates in the second quantum circuit according to the barrier gate, so as to optimize the quantum circuit. The barrier gate is configured to prevent the quantum gates after the barrier gate in the quantum circuit from running prematurely.

[0008] Thus, the computer device determines the first quantum circuit through quantum gate dependencies and timing alignment. This first quantum circuit ensures that all parallelizable quantum gates operate at the same time level, providing a basis for subsequently delaying the processing of single-qubit quantum gates in the quantum circuit using barrier gates and optimizing the circuit structure. Then, the computer device processes target quantum gates in the first quantum circuit that are not natively supported by the computer device architecture to obtain the second quantum circuit. This second quantum circuit includes single-qubit quantum gates and is easier to implement precisely than the first quantum circuit. Finally, the computer device processes the second quantum circuit using barrier gates to obtain the first optimized quantum circuit. Barrier gates prevent quantum gates following the barrier gate from running prematurely, maintaining a specific order or structure for some quantum gates. In this way, the first optimized quantum circuit delays the position of some quantum gates and uses barrier gates to ensure these gates do not run prematurely, ensuring that qubits entering the quantum circuit only participate in computation when necessary. This prevents qubits from entering superposition states prematurely, reduces noise interference during computation, and improves the stability and reliability of the quantum circuit.

[0009] In some embodiments, determining the first quantum circuit based on the quantum gate dependencies in the quantum circuit includes:

[0010] The parallel quantum gates that can operate in parallel in the quantum circuit are determined by the aforementioned dependencies;

[0011] The first quantum circuit is obtained by rearranging the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates.

[0012] In this way, the computer device determines the parallel quantum gates that can be operated in parallel within the quantum circuit through dependencies. Then, the computer device rearranges the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates, obtaining the first quantum circuit. Thus, by rearranging the execution sequence of the quantum gates in the quantum circuit through dependencies, the computer device can operate some quantum gates in parallel, reducing the overall execution time of the quantum circuit and improving the efficiency of quantum computing.

[0013] In some embodiments, the method further includes:

[0014] The first quantum circuit is functionally equivalent to the quantum circuit by performing simulation tests to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0015] In this way, the computer equipment verifies the functional equivalence of the first quantum circuit based on simulation tests to ensure that the first quantum circuit and the original quantum circuit are functionally equivalent. This ensures that the first quantum circuit, optimized by the computer equipment, can correctly execute the computational tasks of the original quantum circuit without sacrificing the correctness of the algorithm.

[0016] In some embodiments, processing the target quantum gate in the first quantum circuit to obtain the second quantum circuit includes:

[0017] The target quantum gate is processed according to the pre-supported quantum instruction set to obtain the second quantum circuit.

[0018] In this way, the computer device processes the target quantum gate according to the pre-supported quantum instruction set to obtain the second quantum circuit. This decomposes the target quantum gate into basic quantum gates within the pre-supported quantum instruction set, transforming complex quantum gate operations into combinations of basic quantum gates, enabling implementation on existing quantum hardware, improving the efficiency of quantum computing, and exhibiting good universality.

[0019] In some embodiments, the step of delaying the single-qubit quantum gate in the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit includes:

[0020] The single-bit quantum gate is postponed to before the nearest two-bit quantum gate, which is used to indicate the first two-bit quantum gate in the second quantum circuit that operates on the same quantum bit as the single-bit quantum gate.

[0021] The first optimized quantum circuit is obtained by adding the barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate.

[0022] In this way, the computer device postpones the single-qubit quantum gate until before the nearest two-qubit quantum gate, which is used to indicate the first two-qubit quantum gate in the second quantum circuit that operates on the same qubit as the single-qubit quantum gate. Then, the computer device adds a barrier gate before the single-qubit quantum gate located before the nearest two-qubit quantum gate, resulting in the first optimized quantum circuit. Thus, by postponing the single-qubit quantum gate until before the nearest two-qubit quantum gate, the time when the qubit enters the superposition state is delayed as much as possible, ensuring that the qubit participates in computation only when necessary, preventing premature entry into the superposition state from having an impact. Furthermore, by adding a barrier gate before the single-qubit quantum gate located before the nearest two-qubit quantum gate, the operation of the single-qubit quantum gate after the barrier gate is prevented from running prematurely, ensuring that some sub-circuits of the quantum circuit maintain a specific order or structure.

[0023] In some embodiments, the optimization method further includes:

[0024] A second optimized quantum circuit is obtained by merging multiple first barrier intervals in the first optimized quantum circuit, wherein the first barrier interval is used to indicate the quantum circuit between every two barrier gates in the first optimized quantum circuit, and the first starting barrier interval and the first ending barrier interval of the first optimized quantum circuit are each determined by one of the barrier gates.

[0025] By sequentially embedding the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit, a third optimized quantum circuit is obtained.

[0026] Thus, the computer device merges multiple first barrier regions in the first optimized quantum circuit to obtain a second optimized quantum circuit. The first barrier regions indicate the quantum circuit between every two barrier gates in the first optimized quantum circuit, and the first starting barrier region and the first ending barrier region of the first optimized quantum circuit are each determined by a barrier gate. Next, the computer device sequentially embeds the single-qubit quantum gates from the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit. In this way, by merging multiple first barrier regions in the first optimized quantum circuit, the depth of the quantum circuit is reduced, and the overall performance of the quantum circuit is improved. Furthermore, the sequential embedding of single-qubit quantum gates from the first optimized quantum circuit into the second optimized quantum circuit ensures that the resulting third optimized quantum circuit is functionally equivalent to the first optimized quantum circuit.

[0027] In some embodiments, the step of merging multiple first barrier regions in the first optimized quantum circuit to obtain a second optimized quantum circuit includes:

[0028] The first initial barrier interval is used as the second final barrier interval of the second optimized quantum circuit;

[0029] A second optimized quantum circuit is obtained by comparing the second end barrier interval with multiple first barrier intervals.

[0030] Thus, the computer device uses the first initial barrier region as the second final barrier region of the second optimized quantum circuit. Next, the computer device compares the second final barrier region with multiple first barrier regions to obtain the second optimized quantum circuit. In this way, by comparing the second final barrier region with multiple first barrier regions, it is determined whether these first barrier regions can be merged into the second final barrier region, thereby reducing the depth of the quantum circuit and improving its execution efficiency.

[0031] In some embodiments, the comparison of the second end barrier interval and a plurality of first barrier intervals to obtain a second optimized quantum circuit includes:

[0032] The two-bit quantum gate in the second end barrier interval and the current two-bit quantum gate in the next first barrier interval are compared to confirm the movement of the current two-bit quantum gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first optimized quantum circuit that is located in the first barrier interval corresponding to the second end barrier interval;

[0033] If it is confirmed that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second last barrier interval to obtain the second optimized quantum circuit.

[0034] Thus, the computer device compares the two-qubit quantum gate in the second final barrier interval with the current two-qubit quantum gate in the next first barrier interval to confirm the movement of the current two-qubit quantum gate in the next first barrier interval. The next first barrier interval indicates the next first barrier interval in the first optimized quantum circuit that corresponds to the second final barrier interval. Then, if it is confirmed that the current two-qubit quantum gate in the next first barrier interval can move to the second final barrier interval, the computer device moves the current two-qubit quantum gate in the next first barrier interval to the second final barrier interval, resulting in the second optimized quantum circuit. In this way, by comparing the two-qubit quantum gate in the second final barrier interval with the current two-qubit quantum gate in the next first barrier interval, it checks whether the two-qubit quantum gate in the next first barrier interval can move to the second final barrier interval without affecting the execution order and result of the circuit. Furthermore, by moving the two-qubit quantum gate in the next first barrier interval to the second final barrier interval, the computer device reduces the depth of the quantum circuit and improves its execution efficiency.

[0035] In some implementations, the comparison process between the two-bit quantum gate in the second final barrier interval and the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval includes:

[0036] If the qubits acting on the current two-bit quantum gate in the next first barrier interval are different from the qubits acting on each two-bit quantum gate in the second last barrier interval, it is confirmed that the current two-bit quantum gate in the next first barrier interval can move to the second last barrier interval.

[0037] If at least one qubit of the current two-bit quantum gate in the next first barrier interval is the same as the qubit of the two-bit quantum gate in the second last barrier interval, it is confirmed that the current two-bit quantum gate in the next first barrier interval cannot move to the second last barrier interval.

[0038] Thus, if the qubits acting on the current two-qubit quantum gate in the next first barrier interval are not the same as those acting on each of the two-qubit quantum gates in the second last barrier interval, the computer device confirms that the current two-qubit quantum gate in the next first barrier interval can be moved to the second last barrier interval. Next, if at least one qubit in the current two-qubit quantum gate in the next first barrier interval is the same as that in the second last barrier interval, the computer device confirms that the current two-qubit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval. In this way, by determining the consistency between the qubits acting on the current two-qubit quantum gate in the next first barrier interval and each of the two-qubit quantum gates in the second last barrier interval, it is confirmed that moving the two-qubit quantum gate will not affect the correct execution of the quantum circuit. If the qubits acting on the current two-qubit quantum gate in the next first barrier interval are completely different from those in the second last barrier interval, i.e., no qubits are the same in both intervals, then the computer device confirms that the current two-qubit quantum gate in the next first barrier interval can be moved to the second last barrier interval, and the move operation is performed to obtain the optimized quantum circuit. If at least one of the qubits acting on the current two-bit quantum gate in the next first barrier interval is the same as the qubits acting on the two-bit quantum gate in the second last barrier interval, then the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval, and the current quantum circuit structure remains unchanged.

[0039] In some embodiments, using the first starting barrier region as the second ending barrier region of the second optimized quantum circuit includes:

[0040] If the next first barrier interval includes a two-bit quantum gate, the next first barrier interval shall be used as the second end barrier interval of the second optimized quantum circuit.

[0041] Thus, if the next first barrier interval includes a two-qubit quantum gate, this next first barrier interval is designated as the second final barrier interval of the second optimized quantum circuit. In this way, the next barrier interval including a two-qubit quantum gate is found in the first optimized quantum circuit; this interval is called the next first barrier interval. Furthermore, designating this next first barrier interval as the second final barrier interval of the second optimized quantum circuit means that the end position of the second optimized quantum circuit is set to this interval including the two-qubit quantum gate. Subsequently, this interval including the two-qubit quantum gate is used to merge the remaining first barrier intervals in the first optimized quantum circuit.

[0042] In some embodiments, the method further includes:

[0043] If the next first barrier interval does not include a two-bit quantum gate, the second end barrier interval and multiple first barrier intervals are compared to obtain a second optimized quantum circuit.

[0044] Thus, if the next first barrier interval does not include a two-qubit quantum gate, the computer device compares the second final barrier interval with multiple first barrier intervals to obtain the second optimized quantum circuit. If the next first barrier interval does not include a two-qubit quantum gate, meaning all two-qubit quantum gates in the next first barrier interval have been merged into the second final barrier interval, then this second final barrier interval is still used as the new second final barrier interval, and the remaining first barrier intervals in the first optimized quantum circuit are merged.

[0045] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0046] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0047] Figure 1 This is one of the flowcharts illustrating the implementation of this application;

[0048] Figure 2 This is a schematic diagram of the first quantum circuit according to an embodiment of this application;

[0049] Figure 3 This is a schematic diagram of the Hadama gate according to an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of the control NOT gate in an embodiment of this application;

[0051] Figure 5 This is a schematic diagram of the second quantum circuit according to an embodiment of this application;

[0052] Figure 6 This is a schematic diagram of the control phase gate in an embodiment of this application;

[0053] Figure 7 This is a schematic diagram of the first optimized quantum circuit according to the embodiments of this application;

[0054] Figure 8 This is a second flowchart illustrating the implementation method of this application;

[0055] Figure 9 This is the third flowchart illustrating the implementation method of this application;

[0056] Figure 10 This is the fourth flowchart illustrating the implementation method of this application;

[0057] Figure 11 This is the fifth flowchart illustrating the implementation method of this application;

[0058] Figure 12 This is the sixth flowchart illustrating the implementation method of this application;

[0059] Figure 13 This is a schematic diagram of the second optimized quantum circuit according to the embodiments of this application;

[0060] Figure 14 This is a schematic diagram of the third optimized quantum circuit according to the embodiments of this application;

[0061] Figure 15 This is the seventh flowchart illustrating the implementation method of this application;

[0062] Figure 16 This is the eighth flowchart illustrating the implementation method of this application;

[0063] Figure 17 This is the ninth flowchart illustrating the implementation method of this application;

[0064] Figure 18 This is the tenth flowchart illustrating the implementation of this application;

[0065] Figure 19 This is the eleventh flowchart illustrating the implementation method of this application. Detailed Implementation

[0066] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application.

[0067] Quantum circuits, used to implement quantum algorithms and quantum information processing, consist of a series of quantum logic gates and are the fundamental building blocks of quantum computers. By manipulating the states of qubits, quantum algorithms can be implemented and the behavior of quantum systems can be simulated.

[0068] However, because qubits exist in a superposition state, they are susceptible to various noises, leading to quantum state decay and errors, which in turn affect the stability of quantum circuit operation. These noises mainly include quantum gate noise, decoherence of the qubits themselves, and bit flipping.

[0069] Quantum gate noise refers to errors introduced during the execution of quantum logic gate operations. This noise can be caused by imperfect gate implementation, environmental interference, errors in the control electronics, and other factors. Quantum gate noise causes the state of a qubit to deviate from the expected ideal state, thus affecting the accuracy of quantum algorithms.

[0070] Decoherence of a qubit refers to the loss of superposition and coherence of its quantum state due to the interaction between the qubit and its environment. This decoherence can be caused by the interaction between the qubit and factors such as thermodynamic noise, electromagnetic fields, and vibrations in the environment. Decoherence leads to the rapid decay of the qubit's quantum state into a classical mixed state, thus affecting the stability of quantum circuit operation and the reliability of computational results.

[0071] A bit flip occurs when the state of a qubit unexpectedly changes from |0> to |1>, or from |1> to |0>. This flip can be caused by random perturbations or noise affecting the qubit. Bit flips are a special type of error that directly alters the quantum state of a qubit, thus impacting the accuracy of quantum algorithms.

[0072] Based on the above issues, please refer to Figure 1 This application provides an optimization method for time-aligned quantum circuits, the method comprising:

[0073] 011: Determine the first quantum circuit based on the quantum gate dependencies in the quantum circuit;

[0074] 012: The target quantum gate in the first quantum circuit is processed to obtain the second quantum circuit;

[0075] 013: The first optimized quantum circuit is obtained by delaying the single-bit quantum gate in the second quantum circuit according to the barrier gate, so as to achieve the optimization of the quantum circuit.

[0076] This application also provides a computer device, including a memory and a processor. The quantum circuit optimization method of this application can be implemented by the computer device of this application. Specifically, the memory stores a computer program, and the processor is used to determine a first quantum circuit based on the dependencies of quantum gates in the quantum circuit; process target quantum gates in the first quantum circuit to obtain a second quantum circuit; and delay single-qubit quantum gates in the second quantum circuit according to barrier gates to obtain a first optimized quantum circuit, thereby achieving optimization of the quantum circuit.

[0077] This application also provides a quantum circuit optimization apparatus. The quantum circuit optimization method of this application can be implemented by the quantum circuit optimization apparatus of this application. Specifically, the quantum circuit optimization apparatus includes a determining module, a processing module, and a delaying module. The determining module is used to determine a first quantum circuit based on the dependency relationship of quantum gates in the quantum circuit. The processing module is used to process the target quantum gate in the first quantum circuit to obtain a second quantum circuit. The delaying module is used to delay the single-qubit quantum gate in the second quantum circuit according to the barrier gate to obtain a first optimized quantum circuit, thereby achieving the optimization of the quantum circuit.

[0078] Specifically, time alignment is used to adjust data from different time points or time series to a unified reference time point or time series.

[0079] Quantum circuits consist of a series of quantum gates, which describe how the quantum gates operate on the state of the qubits. They are the foundation for realizing quantum algorithms and quantum information processing.

[0080] Quantum gates, also known as quantum logic gates, are the basic operational units in quantum computing. They perform specific mathematical operations on qubits to achieve complex computational tasks and to build quantum algorithms and quantum protocols.

[0081] A qubit is the basic unit of a quantum circuit, similar to a bit in classical computing, but it can exist in a superposition state.

[0082] Quantum gate dependency refers to the interaction and ordering relationships between different quantum gate operations in quantum computing. The method for determining this is as follows:

[0083] In a quantum circuit C, quantum operations are said to be dependent on each other if they simultaneously satisfy the following conditions:

[0084] At least one active qubit must be shared;

[0085] Furthermore, the execution order of quantum operations cannot be arbitrarily interchanged to avoid altering the behavior or output of the quantum circuit.

[0086] A barrier gate is a non-interactive gate that prevents operations after a barrier gate from running prematurely when compiling quantum circuits, thus maintaining a specific order or structure for certain parts of the circuit.

[0087] Quantum circuit optimization refers to adjusting and improving the structure, connection method, and operation sequence of quantum circuits. Its significance lies in reducing the depth of quantum circuits and optimizing the ordering of quantum gates, thereby improving the computing speed and accuracy of quantum computers.

[0088] Specifically, the computer device determines the first quantum circuit through quantum gate dependencies and timing alignment. This first quantum circuit ensures that all parallelizable quantum gates operate at the same time level, providing a basis for subsequently delaying the processing of single-qubit quantum gates within the quantum circuit using barrier gates and optimizing the circuit structure. Then, the computer device processes target quantum gates in the first quantum circuit that are not natively supported by the computer device architecture to obtain the second quantum circuit. This second quantum circuit includes single-qubit quantum gates and is easier to implement precisely than the first quantum circuit. Finally, the computer device processes the second quantum circuit using barrier gates to obtain the first optimized quantum circuit. The barrier gates prevent quantum gates following the barrier gate from running prematurely, maintaining a specific order or structure for some quantum gates. Thus, the first optimized quantum circuit delays the position of some quantum gates and uses barrier gates to ensure these gates do not run prematurely. This ensures that qubits entering the quantum circuit only participate in computation when necessary, preventing qubits from entering superposition states prematurely, reducing noise interference during computation, and improving the stability and reliability of the quantum circuit operation. It should be noted that the quantum circuit optimization method provided in this application optimizes the quantum circuit on a classical computer, and then executes the optimized quantum circuit using a quantum computer.

[0089] The following example illustrates the optimization method of quantum circuits in the embodiments of this application. In the embodiments described in this application, the target quantum gate is a complex quantum gate, such as the Toffoli gate, the SWAP gate, or other quantum gates that are difficult to run directly on a physical machine.

[0090] Please see Figure 2 , Figure 2 This is a schematic diagram of the first quantum circuit. This diagram is for reference only. Different quantum circuits may produce different first quantum circuits after different processing. The specific requirements should be determined according to actual needs, and no limitation is made here. Figure 2 This includes qubits such as q6 and q12, Hadamard gates, and controlled NOT gates, i.e., CNOT gates. Please refer to [link / reference]. Figure 3 , Figure 4 Hadamamenru Figure 3 As shown, the CNOT gate is as follows Figure 4 As shown.

[0091] Please see Figure 5 , Figure 5 This is a schematic diagram of the second quantum circuit. This diagram is for reference only. Different first quantum circuits may produce different second quantum circuits after different processing. The specific requirements should be determined based on actual needs, and no limitation is made here. Figure 2 This includes H-gates and control phase gates, also known as CZ gates, which are obtained from CNOT decomposition. See also... Figure 6 CZ Gate Figure 6 As shown.

[0092] Please see Figure 7 , Figure 7 This is a schematic diagram of the first optimized quantum circuit. This schematic diagram is for reference only. Different second quantum circuits may yield different first optimized quantum circuits after different processing. The specific requirements should be determined based on actual needs, and no limitation is made here.

[0093] The computer device determines a first quantum circuit C1 through quantum gate dependencies and timing alignment. This determined first quantum circuit C1 ensures that all parallelizable quantum gates operate at the same time level, providing a basis for subsequently delaying the processing of single-qubit quantum gates in the quantum circuit using barrier gates and optimizing the circuit structure. Then, the computer device processes target quantum gates in the first quantum circuit C1 that are not natively supported by the computer device architecture to obtain a second quantum circuit C2. This second quantum circuit C2 includes single-qubit quantum gates and is easier to implement precisely than the first quantum circuit C1. Finally, the computer device processes the second quantum circuit C2 according to barrier gates to obtain a first optimized quantum circuit C3. Barrier gates prevent quantum gates following the barrier gate from running prematurely, maintaining a specific order or structure for some quantum circuits.

[0094] In summary, in the quantum circuit optimization method and computer device of the embodiments of this application, the computer device delays the position of some quantum gates in the quantum circuit by inserting timing alignment operations and uses barrier gates to ensure that these quantum gates do not run prematurely. This ensures that the qubits entering the quantum circuit only participate in the calculation when necessary, prevents the qubits from entering the superposition state prematurely, reduces the noise interference experienced by the qubits during the calculation process, and improves the stability and reliability of the quantum circuit operation.

[0095] Please see Figure 8 In some implementations, step 011 (determining the first quantum circuit based on the quantum gate dependencies in the quantum circuit) includes the following steps:

[0096] 0111: Identifying parallel quantum gates that can operate in parallel in quantum circuits through dependencies;

[0097] 0112: The first quantum circuit is obtained by rearranging the execution sequence of quantum gates in the quantum circuit according to the parallel quantum gates.

[0098] In some implementations, the determining module is used to determine the parallel quantum gates that can operate in parallel within the quantum circuit based on dependencies. The sorting module is used to rearrange the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain a first quantum circuit.

[0099] In some implementations, the processor is also configured to determine parallel quantum gates that can operate in parallel within the quantum circuit based on dependencies, and to rearrange the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain a first quantum circuit.

[0100] Specifically, the computer device determines the parallel quantum gates that can be operated in parallel within the quantum circuit through dependencies. Then, the computer device rearranges the execution sequence of the quantum gates in the quantum circuit according to the parallel quantum gates to obtain the first quantum circuit. In this way, by rearranging the execution sequence of the quantum gates in the quantum circuit through dependencies, the computer device can operate the quantum gates in parallel, reducing the overall execution time of the quantum circuit and improving the efficiency of quantum computing.

[0101] Following the example above, please refer again. Figure 2 To clearly and intuitively represent the dependencies between quantum gates in quantum circuit C, a dependency graph is typically constructed, mapping the dependencies between quantum gates to nodes and edges in a directed acyclic graph. This dependency graph allows identification of parallel quantum gates that can be executed in parallel within quantum circuit C. Next, the sequence of quantum gates is rearranged on quantum circuit C so that the identified parallel quantum gates can be placed at the same time level, thus obtaining the first quantum circuit C1. In this embodiment, the execution sequence of quantum gates is rearranged according to a left-alignment strategy to obtain the following... Figure 2 The first quantum circuit C1 is shown.

[0102] In this way, computer devices rearrange the execution sequence of quantum gates in quantum circuits through dependencies, thereby enabling parallel operation of some quantum gates, reducing the execution time of the entire quantum circuit, and improving the efficiency of quantum computing.

[0103] Please see Figure 9 In some implementations, the method further includes:

[0104] 014: The functional equivalence of the first quantum circuit is verified by simulation test to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0105] In some implementations, the test module is used to perform functional equivalence verification of the first quantum circuit based on simulation tests to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0106] In some implementations, the processor is also configured to perform functional equivalence verification of the first quantum circuit based on simulation tests to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

[0107] Specifically, simulation testing typically refers to using a classical computer to simulate the behavior of a quantum computer in order to verify the correctness and performance of a quantum circuit or algorithm. By comparing the outputs of two quantum circuits, it can be determined whether they produce the same output for all possible inputs, thus verifying their functional equivalence.

[0108] Functional equivalence verification refers to the process of confirming whether two quantum circuits are functionally identical or equivalent.

[0109] The computer equipment verifies the functional equivalence of the first quantum circuit through simulation tests to ensure that the first quantum circuit and the original quantum circuit are functionally equivalent. This ensures that the first quantum circuit, optimized by the computer equipment, can correctly execute the computational tasks of the original quantum circuit without sacrificing the correctness of the algorithm.

[0110] Continuing the example above, the computer device performs functional equivalence verification on the first quantum circuit C1 based on simulation tests to ensure that the first quantum circuit C1 and the quantum circuit C are functionally equivalent. In some embodiments, the simulation test may involve inputting test data with known output results into the first quantum circuit C1 and comparing the test results output by the first quantum circuit C1 with the known output results. If the test results and the known output results are consistent, it is determined that the first quantum circuit C1 and the original quantum circuit C are functionally equivalent. If the test results and the known output results are inconsistent, it is determined that the first quantum circuit C1 and the original quantum circuit C have different functions, and the first quantum circuit C1 is not equivalent to the quantum circuit C.

[0111] In this way, the first quantum circuit C1, optimized by the computer equipment, can correctly execute the computational tasks of the original quantum circuit, ensuring that the correctness of the algorithm is not sacrificed.

[0112] Please see Figure 10 In some embodiments, step 012 (processing the target quantum gate in the first quantum circuit to obtain the second quantum circuit) includes:

[0113] 0121: The target quantum gate is processed according to the pre-supported quantum instruction set to obtain the second quantum circuit.

[0114] In some implementations, the processing module is used to process the target quantum gate according to a pre-supported set of quantum instructions to obtain a second quantum circuit.

[0115] In some implementations, the processor further processes the target quantum gate according to a pre-supported set of quantum instructions to obtain a second quantum circuit.

[0116] Specifically, a target quantum gate refers to a composite gate that is not natively supported by the architecture of computer devices.

[0117] A quantum instruction set refers to a set of quantum operations that can be executed by quantum computer hardware. The design of a quantum instruction set depends on the physical implementation and architecture of the quantum computer; different quantum computers may have different instruction sets to optimize for their specific hardware characteristics.

[0118] The computer device processes the target quantum gate according to a pre-supported quantum instruction set to obtain a second quantum circuit. In this way, the target quantum gate is decomposed into basic quantum gates in the pre-supported quantum instruction set by the quantum instruction set, and the complex quantum gate operation is transformed into a combination of basic quantum gates so that it can be implemented on existing quantum hardware, while improving the efficiency of quantum computing.

[0119] Continuing with the example above, the Hadamard Gate, or H-gate, is a fundamental gate in quantum computing used to rotate the state of a qubit from its ground state to a superposition state.

[0120] The controlled-NOT gate (CNOT) is a fundamental gate in quantum computing, playing a crucial role in the process. A CNOT gate is a two-qubit gate consisting of a control qubit and a target qubit.

[0121] The computer device processes the target quantum gate in the first quantum circuit C1 according to a pre-supported quantum instruction set to obtain the second quantum circuit C2. Please refer to [further details omitted]. Figure 5 In this embodiment, the target quantum gate is a CNOT gate. By decomposing the relatively complex CNOT gate into H gates and CZ gates, the resulting second quantum circuit is easier to implement precisely compared to the first quantum circuit. Figure 5 We can see that there are H gates acting on stable-state qubits.

[0122] Furthermore, since the quantum circuit optimization method provided in this application can be adapted to most quantum circuits by decomposing complex quantum gates into simple single-bit quantum gates and performing related operations on these simple single-bit quantum gates in subsequent processes, it has good universality.

[0123] In this way, by decomposing the target quantum gate into basic quantum gates in the pre-supported quantum instruction set through the quantum instruction set, complex quantum gate operations are transformed into combinations of basic quantum gates so that they can be implemented on existing quantum hardware, thereby improving the efficiency of quantum computing and having good universality.

[0124] Please see Figure 11 In some embodiments, step 013 (obtaining a first optimized quantum circuit by delaying the single-bit quantum gate in the second quantum circuit according to the barrier gate) includes:

[0125] 0131: Delay the single-qubit quantum gate until before the nearest two-qubit quantum gate;

[0126] 0132: Add a barrier gate before the single-qubit quantum gate located before the nearest two-qubit quantum gate to obtain the first optimized quantum circuit.

[0127] In some implementations, the postponement module is used to postpone a single-qubit quantum gate to before the nearest two-qubit quantum gate. The addition module is also used to add a barrier gate before the single-qubit quantum gate located before the nearest two-qubit quantum gate, resulting in a first optimized quantum circuit.

[0128] In some implementations, the processor is also used to postpone a single-qubit quantum gate to before the nearest two-qubit quantum gate, and to add a barrier gate before the single-qubit quantum gate located before the nearest two-qubit quantum gate, resulting in a first optimized quantum circuit.

[0129] Specifically, a single-qubit quantum gate is a fundamental building block in quantum computing; it is a quantum logic gate that operates on a single qubit.

[0130] A two-qubit quantum gate is a quantum logic gate in quantum computing that operates on two qubits simultaneously.

[0131] The computer device postpones the single-qubit quantum gate until before the nearest two-qubit quantum gate, which indicates the first two-qubit quantum gate in the second quantum circuit that operates on the same qubit as the single-qubit gate. Then, the computer device adds a barrier gate before the single-qubit quantum gate before the nearest two-qubit quantum gate, resulting in a first optimized quantum circuit. In this way, by postponing the single-qubit quantum gate until before the nearest two-qubit quantum gate, the time when the qubit enters the superposition state is delayed as much as possible, ensuring that the qubit participates in computation only when necessary, preventing premature entry into the superposition state from having an impact. Furthermore, by adding a barrier gate before the single-qubit quantum gate before the nearest two-qubit quantum gate, operations after the barrier gate are prevented from running prematurely, ensuring that some sub-circuits of the quantum circuit maintain a specific order or structure.

[0132] Continuing with the above examples, the single-qubit quantum gate is an H-gate. In some implementations, the single-qubit quantum gate is not limited to H-gates, and this is not a limitation here. The two-qubit quantum gate is a CZ-gate. In some implementations, the two-qubit quantum gate is not limited to CZ-gates, and this is not a limitation here.

[0133] When running on a computer device, a qubit in its ground state (|0>) is more stable than a qubit in a superposition state. Qubits in a superposition state are susceptible to noise from quantum gates, decoherence of the qubit itself, and bit flipping. In this embodiment, the H-gate is the key operation for converting a qubit from a stationary state to a superposition state.

[0134] Please refer to the following: Figure 7 Therefore, the computer device postpones the H gate in the second quantum circuit C2 to before the nearest CZ gate, which refers to the CZ gate in the second quantum circuit C2 that operates on the same qubit as the H gate. Next, the computer device adds a barrier gate P before the H gate located before the CZ gate, resulting in the first optimized quantum circuit C3.

[0135] Thus, by delaying the H gate until before the nearest CZ gate, the time when the qubit enters the superposition state is postponed as much as possible, ensuring that the qubit only participates in computation when necessary, preventing premature entry into the superposition state from having an impact. Furthermore, by adding a barrier gate P before the H gate located before the nearest CZ gate, the operation of the H gate after the barrier gate P is prevented from running prematurely, ensuring that some sub-circuits of the quantum circuit maintain a specific order or structure.

[0136] Please see Figure 12 In some implementations, the optimization method further includes:

[0137] 015: Merging multiple first barrier intervals in the first optimized quantum circuit yields the second optimized quantum circuit;

[0138] 016: Sequentially embed the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit to obtain the third optimized quantum circuit.

[0139] In some implementations, the merging module is used to merge multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit. The embedding module is used to sequentially embed single-qubit quantum gates from the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0140] In some embodiments, the processor is further configured to merge multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit, and to sequentially embed single-qubit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0141] Specifically, the computer device merges multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit. The first barrier intervals indicate the quantum circuit between every two barrier gates in the first optimized quantum circuit. The first starting barrier interval and the first ending barrier interval of the first optimized quantum circuit are each determined by a barrier gate. Next, the computer device sequentially embeds the single-qubit quantum gates from the first optimized quantum circuit into the second optimized quantum circuit to obtain a third optimized quantum circuit.

[0142] Following the example above, please refer to Figure 7 , Figure 13 and Figure 14 , Figure 13 For the second optimized quantum circuit, Figure 14 This is the third optimized quantum circuit. Multiple first barrier intervals A are A1-A10.

[0143] The computer device merges multiple first barrier intervals A in the first optimized quantum circuit C3 to obtain a second optimized quantum circuit C4. The first barrier interval A indicates the quantum circuit between every two barrier gates P in the first optimized quantum circuit C3. The first starting barrier interval A1 and the first ending barrier interval A10 of the first optimized quantum circuit C3 are each determined by a barrier gate P. Next, the computer device sequentially embeds the single-qubit quantum gates from the first optimized quantum circuit C3 into the second optimized quantum circuit C4 to obtain a third optimized quantum circuit C5.

[0144] Thus, by merging multiple first barrier intervals A in the first optimized quantum circuit C3, the depth of the quantum circuit is reduced, and the overall performance of the quantum circuit is improved. Furthermore, the single-qubit quantum gates in the first optimized quantum circuit C3 are sequentially embedded into the second optimized quantum circuit C4, ensuring that the resulting third optimized quantum circuit C5 is functionally equivalent to the first optimized quantum circuit C3.

[0145] Please see Figure 15 In some embodiments, step 015 (merging multiple first barrier intervals in the first optimized quantum circuit to obtain a second optimized quantum circuit) includes:

[0146] 0151: The first initial barrier interval is used as the second final barrier interval of the second optimized quantum circuit;

[0147] 0152: Compare the second end barrier interval with multiple first barrier intervals to obtain the second optimized quantum circuit.

[0148] In some embodiments, the processing module is further configured to use the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit. The comparison module is configured to compare the second ending barrier interval with a plurality of first barrier intervals to obtain the second optimized quantum circuit.

[0149] In some embodiments, the processor is further configured to use the first starting barrier region as the second ending barrier region of the second optimized quantum circuit, and to compare the second ending barrier region with a plurality of first barrier regions to obtain the second optimized quantum circuit.

[0150] Specifically, the second final barrier interval refers to the last barrier interval in the second optimized quantum circuit.

[0151] The computer device uses the first initial barrier region as the second final barrier region of the second optimized quantum circuit. Then, the computer device compares the second final barrier region with multiple first barrier regions to obtain the second optimized quantum circuit.

[0152] Following the example above, please refer to Figure 7 and Figure 13 The computer device uses the first starting barrier interval A1 as the second ending barrier interval of the second optimized quantum circuit C4. Then, the computer device compares the second ending barrier interval with multiple first barrier intervals A to obtain the second optimized quantum circuit C4.

[0153] Thus, by comparing the second end barrier interval with multiple first barrier intervals A, it can be confirmed whether these first barrier intervals A can be merged into the second end barrier interval, thereby reducing the depth of the quantum circuit and improving the execution efficiency of the quantum circuit.

[0154] Please see Figure 16 In some embodiments, step 0152 (comparing the second end barrier interval and multiple first barrier intervals to obtain the second optimized quantum circuit) includes:

[0155] 01521: Compare the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval;

[0156] 01522: If it is confirmed that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second last barrier interval to obtain the second optimized quantum circuit.

[0157] In some embodiments, the comparison module is further configured to compare the two-qubit quantum gate in the second end barrier interval with the current two-qubit quantum gate in the next first barrier interval to confirm the movement status of the current two-qubit quantum gate in the next first barrier interval. The movement module, if it confirms that the current two-qubit quantum gate in the next first barrier interval can move to the second end barrier interval, moves the current two-qubit quantum gate in the next first barrier interval to the second end barrier interval, thereby obtaining the second optimized quantum circuit.

[0158] In some embodiments, the processor is further configured to compare the two-qubit quantum gate in the second end barrier interval with the current two-qubit quantum gate in the next first barrier interval to determine the movement of the current two-qubit quantum gate in the next first barrier interval. And if it is determined that the current two-qubit quantum gate in the next first barrier interval can move to the second end barrier interval, the processor moves the current two-qubit quantum gate in the next first barrier interval to the second end barrier interval, thereby obtaining the second optimized quantum circuit.

[0159] Specifically, the computer device compares the two-qubit quantum gate in the second final barrier interval with the current two-qubit quantum gate in the next first barrier interval to confirm the movement of the current two-qubit quantum gate in the next first barrier interval. The next first barrier interval indicates the next first barrier interval in the first optimized quantum circuit that corresponds to the second final barrier interval. Then, if it is confirmed that the current two-qubit quantum gate in the next first barrier interval can move to the second final barrier interval, the computer device moves the current two-qubit quantum gate in the next first barrier interval to the second final barrier interval, thus obtaining the second optimized quantum circuit.

[0160] Following the example above, please refer to Figure 7 and Figure 13 The computer device compares the CZ gate in the second final barrier interval with the current CZ gate in the next first barrier interval A to confirm the movement of the current CZ gate in the next first barrier interval. The next first barrier interval indicates the next first barrier interval in the first optimized quantum circuit C3 located in the first barrier interval A corresponding to the second final barrier interval. Then, if it is confirmed that the current CZ gate in the next first barrier interval can move to the second final barrier interval, the computer device moves the current CZ gate in the next first barrier interval to the second final barrier interval, resulting in the second optimized quantum circuit C4.

[0161] Thus, by comparing the CZ gates in the second final barrier interval with the current CZ gates in the next first barrier interval, it is checked whether the CZ gates in the next first barrier interval can be moved to the second final barrier interval without affecting the execution order and result of the circuit. Furthermore, by moving the CZ gates from the next first barrier interval to the second final barrier interval, the computer device reduces the depth of the quantum circuit and improves its execution efficiency.

[0162] Please see Figure 17 In some embodiments, step 01521 (comparing the two-bit quantum gate in the second end barrier interval with the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval) includes:

[0163] 015211: If the qubits acting on the current two-bit quantum gate in the next first barrier interval are different from the qubits acting on each two-bit quantum gate in the second last barrier interval, it is confirmed that the current two-bit quantum gate in the next first barrier interval can move to the second last barrier interval.

[0164] 015212: If at least one of the qubits acting on the current two-bit quantum gate in the next first barrier interval is the same as the qubits acting on the two-bit quantum gate in the second last barrier interval, it is confirmed that the current two-bit quantum gate in the next first barrier interval cannot move to the second last barrier interval.

[0165] In some embodiments, the verification module is further configured to verify that the current two-qubit quantum gate in the next first barrier interval can move to the second last barrier interval if the qubits acting on the current two-qubit quantum gate in the next first barrier interval are not the same as those acting on each two-qubit quantum gate in the second last barrier interval. The verification module is also configured to verify that the current two-qubit quantum gate in the next first barrier interval cannot move to the second last barrier interval if at least one of the qubits acting on the current two-qubit quantum gate in the next first barrier interval is the same as that acting on at least one of the qubits acting on the current two-qubit quantum gate in the second last barrier interval.

[0166] In some embodiments, the processor is further configured to confirm that the current two-qubit quantum gate in the next first barrier interval can move to the second last barrier interval if the qubits acting on the current two-qubit quantum gate in the next first barrier interval are not the same as those acting on each two-qubit quantum gate in the second last barrier interval; and to confirm that the current two-qubit quantum gate in the next first barrier interval cannot move to the second last barrier interval if at least one of the qubits acting on the current two-qubit quantum gate in the next first barrier interval is the same as that acting on at least one of the qubits acting on the current two-qubit quantum gate in the second last barrier interval.

[0167] Specifically, if the qubits acting on the current two-qubit quantum gate in the next first barrier interval are not the same as those acting on each of the two-qubit quantum gates in the second last barrier interval, the computer device confirms that the current two-qubit quantum gate in the next first barrier interval can be moved to the second last barrier interval. Then, if at least one qubit in the current two-qubit quantum gate in the next first barrier interval is the same as that in the second last barrier interval, the computer device confirms that the current two-qubit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval. Thus, by determining the consistency between the qubits acting on the current two-qubit quantum gate in the next first barrier interval and each of the two-qubit quantum gates in the second last barrier interval, it is confirmed that moving the two-qubit quantum gate will not affect the correct execution of the quantum circuit. If the qubits acting on the current two-qubit quantum gate in the next first barrier interval are completely different from those in the second last barrier interval, i.e., no qubits are the same in both intervals, then the computer device confirms that the current two-qubit quantum gate in the next first barrier interval can be moved to the second last barrier interval, and the move operation is performed to obtain the optimized quantum circuit. If at least one of the qubits acting on the current two-bit quantum gate in the next first barrier interval is the same as the qubits acting on the two-bit quantum gate in the second last barrier interval, then the computer device confirms that the current two-bit quantum gate in the next first barrier interval cannot be moved to the second last barrier interval, and the current quantum circuit structure remains unchanged.

[0168] Following the above example, please refer to Figure 7 and Figure 13If the qubits acting on the current CZ gate in the next first barrier interval are not the same as those acting on each CZ gate in the second final barrier interval, the computer device confirms that the current CZ gate in the next first barrier interval can move to the second final barrier interval. Then, if at least one qubit in the qubits acting on the current CZ gate in the next first barrier interval is the same as that acting on the qubits acting on the two-qubit gate in the second final barrier interval, the computer device confirms that the current two-qubit gate in the next first barrier interval cannot move to the second final barrier interval.

[0169] Thus, by determining the consistency between the qubits affected by the current CZ gate in the next first barrier interval and the qubits affected by each CZ gate in the second final barrier interval, it is confirmed that moving the CZ gate will not affect the correct execution of the quantum circuit. If the qubits affected by the current CZ gate in the next first barrier interval are completely inconsistent with the qubits affected by the CZ gate in the second final barrier interval, i.e., no qubits are the same in both intervals, then the computer device confirms that the current CZ gate in the next first barrier interval can be moved to the second final barrier interval to perform the move operation and obtain the optimized quantum circuit. If at least one qubit is consistent between the qubits affected by the current CZ gate in the next first barrier interval and the qubits affected by the CZ gate in the second final barrier interval, then the computer device confirms that the current CZ gate in the next first barrier interval cannot be moved to the second final barrier interval, and the current quantum circuit structure remains unchanged.

[0170] Please see Figure 18 In some embodiments, step 0151 (using the first starting barrier region as the second ending barrier region of the second optimized quantum circuit) includes:

[0171] 01511: If the next first barrier interval includes a two-qubit quantum gate, the next first barrier interval shall be used as the second end barrier interval of the second optimized quantum circuit.

[0172] In some implementations, the processing module is configured to use the next first barrier interval as the second end barrier interval of the second optimized quantum circuit if the next first barrier interval includes a two-qubit quantum gate.

[0173] In some implementations, the processor is further configured to use the next first barrier interval as the second end barrier interval of the second optimized quantum circuit if the next first barrier interval includes a two-bit quantum gate.

[0174] Specifically, if the next first barrier interval includes a two-qubit quantum gate, the next first barrier interval is used as the second end barrier interval of the second optimized quantum circuit.

[0175] Following the example above, please refer to Figure 7 and Figure 13 If the next first barrier interval includes the CZ gate, the next first barrier interval shall be used as the second end barrier interval of the second optimized quantum circuit C4.

[0176] Thus, in the first optimized quantum circuit C3, the next barrier region including the CZ gate is found, and this region is called the next first barrier region. Furthermore, this next first barrier region is used as the second ending barrier region of the second optimized quantum circuit. This means that the ending position of the second optimized quantum circuit C4 is set to this region including the CZ gate, and subsequently, this region including the CZ gate is used to merge the remaining first barrier regions A in the first optimized quantum circuit C3.

[0177] Please see Figure 19 In some implementations, the method further includes:

[0178] 01523: If the next first barrier interval does not include a two-bit quantum gate, the second end barrier interval and multiple first barrier intervals are compared to obtain the second optimized quantum circuit.

[0179] In some implementations, the comparison module is also used to compare the second end barrier interval and multiple first barrier intervals to obtain a second optimized quantum circuit if the next first barrier interval does not include a two-bit quantum gate.

[0180] In some implementations, the processor is also configured to compare a second end barrier interval with multiple first barrier intervals to obtain a second optimized quantum circuit, provided that the next first barrier interval does not include a two-bit quantum gate.

[0181] Specifically, when the next first barrier interval does not include a two-qubit quantum gate, the computer device compares the second last barrier interval with multiple first barrier intervals to obtain a second optimized quantum circuit.

[0182] Following the example above, please refer to Figure 7 and Figure 13 If the next first barrier interval does not include the CZ gate, the computer device compares the second end barrier interval with multiple first barrier intervals to obtain the second optimized quantum circuit C4.

[0183] Thus, if the next first barrier interval does not include CZ gates, that is, all CZ gates in the next first barrier interval have been merged into the second last barrier interval, then the second last barrier interval is still used as the new second last barrier interval, and the remaining first barrier interval A in the first optimized quantum circuit C3 is merged.

[0184] Following the example above, the merging process of the first optimized quantum circuit will be fully explained below:

[0185] Please see Figure 7 and Figure 13 , Figure 7 The first optimized quantum circuit C3 is divided into 10 first barrier intervals, namely A1-A10. First, the first initial barrier interval A1 is taken as the second final barrier interval of the second optimized quantum circuit C4. The next first barrier interval is then A2. It can be seen that there are no CZ gates (two-qubit quantum gates) in this second final barrier interval. Therefore, there are no CZ gates in A2 acting on the same qubit as the CZ gates in A1. Thus, it can be determined that the CZ gates in A2 can be moved into the second final barrier interval. It can be observed that there are no two-qubit quantum gates in A2, so the second final barrier interval remains the same as before.

[0186] Then, comparing the next first barrier interval A3 of A2 with the second final barrier interval, we can find that one of the qubits affected by the CZ gate in A3 is qubit q24, which is also affected by the CZ gate in the second final barrier interval. We determine that this CZ gate cannot move to the second final barrier interval. Since A3 contains only one CZ gate, after judging this CZ gate, we can determine whether to use this first barrier interval A3 as the new second final barrier interval or keep the second final barrier interval unchanged. We can see that A3 also contains a CZ gate, so we should use this A3 containing the CZ gate as the new second final barrier interval.

[0187] The merging process for the first barrier interval A4 is the same as that for A3, and will not be repeated here.

[0188] After merging the first barrier interval A4, the second final barrier interval is now the second barrier interval B2, which includes two CZ gates. Now, merging the first barrier interval A5, and comparing the qubits affected by the CZ gates in A5 with the two qubits affected by the CZ gates in the second final barrier interval, we can find that qubit q19, used by the CZ gates in A5, is also affected by the CZ gates in the second final barrier interval. We need to determine whether the CZ gates in A5 affecting q19 and q12 can be merged into the second final barrier interval. Assuming A5 contains more than one CZ gate, after determining the CZ gate affecting q19 and q12, we also need to compare the remaining qubits affected by the CZ gates in A5 with the qubits affected by the CZ gates in the second final barrier interval. Determine whether the remaining CZ gates in A5 can be merged into the second end interval. Continue this process until all CZ gates in A5, i.e., two-bit quantum gates, have been determined. Then, determine whether to use this first barrier interval A5 as the new second end barrier interval or to keep the second end barrier interval unchanged.

[0189] The merging process for A6, A7, A8, A9, and A10 is the same as the process for A1-A5 described above, and will not be repeated here. The final second optimized quantum circuit is as follows. Figure 13 As shown.

[0190] This application also provides a computer-readable storage medium containing a computer program. When the computer program is executed by one or more processors, it causes the one or more processors to perform an optimized method for the quantum circuit of this application.

[0191] It is understood that a computer program includes computer program code. Computer program code can be in the form of source code, object code, executable files, or some intermediate form. Computer-readable storage media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, external hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), and software distribution media, etc.

[0192] In this specification, the terms "specifically," "furthermore," "particularly," "understandably," etc., refer to specific features, structures, materials, or characteristics described in connection with embodiments or examples that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0193] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0194] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An optimization method for quantum circuits based on timing alignment, characterized in that, The method includes: The first quantum circuit is determined based on the quantum gate dependencies in the quantum circuit; The target quantum gate in the first quantum circuit is processed to obtain the second quantum circuit; A first optimized quantum circuit is obtained by delaying the single-bit quantum gates in the second quantum circuit according to the barrier gate, so as to optimize the quantum circuit. The barrier gate is configured to prevent the quantum gates after the barrier gate in the quantum circuit from running prematurely. Determining the first quantum circuit based on the quantum gate dependencies in the quantum circuit includes: The parallel quantum gates that can operate in parallel in the quantum circuit are determined by the aforementioned dependencies; The execution sequence of the quantum gates in the quantum circuit is rearranged according to the parallel quantum gates to obtain the first quantum circuit; The process of processing the target quantum gate in the first quantum circuit to obtain the second quantum circuit includes: The target quantum gate is processed according to the pre-supported quantum instruction set to obtain the second quantum circuit.

2. The optimization method according to claim 1, characterized in that, The method further includes: The first quantum circuit is functionally equivalent to the quantum circuit by performing simulation tests to ensure that the first quantum circuit and the quantum circuit are functionally equivalent.

3. The optimization method according to claim 1, characterized in that, The step of delaying the single-bit quantum gates in the second quantum circuit according to the barrier gate to obtain the first optimized quantum circuit includes: The single-bit quantum gate is postponed to before the nearest two-bit quantum gate, which is used to indicate the first two-bit quantum gate in the second quantum circuit that operates on the same quantum bit as the single-bit quantum gate. The first optimized quantum circuit is obtained by adding the barrier gate before the single-bit quantum gate located before the nearest two-bit quantum gate.

4. The optimization method according to claim 1, characterized in that, The optimization method further includes: A second optimized quantum circuit is obtained by merging multiple first barrier intervals in the first optimized quantum circuit, wherein the first barrier interval is used to indicate the quantum circuit between every two barrier gates in the first optimized quantum circuit, and the first starting barrier interval and the first ending barrier interval of the first optimized quantum circuit are each determined by one of the barrier gates. By sequentially embedding the single-bit quantum gates in the first optimized quantum circuit into the second optimized quantum circuit, a third optimized quantum circuit is obtained.

5. The optimization method according to claim 4, characterized in that, The step of merging multiple first barrier regions in the first optimized quantum circuit to obtain the second optimized quantum circuit includes: The first initial barrier interval is used as the second final barrier interval of the second optimized quantum circuit; A second optimized quantum circuit is obtained by comparing the second end barrier interval with multiple first barrier intervals.

6. The optimization method according to claim 5, characterized in that, The comparison of the second end barrier interval and multiple first barrier intervals to obtain the second optimized quantum circuit includes: The two-bit quantum gate in the second end barrier interval and the current two-bit quantum gate in the next first barrier interval are compared to confirm the movement of the current two-bit quantum gate in the next first barrier interval, wherein the next first barrier interval is used to indicate the next first barrier interval in the first optimized quantum circuit that is located in the first barrier interval corresponding to the second end barrier interval; If it is confirmed that the current two-bit quantum gate in the next first barrier interval can be moved to the second last barrier interval, the current two-bit quantum gate in the next first barrier interval is moved to the second last barrier interval to obtain the second optimized quantum circuit.

7. The optimization method according to claim 6, characterized in that, The comparison process between the two-bit quantum gate in the second final barrier interval and the current two-bit quantum gate in the next first barrier interval to confirm the movement of the current two-bit quantum gate in the next first barrier interval includes: If the qubits acting on the current two-bit quantum gate in the next first barrier interval are different from the qubits acting on each two-bit quantum gate in the second last barrier interval, it is confirmed that the current two-bit quantum gate in the next first barrier interval can move to the second last barrier interval. If at least one qubit of the current two-bit quantum gate in the next first barrier interval is the same as the qubit of the two-bit quantum gate in the second last barrier interval, it is confirmed that the current two-bit quantum gate in the next first barrier interval cannot move to the second last barrier interval.

8. The optimization method according to claim 7, characterized in that, The step of using the first starting barrier interval as the second ending barrier interval of the second optimized quantum circuit includes: If the next first barrier interval includes a two-bit quantum gate, the next first barrier interval shall be used as the second end barrier interval of the second optimized quantum circuit.

9. The optimization method according to claim 7, characterized in that, The method further includes: If the next first barrier interval does not include a two-bit quantum gate, the second end barrier interval and multiple first barrier intervals are compared to obtain a second optimized quantum circuit.

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