Clock signal generation circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a clock signal generation circuit, a chip and electronic equipment, and the clock signal generation circuit comprises a reference voltage module which is used for outputting a reference voltage; the voltage-controlled oscillation module is used for oscillating and outputting a clock signal under the control of the control voltage; the voltage feedback module is used for outputting feedback voltage according to the clock signal, and the magnitude of the feedback voltage is negatively correlated with the frequency of the clock signal; the error amplification module is used for outputting a control voltage according to the reference voltage and the feedback voltage; wherein the reference voltage periodically changes in at least part of the time period in the working process of the clock signal generation circuit. According to the application, the frequency of the clock signal is periodically changed near the target frequency, and finally, the electromagnetic interference phenomenon caused by too high fundamental frequency energy of the clock signal is weakened.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock signal generating circuit, a chip and an electronic device. Background Art

[0002] At present, the RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. In circuits on chip systems that do not require high clock source accuracy and frequency, RC oscillators are widely used due to their low cost, fast circuit startup, and easy on-chip integration.

[0003] When the RC oscillator generates a fixed-frequency clock signal to control the operation of the corresponding circuit, for example, when the fixed-frequency clock signal is used to control the switch action, the working circuit will usually generate a large electromagnetic interference (EMI) signal. In the related art, clock spectrum spreading of the RC oscillator is an effective method to reduce chip electromagnetic interference. It adjusts the current of capacitor charging and discharging or changes the capacitance value of the capacitor, thereby changing the charging and discharging speed of the capacitor to expand the frequency of the clock signal, thereby spreading the energy contained in the narrow band of the clock source into a wider frequency band, reducing the peak frequency domain energy of the fundamental frequency and harmonic frequency, and finally weakening the electromagnetic interference phenomenon when the circuit is working.

[0004] However, the clock circuit based on the RC oscillator is subject to many non-ideal factors. For example, during the operation of the RC oscillator, a comparator is required to compare the reference voltage with the voltage during the charging and discharging process of the capacitor. The delay of the comparator will seriously worsen the frequency drift of the RC oscillator, which leads to the problem of reduced output frequency accuracy of the RC oscillator. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide a clock signal generating circuit, a chip and an electronic device to solve the above technical problems.

[0006] In a first aspect, an embodiment of the present application provides a clock signal generating circuit, comprising:

[0007] A reference voltage module, which is used to output a reference voltage;

[0008] A voltage-controlled oscillator module, which is used to oscillate under the control of a control voltage and output a clock signal;

[0009] A voltage feedback module, the voltage feedback module is used to output a feedback voltage according to a clock signal, and the magnitude of the feedback voltage is negatively correlated with the frequency of the clock signal;

[0010] An error amplification module, the error amplification module is used to output a control voltage according to a reference voltage and a feedback voltage;

[0011] The reference voltage changes periodically in at least a partial period of time during the operation of the clock signal generating circuit.

[0012] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned clock signal generating circuit.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or clock signal generating circuit.

[0014] The present application forms a loop through an error amplification module, a voltage feedback module and a voltage-controlled oscillation module, and the voltage feedback module serves as a negative feedback module to output a feedback voltage. Through negative feedback control, the voltage-controlled oscillation module can output a clock signal of a target frequency. The process of generating a clock signal does not require the participation of a comparator, and ultimately the influence of the delay of the comparator on the frequency accuracy of the clock signal can be avoided. At the same time, since the reference voltage changes periodically in some time periods during the operation of the clock signal generating circuit, the clock signal output by the voltage-controlled oscillation module will also change periodically with the reference voltage, thereby causing the frequency of the clock signal to change periodically near the target frequency, which ultimately helps to weaken the electromagnetic interference caused by the clock signal.

[0015] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A circuit diagram of an RC oscillator in the related art is shown.

[0018] Figure 2 A schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0019] Figure 3 A schematic diagram showing a change of reference voltage and control voltage in an embodiment of the present application is shown.

[0020] Figure 4 A schematic diagram of a frequency spectrum of a clock signal in an embodiment of the present application is shown.

[0021] Figure 5 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0022] Figure 6Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0023] Figure 7 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0024] Figure 8 A schematic diagram of a reference voltage module in an embodiment of the present application is shown.

[0025] Fig. 9 Another schematic diagram of the reference voltage module in the embodiment of the present application is shown.

[0026] Fig.10 Another schematic diagram of the reference voltage module in the embodiment of the present application is shown.

[0027] Fig.11 Another schematic diagram of the reference voltage module in the embodiment of the present application is shown.

[0028] Fig.12 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0029] Fig.13 Another schematic diagram of the reference voltage module in the embodiment of the present application is shown.

[0030] Fig.14 Another schematic diagram of the reference voltage module in the embodiment of the present application is shown.

[0031] Fig.15 A schematic diagram of a voltage feedback module in an embodiment of the present application is shown.

[0032] Fig.16 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0033] Among them, 10 is a reference voltage module, 11 is a first current mirror unit, 12 is a second current mirror unit, 13 is a resistance unit, 101 is a charge and discharge unit, 102 is a capacitance unit, 20 is a voltage-controlled oscillation module, 30 is a voltage feedback module, 31 is a non-overlapping clock unit, 40 is an error amplification module,

[0034] Reference voltage Vref, control voltage Vctrl, clock signal CLK, first clock signal CLK1, second clock signal CLK2, feedback voltage VFB, first mirror current I1, second mirror current I2, third mirror current I3, reference voltage VBG, first preset voltage V1, second preset voltage V2, third preset voltage V3;

[0035] A first operational amplifier OP1, a first transistor M1, a first resistor R1, a first mirror transistor MP1, a second mirror transistor MP2, a third mirror transistor MP3, a first switch S1, a second operational amplifier OP2, a second transistor M2, a second resistor R2, a fourth mirror transistor MP4, a fifth mirror transistor MP5, and a second switch S2;

[0036] A first current source IS1, a second current source IS2, a third switch S3, a fourth switch S4, a fifth switch S5, a first comparator COMP1, a second comparator COMP2, a third current source IS3, a first capacitor C1, a second capacitor C2, a sixth switch S6, and a seventh switch S7. DETAILED DESCRIPTION

[0037] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0038] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0039] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0040] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0041] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0042] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0043] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0044] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0045] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0046] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0047] At present, the RC oscillator is an oscillation circuit that generates a clock signal by cyclically charging and discharging a capacitor and comparing the voltage during the charging and discharging process. Figure 1 , Figure 1 A circuit diagram of an RC oscillator in the related art is shown, where the RC oscillator includes a comparator COMP1, a comparator COMP2, an RS trigger composed of two NAND gates, a capacitor Cx, a capacitor Cy, a transistor MN1 for controlling the charging and discharging of the capacitor Cx, and a transistor MN2 for controlling the charging and discharging of the capacitor Cy.

[0048] During the operation of the RC oscillator, the two NAND gates output control signals OUT1 and OUT2 respectively, thereby controlling transistors MN1 and MN2 to alternately charge capacitors Cx and Cy. When the output voltages IN1 and IN2 of capacitors Cx and Cy exceed the reference voltage Vref, one of capacitors Cx and Cy is switched to be charged and the other is discharged, thereby causing the output ends of comparators COMP1 and COMP2 to output clock signals that alternate between high and low levels.

[0049] In an ideal case where loop delay (such as comparator delay) is not considered, the capacitor Cx\Cy is charged to the reference voltage Vref for half a cycle of the clock signal. It can be seen that the oscillation frequency f of the output clock signal is:

[0050] f=N / (2RC)

[0051] Wherein, N is the ratio of the charging current NIref of the capacitor Cx\Cy to the reference current Iref, R is the resistor corresponding to the reference voltage Vref, and C is the capacitance value of the capacitor Cx\Cy.

[0052] In the actual case of considering the comparator delay, the actual oscillation frequency f of the output clock signal is:

[0053] f=N / 2(RC+t)

[0054] Where t is the time corresponding to the comparator delay.

[0055] It can be seen that since the RC oscillator needs to compare the reference voltage with the voltage during the charging and discharging process of the capacitor through a comparator during operation, the delay of the comparator will seriously worsen the frequency drift of the RC oscillator. If the clock signal is spread by adjusting the charging and discharging current of the capacitor or changing the capacitance value of the capacitor, the frequency accuracy of the clock signal will also decrease.

[0056] To this end, the present application provides a clock signal generating circuit, a chip and an electronic device, which are described in detail below.

[0057] First, see Figure 2 , Figure 2 A schematic diagram of a clock signal CLK generating circuit in an embodiment of the present application is shown, wherein the clock signal CLK generating circuit includes a reference voltage module 10, a voltage-controlled oscillation module 20, a voltage feedback module 30 and an error amplification module 40.

[0058] Specifically, the reference voltage module 10 is used to output a reference voltage Vref so as to control the magnitude of the control voltage Vctrl output by the error amplification module 40. In some embodiments of the present application, the reference voltage module 10 can generate the reference voltage Vref through a resistor, for example, the reference voltage module 10 controls the magnitude of the current flowing through the resistor, thereby generating the reference voltage Vref at one end of the resistor into which the current flows. In some embodiments of the present application, the reference voltage module 10 can generate a reference current through a capacitor, for example, the reference voltage module 10 controls the way of charging and discharging the capacitor, thereby generating the reference voltage Vref at one end of the capacitor into which the current flows / flows out.

[0059] It is understandable that the reference voltage module 10 may also output the reference voltage Vref in other ways, such as a bandgap reference circuit, a low voltage drop linear regulator, a BOOST boost circuit, a BUCK buck circuit, etc.

[0060] The control end of the voltage-controlled oscillation module 20 is connected to the output end of the error amplification module 40 to oscillate and output the clock signal CLK under the control of the control voltage Vctrl. The frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is controlled by the size of the control voltage Vctrl. In some embodiments of the present application, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is positively correlated with the size of the control voltage Vctrl. For example, when the control voltage Vctrl is larger, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is larger; conversely, when the control voltage Vctrl is smaller, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is smaller. In some embodiments of the present application, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is negatively correlated with the size of the control voltage Vctrl. For example, when the control voltage Vctrl is smaller, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is larger; conversely, when the control voltage Vctrl is larger, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 is smaller.

[0061] Exemplarily, the voltage-controlled oscillator module 20 may include but is not limited to a harmonic oscillator or a relaxation oscillator, wherein the harmonic oscillator is such as an LC crystal oscillator and a crystal oscillator, and the relaxation oscillator is such as a delay-based ring voltage-controlled oscillator, a grounded capacitor-based voltage-controlled oscillator, and an emitter-coupled voltage-controlled oscillator.

[0062] The voltage feedback module 30 is used to output a feedback voltage VFB according to the clock signal CLK, wherein the magnitude of the feedback voltage VFB is negatively correlated with the frequency of the clock signal CLK. For example, when the frequency of the clock signal CLK is higher, the voltage value of the feedback voltage VFB is larger; conversely, when the frequency of the clock signal CLK is lower, the voltage value of the feedback voltage VFB is smaller.

[0063] In some embodiments of the present application, the voltage feedback module 30 may include a switched capacitor circuit. Since the capacitor has the characteristic of passing alternating current and blocking direct current, the higher the frequency of the clock signal CLK controlling the switch to open / close, the smaller the impedance of the capacitor, and the switched capacitor circuit can generate a larger feedback voltage VFB; conversely, the lower the frequency of the clock signal CLK controlling the switch to open / close, the larger the impedance of the capacitor, and the switched capacitor circuit can generate a smaller feedback voltage VFB.

[0064] In some embodiments of the present application, the voltage feedback module 30 may include a switching inductor circuit. Since the inductor has the characteristic of passing direct current but blocking alternating current, the higher the frequency of the clock signal CLK controlling the switch to open / close, the greater the impedance of the inductor, and the switching inductor circuit can generate a larger feedback voltage VFB; conversely, the lower the frequency of the clock signal CLK controlling the switch to open / close, the smaller the impedance of the inductor, and the switching inductor circuit can generate a smaller feedback voltage VFB.

[0065] The error amplification module 40 is used to output a control voltage Vctrl according to a reference voltage Vref and a feedback voltage VFB, so as to control the voltage-controlled oscillation module 20 to oscillate and output a clock signal CLK through the control voltage Vctrl. As an example, the error amplification module 40 may include an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the reference voltage Vref, and the inverting input terminal of the operational amplifier is connected to the feedback voltage VFB. Due to the virtual short and virtual break characteristics of the operational amplifier, the control voltage Vctrl output by the operational amplifier changes the frequency of the clock signal CLK, so that the feedback voltage VFB follows the frequency change of the clock signal CLK and approaches the reference voltage Vref. Finally, after the error amplification module 40, the voltage feedback module 30 and the voltage-controlled oscillation module 20 form a loop stability, the frequency of the clock signal CLK is locked to ensure the stability of the clock signal CLK.

[0066] It can be seen that the present application enables the error amplification module 40, the voltage feedback module 30 and the voltage-controlled oscillation module 20 to form a loop, and the voltage feedback module 30 is used as a negative feedback module to output the feedback voltage VFB and combine with the reference voltage Vref to control the magnitude of the control voltage Vctrl output by the error amplification module 40, so that the voltage-controlled oscillation module 20 can output the clock signal CLK of the target frequency f0 through negative feedback, and the process of generating the clock signal CLK does not require the participation of the comparator, and finally the delay of the comparator can be avoided. The influence of the frequency accuracy of the oscillation circuit. At the same time, in the embodiment of the present application, since the reference voltage Vref changes periodically in some time periods during the operation of the clock signal CLK generating circuit, the frequency of the clock signal CLK output by the voltage-controlled oscillation module 20 will also change periodically with the reference voltage Vref, so that the frequency of the clock signal CLK changes periodically near the target frequency f0, and finally the electromagnetic interference caused by the clock signal CLK is weakened.

[0067] In some embodiments of the present application, before the frequency of the clock signal CLK is first stabilized, the magnitude of the reference voltage Vref is equal to a first preset value. After the frequency of the clock signal CLK is first stabilized, the reference voltage Vref changes periodically and the average magnitude is equal to the first preset value.

[0068] For example, see Figure 3 , Figure 3 A schematic diagram of the changes of the reference voltage Vref and the control voltage Vctrl in an embodiment of the present application is shown. Before time t1, the reference voltage Vref remains unchanged at the first preset value, and the control voltage Vctrl gradually increases to increase the frequency of the clock signal CLK. After the frequency of the clock signal CLK exceeds the target frequency f0, the control voltage Vctrl decreases, and at time t1, the frequency of the clock signal CLK is stabilized near the target frequency f0 for the first time. After time t2, the reference voltage Vref changes periodically and the average size is equal to the first preset value, so that the control voltage Vctrl output by the error amplification module 40 changes periodically, and finally the purpose of spectrum spreading of the clock signal CLK is achieved under the control of the periodically changing control voltage Vctrl.

[0069] It should be noted that, in combination with the foregoing content, it can be seen that changing the size of the reference voltage Vref can change the frequency of the clock signal CLK. Therefore, the first preset value is a set parameter value corresponding to the frequency of the control clock signal CLK. Technical personnel in this field can set the size of the reference voltage Vref corresponding to the first preset value according to actual needs (such as the frequency of the clock signal CLK), such as 1V, 2V, 2.2V, etc., and this application does not make specific limitations.

[0070] Continue reading Figure 4 , Figure 4A spectrum diagram of the clock signal CLK in the embodiment of the present application is shown. It can be seen that when the frequency of the clock signal CLK is stable at the target frequency f0 between the time t1 and the time t2, the energy of the clock signal CLK is concentrated at the target frequency f0, so the electromagnetic interference phenomenon when the circuit is working is more serious. After the time t2, the frequency of the clock signal CLK changes periodically around the target frequency f0, and the energy contained in the narrow band of the clock signal CLK is spread over a wider frequency band. Compared with the clock signal CLK between the time t1 and the time t2, the peak frequency domain energy of the fundamental frequency and the harmonic frequency is reduced, which is ultimately conducive to weakening the electromagnetic interference phenomenon when the circuit is working.

[0071] It can be understood that in some possible embodiments, the reference voltage module 10 can also make the reference voltage Vref change periodically and the average magnitude equal to the first preset value before the frequency of the clock signal CLK is stabilized for the first time. That is, the reference voltage module 10 can also start the spectrum spreading process of the clock signal CLK before the clock signal CLK is stabilized.

[0072] In some embodiments of the present application, for example, for an embodiment in which the reference voltage module 10 can generate a reference current through a resistor, see Figure 5 , Figure 5 Another schematic diagram of the clock signal CLK generating circuit in an embodiment of the present application is shown, wherein the reference voltage module 10 includes a first current mirror unit 11, a second current mirror unit 12 and a resistor unit 13; the first current mirror unit 11 is used to output a mirror current of a fixed magnitude, and the second current mirror unit 12 is used to output a mirror current of a periodically changing magnitude; the resistor unit 13 is used to generate a reference voltage Vref according to the mirror current output by the first current mirror unit 11 and / or the second current mirror unit 12.

[0073] It should be noted that, since the first current mirror unit 11 can output a mirror current of fixed magnitude, and the second current mirror unit 12 can output a mirror current of periodically changing magnitude, before the frequency of the clock signal CLK is stabilized for the first time, the reference voltage module 10 can control the first current mirror unit 11 to output a mirror current, thereby utilizing the mirror current of fixed magnitude to pass through the resistor unit 13 and generate a reference voltage Vref of fixed magnitude; and after the frequency of the clock signal CLK is stabilized for the first time, the reference voltage module 10 can control the second current mirror unit 12 to output a mirror current, thereby utilizing the mirror current of periodically changing magnitude to pass through the resistor unit 13 and generate a reference voltage Vref of periodically changing magnitude.

[0074] Exemplarily, the first current mirror unit 11 and the second current mirror unit 12 may include one or more current sources, the current source of the first current mirror unit 11 may be such as a voltage-controlled current source (VCCS) or a current-controlled current source (CCCS), and the current source of the second current mirror unit 12 may be such as a triangular wave current source, a pulse current source, a sinusoidal wave current source, etc.

[0075] In some embodiments of the present application, the first current mirror unit 11 and the second current mirror unit 12 can output a single current signal, for example, Figure 6 , Figure 6 Another schematic diagram of the clock signal CLK generating circuit in an embodiment of the present application is shown, the first current mirror unit 11 is used to output the second mirror current I2, the first switch S1 controls whether the second mirror current I2 flows into the resistor unit 13, the second current mirror unit 12 is used to output the third mirror current I3, the second switch S2 controls whether the third mirror current I3 flows into the resistor, wherein the third mirror current I3 changes periodically and its average magnitude is equal to the second mirror current I2, so the reference voltage Vref generated based on the third mirror current I3 will change periodically, and its average magnitude is equal to the magnitude of the reference voltage Vref generated based on the second mirror current I2.

[0076] In some embodiments of the present application, the first current mirror unit 11 and / or the second current mirror unit 12 may output a plurality of current signals, for example, Figure 7 , Figure 7 Another schematic diagram of the clock signal CLK generating circuit in an embodiment of the present application is shown, the first current mirror unit 11 is used to output the first mirror current I1 and the second mirror current I2, the second current mirror unit 12 is used to output the third mirror current I3, the first switch S1 controls whether the second mirror current I2 flows into the resistor unit 13, the second switch S2 controls whether the third mirror current I3 flows into the resistor unit 13, and the third mirror current I3 changes periodically and its average magnitude is equal to the second mirror current I2.

[0077] It should be noted that in Figure 7In the embodiment, whether before or after the frequency of the clock signal CLK is stabilized for the first time, the first mirror current I1 flows into the resistor unit 13. Therefore, before the frequency of the clock signal CLK is stabilized for the first time, the reference voltage Vref output by the reference voltage module 10 is: Vref = (I1 + I2) * R, and after the frequency of the clock signal CLK is stabilized for the first time, the reference voltage Vref output by the reference voltage module 10 is: Vref = (I1 + I3) * R. Since the third mirror current I3 changes periodically and its average value is equal to the second mirror current I2, not only can the reference voltage Vref generated based on the first mirror current I1 and the third mirror current I3 change periodically, but also its average value can be equal to the reference voltage Vref based on the first mirror current I1 and the second mirror current I2.

[0078] It can be understood that the first current mirror unit 11 can also output more fixed mirror currents; or, the second current mirror unit 12 can also output multiple mirror currents with periodic changes in size, or one or more fixed mirror currents and one or more mirror currents with periodic changes in size, so as to adjust the size of the reference voltage Vref.

[0079] As an exemplary embodiment of the first current mirror unit 11, see Figure 8 , Figure 8 A schematic diagram of a reference voltage module 10 in an embodiment of the present application is shown, wherein the first current mirror unit 11 includes a first operational amplifier OP1, a first transistor M1, a first resistor R1, a first mirror transistor MP1 and a second mirror transistor MP2; the first end of the first mirror transistor MP1 is connected to the power supply end VDD, and the control end of the first mirror transistor MP1 is connected to the second end of the first mirror transistor MP1; the first end of the second mirror transistor MP2 is connected to the power supply end VDD, the control end of the second mirror transistor MP2 is connected to the control end of the first mirror transistor MP1, and the second end of the second mirror transistor MP2 is connected to the resistor unit 13 to input the mirror current to the resistor unit 13; the first end of the first transistor M1 is connected to the second end of the first mirror transistor MP1, the second end of the first transistor M1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the ground end; the first input end of the first operational amplifier OP1 is connected to the reference voltage VBG, the second input end of the first operational amplifier OP1 is connected to the first end of the first resistor R1, and the output end of the first operational amplifier OP1 is connected to the control end of the first transistor M1.

[0080] It should be noted that the reference voltage VBG can be provided by a bandgap reference source. Since the operational amplifier has a virtual short and virtual open characteristic, the voltage at the first end of the first resistor R1 is equal to the reference voltage VBG connected to the first input end of the first operational amplifier OP1. Therefore, the current flowing through the first mirror transistor MP1, the first transistor M1, and the first resistor R1 is:

[0081] I=VBG / R1

[0082] At the same time, since the source voltage and gate voltage of the first mirror transistor MP1 and the second mirror transistor MP2 are equal, the first mirror transistor MP1 and the second mirror transistor MP2 form a current mirror. It can be known that the current flowing through the second mirror transistor MP2 (i.e., the first mirror current I1) is:

[0083] I1=I / n1=VBG / (R1*n1)

[0084] Wherein, n1 is the mirror ratio between the first mirror transistor MP1 and the second mirror transistor MP2.

[0085] It can be seen that since the reference voltage VBG is fixed, the above circuit structure can output a first mirror current I1 of fixed magnitude, so that before the frequency of the clock signal CLK is first stabilized, a reference voltage Vref of fixed magnitude is output to the error amplification module 40 through the resistor unit 13.

[0086] In some embodiments of the present application, for example, for an embodiment in which the first current mirror unit 11 can output multiple current signals, see Fig. 9 , Fig. 9 Another schematic diagram of the reference voltage module 10 in the embodiment of the present application is shown, wherein the first current mirror unit 11 further includes a third mirror transistor MP3 and a first switch S1; the first end of the third mirror transistor MP3 is connected to the power supply end VDD, and the control end of the third mirror transistor MP3 is connected to the control end of the second mirror transistor MP2; the first end of the first switch S1 is connected to the second end of the third mirror transistor MP3, and the second end of the first switch S1 is connected to the resistor unit 13.

[0087] Similarly, since the source voltage and gate voltage of the first mirror transistor MP1 and the third mirror transistor MP3 are equal, the first mirror transistor MP1 and the third mirror transistor MP3 form a current mirror. It can be seen that when the first switch S1 is closed, the current (i.e., the second mirror current I2) flowing through the third mirror transistor MP3 is:

[0088] I2=I / n2=VBG / (R1*n2)

[0089] Wherein, n2 is the mirror ratio between the first mirror transistor MP1 and the third mirror transistor MP3.

[0090] Therefore, before the frequency of the clock signal CLK is stabilized for the first time, the first switch S1 is in a closed state, and at this time, the reference voltage Vref generated by the resistor unit 13 is:

[0091] Vref=(I1+I2)*R0=(VBG / (R1*n1)+VBG / (R1*n2))*R0

[0092] It can be seen that since the reference voltage VBG is fixed, a reference voltage Vref of fixed magnitude can be output through the above current mirror structure, so that the clock signal CLK generating circuit can quickly output a clock signal CLK with a stable frequency, and spread the clock signal CLK after stabilization.

[0093] In some embodiments of the present application, see Fig.10 , Fig.10 Another schematic diagram of the reference voltage module 10 in the embodiment of the present application is shown, wherein the second current mirror unit 12 includes a second operational amplifier OP2, a second transistor M2, a second resistor R2, a fourth mirror transistor MP4, a fifth mirror transistor MP5 and a second switch S2; the first end of the fourth mirror transistor MP4 is connected to the power supply terminal VDD, and the control end of the fourth mirror transistor MP4 is connected to the second end of the fourth mirror transistor MP4; the first end of the fifth mirror transistor MP5 is connected to the power supply terminal VDD, and the control end of the fifth mirror transistor MP5 is connected to the control end of the fourth mirror transistor MP4; the first end of the second transistor M2 is connected to the second end of the fourth mirror transistor MP4, the second end of the second transistor M2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the ground end; the first input end of the second operational amplifier OP2 is connected to a periodically changing preset voltage signal, the second input end of the second operational amplifier OP2 is connected to the first end of the second resistor R2, and the output end of the second operational amplifier OP2 is connected to the control end of the second transistor M2; the first end of the second switch S2 is connected to the second end of the fifth mirror transistor MP5, and the first end of the second switch S2 is connected to the resistor unit 13.

[0094] It should be noted that the periodically changing preset voltage signal VTRI can be a triangular wave voltage signal, a sine / cosine AC voltage signal, a pulse voltage signal, etc., and this application does not make specific limitations. Since the operational amplifier has a virtual short and virtual open characteristic, the voltage at the first end of the second resistor R2 is equal to the preset voltage signal connected to the first input end of the second operational amplifier OP2, so the current flowing through the first mirror transistor MP1, the first transistor M1, and the first resistor R1 is:

[0095] I=VTRI / R2

[0096] At the same time, since the source voltage and gate voltage of the fourth mirror transistor MP4 and the fifth mirror transistor MP5 are equal, the fourth mirror transistor MP4 and the fifth mirror transistor MP5 form a current mirror. It can be known that the current flowing through the fifth mirror transistor MP5 (i.e., the third mirror current I3) is:

[0097] I3=I / n3=VTRI / (R1*n3)

[0098] Wherein, n3 is the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5.

[0099] Therefore, after the frequency of the clock signal CLK is stabilized for the first time, the first switch S1 is in an open state, and the second switch S2 is in a closed state. At this time, the reference voltage Vref generated by the resistor unit 13 is:

[0100] Vref=(I1+I3)*R0=(VBG / (R1*n1)+VTRI / (R1*n3))*R0

[0101] It can be seen that, since the preset voltage signal VTRI changes periodically, the third mirror current I3 with periodic changes can be output through the above current mirror structure; at the same time, when the mirror ratio between the first mirror transistor MP1 and the third mirror transistor MP3 is equal to the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5 (i.e., n2=n3), if the average voltage of the preset voltage signal VTRI is equal to the reference voltage VBG, then at this time, the average current magnitude of the third mirror current I3 is also equal to that of the second mirror current I2, so the average magnitude of the reference voltage Vref generated by the resistor unit 13 is the same. At the same time, in combination with the above embodiments, it can be seen that by closing the first switch S1 and opening the second switch S2 before the frequency of the clock signal CLK is first stabilized, a stable reference voltage Vref can be output, and by opening the first switch S1 and closing the second switch S2 after the frequency of the clock signal CLK is first stabilized, a periodically changing reference voltage Vref can be output.

[0102] Understandably, in Fig.10 A single resistor R0 is used as the resistor unit 13. In some possible embodiments, the resistor unit 13 includes a plurality of resistors connected in series and / or in parallel. Meanwhile, in some possible embodiments, the mirror ratio between the first mirror transistor MP1 and the second mirror transistor MP2 may also be equal to the mirror ratio between the fourth mirror transistor MP4 and the fifth mirror transistor MP5 (i.e., n1=n3). For example, see Fig.11 , Fig.11Another schematic diagram of the reference voltage module 10 in an embodiment of the present application is shown. The first current mirror unit 11 controls whether to output the first mirror current I1 through the first switch S1, and the second current mirror unit 12 controls whether to output the third mirror current I3 through the second switch S2. If the average voltage of the preset voltage signal VTRI is equal to the reference voltage VBG, the average current magnitude of the third mirror current I3 is also equal to the first mirror current I1. Therefore, the first current mirror unit 11 does not need to output the second mirror current I2, and the reference voltage module 10 can also output a reference voltage Vref with a fixed voltage and a periodically changing voltage and an average magnitude equal to the first preset value.

[0103] In some embodiments of the present application, for example, for an embodiment in which the reference voltage module 10 can generate a reference current through a capacitor, see Fig.12 , Fig.12 Another schematic diagram of the clock signal CLK generating circuit in an embodiment of the present application is shown, wherein the reference voltage module 10 includes a charge and discharge unit 101 and a capacitor unit 102, and the charge and discharge unit 101 can control the charging or discharging of the capacitor unit 102. Therefore, before the frequency of the clock signal CLK is stabilized for the first time, the charge and discharge unit 101 controls the capacitor unit 102 to be connected to a fixed voltage, so that the capacitor unit 102 can output a reference voltage Vref equal to a first preset value; and after the frequency of the clock signal CLK is stabilized for the first time, the charge and discharge unit 101 alternately charges and discharges the capacitor unit 102, so that the capacitor unit 102 can output a periodically changing reference voltage Vref.

[0104] As an exemplary embodiment of a reference voltage module 10, see Fig.13 , Fig.13 Another schematic diagram of the reference voltage module 10 in an embodiment of the present application is shown, wherein the charge and discharge unit 101 includes a first current source IS1, a second current source IS2, a third switch S3, a fourth switch S4 and a fifth switch S5; the input end of the first current source IS1 is connected to the power supply end VDD, the output end of the first current source IS1 is connected to the first end of the third switch S3, and the second end of the third switch S3 is connected to the capacitor unit 102; the first end of the fourth switch S4 is connected to the capacitor unit 102, the second end of the fourth switch S4 is connected to the input end of the second current source IS2, and the output end of the second current source IS2 is connected to the ground end; the first end of the fifth switch S5 is connected to the first preset voltage V1, and the second end of the fifth switch S5 is connected to the capacitor unit 102.

[0105] It should be noted that, before the frequency of the clock signal CLK is stabilized for the first time, the third switch S3 and the fourth switch S4 are in an open state, and the fifth switch S5 is in a closed state, so the capacitor C0 is charged to the first preset voltage V1 so as to maintain the reference voltage Vref with a fixed output voltage; and after the frequency of the clock signal CLK is stabilized for the first time, the fifth switch S5 is in an open state, and the third switch S3 and the fourth switch S4 are alternately switched to an open state and a closed state, for example, when the third switch S3 is closed, the fourth switch S4 is in an open state, the first current source IS1 charges the capacitor C0 so that the reference voltage Vref increases, when the reference voltage Vref increases to a certain value, the third switch S3 is opened, and the fourth switch S4 is closed, so the second current source IS2 discharges the capacitor C0 so that the reference voltage Vref decreases, when the reference voltage Vref decreases to a certain value, the third switch S3 is closed again, and the fourth switch S4 is opened again, and the above process is repeated, and finally a reference voltage Vref that changes periodically is generated.

[0106] It can be understood that the above embodiment uses a single capacitor C0 as the capacitor unit 102. In some possible embodiments, the capacitor unit 102 includes a plurality of capacitors connected in series and / or in parallel.

[0107] In some embodiments of the present application, see Fig.14 , Fig.14 Another schematic diagram of the reference voltage module 10 in an embodiment of the present application is shown, wherein the reference voltage module 10 also includes a first comparator COMP1, a second comparator COMP2 and an RS trigger; the first input terminal of the first comparator COMP1 is connected to the capacitor unit 102, the second input terminal of the first comparator COMP1 is connected to the second preset voltage V2, and the output terminal of the first comparator COMP1 is connected to the first input terminal of the RS trigger; the second input terminal of the second comparator COMP2 is connected to the capacitor unit 102, the first input terminal of the second comparator COMP2 is connected to the third preset voltage V3, and the output terminal of the second comparator COMP2 is connected to the second input terminal of the RS trigger; the output terminal of the RS trigger is connected to the control terminal of the third switch S3, the output terminal of the RS trigger is connected to the control terminal of the fourth switch S4, and the average value of the second preset voltage V2 and the third preset voltage V3 is equal to the first preset voltage V1.

[0108] It should be noted that, since the first input terminal of the first comparator COMP1 is connected to the capacitor unit 102, and the second input terminal of the first comparator COMP1 is connected to the second preset voltage V2, when the reference voltage Vref output by the capacitor unit 102 is greater than the second preset voltage V2, the first comparator COMP1 will output one of the high-level signal and the low-level signal, otherwise, the first comparator COMP1 outputs the other of the high-level signal and the low-level signal; at the same time, since the second input terminal of the first comparator COMP1 is connected to the capacitor unit 102, and the first input terminal of the first comparator COMP1 is connected to the third preset voltage V3, when the reference voltage Vref output by the capacitor unit 102 is greater than the third preset voltage V3, the second comparator COMP2 will output one of the high-level signal and the low-level signal, otherwise, the first comparator COMP1 outputs the other of the high-level signal and the low-level signal.

[0109] Therefore, the RS trigger can control the third switch S3 and the fourth switch S4 according to the signal CLKc of the first comparator COMP1 and the second comparator COMP2, so as to alternately charge and discharge the capacitor unit 102 and generate a periodically changing reference voltage Vref. For example, when the reference voltage Vref is greater than the second preset voltage V2, the first comparator COMP1 will output a high level signal, and the second comparator COMP2 will output a low level signal, so the RS trigger can control the third switch S3 to be opened and the fourth switch S4 to be closed, so as to stop charging the capacitor unit 102 and discharge the capacitor unit 102 through the second current source IS2, so that the reference voltage Vref decreases until it is less than the third preset voltage V3; and when the reference voltage Vref is less than the third preset voltage V3, the first comparator COMP1 will output a low level signal, and the second comparator COMP2 will output a high level signal, so the RS trigger can control the third switch S3 to be closed and the fourth switch S4 to be opened, so as to stop discharging the capacitor unit 102 and charge the capacitor unit 102 through the first current source IS1, so that the reference voltage Vref increases until it is greater than the second preset voltage V2. Since the above process is repeatedly performed, the purpose of alternately charging and discharging the capacitor unit 102 and generating a periodically changing reference voltage Vref can be finally achieved.

[0110] In some embodiments of the present application, see Fig.15 , Fig.15A schematic diagram of a voltage feedback module 30 in an embodiment of the present application is shown, wherein the voltage feedback module 30 includes a third current source IS3, a first capacitor C1, a second capacitor C2, a sixth switch S6, a seventh switch S7 and a non-overlapping clock unit 31; an input end of the third current source IS3 is connected to the power supply end VDD, an output end of the third current source IS3 is connected to the first end of the first capacitor C1, and a second end of the first capacitor C1 is connected to the ground end; a first end of the sixth switch S6 is connected to the first end of the first capacitor C1, a second end of the sixth switch S6 is connected to the first end of the second capacitor C2, and a second end of the second capacitor C2 is connected to the ground end; a first end of the seventh switch S7 is connected to the first end of the second capacitor C2, and a second end of the seventh switch S7 is connected to the second end of the second capacitor C2; the non-overlapping clock unit 31 is used to output a first clock signal CLK1 and a second clock signal CLK2 according to a clock signal CLK, the first clock signal CLK1 and the second clock signal CLK2 do not overlap each other, and a control end of the sixth switch S6 is connected to the first clock signal CLK1, and a control end of the seventh switch S7 is connected to the second clock signal CLK2.

[0111] It should be noted that the non-overlapping first clock signal CLK1 and second clock signal CLK2 can make the sixth switch S6 and the seventh switch S7 not closed or opened at the same time. For example, when the sixth switch S6 is closed and the seventh switch S7 is opened, the third current source IS3 charges the second capacitor C2; when the sixth switch S6 is opened and the seventh switch S7 is closed, the second capacitor C2 discharges and flows into the ground terminal. According to the calculation formula of the equivalent impedance of the switch capacitor, it can be known that the equivalent impedance R of the second capacitor C2 is:

[0112] R=1 / fC

[0113] Wherein, f is the frequency of the first clock signal CLK1 and the second clock signal CLK2, and C is the capacitance of the second capacitor C2.

[0114] Therefore, the feedback voltage VFB generated by the voltage feedback module 30 is:

[0115] VFB=I0*R=I0 / fC

[0116] Wherein, I0 is the current output by the third current source IS3.

[0117] Taking the error amplification module 40 as an operational amplifier as an example, due to the virtual short and virtual break characteristics of the operational amplifier, during the operation of the clock signal CLK generating circuit, VFB=VREF, and the frequency of the clock signal CLK can be calculated according to the following formula:

[0118] f=I0 / (VREF*C)

[0119] It can be seen from the above formula that the voltage feedback module 30 of the present application can output a feedback voltage VFB according to the clock signal CLK, and make the magnitude of the feedback voltage VFB negatively correlated with the frequency of the clock signal CLK, and finally the reference voltage Vref can be used to control the frequency of the clock signal CLK.

[0120] It is worth noting that the above contents about the clock signal CLK generating circuit are intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can make equivalent modified designs or further designs under the guidance of the present application. For example, refer to Fig.16 , Fig.16 Another schematic diagram of the clock signal CLK generating circuit in the embodiment of the present application is shown, wherein the clock signal CLK generating circuit may further include a frequency divider 50, and the clock signal CLK output by the frequency divider 50 enables the voltage feedback module 30 to output a feedback voltage VFB.

[0121] The embodiment of the present application also provides a chip, which includes the above-mentioned clock signal CLK generating circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip of the present application has the clock signal CLK generating circuit described in the above embodiment, it has all the beneficial effects of the clock signal CLK generating circuit in the above embodiment, which will not be repeated here.

[0122] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0123] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A clock signal generating circuit, characterized in that: include: A reference voltage module, wherein the reference voltage module is used to output a reference voltage; A voltage-controlled oscillation module, the voltage-controlled oscillation module is used to oscillate under the control of a control voltage and output a clock signal; A voltage feedback module, the voltage feedback module is used to output a feedback voltage according to the clock signal, and the magnitude of the feedback voltage is negatively correlated with the frequency of the clock signal; an error amplification module, the error amplification module being used to output the control voltage according to the reference voltage and the feedback voltage; The reference voltage varies periodically at least in a partial period of time during the operation of the clock signal generating circuit.

2. The clock signal generating circuit according to claim 1, wherein: The reference voltage module includes a first current mirror unit, a second current mirror unit and a resistance unit; The first current mirror unit is used to output a mirror current of fixed magnitude, and the second current mirror unit is used to output a mirror current of periodically changing magnitude; The resistance unit is used to generate the reference voltage according to the mirror current output by the first current mirror unit and / or the second current mirror unit.

3. The clock signal generating circuit according to claim 2, wherein: The first current mirror unit is used to output a second mirror current, and the second current mirror unit is used to output a third mirror current, wherein the third mirror current changes periodically and has an average magnitude equal to the second mirror current; or The first current mirror unit is used to output a first mirror current and a second mirror current, and the second current mirror unit is used to output a third mirror current. The third mirror current changes periodically and has an average magnitude equal to the second mirror current.

4. The clock signal generating circuit according to claim 2, wherein: The first current mirror unit includes a first operational amplifier, a first transistor, a first resistor, a first mirror transistor and a second mirror transistor; A first end of the first mirror transistor is connected to a power supply end, and a control end of the first mirror transistor is connected to a second end of the first mirror transistor; A first end of the second mirror transistor is connected to the power supply end, a control end of the second mirror transistor is connected to the control end of the first mirror transistor, and a second end of the second mirror transistor is connected to the resistance unit to input a mirror current to the resistance unit; The first end of the first transistor is connected to the second end of the first mirror transistor, the second end of the first transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the ground end; A first input terminal of the first operational amplifier is connected to a reference voltage, a second input terminal of the first operational amplifier is connected to a first terminal of the first resistor, and an output terminal of the first operational amplifier is connected to a control terminal of the first transistor.

5. The clock signal generating circuit according to claim 4, characterized in that: The first current mirror unit further includes a third mirror transistor and a first switch; A first terminal of the third mirror transistor is connected to the power supply terminal, and a control terminal of the third mirror transistor is connected to a control terminal of the second mirror transistor; A first end of the first switch is connected to a second end of the third mirror transistor, and a second end of the first switch is connected to the resistance unit.

6. The clock signal generating circuit according to claim 2, wherein: The second current mirror unit includes a second operational amplifier, a second transistor, a second resistor, a fourth mirror transistor, a fifth mirror transistor and a second switch; The first end of the fourth mirror transistor is connected to the power supply end, and the control end of the fourth mirror transistor is connected to the second end of the fourth mirror transistor; A first terminal of the fifth mirror transistor is connected to the power supply terminal, and a control terminal of the fifth mirror transistor is connected to a control terminal of the fourth mirror transistor; The first end of the second transistor is connected to the second end of the fourth mirror transistor, the second end of the second transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the ground end; The first input terminal of the second operational amplifier is connected to a preset voltage signal that changes periodically, the second input terminal of the second operational amplifier is connected to the first terminal of the second resistor, and the output terminal of the second operational amplifier is connected to the control terminal of the second transistor; A first end of the second switch is connected to the second end of the fifth mirror transistor, and a first end of the second switch is connected to the resistance unit.

7. The clock signal generating circuit according to claim 1, wherein: The reference voltage module includes a charging and discharging unit and a capacitor unit; Before the frequency of the clock signal is stabilized for the first time, the charge-discharge unit controls the capacitor unit to be connected to a fixed voltage so that the capacitor unit outputs the reference voltage having a magnitude equal to a first preset value; After the frequency of the clock signal is stabilized for the first time, the charge-discharge unit charges and discharges the capacitor unit alternately, so that the capacitor unit outputs the reference voltage that changes periodically.

8. The clock signal generating circuit according to claim 7, wherein: The charging and discharging unit includes a first current source, a second current source, a third switch, a fourth switch and a fifth switch; The input end of the first current source is connected to the power supply end, the output end of the first current source is connected to the first end of the third switch, and the second end of the third switch is connected to the capacitor unit; A first end of the fourth switch is connected to the capacitor unit, a second end of the fourth switch is connected to an input end of the second current source, and an output end of the second current source is connected to a ground end; A first end of the fifth switch is connected to a first preset voltage, and a second end of the fifth switch is connected to the capacitor unit.

9. The clock signal generating circuit according to claim 8, characterized in that: The reference voltage module also includes a first comparator, a second comparator and an RS trigger; The first input terminal of the first comparator is connected to the capacitor unit, the second input terminal of the first comparator is connected to a second preset voltage, and the output terminal of the first comparator is connected to the first input terminal of the RS trigger; The second input terminal of the second comparator is connected to the capacitor unit, the first input terminal of the second comparator is connected to a third preset voltage, and the output terminal of the second comparator is connected to the second input terminal of the RS trigger; The output end of the RS trigger is connected to the control end of the third switch, the output end of the RS trigger is connected to the control end of the fourth switch, and an average value of the second preset voltage and the third preset voltage is equal to the first preset voltage.

10. The clock signal generating circuit according to any one of claims 1 to 9, characterized in that: Before the frequency of the clock signal is stabilized for the first time, the magnitude of the reference voltage is equal to a first preset value; After the frequency of the clock signal is stabilized for the first time, the reference voltage changes periodically and the average magnitude thereof is equal to the first preset value.

11. The clock signal generating circuit according to claim 1, wherein: The voltage feedback module includes a third current source, a first capacitor, a second capacitor, a sixth switch, a seventh switch and a non-overlapping clock unit; The input end of the third current source is connected to the power supply end, the output end of the third current source is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the ground end; A first end of the sixth switch is connected to a first end of the first capacitor, a second end of the sixth switch is connected to a first end of the second capacitor, and a second end of the second capacitor is connected to the ground end; A first end of the seventh switch is connected to a first end of the second capacitor, and a second end of the seventh switch is connected to a second end of the second capacitor; The non-overlapping clock unit is used to output a first clock signal and a second clock signal according to the clock signal, the first clock signal and the second clock signal do not overlap each other, and the control end of the sixth switch is connected to the first clock signal, and the control end of the seventh switch is connected to the second clock signal.

12. A chip, characterized in that: The method comprises the clock signal generating circuit as claimed in any one of claims 1 to 11.

13. An electronic device, characterized in that: Comprising the chip as claimed in claim 12.

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