Multi-channel optical fiber rate dynamic configuration module and method

Abstract

A traditional optical fiber rate configuration module fixedly configures an optical fiber transmission rate according to a specific scene, the rate cannot be changed after being configured, and meanwhile, when different multichannel data processing systems use the optical fiber rate configuration module, the optical fiber rate configuration module needs to be redesigned according to the system rate, so that the development and verification period of the system is long. Therefore, the invention provides a multi-channel optical fiber rate dynamic configuration module and a configuration method, an optical fiber rate dynamic reconfiguration scheme is designed, and optical fiber self-adaptive rate configuration of all quad input and output of the FPGA can be carried out according to the characteristics of an external reference clock, a frequency dividing ratio, a frequency multiplication coefficient and the like of the FPGA. The method has the characteristics of simple parameter configuration, universality in various scenes and convenience in application.

Description

Technical Field

[0001] The present invention belongs to the technical field of optical communication, and in particular relates to a multi-channel optical fiber rate dynamic configuration module and method. Background Art

[0002] In a multi-channel data processing system, parallel computing and processing are generally implemented using a field programmable gate array (FPGA). Data transmission in each subsystem is generally carried out using multi-mode optical fiber. The FPGA provides multiple sets of GT (gigabit transceiver) hard cores for optical fiber data transmission and reception. Due to the differences in data throughput rates, processing platform capabilities, etc. of different multi-channel data processing subsystems, the transmission rates of multi-mode optical fibers are also different. Therefore, different optical fiber transmission rates need to be configured according to the data scenarios in which each subsystem works.

[0003] The traditional fiber rate configuration module configures the fiber transmission rate according to a specific scenario, and the rate cannot be changed after configuration. When the input and output of the multi-channel data processing subsystem are connected to other subsystems with different rates, data cannot be transmitted. At the same time, when different multi-channel data processing systems use the fiber rate configuration module, the fiber rate configuration module needs to be redesigned according to the system rate, resulting in a long system development and verification cycle. Summary of the invention

[0004] The present invention proposes a fiber rate dynamic configuration module and configuration method in a multi-channel data processing system. By designing a fiber rate dynamic reconfiguration scheme, the fiber rate adaptive configuration of all quads of FPGA input and output can be performed according to the characteristics of the FPGA's external reference clock, division ratio, and multiplication factor. It has the characteristics of simple parameter configuration, universality in various scenarios, and convenient application.

[0005] A multi-channel optical fiber rate dynamic configuration module of the present invention comprises: a parameter analysis module, a reference clock management module, a DRP parameter reconfiguration module, a DRP parameter verification module and an adaptive reset state machine.

[0006] The parameter parsing module parses and obtains crystal oscillator selection parameters, PLL selection parameters, frequency division ratio and frequency multiplication coefficient parameters according to the GT line rate mode configured as needed.

[0007] The reference clock management module is used to obtain the reference clock selection signal of each quad of the FPGA; the crystal oscillator selection parameters analyzed by the reference parameter analysis module are combined with the crystal oscillator position and the physical position parameters of the quad to obtain the reference clock selection signal of each quad.

[0008] The DRP parameter reconfiguration module, DRP is a dynamic reconfiguration interface commonly used in FPGA GT transceivers. This module uses the DRP interface to reconfigure the division ratio and multiplication factor, and reconfigures the TX and RX channels of the physical layer to the corresponding rate.

[0009] The DRP parameter verification module is used to verify whether the DRP parameter configuration is correct, and reads the frequency division ratio and the frequency multiplication coefficient through the DRP configuration read address and compares them with the theoretical values.

[0010] The adaptive reset state machine is used to reset the TX and RX channels of the quad physical layer, and adaptively reset the quad phase-locked loop clock or the channel phase-locked loop clock according to the PLL selection parameters, and power off the unused PLL to save power consumption.

[0011] A multi-channel optical fiber rate dynamic configuration method of the present invention comprises the following processing steps:

[0012] (a) FPGAquad grouping: The high-speed GT channels of the FPGA are grouped into quads. Each FPGA quad contains four GT channels, and three adjacent FPGA quads share a set of reference clocks.

[0013] (b) Obtaining rate configuration parameters: The parameter parsing module searches the parameter table according to the GT line rate mode. Each quad of the FPGA uses two crystal oscillators to provide the reference clock. The crystal oscillator selection parameters, PLL selection parameters, division ratio and multiplication factor parameters are pre-configured at different rates. The parameter values ​​are obtained by looking up the table. The reference clock management module finally determines the reference clock selection signal of the quad based on the north-south position of the quad in the group and the crystal oscillator selection parameters.

[0014] (c) DRP interface parameter reconfiguration: The FPGA's GT interface supports DRP reconfiguration. The DRP parameter reconfiguration module configures the write address and enable signal of the DRP interface, and writes the division ratio and multiplication coefficient parameters analyzed by the parameter analysis module into the data port. After configuration, the DRP parameter verification module is used to verify whether the configuration is successful.

[0015] (d) TX and RX CHANNEL reset: The adaptive reset state machine resets the GT channel transmit and receive channels of the quad.

[0016] (e) CPLL or QPLL reset: The adaptive reset state machine performs a corresponding phase-locked loop reset on the phase-locked loop used by the quad according to the PLL selection parameters.

[0017] (f) Waiting for CPLL to lock; after the adaptive reset state machine resets the CPLL or QPLL phase-locked loop, it monitors the phase-locked loop lock signal, and after the phase-locked loop is locked, another set of phase-locked loop power-down signals are pulled to save power consumption.

[0018] (g) The adaptive reset state machine outputs a rate configuration success signal to complete the dynamic configuration of the optical fiber rate.

[0019] The beneficial effects of the present invention are

[0020] 1. A parameterized general design method is adopted to meet the diverse and commonly used application requirements. After configuring the fiber rate mode, parameters such as internal reference clock selection, division ratio and multiplication factor can be adaptively generated to complete the dynamic configuration of the fiber rate.

[0021] 2. The hardware resources are reused to fully utilize the hardware capabilities in different working scenarios. At the same time, the internal phase-locked loop and other modules are powered on in partitions, which can effectively reduce the dynamic power consumption of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Block diagram of the fiber rate dynamic configuration module.

[0023] Figure 2 Workflow diagram of the method for dynamically configuring the optical fiber rate. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] like Figure 1 As shown, a fiber rate dynamic configuration module in a multi-channel data processing system of the present invention includes: a parameter parsing module 1, a reference clock management module 2, a DRP parameter reconfiguration module 3, a DRP parameter verification module 4 and an adaptive reset state machine 5.

[0026] The parameter parsing module 1 parses and obtains the crystal oscillator selection parameters, the PLL selection parameters, the frequency division ratio and the frequency multiplication coefficient parameters according to the GT line rate mode to be configured.

[0027] The reference clock management module 2 is used to obtain the reference clock selection signal of each quad of the FPGA. The reference clock selection signal of each quad is obtained by combining the crystal oscillator selection parameters analyzed by the reference analysis module 1 with the crystal oscillator position and the physical position parameters of the quad.

[0028] DRP parameter reconfiguration module 3, DRP is a dynamic reconfiguration interface commonly used in FPGA's GT transceiver. This module uses the DRP interface to reconfigure the division ratio and multiplication factor, and reconfigure the TX and RX channels of the physical layer to the corresponding rate.

[0029] The DRP parameter verification module 4 is used to verify whether the DRP parameter configuration is correct, and reads the frequency division ratio and the frequency multiplication coefficient through the DRP configuration read address and compares them with the theoretical values.

[0030] The adaptive reset state machine 5 is used to reset the TX and RX channels of the quad physical layer, and adaptively reset the quad phase-locked loop clock or the channel phase-locked loop clock according to the PLL selection parameters, and power off the unused PLL to save power consumption.

[0031] The configuration method of the present invention comprises the following steps:

[0032] (a) FPGA quad grouping: The high-speed GT channels of the FPGA are grouped into quads. A typical FPGA has four GT channels per quad. Three adjacent quads of the FPGA can share a set of reference clocks.

[0033] (b) Rate configuration parameter acquisition: Parameter parsing module 1 searches the parameter table according to the GT line rate mode. In a typical FPGA, each quad can use two crystal oscillators to provide reference clocks. Crystal oscillator selection parameters, PLL selection parameters, frequency division ratio and frequency multiplication coefficient parameters are pre-configured at different rates. The parameter values ​​are obtained by searching the table. Reference clock management module 2 finally determines the reference clock selection signal of the quad according to the north-south position of the quad in the group and the crystal oscillator selection parameters.

[0034] (c) DRP interface parameter reconfiguration: The GT interface of a typical FPGA supports DRP reconfiguration. The DRP parameter reconfiguration module 3 configures the write address and enable signal of the DRP interface, and writes the frequency division ratio and multiplication coefficient parameters analyzed by the parameter analysis module 1 into the data port. After configuration, the DRP parameter verification module 4 verifies whether the configuration is successful;

[0035] (d) TX and RX CHANNEL reset: The adaptive reset state machine 5 resets the GT channel transmit and receive channels of the quad;

[0036] (e) CPLL or QPLL reset: The adaptive reset state machine 5 performs a corresponding phase-locked loop reset on the quad according to the PLL selection parameters.

[0037] (f) Waiting for CPLL to lock; after the adaptive reset state machine 5 resets the CPLL or QPLL phase-locked loop, it monitors the phase-locked loop lock signal, and after the phase-locked loop is locked, another set of phase-locked loop power-down signals are pulled to save power consumption;

[0038] (g) The adaptive reset state machine 5 outputs a rate configuration success signal, indicating that the module has completed the dynamic configuration of the optical fiber rate.

[0039] Figure 2 The workflow diagram of the beam weighting method is described, taking the configuration of 10 Gbps rate as an example.

[0040] Adaptive parameter analysis module 1 calculates the internal selection based on the 10Gbps data rate table as 125M crystal oscillator, QPLL phase-locked loop, division ratio of 80, and multiplication factor of 1. Reference clock management 2 calculates the reference clock selection signal of each quad according to the quad grouping situation. The reference clock selection signal corresponds to 1-6, representing the north clock 1, north clock 2, local clock 1, local clock 2, south clock 1 and south clock 2 of the slave quad respectively;

[0041] according to Figure 2 The DRP parameter reconfiguration module 3 writes the division ratio and multiplication factor information to the 0x36 address. After configuration, the DRP parameter verification module 4 reads out the 0x36 address information to verify whether it is the same as the value written by the DRP parameter reconfiguration module 3, and determines whether the reconfiguration is successful. The adaptive reset state machine 5 completes the TX and RX CHANNEL reset of the physical layer, and completes the QPLL reset at the same time, and powers off the CPLL to save power. When the state machine detects that the QPLL is locked, it outputs a configuration success signal.

[0042] The present invention is not limited to the above specific implementations, and the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made to the above implementations based on the technical essence of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-channel optical fiber rate dynamic configuration module, characterized in that: include: Parameter parsing module, reference clock management module, DRP parameter reconfiguration module, DRP parameter verification module and adaptive reset state machine; The parameter parsing module parses and obtains crystal oscillator selection parameters, PLL selection parameters, frequency division ratio and frequency multiplication coefficient parameters according to the GT line rate mode configured as needed; The reference clock management module is used to obtain the reference clock selection signal of each quad of the FPGA; the crystal oscillator selection parameters analyzed by the reference parameter analysis module are combined with the crystal oscillator position and the physical position parameters of the quad to obtain the reference clock selection signal of each quad; The DRP parameter reconfiguration module, DRP is a dynamic reconfiguration interface commonly used in FPGA GT transceivers. This module uses the DRP interface to reconfigure the frequency division ratio and multiplication factor, and reconfigures the TX and RX channels of the physical layer to the corresponding rate; The DRP parameter verification module is used to verify whether the DRP parameter configuration is correct, and read the frequency division ratio and frequency multiplication coefficient through the DRP configuration read address and compare them with the theoretical value; The adaptive reset state machine is used to reset the TX and RX channels of the quad physical layer, and adaptively reset the quad phase-locked loop clock or the channel phase-locked loop clock according to the PLL selection parameters, and power off the unused PLL to save power consumption.

2. A multi-channel optical fiber rate dynamic configuration method, based on the multi-channel optical fiber rate dynamic configuration module according to claim 1, characterized in that: The following processing steps are included: (a) FPGAquad grouping: The high-speed GT channels of the FPGA are grouped into quads. Each FPGA quad contains four GT channels, and three adjacent quads of the FPGA share a set of reference clocks. (b) Rate configuration parameter acquisition: The parameter parsing module searches the parameter table according to the GT line rate mode. Each quad of the FPGA uses two crystal oscillators to provide reference clocks. Crystal oscillator selection parameters, PLL selection parameters, division ratio and multiplication coefficient parameters are pre-configured at different rates. The parameter values ​​are obtained by looking up the table. The reference clock management module finally determines the reference clock selection signal of the quad according to the north-south position of the quad in the group and the crystal oscillator selection parameters. (c) DRP interface parameter reconfiguration: The FPGA's GT interface supports DRP reconfiguration. The DRP parameter reconfiguration module configures the write address and enable signal of the DRP interface, and writes the frequency division ratio and multiplication coefficient parameters analyzed by the parameter analysis module into the data port. After configuration, the DRP parameter verification module verifies whether the configuration is successful. (d) TX and RX CHANNEL reset: The adaptive reset state machine resets the GT channel transmit and receive channels of the quad; (e) CPLL or QPLL reset: The adaptive reset state machine performs a corresponding phase-locked loop reset on the phase-locked loop used by the quad according to the PLL selection parameters; (f) Waiting for CPLL to lock; after the adaptive reset state machine resets the CPLL or QPLL phase-locked loop, it monitors the phase-locked loop lock signal, and after the phase-locked loop is locked, another set of phase-locked loop power-down signals are pulled to save power consumption; (g) The adaptive reset state machine outputs a rate configuration success signal to complete the dynamic configuration of the optical fiber rate.

Images