Anti-aging clock source multiplexing

Abstract

In certain aspects, an apparatus (110) includes a first gating circuit (420) having an input (422) and an output (426), where the input of the first gating circuit is configured to receive a first clock signal (Clk-sw). The apparatus also includes a delay circuit (430) having an input (432) and an output (434), wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus also includes a control circuit (160) configured to receive the enable signal (EN, 452), detect a logic state (458) at the output of the delay circuit, and cause (456) the first gating circuit to pass or gate the first clock signal based on the enable signal (En, 452) and the detected logic state at the output (output, 458) of the delay circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional patent application No. 17 / 805,014 filed in the U.S. Patent and Trademark Office on June 1, 2022, the contents of which are incorporated herein as if fully set forth in their entirety below and for all applicable purposes. background Technical Field

[0003] Aspects of the present disclosure relate generally to aging, and more particularly, to aging mitigation. Background Art

[0004] The system may include a clock source (e.g., a phase-locked loop) configured to generate a clock signal for timing the operation of one or more circuits (e.g., sequential logic, processors, memory, etc.) in the system. The system may also include a clock path for distributing the clock signal from the clock source to the one or more circuits. A challenge with clock distribution is that asymmetric aging in the clock path may cause duty cycle distortion in the clock signal, which may cause timing issues (e.g., timing violations) in the one or more circuits. Summary of the invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0006] A first aspect relates to an apparatus. The apparatus comprises a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus further comprises a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further comprises a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

[0007] A second aspect relates to a method for short-time pulse interference mitigation. The method includes: receiving a first clock signal; receiving a second clock signal; passing the first clock signal to a clock path during a first mode; passing the second clock signal to the clock path during a second mode; and detecting a change from the first mode to the second mode. The method also includes: in response to detecting the change from the first mode to the second mode, detecting when a high pulse of the first clock signal is equal to or greater than a pulse width; and when the high pulse of the first clock signal is equal to or greater than the pulse width, gating the first clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Examples of systems including clock sources, gating circuits, clock paths, and circuits according to certain aspects of the present disclosure are shown.

[0009] Figure 2A An example of a clock path including a clock buffer in accordance with certain aspects of the present disclosure is shown.

[0010] Figure 2B An example is shown in which an input of a clock path resides low in idle mode in accordance with certain aspects of the present disclosure.

[0011] Figure 2C is a timing diagram illustrating an example of duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure.

[0012] Figure 2D An example is shown in which an input of a clock path resides high in idle mode in accordance with certain aspects of the present disclosure.

[0013] Figure 2E is a timing diagram illustrating another example of duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure.

[0014] Figure 3 An example is shown in which the system further includes a multiplexer in accordance with certain aspects of the present disclosure.

[0015] Figure 4 An example is shown in which the system further includes a glitch mitigation circuit in accordance with certain aspects of the present disclosure.

[0016] Figure 5 An example of a timing diagram illustrating exemplary operation of a glitch mitigation circuit in accordance with certain aspects of the present disclosure is shown.

[0017] Figure 6 Another example of a glitch mitigation circuit in accordance with certain aspects of the present disclosure is shown.

[0018] Figure 7 Another example of a timing diagram illustrating exemplary operation of a glitch mitigation circuit in accordance with certain aspects of the present disclosure is shown.

[0019] Figure 8 An exemplary implementation of a delay circuit according to certain aspects of the present disclosure is shown.

[0020] Fig. 9 An exemplary implementation of a delay device in a delay circuit according to certain aspects of the present disclosure is shown.

[0021] Fig.10 Another example of a glitch mitigation circuit in accordance with certain aspects of the present disclosure is shown.

[0022] Fig.11 Still another example of a timing diagram illustrating exemplary operation of a glitch mitigation circuit in accordance with certain aspects of the present disclosure is shown.

[0023] Fig.12 is a flow chart illustrating a method for glitch mitigation in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0024] The specific embodiments described below in conjunction with the accompanying drawings are intended to be descriptions of various configurations, and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a comprehensive understanding of various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some cases, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0025] Figure 1 An example of a system 110 according to certain aspects is shown, which includes a clock source 115, a gating circuit 120, a clock path 130, and a circuit 140. The circuit 140 may include sequential logic, a processor, a memory, etc. The clock source 115 is configured to generate a functional clock signal (labeled as "Clk_fn") and output the functional clock signal at an output terminal 118. The clock source 115 can be implemented using a phase-locked loop (PLL) or another type of clock source. The functional clock signal is used to time operations of the circuit 140. The functional clock signal may also be referred to as a clock signal, an active clock signal, or another term.

[0026] The clock path 130 has an input 132 and an output 134. The output 134 is coupled to the circuit 140. The clock path 130 is configured to receive the functional clock signal at the input 132 and distribute the functional clock signal to the circuit 140. As used herein, a "clock signal" may be a periodic signal that oscillates between a high and a low. In the present disclosure, a clock signal has a duty cycle, which may be expressed as a percentage or fraction of a clock period (i.e., a clock cycle) during which the clock signal is high (i.e., a logic 1).

[0027] The gating circuit 120 (also referred to as a clock gating cell) has a signal input 122, an enable input 124, and an output 126. The signal input 122 is coupled to the output 118 of the clock source 115, and the output 126 is coupled to the input 132 of the clock path 130. The enable input 124 is configured to receive a functional clock enable signal (labeled "Clk_fn_en"), and the signal input 122 is configured to receive a functional clock signal. As used herein, an "enable input" of a gating circuit is an input that controls whether the gating circuit passes (i.e., de-gates) or gates a signal received at the signal input of the gating circuit based on an enable signal received at the "enable input".

[0028] In operation, the gating circuit 120 is configured to pass the functional clock signal to the output terminal 126 or gate (i.e., block) the functional clock signal based on the functional clock enable signal. For example, the gating circuit 120 may be configured to pass the functional clock signal to the output terminal 126 when the functional clock enable signal has a first logic state, and gate the functional clock signal when the functional clock enable signal has a second logic state. The first logic state may be high (i.e., logic 1), and the second logic state may be low (i.e., logic 0), or vice versa. However, it should be understood that the functional clock enable signal is not limited to this example.

[0029] In some aspects, the functional clock enable signal is generated by a control circuit 160 having an output 162 coupled to an enable input 124 of the gating circuit 120, wherein the control circuit 160 outputs the functional clock enable signal to the gating circuit 120 via the output 162. In these aspects, the control circuit 160 controls whether the gating circuit 120 uses the functional clock enable signal to pass the functional clock signal to the clock path 130 or to gate (i.e., block) the functional clock signal. In one example, the control circuit 160 may cause the gating circuit 120 to pass the functional clock signal (e.g., by setting the functional clock enable signal to a first logic state) when the circuit 140 is in an active mode (also referred to as a functional mode), and cause the gating circuit 120 to gate the functional clock signal (i.e., by setting the functional clock enable signal to a second logic state) when the circuit 140 is in an idle mode (i.e., inactive) to save power. Clock gating is a known technique for reducing dynamic power consumption when a circuit is inactive.

[0030] Despite Figure 1 In FIG. 1 , one gating circuit 120 is shown between the clock source 115 and the clock path 130, but it should be understood that the system 110 may include two or more clock gating circuits (e.g., at different locations along the clock path 130). It should also be understood that the clock path 130 may include multiple branches (not shown) forming a clock tree to distribute the functional clock signal to the clock source 115 and the clock path 130. Figure 1 One or more other circuits (not shown) other than the circuit 140 shown. Figure 1 1 , it should be understood that in some implementations, the system 110 may include multiple clock sources configured to generate multiple clock signals. In these implementations, the system 110 may also include a multiplexer (not shown) configured to select one of the multiple clock signals and input the selected clock signal of the multiple clock signals to the signal input terminal 122 of the gating circuit 120.

[0031] Aging effects such as bias temperature instability (BTI) may degrade the performance of clock path 130 over time. For example, BTI stress in clock path 130 during idle mode may cause a duty cycle shift in clock path 130 over time, which may cause timing issues (e.g., timing violations) to occur in circuit 140.

[0032] Now refer to FIG. 2A to FIG. 2E An example of duty cycle shift due to aging is discussed. Figure 2AAn example is shown in which the clock path 130 includes clock buffers 220-1 through 220-4 coupled in series between the input terminal 132 and the output terminal 134. Although for simplicity, in Figure 2A Four clock buffers 220-1 to 220-4 are shown in FIG. 1 , but it should be understood that the clock path 130 may include a large number of clock buffers. Figure 2A In the example shown, each of the clock buffers 220-1 to 220-4 is implemented using a corresponding complementary inverter including a corresponding transistor (e.g., an n-type field effect transistor) of the transistors 225-1 to 225-4 and a corresponding transistor (e.g., a p-type field effect transistor) of the transistors 230-1 to 230-4. However, it should be understood that each of the clock buffers 220-1 to 220-4 may be implemented using another type of circuit or logic gate.

[0033] When the circuit 140 is in an active mode (i.e., a functional mode), the gating circuit 120 passes a functional clock signal received at the signal input 122 of the gating circuit 120 to the input 132 of the clock path 130, and the functional clock signal is propagated to the circuit 140 through the clock buffers 220-1 to 220-4. When the circuit 140 is in an idle mode, the gating circuit 120 gates the functional clock signal and keeps (i.e., maintains) the input 132 of the clock path 130 high or low.

[0034] Figure 2B An example is shown in which the gating circuit 120 holds the input 132 of the clock path 130 low (ie, logic 0) in idle mode. Figure 2B Also shown are the logic states at the input and output of each of the clock buffers 220-1 to 220-4. In this example, the output 134 of the clock path 130 is low (i.e., logic 0) in idle mode. In this example, transistors 230-1, 225-2, 230-3, and 225-4 are turned on in idle mode, and transistors 225-1, 230-2, 225-3, and 230-4 are turned off in idle mode. Figure 2B, transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in idle mode are shown in bold. The transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in idle mode are stressed in idle mode, while the transistors 225-1, 230-2, 225-3, and 230-4 that are turned off in idle mode are not stressed in idle mode. This can lead to asymmetric aging, where the transistors 230-1, 225-2, 230-3, and 225-4 that are stressed in idle mode age faster than the transistors 225-1, 230-2, 225-3, and 230-4 that are not stressed in idle mode.

[0035] In this example, the asymmetric aging shifts the threshold voltages of transistors 230-1, 225-2, 230-3, and 225-4 that are stressed in the idle mode, thereby causing an increase in the falling edge delay at the output 134 of the clock path 130 relative to the rising edge delay at the output 134 of the clock path 130. The increase in the falling edge delay relative to the rising edge delay causes a shift in the duty cycle in the clock path 130. Figure 2C An example of duty cycle shifting is illustrated in the timing diagram shown. Figure 2C In the example shown, the functional clock signal has a 50% duty cycle at the input 132 of the clock path 130 in the active mode. Figure 2C Also shown is the functional clock signal 260 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 delays the rising edge of the functional clock signal 250 by a delay T r , and delays the falling edge of the functional clock signal 250 by a delay T f .like Figure 2C As shown, due to asymmetric aging, the delay T of the falling edge f Longer than the rising edge delay T r In this example, the longer delay of the falling edge causes the duty cycle of the functional clock signal 260 at the output 134 of the clock path 130 to increase (ie, result in a duty cycle greater than 50%).

[0036] exist Figure 2B and Figure 2C In the example shown, the gating circuit 120 holds the input 132 of the clock path 130 low in the idle mode. Asymmetric aging also occurs when the gating circuit 120 holds the input 132 of the clock path 130 high in the idle mode. In this regard, Figure 2D An example is shown in which the gating circuit 120 holds the input 132 of the clock path 130 high (ie, logic 1) in the idle mode. Figure 2DAlso shown are the logic states at the input and output of each of the clock buffers 220-1 to 220-4. In this example, the output 134 of the clock path 130 is high (i.e., logic 1) in the idle mode. In this example, transistors 225-1, 230-2, 225-3, and 230-4 are turned on in the idle mode, and transistors 230-1, 225-2, 230-3, and 225-4 are turned off in the idle mode. Figure 2D , transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in the idle mode are shown in bold. The transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in the idle mode are stressed in the idle mode, while the transistors 230-1, 225-2, 230-3, and 225-4 that are turned off in the idle mode are not stressed in the idle mode, which results in asymmetric aging, wherein the transistors 225-1, 230-2, 230-3, and 230-4 that are stressed in the idle mode age faster than the transistors 230-1, 225-2, 230-3, and 225-4.

[0037] In this example, the asymmetric aging shifts the threshold voltages of transistors 225-1, 230-2, 225-3, and 230-4 that are stressed in the idle mode, thereby causing an increase in the rising edge delay at the output 134 of the clock path 130 relative to the falling edge delay at the output 134 of the clock path 130. The increase in the rising edge delay relative to the falling edge delay causes a duty cycle shift in the clock path 130. Figure 2E An example of duty cycle shifting is illustrated in the timing diagram shown. Figure 2E In the example shown, a functional clock signal 250 having a 50% duty cycle is input to the clock path 130 in the active mode. Figure 2E Also shown is the functional clock signal 270 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 delays the rising edge of the functional clock signal 250 at the output 134 of the clock path 130 by a delay T r And the falling edge of the functional clock signal 250 is delayed by a delay T f .like Figure 2E As shown, due to asymmetric aging, the delay T of the rising edge r Longer than the falling edge delay T f In this example, the longer delay of the rising edge causes the duty cycle of the functional clock signal 270 at the output 134 of the clock path 130 to be reduced (ie, to a duty cycle of less than 50%).

[0038] Thus, asymmetric aging in idle mode may cause duty cycle shift (i.e., duty cycle distortion) to occur over time at the output 134 of the clock path 130. The duty cycle shift may increase or decrease the duty cycle of the functional clock signal, for example, depending on whether the gating circuit 120 holds the input 132 of the clock path 130 low or high in idle mode and the number of clock buffers 220-1 to 220-4 in the clock path 130. The duty cycle shift may cause timing issues in the circuit 140. For examples where the circuit 140 includes sequential logic (e.g., flip-flops), the duty cycle shift may cause setup and / or hold time violations.

[0039] To address duty cycle distortion due to asymmetric aging, a slow clock signal may be injected into the clock path 130 in idle mode to balance the aging of the devices (e.g., transistors 225-1 to 225-4 and 230-1 to 230-4) in the clock path 130 in idle mode. To reduce dynamic power consumption at idle, the slow clock signal may have a frequency much lower (e.g., two or more orders of magnitude lower) than the frequency of the functional clock signal. The slow clock signal may also be referred to as a low-speed clock signal or another term. As used herein, the term "slow" indicates that the slow clock signal has a lower frequency than the functional clock signal.

[0040] In this method, the much lower frequency of the slow clock signal significantly reduces dynamic power consumption in idle mode compared to active mode, while balancing the aging of devices (e.g., transistors 225-1 to 225-4 and 230-1 to 230-4) in the clock path 130 in idle mode to mitigate duty cycle distortion. The slow clock signal balances the aging of devices in the clock path 130 by switching (i.e., toggling) the input 132 of the clock path 130 high and low at a low frequency, rather than having the input 132 of the clock path 130 reside in the same constant logic state in idle mode.

[0041] Figure 3 An exemplary implementation of the above method according to certain aspects is shown. In this example, the system 110 includes a multiplexer 310 coupled between the gating circuit 120 and the clock path 130. As discussed further below, the multiplexer 310 is used to switch the clock path 130 between a functional clock signal (labeled “Clk_fn”) and a slow clock signal (labeled “Clk_sw”). The functional clock signal may come from Figure 1 A clock source 115 is shown.

[0042] Multiplexer 310 has a first input 312, a second input 314, an output 136, and a select input 318. First input 312 is coupled to output 126 of gate circuit 120, second input 314 is configured to receive a slow clock signal, and output 316 is coupled to input 132 of clock path 130. Select input 318 is coupled to control circuit 160 and is configured to receive a select signal (labeled “Sel”). The select signal is provided to multiplexer 310 by control circuit 160 via output 322 coupled to select input 318 of multiplexer 310. As used herein, a “select input” of a multiplexer is an input that controls which of a plurality of inputs of the multiplexer is selected based on a select signal received at the “select input”.

[0043] The multiplexer 310 is configured to select the first input terminal 312 or the second input terminal 314 based on the selection signal, and couple the selected one of the first input terminal 312 and the second input terminal 314 to the output terminal 316. For example, the multiplexer 310 may select the first input terminal 312 when the selection signal has a first logic value, and select the second input terminal 314 when the selection signal has a second logic value. The first logic value may be 1, and the second logic value may be 0, or vice versa.

[0044] In some aspects, control circuit 160 causes multiplexer 310 to select first input 312 in active mode (e.g., by setting the logic value of a select signal to a first logic value). In active mode, multiplexer 310 passes the functional clock signal from gating circuit 120 to clock path 130. The functional clock signal then propagates through clock path 130 to circuit 140.

[0045] The control circuit 160 causes the multiplexer 310 to select the second input 314 in the idle mode (e.g., by setting the logic value of the select signal to a second logic value). In the idle mode, the multiplexer 310 passes the slow clock signal to the clock path 130. As discussed above, the slow clock signal balances aging in the clock path 130 in the idle mode to mitigate duty cycle distortion.

[0046] When the system 110 transitions from the idle mode to the active mode, the multiplexer 310 switches from the second input 314 to the first input 312. The problem is that switching the multiplexer 310 from the second input 314 to the first input 312 may generate a narrow high pulse (referred to as a glitch) at the output 316. As used herein, a "glitch" is a high pulse with a narrow width (e.g., less than one cycle of a functional clock signal) that may cause timing problems in the circuit 140. For example, when the multiplexer 310 switches from the second input 314 to the first input 312 shortly after the slow clock signal transitions from low to high, the multiplexer 310 may generate a glitch. The glitch may propagate through the clock path 130 to the circuit 140 and cause timing problems (e.g., setup time and / or hold time violations) in the circuit 140.

[0047] One method of preventing glitch generation is to implement the multiplexer 310 using a glitch-free multiplexer. The glitch-free multiplexer includes circuitry (e.g., pipeline registers) for preventing glitch generation when the multiplexer switches between inputs. However, the glitch-free multiplexer may have a delay of at least a plurality of clock cycles (i.e., cycles) of a slow clock signal when switching between inputs. Since the slow clock signal has a low frequency (and therefore a long clock cycle), this causes the glitch-free multiplexer to have a high delay. The high delay of the glitch-free multiplexer translates into a high delay when transitioning the system 110 from an idle mode to an active mode. This delay can be reduced by increasing the frequency of the slow clock signal, but this is at the expense of higher dynamic power consumption in the idle mode.

[0048] In order to prevent glitch while avoiding the high latency of a glitch-free multiplexer, aspects of the present disclosure provide a glitch mitigation circuit for controlling the width of a high pulse of a slow clock signal passing through the multiplexer 310 during a transition between an idle mode and an active mode. In certain aspects, the glitch mitigation circuit ensures that the width of the high pulse of the slow clock signal meets a minimum pulse width (e.g., greater than one cycle of the functional clock signal) to prevent timing issues. Since the period of the functional clock signal is much shorter than the period of the slow clock period, the width of the high pulse can be greater than the period of the functional clock signal to prevent timing issues while still being much shorter than the period of the slow clock signal, thereby providing a much shorter latency than a glitch-free multiplexer. Various aspects of the present disclosure are further discussed below.

[0049] Figure 4An example is shown in which the system 110 includes a glitch mitigation circuit 410 according to certain aspects. The glitch mitigation circuit 410 has an input 412 configured to receive a slow clock signal and an output coupled to the second input 314 of the multiplexer 310. In this example, the slow clock signal is passed through the glitch mitigation circuit 410 to the multiplexer 310. Note that for ease of illustration, Figure 4 Clock path 130 and circuit 140 are not shown.

[0050] As discussed further below, the glitch mitigation circuit 410 is configured to ensure that the width of the high pulse of the slow clock signal at the output 414 satisfies a minimum pulse width (e.g., greater than one period of the functional clock signal) to prevent the high pulse from causing timing problems in the circuit 140. In some aspects, the width of the high pulse of the slow clock signal satisfies the minimum pulse width when the width of the high pulse of the slow clock signal is equal to or greater than the minimum pulse width. It should be understood that the minimum pulse width may be greater than the absolute minimum pulse width to prevent timing problems in the circuit 140. For example, the minimum pulse width may be equal to the absolute minimum pulse width plus a margin to account for uncertainties in the system 110 and / or operating conditions. The minimum pulse width to prevent timing problems may be determined, for example, by computer simulation of the system 110 and / or by performing tests on the system 110.

[0051] In this example, the glitch mitigation circuit 410 includes a gating circuit 420 and a delay circuit 430. The gating circuit 420 (also referred to as a clock gating unit) has a signal input 422, an enable input 424, and an output 426. The signal input 122 is coupled to the input 412 of the glitch mitigation circuit 410 to receive a slow clock signal (labeled “Clk_sw”). The enable input 424 is configured to receive a slow clock enable signal (labeled “Clk_sw_en”). In some aspects, the slow clock enable signal is provided to the gating circuit 420 by the control circuit 160 via the output 456 coupled to the enable input 424 of the gating circuit 420.

[0052] In operation, the gating circuit 420 is configured to pass the slow clock signal to the output terminal 426 or gate (i.e., block) the slow clock signal based on the slow clock enable signal from the control circuit 160. For example, the gating circuit 420 may be configured to pass the slow clock signal to the output terminal 426 when the slow clock enable signal has a first logic state, and gate the slow clock signal when the slow clock enable signal has a second logic state. The first logic state may be high (i.e., logic 1), and the second logic state may be low (i.e., logic 0), and vice versa. In one example, the gating circuit 420 may be implemented using an AND gate (not shown), wherein a first input of the AND gate is coupled to the signal input terminal 422, a second input of the AND gate is coupled to the enable input terminal 424, and an output of the AND gate is coupled to the output terminal 426. However, it should be understood that the gating circuit 420 is not limited to this example.

[0053] The delay circuit 430 has an input 432 coupled to the output 426 of the gating circuit 420 and an output 434 coupled to the output 414 of the glitch mitigation circuit 410. The delay circuit 430 is configured to receive the slow clock signal from the gating circuit 420, delay the slow clock signal by a time delay, and output the delayed slow clock signal at the output 426. As discussed further below, the time delay of the delay circuit 430 may be used to control the width of the high pulse of the slow clock signal output by the glitch mitigation circuit 410.

[0054] exist Figure 4 In the example of , the control circuit 450 has an input 454 coupled to the input 412 of the short-time pulse interference mitigation circuit 410 to receive the slow clock signal and an input 458 coupled to the output 434 of the delay circuit 430. The control circuit 450 also has an input 452 configured to receive an enable signal (labeled as "En"). For example, the enable signal may indicate whether a functional clock signal or a slow clock signal is injected into the clock path 130. For example, the enable signal may have a first logic value indicating a functional clock signal (i.e., an active mode) and a second logic value indicating a slow clock signal (i.e., an idle mode). The first logic value may be 1, and the second logic value may be 0, and vice versa.

[0055] An exemplary operation of the system 110 will now be discussed in accordance with certain aspects of the present disclosure. If the enable signal indicates a functional clock signal (e.g., the enable signal has a first logic value), the control circuit 160 causes the gating circuit 120 to pass the functional clock signal using the functional clock enable signal, and causes the gating circuit 420 in the short-term pulse interference mitigation circuit 410 to gate the slow clock signal using the slow clock enable signal. The control circuit 160 also causes the multiplexer 310 to select the first input terminal 312 using the selection signal. In this case, the functional clock signal is passed to the clock path 130 ( Figure 4 not shown).

[0056] If the enable signal indicates a slow clock signal (e.g., the enable signal has a second logic value), the control circuit 160 causes the gating circuit 120 to gate the functional clock signal using the functional clock enable signal, and causes the gating circuit 420 in the glitch mitigation circuit 410 to pass the slow clock signal using the slow clock enable signal. The control circuit 160 also causes the multiplexer 310 to select the second input terminal 314 using the selection signal. In this case, the slow clock signal is passed to the clock path 130 ( ) through the glitch mitigation circuit 410 and the multiplexer 310. Figure 4 not shown).

[0057] When the system 110 transitions (i.e., changes) from the idle mode to the active mode, the control circuit 160 uses the glitch mitigation circuit 410 to ensure that the high pulse at the output 414 of the glitch mitigation circuit 410 meets the minimum pulse width to prevent timing issues. In this regard, Figure 5 1 illustrates exemplary operation of the control circuit 160 and the short pulse interference mitigation circuit 410 during a transition (ie, change) from an idle mode to an active mode according to certain aspects. More specifically, Figure 5 An exemplary timing diagram of an enable signal (labeled "En"), a slow clock signal (labeled "Clk_sw"), a slow clock enable signal (labeled "Clk_sw_en"), and an output of the delay circuit 430 (labeled "Output") during a transition from an idle mode to an active mode is shown. Prior to time T1, the enable signal has a second logic value (e.g., 0) indicating a slow clock signal, the slow clock signal is low, and the slow clock enable signal has a first logic value (e.g., 1) that causes the gating circuit 420 to pass the slow clock signal. At about time T1, the slow clock signal transitions from low to high (i.e., a rising edge), which starts a high pulse.

[0058] At about time T1, the enable signal transitions from the second logic value (e.g., 0) to the first logic value (e.g., 1), thereby indicating a transition from the idle mode to the active mode. This transition allows the control circuit 160 to detect the change from the idle mode to the active mode. In response, the control circuit 160 detects the logic state at the signal input 422 of the gating circuit 420 via the input 454, and detects the logic state at the output 434 of the delay circuit 430 via the input 458. In this example, the control circuit 160 detects that the signal input 422 of the gating circuit 420 is high (i.e., logic 1) and detects that the output 434 of the delay circuit 430 is low (i.e., logic 0) at time T1. This indicates that the rising edge of the slow clock signal has not yet propagated to the output 434 of the delay circuit 430, and indicates that the gated slow clock signal will generate a narrow high pulse (i.e., a short pulse interference) at about time T1, thereby potentially causing timing problems.

[0059] In this case, the control circuit 160 waits for the output 434 of the delay circuit 430 to go high (i.e., transition from low to high). When the output 434 goes high at time T2, the control circuit 160 causes the gating circuit 420 to gate the slow clock signal using the slow clock enable signal. After gating the slow clock signal, the control circuit 160 waits for the output 434 of the delay circuit 430 to go low (i.e., transition from high to low). When the output 434 goes low at time T3, the high pulse has propagated through the delay circuit 430 to the multiplexer 310.

[0060] In this example, the width of the high pulse of the slow clock signal output by the short-time pulse interference mitigation circuit 410 is at least equal to the time delay of the delay circuit 430. Therefore, the width of the high pulse of the slow clock signal can be controlled by setting the time delay of the delay circuit 430 accordingly. The longer the time delay, the longer the width of the high pulse. In some aspects, the time delay of the delay circuit 430 can be set to ensure that the width of the high pulse of the slow clock signal meets the time delay of the minimum pulse width discussed above. After the output terminal 434 of the delay circuit 430 becomes low and the high pulse has passed through the multiplexer 310, the control circuit 160 can use the selection signal to switch the multiplexer 310 from the second input terminal 314 to the first input terminal 312. After the multiplexer 310 is switched to the first input terminal 312, the control circuit 160 can cause the gating circuit 120 to pass the functional clock signal to the multiplexer 310 using the functional clock enable signal.

[0061] exist Figure 5In the illustrated example, when the enable signal changes from the second logic value (e.g., 0) to the first logic value (e.g., 1) at time T1, the control circuit 160 detects that the signal input terminal 422 of the gating circuit 420 is high and the output terminal 434 of the delay circuit 430 is low. On the other hand, if the control circuit 160 detects that the signal input terminal 422 of the gating circuit 420 is high and the output terminal 434 of the delay circuit 430 is high, the control circuit 160 may cause the gating circuit 420 to gate the slow clock signal without waiting. This is because the high at the output terminal 434 of the delay circuit 430 indicates that the width of the high pulse has satisfied the minimum pulse width without waiting. In this case, after gating the slow clock signal, the control circuit 160 may wait before switching the multiplexer 310 from the second input terminal 314 to the first input terminal 312 until the high pulse passes through the delay circuit 430 and the output terminal 434 of the delay circuit 430 becomes low.

[0062] If the control circuit 160 detects that the signal input 422 of the gating circuit 420 is low and the output 434 of the delay circuit 430 is low, the control circuit 160 may cause the gating circuit 420 to gate the slow clock without waiting. This is because the low at both the signal input 422 of the gating circuit 420 and the output 434 of the delay circuit 430 indicates that there is currently no high pulse. After gating the slow clock signal, the control circuit 160 may switch the multiplexer 310 from the second input 314 to the first input 312.

[0063] When the system 110 transitions from the active mode to the idle mode, the control circuit 160 may cause the gating circuit 120 to gate the functional clock signal using the functional clock enable signal. After gating the functional clock signal, the control circuit 160 may cause the multiplexer 310 to switch from the first input terminal 312 to the second input terminal 314 using the selection signal. After switching the multiplexer 310 to the second input terminal 314, the control circuit 160 may cause the gating circuit 420 in the glitch mitigation circuit 410 to pass (i.e., de-gate) the slow clock signal.

[0064] Figure 6 An example is shown where the glitch mitigation circuit 410 also includes an OR gate 610. As discussed further below, the OR gate 610 is configured to combine the high pulse from the gating circuit 420 with a delayed version of the high pulse from the delay circuit 430 to generate a high pulse at the output 414 of the glitch mitigation circuit 410. It should be appreciated that the OR gate 610 may be implemented using one or more NAND gates, one or more NOR gates, one or more inverters, one or more other logic gates, or any combination thereof.

[0065] OR gate 610 has a first input 612, a second input 614, and an output 616. The first input is coupled to output 434 of delay circuit 430, the second input 614 is coupled to output 426 of gating circuit 420, and the output 616 is coupled to output 414 of glitch mitigation circuit 410.

[0066] Reference will now be made to certain aspects of the present disclosure. Figure 7 To discuss Figure 6 0048] FIG. 2 is an exemplary operation of the glitch mitigation circuit 410 during a transition from an idle mode to an active mode. Figure 7 An exemplary timing diagram is shown of an enable signal (labeled “En”), a slow clock signal (labeled “Clk_sw”), a slow clock enable signal (labeled “Clk_sw_en”), an output of the gate circuit (labeled “Out_gate”), an output of the delay circuit 430 (labeled “Out_del”), and an output of the short-time pulse interference mitigation circuit 410 (labeled “Output”) during a transition from an idle mode to an active mode.

[0067] Prior to time T1, the enable signal has a second logic value (e.g., 0) indicating the slow clock signal, the slow clock signal is low, and the slow clock enable signal has a first logic value (e.g., 1) that causes the gating circuit 420 to pass the slow clock signal. At about time T1, the slow clock signal transitions from low to high (i.e., a rising edge), which starts a high pulse.

[0068] At approximately time T1, the enable signal transitions from the second logic value (e.g., 0) to the first logic value (e.g., 1), thereby indicating a transition from the idle mode to the active mode. In response, the control circuit 160 detects the logic state at the signal input 422 of the gating circuit 420 via the input 454, and detects the logic state at the output 434 of the delay circuit 430 via the input 458. In this example, the control circuit 160 detects that the signal input 422 of the gating circuit 420 is high (i.e., logic 1) at time T1 and detects that the output 434 of the delay circuit 430 is low (i.e., logic 0). This indicates that the rising edge of the slow clock signal has not yet propagated to the output 434 of the delay circuit 430, and indicates that the gated slow clock signal will generate a narrow high pulse (i.e., a short-time pulse interference) at approximately time T1, thereby potentially causing timing problems. At approximately time T1, the output 426 of the gating circuit 420 transitions from low to high. Note that for simplicity, at Figure 7 The delay in the gating circuit 420 is ignored.

[0069] In this case, the control circuit 160 waits for the output 434 of the delay circuit 430 to go high (i.e., change from low to high). When the output 434 of the delay circuit 430 goes high at time T2, the rising edge at the output 426 of the gating circuit 420 has propagated to the output 434 of the delay circuit 430. In response to the output 434 of the delay circuit 430 going high, the control circuit 160 may cause the gating circuit 420 to gate the slow clock signal using the slow clock enable signal. Figure 7 In the example of FIG. 1 , the control circuit 160 waits for a short delay after detecting that the output 434 of the delay circuit 430 goes high before gating the slow clock signal at time T3. In this example, the short delay helps ensure that the high pulse from the output 426 of the gating circuit 420 overlaps with the delayed version of the high pulse from the output 434 of the delay circuit 430.

[0070] After gating the slow clock signal, the control circuit 160 waits for the output 434 of the delay circuit 430 to go low (i.e., transition from high to low). When the output 434 goes low at time T4, the high pulse has propagated through the delay circuit 430. As discussed above, after the output 434 goes low, the control circuit 160 can switch the multiplexer 310 from the second input 314 to the first input 312.

[0071] OR gate 610 performs an OR operation on the high pulse from output 426 of gating circuit 420 and the delayed version of the high pulse from output 434 of delay circuit 430 to generate a high pulse at output 414 of glitch mitigation circuit 410. Figure 7 As shown, the high pulse at output 414 is a combination of a delayed version of the high pulse from output 426 of gate circuit 420 and the high pulse from output 434 of delay circuit 430. In this example, the high pulse at second input 614 of OR gate 610 bypasses delay circuit 430.

[0072] In this example, the width of the high pulse at the output 414 of the glitch mitigation circuit 410 is greater than the time delay of the delay circuit 430 (e.g., approximately equal to twice the time delay of the delay circuit 430 minus the overlap between the high pulse from the output 426 of the gating circuit 420 and the delayed version of the high pulse from the output 434 of the delay circuit 430). Therefore, the width of the high pulse at the output 414 can be controlled by setting the time delay of the delay circuit 430 accordingly. In certain aspects, the time delay of the delay circuit 430 can be set to a time delay that ensures that the width of the high pulse at the output 414 meets the minimum pulse width to prevent the timing issues discussed above.

[0073] exist Figure 7In the example of , the control circuit 160 waits for a short delay after detecting that the output 434 of the delay circuit 430 goes high before gating the slow clock signal to ensure that the high pulse from the output 426 of the gating circuit 420 overlaps with the delayed version of the high pulse from the output 434 of the delay circuit 430. The overlap can also be achieved by inserting a delay element (not shown) between the output 426 of the gating circuit 420 and the second input 614 of the OR gate 610. In this example, the delay element introduces a short delay in the high pulse at the second input 614 of the OR gate 610, which helps to ensure the overlap between the high pulse at the second input 614 of the OR gate 610 and the delayed version of the high pulse at the first input 612 of the OR gate 610. In some aspects, the two methods discussed above can be used in combination to ensure overlap.

[0074] In some aspects, the delay circuit 430 may include a plurality of delay devices coupled in series between an input terminal 432 and an output terminal 434. Each of the delay devices may also be referred to as a delay stage, a delay element, a delay cell, a delay buffer, or another term. In these aspects, the time delay of the delay circuit 430 may be approximately equal to the sum of the time delays of the delay devices.

[0075] In some aspects, the delay circuit 430 may have a programmable time delay. This allows the minimum pulse width to be programmed, for example, to accommodate various system designs, functional clock frequencies, etc. In this regard, Figure 8 An exemplary implementation of a delay circuit 430 with a programmable delay in accordance with certain aspects of the present disclosure is shown. Figure 8 The exemplary implementation shown can be used to implement Figure 4 or Figure 6 The delay circuit 430 in FIG.

[0076] In this example, the delay circuit 430 includes a plurality of delay devices 810-1 to 810-N coupled in series to form a delay line. Each of the delay devices 810-1 to 810-N has a corresponding input terminal 812-1 to 812-N and a corresponding output terminal 814-1 to 814-N. Each of the delay devices 810-1 to 810-N may have substantially the same time delay. The input terminal 812-1 of the delay device 810-1 is coupled to the input terminal 432 of the delay circuit 430. Each of the delay devices 810-1 to 810-N may also be referred to as a delay stage, a delay element, a delay unit, a delay buffer or another term.

[0077] The delay circuit 430 also includes a multiplexer 830 having a plurality of input terminals 832-1 to 832-N, an output terminal 834, and a selection input terminal 836. Each of the input terminals 832-1 to 832-N of the multiplexer 830 is coupled to an output terminal 814-1 to 814-N of a corresponding one of the delay devices 810-1 to 810-N in the delay line. Therefore, each of the input terminals 832-1 to 832-N is coupled to a different point on the delay line corresponding to a different time delay. The output terminal 834 of the multiplexer 830 is coupled to the output terminal 434 of the delay circuit 430, and the selection input terminal 836 of the multiplexer 830 is configured to receive a delay control signal.

[0078] The multiplexer 830 is configured to select one of the inputs 832-1 through 832-N based on the received delay control signal and couple the selected one of the inputs 832-1 through 832-N to the output 834 of the multiplexer 830. Because each of the inputs 832-1 through 832-N is coupled to a different point on the delay line corresponding to a different time delay, the delay control signal controls the time delay of the delay circuit 430 by controlling which of the inputs 832-1 through 832-N is selected by the multiplexer 830. In some aspects, the delay control signal may be a digital signal including one or more bits, where the value of the one or more bits indicates one of the inputs 832-1 through 832-N.

[0079] It should be understood that the delay circuit 430 is not limited to Figure 8 In general, the delay circuit 430 may include a plurality of delay devices and circuitry for selectively switching the delay devices into and out of a delay path between an input 432 and an output 434 of the delay circuit 430 based on a delay control signal. The circuitry may include switches, one or more multiplexers, logic gates, or any combination thereof.

[0080] Fig. 9 An exemplary implementation of delay devices 810-1 to 810-N according to certain aspects of the present disclosure is shown. In this example, each of the delay devices 810-1 to 810-N includes a corresponding register 910-1 to 910-N (e.g., a D flip-flop) clocked by a control clock signal (labeled "Clk_c"). Each register 910-1 to 910-N may also be referred to as a latch, a flip-flop, or another term.

[0081] In this example, each register 910-1 to 910-N has a signal input (labeled "D"), a clock input (represented by a triangle), and an output (labeled "Q"). The clock input of each register 910-1 to 910-N is configured to receive a control clock signal. The signal input of register 910-1 is coupled to the input 432 of delay circuit 430. The output of each of registers 910-1 to 910-(N-1) is coupled to the signal input of the next register 910-2 to 910-N in the delay line. Each input 832-1 to 832-N of multiplexer 830 is coupled to the output of a corresponding one of registers 910-1 to 910-N.

[0082] In operation, each register 910-1 to 910-N is configured to latch the logic value at the corresponding signal input terminal on the trigger edge of the control clock signal, and output the latched logic value at the corresponding output terminal. The trigger edge can be the rising edge of the rising edge trigger register or the falling edge of the falling edge trigger register. In this example, the time delay of each register 910-1 to 910-N is approximately equal to one cycle (i.e., cycle) of the control clock signal. In this example, the time delay of the delay circuit 430 is approximately equal to m·Tc, where Tc is one cycle of the control clock signal, and m is a multiple that can be programmed using the delay control signal. For example, when the delay control signal selects the input terminal 832-1, the time delay is approximately Tc, and when the delay control signal selects the input terminal 832-2, the time delay is approximately 2Tc, and so on. Therefore, in this example, the time delay of the delay circuit 430 is approximately equal to a multiple of the cycle of the control clock signal, where the multiple can be programmed using the delay control signal.

[0083] The delay circuit 430 may result in a smaller increase in the duty cycle of the slow clock signal passing through the glitch mitigation circuit 410. This is because the glitch mitigation circuit 410 extends the width of the high pulse of the slow clock signal to meet the minimum pulse width discussed above. The duty cycle offset may be made very small by making the frequency of the control clock signal much higher (e.g., at least two orders of magnitude higher) than the frequency of the slow clock signal. This makes the period of the control clock signal much smaller than the period of the slow clock signal, which ensures that the extension of the high pulse of the slow clock signal caused by the glitch mitigation circuit 410 is much smaller than the period of the slow clock signal, and therefore ensures that the extension of the high pulse has a small effect on the duty cycle of the slow clock signal. Since the period of the functional clock signal is much smaller than the period of the slow clock signal, the period of the control clock signal may also be made much smaller than the period of the slow clock signal while still allowing the high pulse to be extended by the glitch mitigation circuit 410 to meet the minimum pulse width. In some aspects, the control clock signal may have a frequency that is the same as or close to (eg, within an order of magnitude of) the frequency of the functional clock signal.

[0084] Fig.10 1 shows an example in which the short-time pulse interference mitigation circuit 410 also includes a sampler 1010 and a delay device 1020. In this example, the use Fig. 9 The exemplary implementation shown implements delay circuit 430 .

[0085] The sampler 1010 has a signal input 1012, a clock input 1016, and an output 1014. The signal input 1012 is coupled to the input 412 of the short-time pulse interference mitigation circuit 410 to receive the slow clock signal. The clock input 1016 is configured to receive the control clock signal. The output 1014 is coupled to the signal input 422 of the gating circuit 420. In operation, the sampler 1010 is configured to sample the logic state (i.e., logic value) of the slow clock signal on the edge (e.g., rising edge) of the control clock signal. Sampling the slow clock signal on the edge of the control clock signal synchronizes the slow clock signal with the control clock signal. The sampler 1010 outputs the resulting synchronized slow clock signal at the output 1014. Therefore, in this example, the gating circuit 420 receives the synchronized slow clock signal from the sampler 1010. The sampler 1010 can be implemented, for example, using one or more registers or another type of sampler clocked by the control clock signal.

[0086] The delay device 1020 is coupled between the output terminal 426 of the gate control circuit 420 and the second input terminal 614 of the OR gate 610. The delay device 1020 is also coupled between the output terminal 426 of the gate control circuit 420 and the input terminal 432 of the delay circuit 430. Fig.10In the example of FIG. 4 , the delay device 1020 is implemented using a register 1030 having a signal input terminal (labeled “D”) coupled to the output terminal 426 of the gate circuit 420, a clock input terminal (represented by a triangle) configured to receive the control clock signal, and an output terminal (labeled “Q”) coupled to the second input terminal 614 of the “OR” gate 610 and the input terminal 432 of the delay circuit 430. In this example, the register 1030 is configured to latch a logic value at the input terminal of the register 1030 on a triggering edge of the control clock signal, and output the latched logic value at the output terminal of the register 1030. Since the register 1030 is clocked using the control clock signal, the register 1030 provides a time delay of one period (i.e., cycle) of the control clock signal to the delay device 1020. Therefore, in this example, the delay device 1020 delays the high pulse from the gating circuit 420 by one period (i.e., cycle) of the control clock signal before inputting the high pulse to the second input terminal 614 of the OR gate 610 and the input terminal 432 of the delay circuit 430. However, it should be understood that the present disclosure is not limited to this example, and the delay device 1020 may delay the high pulse by a different time delay.

[0087] Reference will now be made to certain aspects of the present disclosure. Fig.11 To discuss Fig.10 0048] FIG. 2 is an exemplary operation of the glitch mitigation circuit 410 during a transition from an idle mode to an active mode. Fig.11 An exemplary timing diagram of an enable signal (labeled “En”), a synchronized slow clock signal (labeled “Clk_sw_sync”), a slow clock enable signal (labeled “Clk_sw_en”), an output of a gate circuit (labeled “Out_gate”), an output of a delay device 1020 (labeled “Del_1”), an output of a delay circuit 430 (labeled “Out_del”), and an output of a glitch mitigation circuit 410 (labeled “Output”) during a transition from an idle mode to an active mode is shown. In this example, the delay device 1020 is programmed to delay the synchronized slow clock signal by two periods (i.e., cycles) of the control clock signal. The total delay at the output 434 of the delay circuit 430 is the sum of the delay of the delay circuit 430 and the delay of the delay device 1020, which in this example is approximately three periods (i.e., cycles) of the control clock signal. In the following discussion, a cycle refers to a period (i.e., cycle) of the control clock signal.

[0088] exist Fig.11 In the timing diagram shown, time is shown on the horizontal axis in terms of periods (i.e., cycles) of the control clock signal. For example, 1 indicates one period (i.e., cycle) starting from time 0, 2 indicates two periods (i.e., cycles) starting from time 0, and so on.

[0089] Prior to time 0, the enable signal has a second logic value (eg, 0) indicating a slow clock signal, the synchronized slow clock signal is low, and the slow clock enable signal has a first logic value (eg, 1) causing the gating circuit 420 to pass the synchronized slow clock signal.

[0090] At approximately time 0, the synchronized slow clock signal transitions from low to high, and the enable signal transitions from the second logic value (e.g., 0) to the first logic value (e.g., 1), thereby indicating a transition from the idle mode to the active mode. In response to the transition of the enable signal, the control circuit 160 detects the logic state at the signal input 422 of the gating circuit 420 via the input 454, and detects the logic state at the output 434 of the delay circuit 430 via the input 458. In this example, the control circuit 160 detects that the signal input 422 of the gating circuit 420 is high (i.e., logic 1) and detects that the output 434 of the delay circuit 430 is low (i.e., logic 0) at time zero. This indicates that the rising edge of the synchronized slow clock signal has not yet propagated to the output 434 of the delay circuit 430. At approximately time 0, the output 426 of the gating circuit 420 transitions from low to high. Note that for simplicity, at Fig.11 Ignore the delay in the gating circuit 420. Fig.11 As shown, the output of the delay device 1020 changes from low to high after one cycle delay.

[0091] In this case, the control circuit 160 waits for the output 434 of the delay circuit 430 to go high (ie, transition from low to high), which in this example occurs after a three cycle delay. Fig.11 As shown, in response to the output terminal 434 of the delay circuit 430 going high, the control circuit 160 may cause the gating circuit 420 to gate the synchronized slow clock signal using the slow clock enable signal after a one cycle delay.

[0092] like Fig.11 As shown, after gating the synchronized slow clock signal, the output of the delay device 1020 changes from high to low after one cycle delay. Then, the control circuit 160 waits for the output 434 of the delay circuit 430 to become low (i.e., change from high to low). As discussed above, when the output 434 becomes low at about time 7, the control circuit 160 can switch the multiplexer 310 from the second input 314 to the first input 312.

[0093] OR gate 610 performs an OR operation on the high pulse from delay device 1020 and the high pulse from output 434 of delay circuit 430 to generate a high pulse at output 414 of glitch mitigation circuit 410. Fig.11As shown, the high pulse at output 414 is a combination of the high pulse from delay device 1020 and the high pulse from output 434 of delay circuit 430. Fig.11 In the example in , the high pulse at the output 414 has a width of about six cycles. However, it should be understood that the present disclosure is not limited to this example.

[0094] In this example, the high pulse from the delay device 1020 overlaps two cycles with the high pulse from the output 434 of the delay circuit 430. The two-cycle overlap includes a one-cycle delay in the control circuit 160 that gates the synchronized slow clock signal and a one-cycle delay in the delay device 1020. However, it should be understood that the present disclosure is not limited to this example.

[0095] Fig.12 A method 1200 for glitch mitigation according to certain aspects is illustrated. The method 1200 may be performed by the glitch mitigation circuit 410, the control circuit 160, and the multiplexer 310.

[0096] At block 1210, a first clock signal is received. The first clock signal may correspond to a slow clock signal.

[0097] At block 1220, a second clock signal is received. The second clock signal may correspond to a functional clock signal.

[0098] At block 1230 , the first clock signal is passed to a clock path during a first mode. For example, the clock path may correspond to clock path 130 , and the first mode may correspond to an idle mode. The first clock signal may be passed to the clock path by multiplexer 310 .

[0099] At block 1240 , the second clock signal is passed to the clock path during a second mode. For example, the second mode may correspond to an active mode. The second clock signal may be passed to the clock path by the multiplexer 310 .

[0100] At block 1250, a change from the first mode to the second mode is detected. For example, when the enable signal changes from the second logic value (e.g., 0) to the first logic value (e.g., 1), the control circuit 160 may detect the change from the first mode (e.g., idle mode) to the second mode (e.g., active mode).

[0101] At block 1260, in response to detecting the change from the first mode to the second mode, detecting when the width of the high pulse of the first clock signal is equal to or greater than a minimum pulse width. For example, when the logic state at the output of the delay circuit (e.g., delay circuit 430) is high, the control circuit 160 may detect when the high pulse is equal to or greater than the pulse width. The pulse width may correspond to the minimum pulse width discussed above, which may be greater than the period of the second clock signal (e.g., functional clock signal).

[0102] At block 1270, when the width of the high pulse of the first clock signal is equal to or greater than the pulse width, the first clock signal is gated. For example, the control circuit 160 may cause the gating circuit 420 to gate the first clock signal (eg, the slow clock signal).

[0103] In some aspects, method 1200 may include passing the first clock signal through a delay circuit (e.g., delay circuit 430), wherein detecting when the high pulse of the first clock signal is equal to or greater than the pulse width includes detecting a logic state at an output of the delay circuit. For example, the logic state may be detected by control circuit 160. In some aspects, detecting when the high pulse of the first clock signal is equal to or greater than the pulse width includes detecting that the high pulse of the first clock signal is equal to or greater than the pulse width when the detected logic state at the output of the delay circuit is high.

[0104] In some aspects, the time delay of the delay circuit is greater than a period of the second clock signal (eg, the functional clock signal).

[0105] In some aspects, method 1200 may include combining the high pulse of the first clock signal that passes through the delay circuit with the high pulse of the first clock signal that bypasses the delay circuit to obtain a combined high pulse. For example, the combination may be performed by an OR gate 610, and the high pulse that bypasses the delay circuit may propagate along a signal path between the gating circuit 420 and the second input 614 of the OR gate 610. In these aspects, passing the high pulse of the first clock signal to the clock path includes passing the combined high pulse to the clock path.

[0106] In some aspects, the first clock signal (e.g., slow clock signal) has a first frequency, the second clock signal (e.g., functional clock signal) has a second frequency, and the second frequency is higher than the first frequency. For example, the second frequency can be at least two orders of magnitude higher (e.g., 100 times higher) than the first frequency.

[0107] In some aspects, the method 1200 may include receiving an enable signal, wherein detecting the change from the first mode to the second mode includes detecting the change from the first mode to the second mode based on the enable signal. For example, when the enable signal changes from the second logic value (e.g., 0) discussed above to the first logic value (e.g., 1), the control circuit 160 may detect the change.

[0108] In some aspects, detecting the change from the first mode to the second mode based on the enable signal includes detecting the change from the first mode to the second mode when the enable signal changes from a first value to a second value. In these aspects, the first value may correspond to the second logic value (e.g., 0) discussed above, and the second value may correspond to the second logic value (e.g., 0) discussed above with reference to Figure 5 , Figure 7 and Fig.11 The first logical value in question (eg, 1).

[0109] The control circuit 160 may be implemented using a finite state machine, a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor may perform the functions described herein by executing software including code for performing the functions described herein. The software may be stored on a computer readable storage medium such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk.

[0110] Specific implementation examples are described in the following numbered clauses:

[0111] 1. A device, comprising:

[0112] a first gating circuit, the first gating circuit having an input terminal and an output terminal, wherein the input terminal of the first gating circuit is configured to receive a first clock signal;

[0113] a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit; and

[0114] A control circuit, the control circuit being configured to:

[0115] Receive an enable signal;

[0116] detecting a logic state at the output of the delay circuit; and

[0117] The first gating circuit is caused to pass or gate the first clock signal based on the enable signal and a logic state detected at the output of the delay circuit.

[0118] 2. The apparatus of clause 1, wherein the control circuit is configured to:

[0119] detecting a change from a first mode to a second mode based on the enable signal; and in response to detecting the change from the first mode to the second mode, causing the first gating circuit to gate the first clock signal when a logic state detected at the output end of the delay circuit changes from low to high.

[0120] 3. The apparatus of clause 2, wherein the control circuit is configured to:

[0121] When the enable signal indicates the first mode, causing the first gating circuit to pass the first clock signal; and

[0122] When the enable signal indicates the second mode, the first gating circuit is enabled to gate the first clock signal.

[0123] 4. The apparatus of clause 1, wherein the control circuit is configured to:

[0124] detecting a logic state at the input terminal of the first gating circuit;

[0125] detecting a change from a first mode to a second mode based on the enable signal; and

[0126] in response to detecting the change from the first mode to the second mode, causing the first gating circuit to pass the first clock signal when the logic state detected at the input of the first gating circuit is high and the logic state detected at the output of the delay circuit is low; and

[0127] The first gating circuit is caused to gate the first clock signal when the logic state detected at the input of the first gating circuit is high and the logic state detected at the output of the delay circuit is high.

[0128] 5. The apparatus of any of clauses 1 to 4, wherein the time delay of the delay circuit is programmable.

[0129] 6. The apparatus of clause 5, wherein the delay circuit is configured to:

[0130] receiving a delay control signal comprising one or more bits, and

[0131] The time delay of the delay circuit is set to one of a plurality of time delays based on the one or more bits.

[0132] 7. An apparatus according to any of clauses 1 to 6, wherein the delay circuit is configured to receive a second clock signal, and the time delay of the delay circuit is approximately equal to a multiple of a period of the second clock signal.

[0133] 8. The apparatus of clause 7, wherein the multiple is programmable.

[0134] 9. An apparatus according to clause 7 or 8, wherein a period of the first clock signal is greater than the period of the second clock signal.

[0135] 10. The apparatus of clause 9, wherein the period of the first clock signal is at least two orders of magnitude greater than the period of the second clock signal.

[0136] 11. An apparatus according to any one of clauses 1 to 6, further comprising an OR gate having a first input, a second input and an output, wherein the first input is coupled to the output of the delay circuit and the second input is coupled to the output of the first gating circuit.

[0137] 12. The apparatus according to clause 11, further comprising:

[0138] a second gating circuit having an input and an output, wherein the input of the second gating circuit is configured to receive a second clock signal; and

[0139] A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the second gating circuit, and the second input of the multiplexer is coupled to the output of the OR gate.

[0140] 13. The apparatus of clause 12, further comprising a clock path coupled to the output of the multiplexer.

[0141] 14. The apparatus of clause 12 or 13, wherein the first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is higher than the first frequency.

[0142] 15. The apparatus of clause 14, wherein the second frequency is at least two orders of magnitude higher than the first frequency.

[0143] 16. An apparatus according to any of clauses 12 to 15, wherein a time delay of the delay circuit is greater than a period of the second clock signal.

[0144] 17. An apparatus according to any of clauses 12 to 16, wherein the control circuit is configured to:

[0145] detecting a change from a first mode to a second mode based on the enable signal; and in response to detecting the change from the first mode to the second mode, causing the first gating circuit to gate the first clock signal when a logic state detected at the output end of the delay circuit changes from low to high.

[0146] 18. The apparatus of clause 17, wherein the control circuit is configured to:

[0147] When the enable signal indicates the first mode, causing the multiplexer to select the second input terminal; and

[0148] When the enable signal indicates the second mode, the multiplexer is enabled to select the first input terminal.

[0149] 19. An apparatus according to clause 17 or 18, wherein the control circuit is configured to:

[0150] When the enable signal indicates the first mode, causing the first gating circuit to pass the first clock signal, and causing the second gating circuit to gate the second clock signal; and

[0151] When the enable signal indicates the second mode, the first gating circuit is enabled to gate the second clock signal, and the second gating circuit is enabled to pass the second clock signal.

[0152] 20. A method for short-term pulse interference mitigation, the method comprising:

[0153] receiving a first clock signal;

[0154] receiving a second clock signal;

[0155] passing the first clock signal to a clock path during a first mode;

[0156] passing the second clock signal to the clock path during a second mode;

[0157] detecting a change from the first mode to the second mode;

[0158] responsive to detecting the change from the first mode to the second mode, detecting when a high pulse of the first clock signal is equal to or greater than a pulse width; and

[0159] When the high pulse of the first clock signal is equal to or greater than the pulse width,

[0160] The first clock signal is gated.

[0161] 21. The method of clause 20, further comprising passing the first clock signal through a delay circuit, and wherein detecting when the high pulse of the first clock signal is equal to or greater than the pulse width comprises detecting a logic state at an output of the delay circuit.

[0162] 22. A method according to clause 21, wherein detecting when the high pulse of the first clock signal is equal to or greater than the pulse width includes detecting that the high pulse of the first clock signal is equal to or greater than the pulse width when the detected logic state at the output end of the delay circuit is high.

[0163] 23. A method according to clause 21 or 22, wherein a time delay of the delay circuit is greater than a period of the second clock signal.

[0164] 24. The method according to any one of clauses 21 to 23, further comprising:

[0165] combining the high pulse of the first clock signal that passes through the delay circuit with the high pulse of the first clock signal that bypasses the delay circuit to obtain a combined high pulse;

[0166] Wherein delivering the high pulse of the first clock signal to the clock path comprises delivering the combined high pulse to the clock path.

[0167] 25. The method of any of clauses 20 to 24, wherein the first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is higher than the first frequency.

[0168] 26. The method of clause 25, wherein the second frequency is at least two orders of magnitude higher than the first frequency.

[0169] 27. A method according to any of clauses 20 to 26, the method further comprising receiving an enable signal, and wherein detecting the change from the first mode to the second mode comprises detecting the change from the first mode to the second mode based on the enable signal.

[0170] 28. The method of clause 27, wherein detecting the change from the first mode to the second mode based on the enable signal comprises detecting the change from the first mode to the second mode when the enable signal changes from a first value to a second value.

[0171] 29. A method according to any of clauses 20 to 28, wherein the pulse width is greater than a period of the second clock signal.

[0172] 30. An apparatus according to any one of clauses 7 to 10, further comprising an OR gate having a first input, a second input and an output, wherein the first input is coupled to the output of the delay circuit and the second input is coupled to the output of the first gating circuit.

[0173] 31. The apparatus of clause 30, further comprising:

[0174] a second gating circuit having an input and an output, wherein the input of the second gating circuit is configured to receive a third clock signal; and

[0175] A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the second gating circuit, and the second input of the multiplexer is coupled to the output of the OR gate.

[0176] 32. The apparatus of clause 31 , further comprising a clock path coupled to the output of the multiplexer.

[0177] 33. An apparatus according to clause 31 or 32, wherein the first clock signal has a first frequency, the third clock signal has a third frequency, and the third frequency is higher than the first frequency.

[0178] 34. The apparatus of clause 33, wherein the third frequency is at least two orders of magnitude higher than the first frequency.

[0179] 35. An apparatus according to any of clauses 30 to 34, wherein a time delay of the delay circuit is greater than a period of the third clock signal.

[0180] 36. An apparatus according to any of clauses 30 to 35, wherein the control circuit is configured to:

[0181] detecting a change from a first mode to a second mode based on the enable signal; and in response to detecting the change from the first mode to the second mode, causing the first gating circuit to gate the first clock signal when a logic state detected at the output end of the delay circuit changes from low to high.

[0182] 37. The apparatus of clause 36, wherein the control circuit is configured to:

[0183] When the enable signal indicates the first mode, causing the multiplexer to select the second input terminal; and

[0184] When the enable signal indicates the second mode, the multiplexer is enabled to select the first input terminal.

[0185] 38. An apparatus according to clause 36 or 37, wherein the control circuit is configured to:

[0186] When the enable signal indicates the first mode, the first gating circuit is enabled to pass the first clock signal, and the second gating circuit is enabled to gate the third clock signal; and

[0187] When the enable signal indicates the second mode, the first gating circuit is enabled to gate the second clock signal, and the second gating circuit is enabled to pass the third clock signal.

[0188] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or superior to other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0189] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device, comprising: a first gating circuit, the first gating circuit having an input terminal and an output terminal, wherein the input terminal of the first gating circuit is configured to receive a first clock signal; a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit; and A control circuit, the control circuit being configured to: Receive an enable signal; detecting a logic state at the output of the delay circuit; as well as The first gating circuit is caused to pass or gate the first clock signal based on the enable signal and a logic state detected at the output of the delay circuit.

2. The apparatus according to claim 1, wherein the control circuit is configured to: detecting a change from a first mode to a second mode based on the enable signal; and In response to detecting the change from the first mode to the second mode, the first gating circuit is caused to gate the first clock signal when the logic state detected at the output of the delay circuit changes from low to high.

3. The apparatus according to claim 2, wherein the control circuit is configured to: When the enable signal indicates the first mode, causing the first gating circuit to pass the first clock signal; and When the enable signal indicates the second mode, the first gating circuit is enabled to gate the first clock signal.

4. The apparatus according to claim 1, wherein the control circuit is configured to: detecting a logic state at the input terminal of the first gating circuit; detecting a change from a first mode to a second mode based on the enable signal; as well as In response to detecting the change from the first mode to the second mode, causing the first gating circuit to pass the first clock signal when the logic state detected at the input of the first gating circuit is high and the logic state detected at the output of the delay circuit is low; as well as The first gating circuit is caused to gate the first clock signal when the logic state detected at the input of the first gating circuit is high and the logic state detected at the output of the delay circuit is high. The apparatus of claim 1 , wherein a time delay of the delay circuit is programmable.

6. The apparatus of claim 5, wherein the delay circuit is configured to: receiving a delay control signal comprising one or more bits, and The time delay of the delay circuit is set to one of a plurality of time delays based on the one or more bits. 7 . The apparatus of claim 1 , wherein the delay circuit is configured to receive a second clock signal, and a time delay of the delay circuit is approximately equal to a multiple of a period of the second clock signal.

8. The apparatus of claim 7, wherein the multiple is programmable.

9. The apparatus of claim 7, wherein a period of the first clock signal is greater than the period of the second clock signal.

10. The apparatus of claim 9, wherein the period of the first clock signal is at least two orders of magnitude greater than the period of the second clock signal.

11. The apparatus of claim 1 , further comprising an OR gate having a first input, a second input, and an output, wherein the first input is coupled to the output of the delay circuit and the second input is coupled to the output of the first gating circuit.

12. The device according to claim 11, further comprising: a second gating circuit, the second gating circuit having an input terminal and an output terminal, wherein the input terminal of the second gating circuit is configured to receive a second clock signal; and A multiplexer having a first input, a second input and an output, wherein the first input of the multiplexer is coupled to the output of the second gating circuit and the second input of the multiplexer is coupled to the output of the OR gate.

13. The apparatus of claim 12, further comprising a clock path coupled to the output of the multiplexer.

14. The apparatus of claim 12, wherein the first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is higher than the first frequency.

15. The apparatus of claim 14, wherein the second frequency is at least two orders of magnitude higher than the first frequency.

16. The apparatus of claim 12, wherein a time delay of the delay circuit is greater than a period of the second clock signal.

17. The apparatus of claim 12, wherein the control circuit is configured to: detecting a change from a first mode to a second mode based on the enable signal; and In response to detecting the change from the first mode to the second mode, the first gating circuit is caused to gate the first clock signal when the logic state detected at the output of the delay circuit changes from low to high.

18. The apparatus of claim 17, wherein the control circuit is configured to: When the enable signal indicates the first mode, causing the multiplexer to select the second input terminal; and When the enable signal indicates the second mode, the multiplexer is enabled to select the first input terminal.

19. The apparatus of claim 17, wherein the control circuit is configured to: When the enable signal indicates the first mode, causing the first gating circuit to pass the first clock signal, and causing the second gating circuit to gate the second clock signal; and When the enable signal indicates the second mode, the first gating circuit is enabled to gate the second clock signal, and the second gating circuit is enabled to pass the second clock signal.

20. A method for short-term pulse interference mitigation, the method comprising: receiving a first clock signal; receiving a second clock signal; passing the first clock signal to a clock path during a first mode; passing the second clock signal to the clock path during a second mode; detecting a change from the first mode to the second mode; responsive to detecting the change from the first mode to the second mode, detecting when a high pulse of the first clock signal is equal to or greater than a pulse width; as well as When the high pulse of the first clock signal is equal to or greater than the pulse width, the first clock signal is gated.

21. The method of claim 20, further comprising passing the first clock signal through a delay circuit, and wherein detecting when the high pulse of the first clock signal is equal to or greater than the pulse width comprises detecting a logic state at an output of the delay circuit.

22. The method of claim 21 , wherein detecting when the high pulse of the first clock signal is equal to or greater than the pulse width comprises detecting that the high pulse of the first clock signal is equal to or greater than the pulse width when the logic state detected at the output of the delay circuit is high.

23. The method of claim 21, wherein a time delay of the delay circuit is greater than a period of the second clock signal.

24. The method according to claim 21, further comprising: combining the high pulse of the first clock signal that passes through the delay circuit with the high pulse of the first clock signal that bypasses the delay circuit to obtain a combined high pulse; Wherein delivering the high pulse of the first clock signal to the clock path comprises delivering the combined high pulse to the clock path.

25. The method of claim 20, wherein the first clock signal has a first frequency, the second clock signal has a second frequency, and the second frequency is higher than the first frequency.

26. The method of claim 25, wherein the second frequency is at least two orders of magnitude higher than the first frequency.

27. The method of claim 20, further comprising receiving an enable signal, and wherein detecting the change from the first mode to the second mode comprises detecting the change from the first mode to the second mode based on the enable signal.

28. The method of claim 27, wherein detecting the change from the first mode to the second mode based on the enable signal comprises detecting the change from the first mode to the second mode when the enable signal changes from a first value to a second value.

29. The method of claim 20, wherein the pulse width is greater than a period of the second clock signal.

Images