Hardware consistency screening method, device, equipment and medium

Abstract

The application relates to the computer technical field and discloses a hardware consistency screening method, device, equipment and medium, which comprises the following steps: in a primary sub-cycle, fixing the phase of a data selection signal in a first double-rate synchronous dynamic random access memory (DDR); in each cycle round, selecting a delay value corresponding to each cycle round from a plurality of pre-configured delay values for a delay phase of a first data bit in the first DDR; sequentially starting and executing a continuous write command to obtain a write data code stream; after obtaining the write data code stream each time, starting and executing a continuous read command to obtain a read data code stream; then determining a minimum delay value and a maximum delay value; and then sequentially determining a first candidate delay value and a target delay value corresponding to each data bit of each DDR in the plurality of DDRs; and statistically analyzing the target delay value to determine a screening threshold. The method can improve the accuracy and reliability of data.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to hardware consistency screening methods, apparatus, devices, and media. Background Technology

[0002] Double Data Rate (DDR) synchronous dynamic random access memory has become an indispensable component in modern circuit design due to its advantages such as high access speed, small size, and relatively low price. DDR is further divided into conventional DDR, Low Power Double Data Rate (LPDDR), and Graphics Double Data Rate (GDDR).

[0003] Data in DDR is transmitted via dual-edge transmission. To ensure object-to-object operation between the source synchronization clock and the data signal at the receiving end, this can be achieved by setting the DQS delay parameter. While the method for obtaining the DQS delay parameter is simple and fast, it also has certain drawbacks. For example, for the same PCB board, training results may differ after multiple power-ups. A large delay step size can easily lead to significant discrepancies between multiple acquired delay values, which can significantly impact data readability regardless of the chosen delay value. Furthermore, when hardware consistency issues are prominent, delay parameter differences can be substantial. For instance, Application-Specific Integrated Circuits (ASICs) have long design iteration cycles, high development costs, and are complex electronic devices. Manufacturing them presents challenges, objectively leading to production consistency issues. In practical applications, these consistency problems can cause DDR instability. Summary of the Invention

[0004] In view of this, the present invention provides a hardware consistency screening method, apparatus, device and medium to solve the problem that the inability to accurately assess device consistency, and thus the inability to screen out devices that meet the conditions, may lead to unstable operation of DDR.

[0005] In a first aspect, the present invention provides a hardware conformance screening method, the method comprising:

[0006] Within the first-level sub-loop, the phase of the data strobe signal in the first DDR is fixed. In each loop, the delay phase of the first data bit in the first DDR is selected from a plurality of pre-configured delay values, and the delay value corresponding to each loop is selected. The continuous write command is started and executed sequentially to obtain the write data bit stream. After each acquisition of the write data bit stream, the continuous read command is started and executed to obtain the read data bit stream.

[0007] Based on the write data stream and read data stream obtained in one or more cyclic rounds, determine the minimum latency value corresponding to the first data bit; and after determining the minimum latency value, determine the maximum latency value corresponding to the first data bit based on the write data stream and read data stream obtained in one or more cyclic rounds; wherein, the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR;

[0008] Based on the minimum and maximum delay values, determine the first candidate delay value corresponding to the first data bit, and the current first-level sub-loop ends the operation;

[0009] After continuously executing the same number of first-level sub-loops as the number of data bits included in the first DDR, and obtaining the first candidate delay value corresponding to each data bit in the first DDR, the current second-level sub-loop is determined to end. The second-level sub-loop includes multiple first-level sub-loops.

[0010] After executing multiple secondary sub-loop operations, obtain multiple candidate delay values ​​corresponding to each data bit included in the first DDR;

[0011] Based on the multiple candidate delay values ​​corresponding to each data bit of the first DDR, the target delay value corresponding to each data bit of the first DDR is selected respectively. The current three-level sub-loop ends the operation. The current three-level sub-loop is used to obtain the target delay value corresponding to each data bit of the first DDR.

[0012] After executing multiple three-level sub-loop operations, obtain the target latency value corresponding to each data bit of each DDR in the multiple DDRs;

[0013] Statistical analysis is performed on the target latency values ​​corresponding to each data bit of each DDR in multiple DDRs to determine the screening threshold, which is used to screen out hardware devices that meet hardware consistency requirements.

[0014] The hardware consistency screening method provided by this invention has the following advantages:

[0015] By fixing the phase of the data strobe signal and selecting different delay values ​​in each loop, write and read data streams are obtained. Then, the minimum and maximum delay values ​​are determined based on these data streams. Next, the first candidate delay value is determined based on the minimum and maximum delay values, and the first candidate delay value for each data bit is obtained after the first-level sub-loop. In the second-level sub-loop, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-loop, the target delay value for each data bit is selected based on the multiple candidate delay values, and statistical analysis is performed on the target delay values ​​of each data bit in each DDR across multiple DDRs to determine the screening threshold. By precisely adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, improving data accuracy and reliability. Determining the optimal delay value for each data bit makes data transmission more efficient, thereby improving the overall system performance. By statistically analyzing the target delay values ​​of each data bit in multiple DDRs to determine the screening threshold, hardware devices that meet hardware consistency requirements can be quickly screened, eliminating hardware consistency risks early on and improving product quality and stability. This solution can adapt to different DDR types and hardware configurations, exhibiting strong versatility and scalability. Furthermore, ensuring the stability and reliability of data transmission reduces system failures and performance degradation caused by hardware inconsistencies.

[0016] In one optional implementation, the minimum delay value corresponding to the first data bit is determined based on the write data bitstream and read data bitstream acquired in one or more cyclic rounds, specifically including:

[0017] Compare the write data stream and read data stream obtained in each cycle.

[0018] When it is first determined that the write data stream and the read data stream generated in the first loop are the same, the delay value corresponding to the first loop is determined to be the minimum delay value corresponding to the first data bit, wherein the first loop is any loop within the first-level sub-loop.

[0019] Specifically, by comparing the write and read data streams acquired in each loop, the loop in which the write and read data streams first appear to be identical can be accurately identified. This ensures that the determined minimum latency value corresponds to the actual minimum value of the first data bit, improving the accuracy of latency setting. This method is applicable to any loop within a first-level sub-loop, offering high flexibility. Regardless of the loop in which the write and read data streams first appear identical, the latency value corresponding to that loop can be determined as the minimum latency value. This allows the method to adapt to different data transmission conditions and system configurations. Determining the minimum latency value helps optimize system performance. By setting an appropriate latency value, latency and jitter in data transmission can be reduced, improving data accuracy and reliability. Determining the minimum latency value helps the system minimize latency while meeting performance requirements. This method can be applied to multiple data bits or other similar scenarios. By performing similar loops and comparisons for each data bit, the minimum latency value for each data bit can be determined, thereby achieving latency optimization for the entire system. Because the method considers the actual data transmission conditions in each loop, it can adapt to changes in system load, data transmission rate, and other factors. If system conditions change, re-executing the loop rounds and comparisons can update the minimum latency value to maintain optimal system performance.

[0020] In one optional implementation, after determining the minimum delay value, the maximum delay value corresponding to the first data bit is determined based on the write data bitstream and read data bitstream acquired in one or more cyclic rounds, specifically including:

[0021] After determining the minimum delay value, continue to execute continuous write commands sequentially to obtain the write data stream, and after each acquisition of the write data stream, start and execute continuous read commands to obtain the read data stream;

[0022] After obtaining the write data stream and read data stream in the second loop, the write data stream and read data stream obtained in the second loop will be compared. The second loop is any loop after obtaining the minimum delay value in the first-level sub-loop.

[0023] When the write data stream and read data stream obtained in the second cycle are different, the delay value corresponding to the second cycle is determined to be the maximum delay value corresponding to the first data bit.

[0024] Specifically, by continuing to perform loops after determining the minimum latency value and comparing the write and read data streams in each loop, the loop in which the write and read data streams first differ can be accurately identified. Ensuring that the determined maximum latency value is the actual maximum value corresponding to the first data bit improves the accuracy of latency setting. This method is applicable to any loop within a first-level sub-loop, offering high flexibility. Regardless of the loop in which the write and read data streams first differ, the latency value corresponding to that loop can be determined as the maximum latency value. This allows the method to adapt to different data transmission conditions and system configurations. Determining the maximum latency value helps optimize system performance. By setting an appropriate latency value, data transmission efficiency can be maximized while maintaining data accuracy and reliability. Determining the maximum latency value helps the system minimize latency without impacting performance. This method can be applied to multiple data bits or other similar scenarios. By performing similar loops and comparisons for each data bit, the maximum latency value for each data bit can be determined, thereby achieving latency optimization for the entire system. Because the method considers the actual data transmission conditions in each loop, it can adapt to changes in system load, data transmission rate, and other factors. If system conditions change, re-executing the loop rounds and comparisons can update the maximum latency value to maintain optimal system performance.

[0025] In one optional implementation, determining a first candidate delay value corresponding to the first data bit based on the minimum delay value and the maximum delay value specifically includes:

[0026] The average value is determined based on the minimum and maximum delay values, and used as the first candidate delay value corresponding to the first data bit.

[0027] Specifically, by taking the average of the minimum and maximum latency values ​​as the first candidate latency value, a balance can be struck between latency and performance. This avoids excessive latency that could degrade system performance while ensuring a certain level of latency tolerance. Using an average value reduces the impact of extreme values ​​on latency settings. Considering only the minimum or maximum latency values ​​may lead to unstable latency settings due to abnormal conditions or transient fluctuations. The average value provides a more stable latency reference, helping to maintain good performance under different system environments and workloads.

[0028] In one optional implementation, a target delay value corresponding to each data bit of the first DDR is selected based on multiple candidate delay values ​​corresponding to each data bit of the first DDR, specifically including:

[0029] Count the number of occurrences of each candidate delay value among the multiple candidate delay values ​​corresponding to each data bit;

[0030] The candidate delay value that appears more than or equal to a preset threshold among the multiple candidate delay values ​​corresponding to each data bit is selected as the target delay value corresponding to the data bit.

[0031] Specifically, by counting the occurrences of candidate delay values ​​for each data bit and selecting those with occurrences greater than or equal to a preset threshold as the target delay value, the reliability of delay settings can be improved. Candidate delay values ​​with higher occurrence frequencies generally better represent the actual delay requirements of that data bit, thus reducing the impact of outliers or noise on delay settings. This helps ensure the stability of delay settings. By selecting candidate delay values ​​with higher occurrence frequencies, the excessive impact of individual abnormal or unstable delay values ​​on system performance can be avoided, improving the stability and consistency of the system under different operating conditions. This method has a certain degree of adaptability to different data transmission scenarios. Even in different test or operating environments, candidate delay values ​​with higher occurrence frequencies can still reflect the common delay requirements of data bits. This helps the system maintain good performance under different conditions. It ensures that the system can transmit data with optimal delay settings in most cases, improving data accuracy and reliability, thereby enhancing overall system performance.

[0032] In one optional implementation, the method further includes: storing a first candidate delay value into a preset storage device;

[0033] In addition, the target latency value corresponding to each data bit of the first DDR is stored in a preset storage device.

[0034] In one optional implementation, in every two adjacent cycle rounds, the delay value corresponding to the later cycle round is the sum of the delay value corresponding to the previous cycle round and the preset delay step size;

[0035] Within the first-level sub-loop, the phase of the data strobe signal in the first DDR is fixed. Before selecting the delay value corresponding to each loop cycle from a pre-configured plurality of delay values ​​for the delay phase of the first data bit in the first DDR, the method further includes:

[0036] Obtain the influencing factors corresponding to the delay value of the current loop round. The influencing factors include any one of the following: data transmission rate, data type, and system load. The data type is determined based on the data's impact, real-time performance, and sensitivity.

[0037] Based on the influencing factors, match the calculation formula corresponding to the preset delay step size;

[0038] Based on the calculation formula, determine the preset delay step size within the first-level sub-loop;

[0039] The calculation formula corresponding to the preset delay step size includes the following:

[0040] Preset delay step size = Minimum delay step size + (Data transmission rate / Maximum transmission rate) (Maximum delay step size - Minimum delay step size);

[0041] or,

[0042] Preset delay step size = standard delay step size Data type weights;

[0043] Among them, the standard delay step size is the pre-configured baseline delay step size, the preset delay step size applies to all first-level sub-loops, and the minimum delay step size, maximum transmission rate, maximum delay step size, standard delay step size, and data type weight corresponding to the data type are pre-configured data.

[0044] Specifically, by considering factors such as data transmission rate and data type, the preset delay step size can be dynamically adjusted according to actual conditions. This allows the delay setting to better adapt to different system operating conditions and data transmission requirements, improving the system's adaptability and flexibility. Determining the preset delay step size based on influencing factors can optimize system performance. For example, at high data transmission rates, appropriately increasing the delay step size can avoid data conflicts and errors; for different types of data, the delay step size can be adjusted according to their importance and real-time requirements to ensure data accuracy and timeliness. By using the same calculation formula and standard delay step size, a consistent preset delay step size can be ensured in all first-level sub-loops. This helps maintain the stability and consistency of the system at different stages and in different operations.

[0045] In a second aspect, the present invention provides a hardware consistency screening device, the device comprising:

[0046] The selection module is used to fix the phase of the data strobe signal in the first DDR within the first sub-loop, and select the delay value corresponding to each loop from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each loop.

[0047] The startup module is used to sequentially start and execute continuous write commands to obtain the write data stream; and after each acquisition of the write data stream, to start and execute continuous read commands to obtain the read data stream.

[0048] The processing module is used to determine the minimum latency value corresponding to the first data bit based on the write data stream and read data stream obtained in one or more loop rounds; and after determining the minimum latency value, to determine the maximum latency value corresponding to the first data bit based on the write data stream and read data stream obtained in one or more loop rounds; wherein, the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR; based on the minimum latency value and the maximum latency value, a first candidate latency value corresponding to the first data bit is determined, and the current first-level sub-loop ends the operation; when the number of first-level sub-loops is the same as the number of a plurality of data bits included in the first DDR is executed consecutively, and each of the first DDRs is obtained... After determining the first candidate delay value corresponding to each data bit, the current second-level sub-loop ends. Each second-level sub-loop includes multiple first-level sub-loops. After executing multiple second-level sub-loops, multiple candidate delay values ​​corresponding to each data bit of the first DDR are obtained. Based on these candidate delay values, a target delay value corresponding to each data bit of the first DDR is selected, and the current third-level sub-loop ends. This third-level sub-loop is used to obtain the target delay value corresponding to each data bit of the first DDR. After executing multiple third-level sub-loops, the target delay value corresponding to each data bit of each DDR in the multiple DDRs is obtained.

[0049] The analysis module is used to perform statistical analysis on the target latency value corresponding to each data bit of each DDR in multiple DDRs, and determine the screening threshold. The screening threshold is used to filter out hardware devices that meet the hardware consistency requirements.

[0050] The hardware consistency screening device provided by this invention has the following advantages:

[0051] By fixing the phase of the data strobe signal and selecting different delay values ​​in each loop, write and read data streams are obtained. Then, the minimum and maximum delay values ​​are determined based on these data streams. Next, the first candidate delay value is determined based on the minimum and maximum delay values, and the first candidate delay value for each data bit is obtained after the first-level sub-loop. In the second-level sub-loop, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-loop, the target delay value for each data bit is selected based on the multiple candidate delay values, and statistical analysis is performed on the target delay values ​​of each data bit in each DDR across multiple DDRs to determine the screening threshold. By precisely adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, improving data accuracy and reliability. Determining the optimal delay value for each data bit makes data transmission more efficient, thereby improving the overall system performance. By statistically analyzing the target delay values ​​of each data bit in multiple DDRs to determine the screening threshold, hardware devices that meet hardware consistency requirements can be quickly screened, eliminating hardware consistency risks early on and improving product quality and stability. This solution can adapt to different DDR types and hardware configurations, exhibiting strong versatility and scalability. Furthermore, ensuring the stability and reliability of data transmission reduces system failures and performance degradation caused by hardware inconsistencies.

[0052] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the hardware conformance screening method of the first aspect or any corresponding embodiment described above.

[0053] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the hardware conformance screening method of the first aspect or any corresponding embodiment thereof.

[0054] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the hardware conformance screening method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0055] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0056] Figure 1 This is a flowchart illustrating a hardware consistency screening method provided in an embodiment of the present invention;

[0057] Figure 2 This is a flowchart illustrating another hardware consistency screening method provided in an embodiment of the present invention;

[0058] Figure 3 This is a flowchart illustrating another hardware consistency screening method provided in an embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of the overall architecture of the hardware consistency screening method provided by the present invention;

[0060] Figure 5 This is a schematic diagram of an exemplary part of the hardware consistency screening method provided by the present invention;

[0061] Figure 6 This is a structural block diagram of a hardware consistency screening device provided in an embodiment of the present invention;

[0062] Figure 7 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] DDR, with its advantages of fast access speed, small size, and relatively low price, has become an indispensable component in modern circuit design. DDR is further divided into conventional DDR, Low Power Double Data Rate SDRAM (LPDDR), and Graphics Double Data Rate DRAM (GDDR).

[0065] Data in DDR is transmitted on both edges. The source synchronous clock DQS is used to sample the data signal DQ. When reading from DDR, the DDR chip outputs DQS and aligns the edges with the DQ. The DDR controller or PHY, which is the data receiving end, performs the operation of aligning the DQS edge with the center of DQ.

[0066] Specifically, in DDR, data is transmitted using a two-edge transmission method. This means that data can be transmitted on both the rising and falling edges of the clock signal, thereby increasing the data transmission rate.

[0067] To ensure accurate data sampling, a source-synchronous clock, DQS (Data Strobe), is used. DQS is a clock signal synchronized with the data signal DQ, used to indicate the valid edge of the data. During DDR reads, the DDR chip (memory chip) outputs the DQS signal, and the DQS edge is aligned with the DQ edge.

[0068] However, the DDR controller or PHY (physical layer) acting as the data receiver needs to align the DQS edge with the DQ center. This is because, when receiving data, to improve sampling accuracy, it is generally desirable to sample at the center of the data signal, rather than at the edge. By aligning the DQS edge with the DQ center, changes in the data can be captured more effectively, reducing sampling errors.

[0069] Among related technologies, methods for obtaining DQS latency parameters are simple and fast to implement, but they also have certain drawbacks. For the same PCB board, training results may differ after multiple power-ups; a large latency step size can easily lead to significant differences between multiple latency values, and regardless of the selected latency value, the impact on correct data reading will be substantial. Furthermore, when hardware consistency issues are prominent, latency parameter differences can be significant. For example, ASICs, with their long design iteration cycles and high development costs, are complex electronic devices, presenting certain manufacturing challenges and objectively leading to production consistency issues. In practical applications, consistency problems can cause DDR instability; therefore, early detection of consistency risks is of practical significance.

[0070] To address the aforementioned issues, this invention provides a hardware conformance screening embodiment. It should be noted that the steps shown in the flowcharts in the accompanying drawings can be executed in a computer system (computer device) including a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0071] This embodiment provides a hardware consistency screening method, which can be used in the aforementioned terminal devices, such as mobile phones and tablet computers. Figure 1 This is a flowchart illustrating a hardware consistency screening method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the process includes the following steps:

[0072] Step S101: Within the first-level sub-loop, fix the phase of the data strobe signal in the first DDR. In each loop, select the delay value corresponding to each loop from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR, and sequentially start and execute the continuous write command to obtain the write data bit stream.

[0073] Step S102: After each acquisition of the write data stream, start and execute the continuous read command to acquire the read data stream.

[0074] Specifically, during the process of obtaining the preset threshold in the entire training process, there are multiple DDRs. The first DDR is any one of the multiple DDRs, and each DDR includes multiple data bits. Therefore, the first data bit is any one of the multiple data bits included in the first DDR.

[0075] In this embodiment, the method of obtaining the maximum and minimum latency values ​​is illustrated using the first data bit in the first DDR as an example. In reality, similar steps are required for each data bit in all DDRs to obtain the maximum and minimum latency values, and then the target latency value corresponding to that data bit is determined based on these values. The specific implementation process will be described in detail below. First, within the first-level sub-loop, the phase of the data strobe signal (DQS) in the first DDR is fixed. Then, in each loop iteration, the latency phase of the first data bit (i.e., the first data queue, DQ) in the first DDR is selected from a pre-configured set of latency values, corresponding to the latency value of each loop iteration. Continuous write commands are then sequentially initiated and executed to obtain the write data stream.

[0076] In this loop, the first data bit can start with an initial delay value from among multiple pre-configured delay values, then initiate a continuous write command to obtain the write data stream. Afterwards, a continuous read command is executed to obtain the read data stream. Subsequently, the delay value needs to be changed after each loop iteration. In an optional example, in every two adjacent loop iterations, the delay value for the later loop iteration can be configured as the sum of the delay value for the previous loop iteration and a preset delay step size.

[0077] Step S103: Determine the minimum delay value corresponding to the first data bit based on the write data bitstream and read data bitstream obtained in one or more cyclic rounds.

[0078] Specifically, after obtaining the write data stream and read data stream in each loop, it is necessary to determine whether the current delay value is the minimum delay value corresponding to the first data bit based on the write data stream and read data stream.

[0079] In one optional example, the write data stream and the read data stream can be compared to determine whether the current loop is the target loop. If it is the target loop, the delay value corresponding to the target loop can be determined to be the minimum delay value corresponding to the first data.

[0080] Step S104: After determining the minimum delay value, determine the maximum delay value corresponding to the first data bit based on the write data bitstream and read data bitstream obtained in one or more cyclic rounds.

[0081] Specifically, similar to determining the minimum latency value, after determining the minimum latency value, the write data stream and read data stream acquired in one or more loops can be compared, and the latency value corresponding to the different loops of the write data stream and read data stream can be selected as the maximum latency value.

[0082] Step S105: Determine the first candidate delay value corresponding to the first data bit based on the minimum delay value and the maximum delay value, and the current first-level sub-loop ends the operation.

[0083] Specifically, to avoid the instability of DDR operation in subsequent work due to the selected delay value being too large or too small, in order to select the minimum or maximum delay value, the solution in this application also needs to determine the first candidate delay value corresponding to the first data bit based on the minimum and maximum delay values.

[0084] Step S106: After continuously executing the first-level sub-loop with the same number of data bits as the first DDR, and obtaining the first candidate delay value corresponding to each data bit in the first DDR, determine that the current second-level sub-loop ends.

[0085] Specifically, as described above, the first DDR includes multiple data bits, and each data bit needs to undergo the aforementioned operation within a first-level sub-loop to obtain its corresponding candidate latency value before the operation ends. This means the current second-level sub-loop ends its operation. The second-level sub-loop includes multiple first-level sub-loops, and the number of first-level sub-loops in the second-level sub-loop is the same as the number of data bits in the first DDR.

[0086] Step S107: After executing multiple secondary sub-loop operations, obtain multiple candidate delay values ​​corresponding to each data bit included in the first DDR.

[0087] Specifically, to ensure the accuracy of the subsequently determined preset threshold, after executing any of the aforementioned secondary sub-loops to obtain candidate delay values ​​corresponding to each data bit included in the first DDR, the method may further include repeating the aforementioned secondary sub-loop operation. This process continues until multiple secondary sub-loop operations are executed, at which point multiple candidate delay values ​​corresponding to each data bit included in the first DDR can be obtained.

[0088] Step S108: Based on the multiple candidate delay values ​​corresponding to each data bit of the first DDR, select the target delay value corresponding to each data bit of the first DDR, and the current three-level sub-loop operation ends.

[0089] Specifically, after multiple candidate delay values ​​have been obtained for each data bit in the first DDR, one or more candidate delay values ​​can be selected from the multiple candidate delay values ​​as the target delay value corresponding to each data bit.

[0090] Step S109: After executing multiple three-level sub-loop operations, obtain the target delay value corresponding to each data bit of each DDR in the multiple DDRs.

[0091] Specifically, as described above, the first DDR is actually any one of multiple DDRs. Therefore, steps 101 to 108 are exemplary operations using the first DDR as an example. In reality, multiple DDRs all need to perform similar operations as steps 101 to 108. Assuming that steps 101 to 108 are understood as a three-level sub-loop, then multiple three-level sub-loops, equal to the number of DDRs, need to be executed in the multiple DDRs. This allows us to obtain the target latency value corresponding to each data bit of each DDR in the multiple DDRs.

[0092] Step S110: Perform statistical analysis on the target latency values ​​corresponding to each data bit of each DDR in the multiple DDRs to determine the screening threshold.

[0093] The screening threshold is used to filter out hardware devices that meet hardware consistency requirements.

[0094] Specifically, when performing statistical analysis on the target latency values ​​corresponding to each data bit of each DDR in multiple DDRs, the Three Sigma Rule can be used. The final analysis result is then used as the selection threshold. The specific process of using the Three Sigma Rule for statistical analysis will not be elaborated upon here.

[0095] Subsequently, during the application process, a target latency value of a DDR to be confirmed can be obtained through steps similar to steps 101 to 109. Then, the target latency value is compared with the screening threshold to determine whether the hardware device to which the DDR belongs meets the hardware consistency requirements.

[0096] The hardware consistency screening method provided in this embodiment obtains write and read data streams by fixing the phase of the data strobe signal and selecting different delay values ​​in each loop. Then, the minimum and maximum delay values ​​are determined based on these data streams. Next, a first candidate delay value is determined based on the minimum and maximum delay values, and the first candidate delay value for each data bit is obtained after the first-level sub-loop. In the second-level sub-loop, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-loop, the target delay value for each data bit is selected based on the multiple candidate delay values, and statistical analysis is performed on the target delay values ​​of each data bit in each DDR across multiple DDRs to determine the screening threshold. By precisely adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, improving data accuracy and reliability. Determining the optimal delay value for each data bit makes data transmission more efficient, thereby improving the performance of the entire system. By statistically analyzing the target delay values ​​of each data bit in multiple DDRs to determine the screening threshold, hardware devices that meet hardware consistency requirements can be quickly screened, eliminating hardware consistency risks early and improving product quality and stability. This solution can adapt to different DDR types and hardware configurations, exhibiting strong versatility and scalability. Furthermore, ensuring the stability and reliability of data transmission reduces system failures and performance degradation caused by hardware inconsistencies.

[0097] This embodiment provides a hardware consistency screening method, which can be used in the aforementioned mobile terminals, such as mobile phones and tablet computers. Figure 2 This is a flowchart illustrating the hardware consistency screening method provided in an embodiment of the present invention, as shown below. Figure 2 As shown, based on the aforementioned embodiments, determining the minimum delay value corresponding to the first data bit based on the write data bitstream and read data bitstream obtained in one or more cyclic rounds may include the following steps:

[0098] Step S201: Compare the write data stream and read data stream obtained in each cycle.

[0099] Step S202: When it is first determined that the write data stream and read data stream generated in the first cycle are the same, the delay value corresponding to the first cycle is determined to be the minimum delay value corresponding to the first data bit.

[0100] Specifically, if the generated write data stream and read data stream are the same in the first loop, then the delay value corresponding to the first loop can be determined to be the minimum delay value corresponding to the first data bit. This first loop can be any loop within a first-level sub-loop.

[0101] This invention provides a hardware consistency screening method that accurately identifies the cycle in which the write and read data streams first appear identical by comparing them in each cycle. This ensures that the determined minimum latency value corresponds to the actual minimum value of the first data bit, improving the accuracy of latency setting. This method is applicable to any cycle within a first-level sub-cycle, offering high flexibility. Regardless of the cycle in which the write and read data streams first appear identical, the latency value corresponding to that cycle can be determined as the minimum latency value. This allows the method to adapt to different data transmission conditions and system configurations. Determining the minimum latency value helps optimize system performance. By setting an appropriate latency value, latency and jitter in data transmission can be reduced, improving data accuracy and reliability. Determining the minimum latency value helps the system minimize latency while meeting performance requirements. This method can be applied to multiple data bits or other similar scenarios. By performing similar cycle rounds and comparisons for each data bit, the minimum latency value for each data bit can be determined, thereby optimizing the latency of the entire system. Because the method considers the actual data transmission situation in each cycle, it can adapt to changes in system load, data transmission rate, and other factors. If system conditions change, re-executing the loop rounds and comparisons can update the minimum latency value to maintain optimal system performance.

[0102] This embodiment provides a hardware consistency screening method, which can be used in the aforementioned mobile terminals, such as mobile phones and tablet computers. Figure 3 This is a flowchart illustrating a hardware consistency screening method provided in an embodiment of the present invention, as shown below. Figure 3 As shown, after determining the minimum delay value, the maximum delay value corresponding to the first data bit is determined based on the write data bitstream and read data bitstream obtained in one or more cyclic rounds. This may include the following steps:

[0103] Step S301: After determining the minimum delay value, continue to execute the continuous write command sequentially to obtain the write data bitstream, and after each acquisition of the write data bitstream, start and execute the continuous read command to obtain the read data bitstream.

[0104] Step S302: After obtaining the write data stream and read data stream in the second loop, compare the write data stream and read data stream obtained in the second loop.

[0105] Step S303: When the write data stream and read data stream obtained in the second cycle are different, determine the delay value corresponding to the second cycle as the maximum delay value corresponding to the first data bit.

[0106] Specifically, after determining the minimum latency value, the latency value is further increased, and then the test enters the next loop round to obtain the write data stream and read data stream. This continues until the write data stream and read data stream change from being the same in the previous loop round to being different in the current loop round. At this point, the latency value corresponding to the current loop round, i.e., the second loop round, is determined as the maximum latency value. The second loop round is any loop round after obtaining the minimum latency value within the first-level sub-loop.

[0107] By continuing to iterate through rounds after determining the minimum latency value and comparing the write and read data streams in each round, the round in which the write and read data streams first differ can be accurately identified. Ensuring that the determined maximum latency value is the actual maximum value corresponding to the first data bit improves the accuracy of latency setting. This method is applicable to any round within a first-level sub-loop, offering high flexibility. Regardless of the round in which the write and read data streams first differ, the latency value corresponding to that round can be determined as the maximum latency value. This allows the method to adapt to different data transmission conditions and system configurations. Determining the maximum latency value helps optimize system performance. By setting an appropriate latency value, data transmission efficiency can be maximized while maintaining data accuracy and reliability. Determining the maximum latency value helps the system minimize latency without impacting performance. This method can be applied to multiple data bits or other similar scenarios. By performing similar rounds and comparisons for each data bit, the maximum latency value for each data bit can be determined, thereby achieving latency optimization for the entire system. Because the method considers the actual data transmission conditions in each round, it can adapt to changes in system load, data transmission rate, and other factors. If system conditions change, re-executing the loop rounds and comparisons can update the maximum latency value to maintain optimal system performance.

[0108] In an optional example, a first candidate delay value corresponding to the first data bit is determined based on the minimum delay value and the maximum delay value, specifically including:

[0109] The average value is determined based on the minimum and maximum delay values, and used as the first candidate delay value corresponding to the first data bit.

[0110] Specifically, by taking the average of the minimum and maximum latency values ​​as the first candidate latency value, a balance can be struck between latency and performance. This avoids excessive latency that could degrade system performance while ensuring a certain level of latency tolerance. Using an average value reduces the impact of extreme values ​​on latency settings. Considering only the minimum or maximum latency values ​​may lead to unstable latency settings due to abnormal conditions or transient fluctuations. The average value provides a more stable latency reference, helping to maintain good performance under different system environments and workloads.

[0111] In an optional example, based on multiple candidate delay values ​​corresponding to each data bit of the first DDR, a target delay value corresponding to each data bit of the first DDR is selected, specifically including the following method steps:

[0112] Step a1: Count the number of occurrences of each candidate delay value among the multiple candidate delay values ​​corresponding to each data bit.

[0113] Step a2: Select the candidate delay value that appears more than or equal to a preset threshold number of times among the multiple candidate delay values ​​corresponding to each data bit as the target delay value corresponding to the data bit.

[0114] Specifically, by counting the number of times the candidate delay value corresponding to each data bit appears, and selecting the candidate delay value whose appearance frequency is greater than or equal to a preset threshold as the target delay value, the reliability of the delay setting can be improved.

[0115] Among these, candidate delay values ​​that appear more frequently are generally more representative of the actual delay requirement for that data bit. Therefore, selecting candidate delay values ​​with a frequency greater than or equal to a preset threshold as the target delay value can reduce the impact of outliers or noise on the delay setting, thereby helping to ensure the stability of the delay setting.

[0116] The preset number threshold can be determined, for example, based on the total number of secondary sub-loops, such as the value obtained by dividing the total number of secondary sub-loops by 2.

[0117] By selecting candidate delay values ​​that appear most frequently, it is possible to avoid the excessive impact of individual abnormal or unstable delay values ​​on system performance. This improves the stability and consistency of the system under different operating conditions.

[0118] Moreover, this method is adaptable to different data transmission scenarios. Even in different test or operational environments, the candidate latency values ​​that appear most frequently still reflect the common latency requirements of data bits. This helps the system maintain good performance under different conditions. It ensures that the system can transmit data with optimal latency settings in most situations, improving data accuracy and reliability, thereby enhancing overall system performance.

[0119] In an optional example, the method may also include:

[0120] Store the first candidate delay value to a preset storage device;

[0121] In addition, the target latency value corresponding to each data bit of the first DDR is stored in a preset storage device.

[0122] In an optional example, in every two adjacent loop iterations, the delay value corresponding to the later loop iteration is the sum of the delay value corresponding to the previous loop iteration and a preset delay step size; within a first-level sub-loop, the phase of the data strobe signal in the first DDR is fixed, and before selecting the delay value corresponding to each loop iteration from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR, the method further includes the following method steps:

[0123] Step b1: Obtain the influencing factors corresponding to the delay value of the current loop cycle. The influencing factors include any one of the following: data transmission rate, data type, and system load.

[0124] The data type is determined based on the data's impact, real-time nature, and sensitivity.

[0125] Specifically, besides the write and read data streams, other factors can also affect the latency value. For example, the preset latency step size. This preset latency step size can be determined not only based on a large amount of experimental data, but also by considering factors such as data transmission rate, data type, and system load.

[0126] Step b2: Match the calculation formula corresponding to the preset delay step size based on the influencing factors.

[0127] Step b3: Determine the preset delay step size within the first-level sub-loop according to the calculation formula.

[0128] Specifically, data transfer rate can be obtained by monitoring the actual DDR data transfer rate and then using hardware counters or software measurement tools. Data type can be determined based on factors such as data impact, real-time performance, and sensitivity. For example, critical data may have higher priority and lower latency requirements, while non-critical data can tolerate higher latency. Assessing system load can include evaluations based on CPU utilization, memory usage, and network bandwidth.

[0129] When matching the calculation formula corresponding to the preset delay step size based on the influencing factors, you can choose the calculation formula that matches the influencing factors.

[0130] The calculation formula corresponding to the preset delay step size includes the following:

[0131] Preset delay step size = Minimum delay step size + (Data transmission rate / Maximum transmission rate) (Maximum delay step size - Minimum delay step size) (Formula 1);

[0132] or,

[0133] Preset delay step size = standard delay step size Data type weights (Formula 2).

[0134] The standard delay step size is a pre-configured baseline delay step size, and the preset delay step size applies to all first-level sub-loops.

[0135] Then, by substituting the specific values ​​into the above formula, the preset delay step size can be directly obtained. The minimum delay step size, maximum transmission rate, maximum delay step size, standard delay step size, and data type weight corresponding to the data type are pre-configured data.

[0136] Formula 1 is a formula for determining the preset delay step based on the data transmission rate, and its meaning includes:

[0137] If the data transfer rate is high, a smaller preset delay step can be selected to finely adjust the delay value and avoid data loss or errors. If the transfer rate is low, a larger preset delay step can be selected to find a suitable delay value more quickly.

[0138] Formula 2 is a formula for determining the preset delay step size based on data type, and its meaning includes:

[0139] For critical data types (primary data types), a smaller preset delay step can be set to ensure timeliness and accuracy. For non-critical data types (secondary data types), a larger preset delay step can be used to balance system performance and resource utilization.

[0140] By considering factors such as data transmission rate and data type, the preset delay step size can be dynamically adjusted according to actual conditions. This allows the delay setting to better adapt to different system operating conditions and data transmission requirements, improving the system's adaptability and flexibility. Determining the preset delay step size based on influencing factors can optimize system performance. For example, at high data transmission rates, appropriately increasing the delay step size can avoid data conflicts and errors; for different types of data, the delay step size can be adjusted according to their importance and real-time requirements to ensure data accuracy and timeliness. By using the same calculation formula and standard delay step size, a consistent preset delay step size can be ensured in all first-level sub-loops. This helps maintain the stability and consistency of the system across different stages and operations.

[0141] In an optional example, besides determining the preset delay step size using the methods described above, the method can also determine the preset delay step size using the following method. See the following formula for details:

[0142] Preset delay step size = load adjustment factor (System load / Maximum load) Standard delay step size (Formula 3)

[0143] Formula 3 is a formula for determining the preset delay step size based on system load, and its meaning includes:

[0144] When the system load is high, a smaller preset delay step can be selected to reduce the consumption of system resources.

[0145] Alternatively, when the load is low, a larger preset delay step can be selected to improve the efficiency of delay adjustment.

[0146] Among them, the load adjustment factor and maximum load are pre-configured data.

[0147] By considering the impact of system load in the above manner, insufficient latency issues under high load conditions can be avoided, thereby improving system reliability. Adjusting the latency step size according to load conditions allows for better handling of situations where system resources are strained.

[0148] The above method allows for easy expansion and adaptation to new influencing factors or needs. If other factors need to be considered, corresponding calculation formulas can be added or the parameters of existing formulas can be adjusted to meet the continuous development and changes of the system.

[0149] In a specific example, the execution of the aforementioned method steps can be seen in the following example:

[0150] The first step is to fix the DQS phase for DQ0 (the first data bit of the first DDR) and confirm the adjustable range of the phase. The DQ0 delay phase starts from the minimum delay value and continuous write and read commands are started. After the write and read commands are completed, the DQ0 code stream of the read data is compared with the DQ0 code stream of the write data. If they are the same, the minimum delay value is determined. If they are different, the DQ0 delay phase is gradually increased. When the comparison result is that the DQ0 code stream of the read data changes from being different in the previous cycle to being the same in the current cycle, the delay value of the current cycle is determined to be the minimum available delay value of DQ0.

[0151] Then continue to increase the DQ0 phase delay until the comparison between the read data stream and the write data stream changes from the same to different. The DQ0 delay at this point is recorded as the maximum available delay value of DQ0.

[0152] The second step is to take the average of the available minimum delay value and the available maximum delay value as the phase delay value of DQ0 and write it into the RAM cache at address A00.

[0153] The third step is to repeat the first and second steps until the delayed training of DQ1, ... DQn is completed, and write them to the RAM cache at addresses A01, ... A0n respectively.

[0154] The fourth step is to repeat the first, second, and third steps m-1 times to obtain the training results of DQ0, DQ1, ..., DQn M times, and write the results to the RAM cache at addresses A10, A11, ..., A1n, ..., A(m-1)0, A(m-1)1, ..., A(m-1)n.

[0155] Fifth step: Read the RAM cache, count the training results of DQ0, find the value that appears more than or equal to M / 2 times as the final training result of DQ0, and write it into the RAM cache at address B00;

[0156] Step 6: Repeat step 5 to obtain the final training results of DQ1, ..., DQn in sequence, and write them into the RAM cache at addresses B01, ..., B0n.

[0157] Step 7: Manually modify the phase delays of DQ0, DQ1, ..., DQn to the results of steps 5 and 6;

[0158] Step 8: Export B00, B01, ..., B0n.

[0159] Step 9: Perform steps 1 through 8 on multiple mass-produced boards, export the results sequentially, and perform statistical analysis to obtain the statistical results of the Three Sigma criterion.

[0160] Step 10: Write the three sigma statistical threshold into the mass production board screening and testing software. In production, perform steps 1 to 8 on the remaining boards. If the phase adjustment result exceeds the three sigma criterion, it is considered a gross error. The board is considered to have a hardware consistency problem and is removed for further analysis of specific consistency differences.

[0161] See details Figure 4 As shown, Figure 4 The diagram illustrates the overall architecture of the hardware consistency screening method.

[0162] This includes: a PC connecting to an ASIC via a serial port; the ASIC containing a DDR controller and a PHY; and the program code corresponding to the specific execution flow of the storage hardware consistency screening method within the DDR controller. The DDR controller establishes communication connections with the board via CTRL BUS, ADDRBUS, and DQ BUS buses to verify the stability of the DDR chips, thereby further determining whether the board has gross errors and whether it needs to be rejected.

[0163] In a specific example, see [link to example]. Figure 5 As shown, Figure 5 The diagram illustrates the method flow from steps S001 to S008 in the following text. Steps S009 to S015 are... Figure 5 Based on this, the corresponding method flow is executed, therefore in Figure 5 The specific operational procedures for steps 9 to 15 are not detailed in the document. The overall method flow includes the following implementation steps:

[0164] S001, DQ0 phase adjustment: Determine the leftmost starting point P0 and the rightmost starting point P1 of the phase adjustment based on the adjustable phase range, and confirm the step size of each phase adjustment, denoted as T.

[0165] S002, first set the DQ0 phase to P0 for read and write training, write 8 sets of data continuously, DQ0 is 01010101 in sequence, and then read out 8 sets of data continuously.

[0166] S003, compare the DQ0 of the 8 sets of data read out with the DQ0 of the 8 sets of data written;

[0167] S004, if they are the same, record it as the minimum available delay value Q0; if they are different, increase the phase delay of DQ0 by T each time, and repeat steps S002 and S003 until Q0 is found.

[0168] S005, set the phase delay of DQ0 to Q0+T, and repeat S002 and S003;

[0169] S006, compare the DQ0 of the 8 sets of data read out with the DQ0 of the 8 sets of data written;

[0170] S007, if they are different, do not record the current DQ0 phase delay, and record the previous DQ0 phase delay value as the maximum available delay value Q1; if they are the same, increase the DQ0 phase delay setting by T each time, repeat steps S002 and S003 until they are different, and record the previous DQ0 phase delay value as the maximum available delay value Q1.

[0171] S008, take the average of the available minimum latency value Q0 and the available maximum latency value Q1 as the training result of DQ0 this time, and write it into the RAM cache at address A00.

[0172] S009, repeat S001, ..., S008 until the delayed training of DQ1, ... DQ15 is completed, and write them to the RAM cache at addresses A01, ... A015 respectively;

[0173] S010, execute S001~S009 5 times in a loop to obtain the training results of DQ0, DQ1, ...DQ15 5 times, and write the results to the RAM cache with addresses A10, A11, ...A115, ...A40, A41, ...A415;

[0174] S011, Read the training results of DQ0 5 times, with RAM addresses A00, A10, ..., A40 respectively, and perform statistics to find the results that appear at least 3 times. These results are taken as the final training results of DQ0 and written to the RAM cache at address B00.

[0175] S012, sequentially read and statistically analyze the 5 training results of DQ1, ..., DQ15, respectively, and write the final training results of DQ1, ..., DQ15 into RAM cache, with addresses B01, ..., B0n;

[0176] S013, configure the final training results of DQ0, DQ1, ..., DQ15 as the usage value of DDR phase delay for subsequent DDR read and write;

[0177] S014, export the final training results of DQ0, DQ1, ..., DQ15 to the host computer via serial port;

[0178] S015, execute S001~S014 above on 100 mass-produced boards, export the results in sequence, and perform statistical analysis to obtain the three sigma criterion statistical results of the final training results of DQ0, DQ1, ..., DQ15.

[0179] S016: The statistical results of the three sigma criterion are written into the mass production board test program as a threshold, and S001~S014 are executed on the mass production boards to obtain the final training results of DQ0, DQ1, ..., DQ15 for each board. The statistical results of the three sigma criterion obtained in S015 are used as the screening conditions for mass production boards. For mass production boards whose final training results of DQ0, DQ1, ..., DQ15 exceed the three sigma criterion, they are regarded as problematic boards and are removed to further locate and analyze the cause of the anomaly.

[0180] This embodiment also provides a hardware conformance screening device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0181] This embodiment provides a hardware consistency screening device, such as... Figure 6 The module includes: a selection module 601, a startup module 602, a processing module 603, and an analysis module 604.

[0182] The selection module 601 is used to fix the phase of the data strobe signal in the first double rate synchronous dynamic random access memory (DDR) within the first-level sub-loop, and select the delay value corresponding to each loop from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each loop.

[0183] The startup module 602 is used to sequentially start and execute continuous write commands to obtain write data streams; and after each acquisition of write data streams, to start and execute continuous read commands to obtain read data streams.

[0184] Processing module 603 is configured to determine the minimum latency value corresponding to the first data bit based on the write data stream and read data stream obtained in one or more loop iterations; and after determining the minimum latency value, determine the maximum latency value corresponding to the first data bit based on the write data stream and read data stream obtained in one or more loop iterations; wherein, the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR; based on the minimum latency value and the maximum latency value, a first candidate latency value corresponding to the first data bit is determined, and the current first-level sub-loop ends the operation; when the number of first-level sub-loops is the same as the number of a plurality of data bits included in the first DDR is executed consecutively, and the data in the first DDR is obtained... After determining the first candidate delay value for each data bit, the current second-level sub-loop ends. Each second-level sub-loop includes multiple first-level sub-loops. After executing multiple second-level sub-loops, multiple candidate delay values ​​corresponding to each data bit in the first DDR are obtained. Based on these candidate delay values, the target delay value corresponding to each data bit in the first DDR is selected, and the current third-level sub-loop ends. This third-level sub-loop is used to obtain the target delay value corresponding to each data bit in the first DDR. After executing multiple third-level sub-loops, the target delay value corresponding to each data bit in each of the multiple DDRs is obtained.

[0185] Analysis module 604 is used to perform statistical analysis on the target latency value corresponding to each data bit of each DDR in multiple DDRs, and determine the screening threshold. The screening threshold is used to screen out hardware devices that meet hardware consistency requirements.

[0186] In an optional example, processing module 603 is specifically used to compare the write data bitstream and read data bitstream acquired in each loop round.

[0187] When it is first determined that the write data stream and the read data stream generated in the first loop are the same, the delay value corresponding to the first loop is determined to be the minimum delay value corresponding to the first data bit, wherein the first loop is any loop within the first-level sub-loop.

[0188] In an optional example, the processing module 603 is specifically used to continue sequentially executing continuous write commands to obtain the write data stream after determining the minimum delay value, and to start and execute continuous read commands to obtain the read data stream after each acquisition of the write data stream;

[0189] After obtaining the write data stream and read data stream in the second loop, the write data stream and read data stream obtained in the second loop will be compared. The second loop is any loop after obtaining the minimum delay value in the first-level sub-loop.

[0190] When the write data stream and read data stream obtained in the second cycle are different, the delay value corresponding to the second cycle is determined to be the maximum delay value corresponding to the first data bit.

[0191] In an optional example, processing module 603 is specifically configured to determine an average value based on the minimum delay value and the maximum delay value as a first candidate delay value corresponding to the first data bit.

[0192] In an optional example, the processing module 603 is specifically used to count the number of occurrences of each candidate delay value among the multiple candidate delay values ​​corresponding to each data bit;

[0193] The candidate delay value that appears more than or equal to a preset threshold among the multiple candidate delay values ​​corresponding to each data bit is selected as the target delay value corresponding to the data bit.

[0194] In an optional example, the processing module 603 is further configured to store the first candidate delay value to a preset storage device;

[0195] In addition, the target latency value corresponding to each data bit of the first DDR is stored in a preset storage device.

[0196] In an optional example, in every two adjacent loops, the delay value for the later loop is the sum of the delay value for the previous loop and the preset delay step.

[0197] The processing module 603 is also used to obtain the influencing factors corresponding to the delay value of the current cycle, wherein the influencing factors include any one of the data transmission rate, data type and system load, wherein the data type is determined based on the impact, real-time performance and sensitivity of the data;

[0198] Based on the influencing factors, match the calculation formula corresponding to the preset delay step size;

[0199] Based on the calculation formula, determine the preset delay step size within the first-level sub-loop;

[0200] The calculation formula corresponding to the preset delay step size includes the following:

[0201] Preset delay step size = Minimum delay step size + (Data transmission rate / Maximum transmission rate) (Maximum delay step size - Minimum delay step size);

[0202] or,

[0203] Preset delay step size = standard delay step size Data type weights;

[0204] or,

[0205] Preset delay step size = load adjustment factor (System load / Maximum load) Standard delay step size;

[0206] Among them, the standard delay step size is a pre-configured baseline delay step size. The preset delay step size applies to all first-level sub-loops. The minimum delay step size, maximum transmission rate, maximum delay step size, standard delay step size, data type weight corresponding to the data type, load adjustment factor, and maximum load are all pre-configured data.

[0207] In this embodiment, the hardware conformance screening device is presented in the form of a functional module. Here, a module refers to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0208] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0209] This invention provides a hardware consistency screening device that obtains write and read data streams by fixing the phase of a data strobe signal and selecting different delay values ​​in each loop. Then, a minimum and maximum delay value are determined based on these data streams. Next, a first candidate delay value is determined based on the minimum and maximum delay values, and the first candidate delay value for each data bit is obtained after the first-level sub-loop. In the second-level sub-loop, the above process is repeated to obtain multiple candidate delay values. Finally, in the third-level sub-loop, a target delay value for each data bit is selected based on the multiple candidate delay values, and statistical analysis is performed on the target delay values ​​of each data bit in each of the multiple DDRs to determine a screening threshold. By precisely adjusting the phase and delay value of the data strobe signal, errors and interference in data transmission can be reduced, improving data accuracy and reliability. Determining the optimal delay value for each data bit makes data transmission more efficient, thereby improving the performance of the entire system. By statistically analyzing the target delay values ​​of each data bit in multiple DDRs to determine the screening threshold, hardware devices that meet hardware consistency requirements can be quickly screened, eliminating hardware consistency risks early and improving product quality and stability. This solution can adapt to different DDR types and hardware configurations, exhibiting strong versatility and scalability. Furthermore, ensuring the stability and reliability of data transmission reduces system failures and performance degradation caused by hardware inconsistencies.

[0210] This invention also provides a computer device having the above-described features. Figure 6 The hardware consistency screening device shown.

[0211] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0212] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include an integrated circuit. The integrated circuit may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPRS), or any combination thereof.

[0213] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0214] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device as shown by a landing page for an app. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0215] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0216] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0217] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0218] This invention also provides a computer-readable storage medium. The methods provided in the above embodiments can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0219] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0220] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A hardware conformance screening method, characterized in that, The method includes: Within the first-level sub-loop, the phase of the data strobe signal in the first double-rate synchronous dynamic random access memory (DDR) is fixed. In each loop iteration, the delay phase of the first data bit in the first DDR is selected from a plurality of pre-configured delay values ​​corresponding to each loop iteration. Continuous write commands are then initiated and executed sequentially to acquire the write data stream. After each acquisition of the write data stream, a continuous read command is initiated and executed to acquire the read data stream. Based on the write data stream and read data stream obtained in one or more cyclic rounds, determine the minimum latency value corresponding to the first data bit; and after determining the minimum latency value, determine the maximum latency value corresponding to the first data bit based on the write data stream and read data stream obtained in one or more cyclic rounds; wherein, the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR; Based on the minimum delay value and the maximum delay value, a first candidate delay value corresponding to the first data bit is determined, and the current first-level sub-loop ends the operation; When the number of first-level sub-loops is the same as the number of data bits included in the first DDR, and the first candidate delay value corresponding to each data bit in the first DDR is obtained, the current second-level sub-loop is determined to end. The second-level sub-loop includes multiple first-level sub-loops. After executing multiple secondary sub-loop operations, multiple candidate delay values ​​corresponding to each data bit included in the first DDR are obtained respectively; Based on the multiple candidate delay values ​​corresponding to each data bit included in the first DDR, the target delay value corresponding to each data bit of the first DDR is selected respectively, and the current three-level sub-loop ends the operation. The current three-level sub-loop is used to obtain the target delay value corresponding to each data bit of the first DDR. After executing multiple of the three-level sub-loop operations, obtain the target delay value corresponding to each data bit of each of the multiple DDRs; Statistical analysis is performed on the target latency values ​​corresponding to each data bit of each of the multiple DDRs to determine the screening threshold, wherein the screening threshold is used to screen out hardware devices that meet hardware consistency requirements.

2. The method according to claim 1, characterized in that, The step of determining the minimum delay value corresponding to the first data bit based on the write data bitstream and read data bitstream obtained from one or more cyclic rounds specifically includes: Compare the write data stream and read data stream obtained in each cycle. When it is first determined that the write data stream and the read data stream generated in the first loop are the same, the delay value corresponding to the first loop is determined to be the minimum delay value corresponding to the first data bit, wherein the first loop is any loop within the first-level sub-loop.

3. The method according to claim 1 or 2, characterized in that, After determining the minimum delay value, the step of determining the maximum delay value corresponding to the first data bit based on the write data bitstream and read data bitstream obtained in one or more cyclic rounds specifically includes: After determining the minimum delay value, continue to execute continuous write commands sequentially to obtain the write data stream, and after each acquisition of the write data stream, start and execute continuous read commands to obtain the read data stream; After obtaining the write data stream and read data stream in the second loop, the write data stream and read data stream obtained in the second loop will be compared. The second loop is any loop after obtaining the minimum delay value in the first-level sub-loop. When the write data stream and read data stream obtained in the second cycle are different, the delay value corresponding to the second cycle is determined to be the maximum delay value corresponding to the first data bit.

4. The method according to claim 1 or 2, characterized in that, The step of determining the first candidate delay value corresponding to the first data bit based on the minimum delay value and the maximum delay value specifically includes: The average value is determined based on the minimum delay value and the maximum delay value, and is used as the first candidate delay value corresponding to the first data bit.

5. The method according to claim 4, characterized in that, The step of selecting a target delay value corresponding to each data bit of the first DDR based on multiple candidate delay values ​​corresponding to each data bit of the first DDR specifically includes: Count the number of occurrences of each candidate delay value among the multiple candidate delay values ​​corresponding to each data bit; The candidate delay value that appears more than or equal to a preset threshold number of times among the multiple candidate delay values ​​corresponding to each data bit is selected as the target delay value corresponding to the data bit.

6. The method according to claim 5, characterized in that, The method further includes: Store the first candidate delay value into a preset storage device; In addition, the target latency value corresponding to each data bit of the first DDR is stored in the preset storage device.

7. The method according to claim 1 or 2, characterized in that, In each pair of adjacent loops, the delay value corresponding to the later loop is the sum of the delay value corresponding to the previous loop and the preset delay step size; Within the first-level sub-loop, before fixing the phase of the data strobe signal in the first DDR, and before selecting the delay value corresponding to each loop cycle from a pre-configured plurality of delay values ​​for the delay phase of the first data bit in the first DDR, the method further includes: Obtain the influencing factors corresponding to the delay value of the previous cycle, wherein the influencing factors include any one of data transmission rate, data type, and system load, wherein the data type is determined based on the data's impact, real-time performance, and sensitivity. Based on the influencing factors, a calculation formula corresponding to the preset delay step size is matched; The preset delay step size within the first-level sub-loop is determined according to the calculation formula. The calculation formula corresponding to the preset delay step size includes the following: Preset delay step size = Minimum delay step size + (Data transmission rate / Maximum transmission rate) (Maximum delay step size - Minimum delay step size); or, The preset delay step size = standard delay step size Data type weights; Wherein, the standard delay step size is a pre-configured baseline delay step size, the preset delay step size applies to all the first-level sub-loops, and the minimum delay step size, the maximum transmission rate, the maximum delay step size, the standard delay step size, and the data type weight corresponding to the data type are pre-configured data.

8. A hardware consistency screening device, characterized in that, The device includes: The selection module is used to fix the phase of the data strobe signal in the first double rate synchronous dynamic random access memory (DDR) within the first sub-loop, and select the delay value corresponding to each loop from a plurality of pre-configured delay values ​​for the delay phase of the first data bit in the first DDR in each loop. The startup module is used to sequentially start and execute continuous write commands to obtain write data streams; and, after each acquisition of the write data stream, to start and execute continuous read commands to obtain read data streams. The processing module is configured to determine a minimum latency value corresponding to the first data bit based on the write data stream and read data stream acquired in one or more loop iterations; and, after determining the minimum latency value, determine a maximum latency value corresponding to the first data bit based on the write data stream and read data stream acquired in one or more loop iterations; wherein, the first DDR is any one of a plurality of DDRs, and the first data bit is any one of a plurality of data bits included in the first DDR; based on the minimum latency value and the maximum latency value, a first candidate latency value corresponding to the first data bit is determined, and the current first-level sub-loop ends the operation; when the number of first-level sub-loops is the same as the number of a plurality of data bits included in the first DDR is executed consecutively, and each data bit in the first DDR is acquired... After determining the first candidate delay value corresponding to each bit, the current second-level sub-loop ends. The second-level sub-loop includes multiple first-level sub-loops. After executing multiple second-level sub-loop operations, multiple candidate delay values ​​corresponding to each data bit of the first DDR are obtained. Based on the multiple candidate delay values ​​corresponding to each data bit of the first DDR, a target delay value corresponding to each data bit of the first DDR is selected. The current third-level sub-loop ends. The current third-level sub-loop is used to obtain the target delay value corresponding to each data bit of the first DDR. After executing multiple third-level sub-loop operations, the target delay value corresponding to each data bit of each of the multiple DDRs is obtained. The analysis module is used to perform statistical analysis on the target latency value corresponding to each data bit of each of the multiple DDRs to determine the screening threshold, wherein the screening threshold is used to screen out hardware devices that meet the hardware consistency requirements.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the hardware conformance screening method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the hardware conformance screening method according to any one of claims 1 to 7.

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