Multiplexing data transmission method and electronic device using same

Abstract

The present disclosure relates to a method for multiplexing data transmission between entities and an electronic device using the same, the method comprising: transmitting a first read enable signal indicating that data is ready to be received to an external device; receiving a first data strobe signal indicating a start of data transmission and first data from an external device; receiving subsequent data following the first data from the external device; and receive, from the external device, a second data strobe signal indicating an end of the data transmission and final data.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a multiplexed data transmission method between entities. Background Art

[0002] An electronic device is a device that performs operations to transmit or receive data between each other by using a plurality of chips included therein.

[0003] For example, a storage device is a device capable of storing data based on a request from an external device such as a computer, a mobile terminal (e.g., a smart phone, a tablet PC), or various electronic devices. The storage device includes a plurality of memories and a memory controller for controlling the memories. The memory controller can store data in the memory or read data from the memory by sending control information to the memory.

[0004] In addition, the memory controller can read data from the memory, write / program data into the memory, or perform or control an operation to erase data in the memory based on an input command input from the external device. That is, the external device and the memory controller can perform operations while sending and receiving information (e.g., commands and messages sent in response to the commands) between each other.

[0005] The agreement for transmission between entities is called a protocol (or standard / specification), and many protocols have been proposed and used depending on the type of chip, the type of data being transmitted, and the data transmission rate. However, the method of transmitting data according to the current protocol has the problem of consuming a lot of power. Summary of the invention

[0006] Embodiments of the present disclosure are directed to providing a method for transmitting data, which is capable of minimizing the use of a strobe signal during data transmission between entities to reduce power consumption.

[0007] The technical problems to be solved by the present disclosure are not limited to the above-mentioned technical problems, and ordinary technicians in the field to which the present disclosure belongs will clearly understand other technical problems not mentioned through the following description.

[0008] According to an embodiment of the present disclosure, an electronic device may include: a first terminal, connected to a first wire, and configured to send a read enable signal to an external device, the read enable signal indicating whether data reception is possible; a second terminal, connected to a second wire, and configured to send a data select signal to an external device or receive a data select signal from an external device, the data select signal indicating the start and end of data transmission; a third terminal, connected to a third wire, and configured to send data to an external device or receive data from an external device; and an interface, configured to control the sending of data to an external device or the receiving of data from an external device, wherein the interface is configured to send a first read enable signal to an external device indicating whether the first terminal is ready to receive data, while receiving a first data select signal indicating the start of data transmission from an external device through the second terminal and receiving first data from the external device through the third terminal, receiving subsequent data after the first data from the external device through the third terminal, and receiving a second data select signal indicating the end of data transmission from the external device through the second terminal and receiving last data through the third terminal.

[0009] According to an embodiment of the present disclosure, an electronic device may include: a first terminal, connected to a first wire, and configured to receive a read enable signal from an external device, the read enable signal indicating whether data reception is possible; a second terminal, connected to a second wire, and configured to send a data select signal to an external device or receive a data select signal from an external device, the data select signal indicating the start and end of data transmission; a third terminal, connected to a third wire, and configured to send data to an external device or receive data from an external device; and an interface, configured to control sending data to an external device or receiving data from an external device, wherein the interface is configured to receive a first read enable signal from an external device indicating whether the first terminal is ready to receive data, and at the same time send a first data select signal indicating the start of data transmission to the external device through the second terminal and send first data to the external device through the third terminal, send subsequent data after the first data to the external device through the third terminal, and send a second data select signal indicating the end of data transmission to the external device through the second terminal and send last data to the external device through the third terminal.

[0010] According to an embodiment of the present disclosure, an electronic device may include: a first entity, configured to perform a first function; a second entity, configured to perform a second function; and a plurality of wires connected between the first entity and the second entity for data transmission, wherein the plurality of wires include: a first wire, configured to transmit a read enable signal indicating whether data transmission is possible, a second wire, configured to transmit a data select signal indicating the start and end of data transmission; and a third wire, configured to transmit data, wherein the first entity is configured to send a first read enable signal indicating whether the first wire is ready to receive data to the second entity, receive the first data select signal indicating the start of data transmission from the second entity via the second wire, and transmit the first data select signal from the second entity via the third wire. The first entity receives first data, receives subsequent data after the first data from a second entity through a third wire, and receives a second data select signal indicating an end of data transmission from the second entity through the second wire and receives last data from the second entity through the third wire, wherein the second entity is configured to receive a first read enable signal indicating whether the first wire is ready to receive data from the first entity, send the first data select signal indicating the start of data transmission to the first entity through the second wire and send the first data to the first entity through the third wire, send subsequent data after the first data to the first entity through the third wire, and send the second data select signal indicating the end of data transmission to the first entity through the second wire and send the last data to the first entity through the third wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a connection for data transmission between entities according to an embodiment of the present disclosure.

[0012] Figure 2 is a view showing an example of a protocol for data transmission between entities.

[0013] Figure 3 is a schematic configuration diagram of a storage device.

[0014] Figure 4 is a diagram illustrating a connection relationship between signals for data transmission between a controller and a nonvolatile memory according to an embodiment of the present disclosure.

[0015] Figure 5 This is a timing diagram when data is transferred to the memory to write data according to the multiplexed data transfer method.

[0016] Figure 6 This is a timing diagram when reading data from the memory according to the multiplexed data transmission method.

[0017] Figure 71 is a timing diagram when data is transferred to a memory to write data in a multiplexed data transmission method according to an embodiment of the present disclosure.

[0018] Figure 8 is a timing diagram when data is read from a memory using a multiplexed data transmission method according to another embodiment of the present disclosure.

[0019] Fig. 9 is a timing diagram illustrating an operation between a controller and a memory for reading data from the memory according to an embodiment of the present disclosure.

[0020] Fig.10 is a timing diagram illustrating an operation between a controller and a memory for writing data to the memory according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0022] Figure 1 is a diagram illustrating a connection for data transmission between entities according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the electronic device may include a first entity 10, a second entity 21, and a third entity 23. The electronic device may further include connections 31, 33, and 35 for data transmission between the entities 10, 21, and 23. The entities 10, 21, and 23 may include different types of devices. For example, the entities may include a digital camera and a memory connected using a connector. The entities may include a host and a storage device connected using a connector. Further, the entities may include a digital camera and two separate laptops connected to each other via a network.

[0024] In another embodiment, the entity may be two chips disposed on a single substrate. For example, the entity may include a NAND flash memory disposed inside a solid-state drive (SSD) and a memory controller chip controlling the NAND flash memory, and the connection between them for data transmission may be realized by a wire disposed on the substrate.

[0025] The data transmission between entities may be implemented in a form where at least two chips are connected via a bus and one chip transmits data to another chip.

[0026] Two entities connected to each other can transmit data using wires based on a preset protocol.

[0027] Figure 2 is a view showing an example of a protocol for data transmission between entities.

[0028] Figure 2An example of a protocol used by a first entity 10 (eg, an SDRAM controller) to read data stored in a second entity 21 (eg, an SDRAM) is shown.

[0029] Reference Figure 2 , the first entity 10 can send a clock CK, a command, an address, and a data strobe signal DQS, and receive data DQ from the second entity 21. The first entity 10 can further send an inverted clock CK# and an inverted data strobe signal DQS#. In this case, the required signal levels and the timing of the signals are defined in the protocol.

[0030] Figure 3 is a schematic configuration diagram of the storage device 100 .

[0031] Connections between entities for data transfer can be used for all electronic devices. Such connections can be configured such as Figure 3 The memory 110 is shown between an external device (ie, a host) 150 and the memory device 100, and between the memory 110 and a controller 120 (also referred to as a memory controller). The memory 110 may be implemented by an additional chip inside the memory device 100.

[0032] Hereinafter, a data transmission technology based on the connection between the memory 110 and the controller 120 will be described, however, it is obvious that this data transmission technology can be used for all connections between electronic devices, or connections between multiple chips arranged inside an electronic device.

[0033] Reference Figure 3 , the storage device 100 may include a memory 110 and a controller 120 configured to control the memory 110. The storage device 100 may further include additional components.

[0034] The memory 110 may operate under the control of the controller 120. The operation of the memory 110 may include, for example, a read operation, a program operation (also referred to as a "write operation"), and an erase operation.

[0035] For example, the memory 110 may be at least one of various non-volatile memories such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric resistive random access memory (FRAM), and spin transfer torque random access memory (STT-RAM).

[0036] The memory 110 may be configured with a plurality of chips or cores, and each of the plurality of chips may have a different interface for communicating with the controller 120 .

[0037] The memory 110 may receive a command and an address from the controller 120 through a wire connected to the controller 120, and access a region selected by the address among the memory cell array included therein. That is, the memory 110 may perform an operation indicated by the command on the region selected by the address.

[0038] The memory 110 can perform a programming operation (or a write operation), a read operation, and an erase operation. For example, when performing a programming operation, the memory 110 can program data into an area selected by an address. When performing a read operation, the memory 110 can read data from an area selected by an address. When performing an erase operation, the memory 110 can erase data stored in an area selected by an address.

[0039] The controller 120 may control programming operations, reading operations, erasing operations, and background operations on the memory device 110. The background operations may include one or more of a garbage collection (GC) operation, a wear leveling (WL) operation, a read reclaim (RR) operation, or a bad block management (BBM) operation.

[0040] The controller 120 may be connected to an external device (e.g., a host) 150 located outside the storage device 100, and may control the operation of the memory 110 according to information (also referred to as a “command”) transmitted through a wire (e.g., a wire connecting two electronic devices to each other using a cable or a connector) connected to the external device 150. In addition, the controller 120 may control the operation of the memory 110 regardless of a request of the external device 150.

[0041] The external device 150 can be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet, a mobile phone, a smart phone, a smart wearable device, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital video recorder, a digital video player, a storage device constituting a data center, one of the electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, a radio frequency identification (RFID) device, and a mobile device (e.g., a vehicle, a robot, a drone) that is controlled by humans or moves autonomously on the ground, water, or in the air.

[0042] Reference Figure 3 , the controller 120 may include a host interface 121 , a memory interface 122 , and a control circuit 123 .

[0043] The host interface 121 may provide an interface for transmitting data to or from the external device 150. For example, the host interface 121 may provide an interface using at least one of various communication interfaces or standards such as a USB (Universal Serial Bus) protocol, an MMC (Multimedia Card) protocol, a PCI (Peripheral Component Interconnect) protocol, a PCI-E (PCI-Express) protocol, an ATA (Advanced Technology Attachment) protocol, a Serial ATA protocol, a Parallel ATA protocol, a SCSI (Small Computer System Interface) protocol, an ESDI (Enhanced Small Disk Interface) protocol, an IDE (Electronic Integrated Drive) protocol, an SM bus (System Management Bus) protocol, an I2C (Inter-Integrated Circuit) protocol, an I3C (Improved Inter-Integrated Circuit) protocol, and a proprietary protocol, etc. In another embodiment, the host interface 121 may provide an interface based on a multiplexed data transmission method to be described later in the present disclosure.

[0044] The memory interface 122 is connected to the memory 110 and can provide an interface for transmitting data to or from the memory 110. That is, the memory interface 122 can provide an interface for data transmission between the memory 110 and the controller 120 under the control of the control circuit 123, and the interface for data transmission can use a multiplexed data transmission method to be described later in the present disclosure in addition to the existing protocol already adopted.

[0045] The control circuit 123 may receive a command through the host interface 121 and execute the received command.

[0046] The control circuit 123 may control the operation of the memory 110 by performing general control operations of the controller 120. To this end, the control circuit 123 may include a processor 124 and a working memory 125, and may further include an error detection and correction circuit (ECC circuit) 126 according to an embodiment.

[0047] The processor 124 may control various operations of the controller 120 .

[0048] The processor 124 may communicate with the external device 150 through the host interface 121 , and communicate with the memory 110 through the memory interface 122 .

[0049] The processor 124 may perform the function of a flash translation layer (FTL). The processor 124 may convert a logical block address provided by an external device into a physical block address through the flash translation layer (FTL). The flash translation layer may receive a logical block address and convert the logical block address into a physical block address using a mapping table. The logical address and the physical address may be a logical block address or a physical block address representing a memory area.

[0050] According to the mapping unit, the flash translation layer can adopt multiple address mapping methods. Common address mapping methods include page mapping method, block mapping method and hybrid mapping method.

[0051] Processor 124 may perform background functions for memory 110 , such as garbage collection (GC), wear leveling (WL), and bad block management.

[0052] The processor 124 may control the operation of the controller 120 by running the firmware. The processor 124 may control the operation of the controller 120 and run (drive) the firmware stored in the working memory 125 during startup. Hereinafter, the operation of the storage device 100 described in the embodiments of the present disclosure may be implemented in a manner that the processor 124 runs the firmware defining the corresponding operation.

[0053] The firmware is a program that runs in the storage device 100 to drive the storage device 100, and may include various functional layers. For example, the firmware may include binary data in which a code for running each of the above-mentioned functional layers is defined.

[0054] The working memory 125 may store firmware, program codes, commands or data segments for driving the memory controller 120. The working memory 125 may include at least one of various volatile memories such as static RAM (SRAM), dynamic RAM (DRAM) and synchronous RAM (SDRAM).

[0055] In addition, the working memory 125 may be used as a device buffer to temporarily store therein data to be written to the memory 110 or data to be read from the memory 110 .

[0056] Therefore, the working memory 125 and the processor 124 need to be connected for data transmission, and the data transmission between the two can be performed based on the method provided in the embodiment of the present disclosure.

[0057] The error detection and correction circuit 126 may detect error bits of target data using an error correction code and correct the detected error bits. For example, the target data may be data stored in the working memory 125, data read from the memory device 110, or the like.

[0058] The bus 127 may provide a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. The bus 127 may include, for example, a control bus for transferring various types of control signals and commands, and a data bus for transferring various types of data.

[0059] On the other hand, some of the above-mentioned constituent elements 121, 122, 124, 125 and 126 of the controller 120 may be omitted, or some of these constituent elements may be integrated into a single element. In this case, in addition to the above-mentioned elements, the controller 120 may further include one or more other elements.

[0060] Figure 4 is a diagram illustrating a connection relationship between signals for data transmission between a controller and a nonvolatile memory according to an embodiment of the present disclosure.

[0061] Reference Figure 4 , the controller (or memory controller) 120 can send a chip selection signal CS# to the memory 110 through the first wire 210. In addition, the controller 120 can send a plurality of control signals to the memory 110 through the second wire 220. Further, the controller 120 can send data to be written to the memory 110 through the third wire 230, or receive data read from the memory 110. Each of the wires 210 to 230 may include one or more wires. In addition, each wire may be connected to a terminal that performs connection with the outside of the controller 120. Therefore, the signal sent by the controller 120 can be sent to the memory 110 through the terminal and the wire, and the signal sent by the memory 110 can reach the controller 120 through the terminal and the wire.

[0062] If multiple memories are connected to the controller 120, the chip select signal CS# can be used to select the control signal to be sent through the second wire 220 and the third wire 230 and the memory receiving the data. The symbol # indicates that the corresponding signal is a low-active signal, and when the signal is at a logic low level, the low-active signal is ON (i.e., chip selection state), and when the signal state is a logic high level, the low-active signal is OFF (i.e., non-chip selection state). According to an embodiment, when the memory 110 receives the chip select signal CS# having a logic low level, the memory 110 can recognize its selection.

[0063] The control signal may vary according to a data transmission method of a protocol set between the controller 120 and the memory 110 .

[0064] According to an embodiment, if the data transmission method is a multiplexed data transmission method in which a command, an address, and data are sent or received in a multiplexed manner on the third wire 230, the control signal sent and received by the controller 120 through the second wire 220 may include a command latch enable (CLE) signal, an address latch enable (ALE) signal, a read enable (RE) signal, and a data strobe (DQS) signal.

[0065] The CLE signal may be a signal that allows information to be transmitted through the third wire 230 and is recognized as a command.

[0066] The ALE signal may be a signal that allows information to be transmitted through the third conductive line 230 and is recognized as an address.

[0067] The RE signal indicates a state in which the controller 120 is able to receive data, and may be used only in a read operation.

[0068] The DQS signal may be a signal that allows the memory 110 to recognize the timing of the strobe data transmitted through the third conductive line 230. During a read operation, the memory 110 may generate and transmit the DQS signal to the controller 120, and when the controller 120 transmits data to the memory 110 for writing, the controller 120 may generate and transmit the DQS signal to the memory 110.

[0069] In another embodiment, in a data transmission method in which a conductor for address transmission and a conductor for data transmission are separately provided, the control signal sent and received by the controller 120 through the second conductor 230 may include a signal RD / WR# indicating whether the command is for a read operation or a write operation, an address signal for writing or reading data, a read enable (RE) signal, and a data strobe (DQS) signal. In this case, only data may be transmitted through the third conductor 230.

[0070] Figure 5 is a timing diagram when data is transferred to the memory to write data according to the multiplexed data transmission method, Figure 6 This is a timing diagram when reading data from the memory according to the multiplexed data transmission method.

[0071] The controller 120 can send a chip select signal CS# with a logic low state through a first wire connected to the memory to which the command is to be sent to indicate that the corresponding memory is selected. In addition, the controller 120 can send a command through a third wire 230 when activating the state of the CLE signal to a logic high state.

[0072] Afterwards, in Figure 5 In the case of data writing shown, when switching the DQS signal, the controller 120 can send signals D1 to Dn, so that the data to be written to the memory can be sent from the third wire 230 at the time point when the state of the DQS signal changes from logic low to logic high and from logic high to logic low.

[0073] exist Figure 6In the case of data reading shown, the controller 120 can indicate to the memory 110 that the controller 120 can receive data when the RE signal is switched. The memory 110 can send signals D1 to Dn when the DQS signal is switched based on the received RE signal, so that the data read from the memory 110 can be sent from the third wire 230 at the time point when the state of the DQS signal changes from logic low to logic high and from logic high to logic low.

[0074] When the memory recognizes that the chip select signal CS# is activated to a logic low state through the first wire 210 connected to the memory 110, the memory 110 can recognize that the subsequent control signal and data received by the memory 110 through the second wire 220 and the third wire 230 are for the memory 110. In the state where the CLE signal is activated to a logic high state, the memory 110 can recognize the signal received through the third wire 230 as a command. The command may include a memory write command or a memory read command. In addition, in the case where the state of the ALE signal is activated to a logic high, the memory 110 can recognize the signal received through the third wire 230 as an address signal. In addition, in Figure 5 In the example of , the memory 110 may recognize the signal received through the third conductive line 230 as data D1 to Dn to be written to the memory at a time point when the DQS signal changes from a logic low state to a logic high state or from a logic high state to a logic low state. Figure 6 In the example, the memory 110 can recognize that the controller 120 is ready to receive data based on the received RE signal, and can send a signal so that the data read at the time point when the DQS signal changes from a logic low state to a logic high state or from a logic high state to a logic low state can be loaded at the third wire 230.

[0075] Reference Figure 5 and Figure 6 As shown in the timing diagram, the RE signal should indicate that it is ready to receive data each time it switches, and the DQS signal should indicate that there is a signal in the third conductor 230 each time it switches. Changing the RE signal and / or the DQS signal by each switching as described above may consume a lot of power.

[0076] Therefore, embodiments of the present disclosure propose measures to reduce power consumption by suppressing switching of the RE signal and / or the DQS signal.

[0077] Figure 7 is a timing diagram when sending data to a memory to write data in a multiplexed data transmission method according to an embodiment of the present disclosure, Figure 8 is a timing diagram when data is read from a memory using a multiplexed data transmission method according to another embodiment of the present disclosure.

[0078] exist Figure 7 and Figure 8 In the embodiment of the present invention, a multiplexed data transmission method is taken as an example, however, the measures to be described below can be directly used in a method of providing an address connection and a data connection separately.

[0079] Reference Figure 7 , the controller 120 may send a chip select signal CS# in a logic low state through the first wire 210 connected to the memory to which the controller 120 intends to send a command to indicate that the corresponding memory is selected. In addition, the controller 120 may send a command through the third wire 230 when the CLE signal sent through the third wire 230 is activated to a logic high state. The corresponding command may include a data read command or a data write command. Next, the controller 120 may send an address through the third wire 230 when the ALE signal that has been sent through the second wire 220 is activated to a logic high state.

[0080] Afterwards, in Figure 7 In the case of data writing shown, the controller 120 can complete data transmission through two-step switching 510, in which the DQS signal is switched once at the time point of sending the initial data and switched again at the time point of sending the last data, instead of continuously switching the DQS signal.

[0081] In addition, refer to Figure 8 In the case of data reading, the controller 120 can complete the data reading by switching the RE signal only once when the controller 120 is ready to receive data and switching the RE signal again when the controller 120 only needs to receive the last data. In response to the above operation, the memory 110 can complete the data transmission only through the two-step switching 610, in which the DQS signal is switched once at the time point when the read data is transmitted to the controller 120 in response to the switching of the first RE signal, and the DQS signal is switched again at the time point when the last read data is transmitted to the controller 120.

[0082] Therefore, since switching of the RE signal and the DQS signal can be significantly reduced, power consumption can be reduced.

[0083] exist Figure 7 and Figure 8 In the embodiment, for more accurate operation, the same clock frequency synchronized between the controller 120 and the memory 110 or the same clock frequency asynchronously between the controller 120 and the memory 110 may be used. Therefore, the data transmission rate may be shared between the controller 120 and the memory 110.

[0084] In addition, the controller 120 may indicate the size of the data read from or written to the memory 110 before starting to transmit. According to an embodiment, the size information of the data may be included in Figure 7 and Figure 8 and is transferred to the memory 110.

[0085] Fig. 9 is a timing diagram illustrating an operation between the controller 120 and the memory 110 for reading data from the memory according to an embodiment of the present disclosure.

[0086] Reference Fig. 9 In operation S710, the controller 120 may set an interface rate between the controller 120 and the memory 110. According to an embodiment, setting the interface rate may be setting a frequency of a clock used by the interface. According to an embodiment, the controller 120 may set the interface rate only once after power is first applied. In another embodiment, the setting value may be changed based on the performance or state of the memory.

[0087] In operation S720, the controller 120 may transmit the size of the data to be read from the memory 110. According to an embodiment, the controller 120 may include the size of the data intended to be read in a read command to be transmitted to the memory 110. However, the controller 120 may additionally perform operation S720. Even if operation S720 is not performed, the memory 110 and the controller 120 may recognize the size of the data intended to be read based on the RE signal or the DQS signal to be transmitted later.

[0088] In operation S730, the controller 120 may transmit a first RE signal to the memory 110 to indicate that it is ready to receive data. According to an embodiment, the controller 120 may transmit the first RE signal when the controller can receive all the intended read data sizes set in operation S720.

[0089] In operation S740, the memory 110 may transmit a first DQS signal and first data based on the reception of the first RE signal. The first DQS signal may be used as a signal indicating the start of data transmission.

[0090] In operation S750 , the memory 110 may transmit only data to the controller 120 without switching the DQS signal.

[0091] In operation S760, the controller 120 may send a second RE signal. The second RE signal may be a signal indicating that the controller is not ready to receive data. In another embodiment, the second RE signal may be a signal indicating that the controller has received the intended read data size set in operation S720.

[0092] If the controller 120 has already sent the size of the data intended to be read in advance in operation S720, the controller 120 may omit operation S760 of sending the second RE signal. In another embodiment, if the controller has not received data of the preset size even though the size of the data to be read has been sent in advance in operation S720, the controller 120 may perform operation S760 of sending the second RE signal to stop data transmission of the memory 110 in order to indicate that it is ready to receive data.

[0093] In operation S770 , if the memory 110 receives the second RE signal from the controller 120 , the memory 110 may transmit the second DQS signal and the last data, or transmit the last data having the size received in operation S720 .

[0094] In operations S740 to S770, the controller 120 may use the internal clock to receive data transmitted by the memory 110. In this case, if a reception clock used by the memory 110 to receive data and a transmission clock used by the controller 120 to transmit data are not synchronized, an error may occur due to a mismatch between the reception clock and the transmission clock, but the possibility of an error occurring may be eliminated by adjusting the amount of data being transmitted or by synchronizing the reception clock and the transmission clock.

[0095] When the controller 120 receives all the data sent by the memory 110 , the read operation may be completed.

[0096] Fig.10 is a timing diagram illustrating an operation between a controller and a memory for writing data to the memory according to another embodiment of the present disclosure.

[0097] Reference Fig.10 In operation S810, the controller 120 may set an interface rate between the controller 120 and the memory 110. According to an embodiment, the setting may be to set the frequency of a clock used in the interface. The controller 120 may set the interface rate only once after power is first applied, and may apply the set rate to all subsequent data reads or data writes. In another embodiment, the setting value may be changed based on the performance or state of the memory.

[0098] According to an embodiment, the controller 120 may be configured differently according to Fig. 9 The data read interface rate and according to Fig.10 The interface rate at which data is written.

[0099] In operation S820, the controller 120 may transmit the size of data to be written to the memory 110 to the memory 110. According to an embodiment, the controller 120 may include the size of the data in a write command to be transmitted to the memory 110. However, the controller 120 may additionally perform operation S820. Even if operation S820 is not performed, the memory 110 may recognize the size of the data intended to be written based on the DQS signal to be transmitted later.

[0100] In operation S830, the controller 120 may transmit a first DQS signal and first data. The first DQS signal may be used as a signal indicating the start of data transmission.

[0101] In operation S840 , the controller 120 may transmit only data to the memory 110 without switching the DQS signal.

[0102] In operation S850 , the controller 120 may complete data transmission after transmitting the second DQS signal and the last data.

[0103] In operations S830 to S850, the memory 110 may use an internal clock to receive data transmitted by the controller 120. In this case, if a reception clock used by the memory 110 to receive data and a transmission clock used by the controller 120 to transmit data are not synchronized, an error may occur due to a mismatch between the reception clock and the transmission clock, but the possibility of an error occurring may be eliminated by adjusting the amount of data being transmitted or by synchronizing the reception clock and the transmission clock.

[0104] The controller 120 may complete data writing after transmitting all data to be written in the memory 110 to the memory 110 .

[0105] As described above, the method for transmitting data between the controller 120 and the memory 110 included in the memory device 100 proposed in the present disclosure can minimize the power consumed by the memory device 100 by suppressing the switching performed at each data transmission of the DQS signal indicating that there is data in the third wire 230 and the RE signal indicating whether the controller 120 is available for reception. The above method can be summarized as follows.

[0106] According to an embodiment of the present disclosure, an electronic device (e.g., a controller (120) or a host (150)) may include: a first terminal connected to a first wire and configured to send a read enable signal to an external device (e.g., a memory (110) or a storage device (100)), the read enable signal indicating whether data reception is possible; a second terminal connected to a second wire and configured to send a data select signal to the external device or receive a data select signal from the external device, the data select signal indicating the start and end of data transmission; a third terminal connected to a third wire and configured to send a data select signal to the external device; and an interface configured to control sending data to or receiving data from an external device, wherein the interface is configured to send a first read enable signal to the external device indicating whether the first terminal is ready to receive data, and simultaneously receive a first data select signal indicating the start of data transmission from the external device through the second terminal and receive the first data from the external device through the third terminal, receive subsequent data after the first data from the external device through the third terminal, and receive a second data select signal indicating the end of data transmission from the external device through the second terminal and receive the last data from the external device through the third terminal.

[0107] According to an embodiment of the present disclosure, the interface may be configured to send a second read enable signal requesting to stop data transmission to the external device through the first terminal.

[0108] According to an embodiment of the present disclosure, the interface may be configured to transmit the size of the data to be read to the external device through the third terminal before transmitting the first read enable signal.

[0109] According to an embodiment of the present disclosure, the frequency of a clock used by an interface may be set equal to the frequency of a clock used by an external device.

[0110] According to an embodiment of the present disclosure, a clock used by an interface may be synchronized with a clock used by an external device.

[0111] According to an embodiment of the present disclosure, the interface can be configured to send a third data selection signal and first write data indicating the start of write data transmission to an external device through a second terminal and a third terminal, send subsequent write data after the first write data to the external device through the third terminal, and send a fourth data selection signal and last write data indicating the end of write data transmission to the external device through the second terminal and the third terminal.

[0112] According to an embodiment of the present disclosure, the interface may be configured to transmit the size of the data to be written to the external device before transmitting the third data strobe signal and the first data.

[0113] According to an embodiment of the present disclosure, an electronic device may include: a first terminal, connected to a first wire, and configured to receive a read enable signal from an external device, the read enable signal indicating whether data reception is possible; a second terminal, connected to a second wire, and configured to send a data select signal to an external device or receive a data select signal from an external device, the data select signal indicating the start and end of data transmission; a third terminal, connected to a third wire, and configured to send data to an external device or receive data from an external device; and an interface, configured to control sending data to an external device or receiving data from an external device, wherein the interface is configured to receive a first read enable signal from an external device indicating whether the first terminal is ready to receive data, and at the same time send a first data select signal indicating the start of data transmission to the external device through the second terminal and send first data to the external device through the third terminal, send subsequent data after the first data to the external device through the third terminal, and send a second data select signal indicating the end of data transmission to the external device through the second terminal and send last data to the external device through the third terminal.

[0114] According to an embodiment of the present disclosure, the interface can be configured to send a second read select signal and the last write data indicating the end of write data transmission to the external device through the second terminal and the third terminal when the interface receives a second read enable signal requesting to stop data transmission from the external device.

[0115] According to an embodiment of the present disclosure, the interface can be configured to receive the size of the data to be sent from the external device through the third terminal before receiving the first read enable signal, and control the transmission of the first data selection signal and the second data selection signal, thereby performing data transmission according to the data size.

[0116] According to an embodiment of the present disclosure, the frequency of a clock used by an interface may be set equal to the frequency of a clock used by an external device.

[0117] According to an embodiment of the present disclosure, a clock used by an interface may be synchronized with a clock used by an external device.

[0118] According to an embodiment of the present disclosure, the interface can be configured to receive a third data selection signal and first write data indicating the start of write data transmission from an external device through a second terminal and a third terminal, receive subsequent write data after the first write data from the external device through the third terminal, and receive a fourth data selection signal and last write data indicating the end of write data transmission from the external device through the second terminal and the third terminal.

[0119] According to an embodiment of the present disclosure, the interface may be configured to receive the size of data to be written from the external device before receiving the third data strobe signal and the first data.

[0120] According to an embodiment of the present disclosure, an electronic device (e.g., a storage device (100)) may include: a first entity (e.g., a controller (120)), configured to perform a first function; a second entity (e.g., a memory (110)), configured to perform a second function; and a plurality of wires connected between the first entity and the second entity for data transmission, wherein the plurality of wires include: a first wire, configured to transmit a read enable signal indicating whether data transmission is possible; a second wire, configured to transmit a data selection signal indicating the start and end of data transmission; and a third wire, configured to transmit data, wherein the first entity is configured to send a first read enable signal to the second entity indicating whether the first wire is ready to receive data, and receive a first read enable signal from the second entity via the second wire indicating the start of data transmission. The invention relates to a method for transmitting the first data to the first entity and receiving the first data from the second entity through a third wire, receiving subsequent data after the first data from the second entity through the third wire, and receiving a second data strobe signal indicating an end of data transmission from the second entity through the second wire, and receiving the last data from the second entity through the third wire, wherein the second entity is configured to receive a first read enable signal indicating whether the first wire is ready to receive data from the first entity, send the first data strobe signal indicating the start of data transmission to the first entity through the second wire, and send the first data to the first entity through the third wire, send subsequent data after the first data to the first entity through the third wire, and send the second data strobe signal indicating the end of data transmission to the first entity through the second wire and send the last data to the first entity through the third wire.

[0121] According to an embodiment of the present disclosure, the first entity is further configured to send a third data selection signal and first write data indicating the start of write data transmission to the second entity through the second wire and the third wire, send subsequent write data after the first write data to the second entity through the third wire, and send a fourth data selection signal and last write data indicating the end of write data transmission to the second entity through the second wire and the third wire.

[0122] According to an embodiment of the present disclosure, the second entity is further configured to receive a third data selection signal and first write data indicating the start of write data transmission from the first entity through the second wire and the third wire, receive subsequent write data after the first write data from the first entity through the third wire, and receive a fourth data selection signal and last write data indicating the end of write data transmission from the first entity through the second wire and the third wire.

[0123] According to an embodiment of the present disclosure, a method for operating an electronic device may include: sending a first read enable signal to an external device indicating whether data is ready to be received, receiving a first data select signal and first data indicating the start of data transmission from the external device, receiving subsequent data after the first data from the external device, and receiving a second data select signal and last data indicating the end of data transmission from the external device.

[0124] According to an embodiment of the present disclosure, a method for operating an electronic device may include: receiving a first read enable signal from an external device indicating whether data is ready to be received, sending a first data select signal and first data indicating the start of data transmission to the external device, sending subsequent data after the first data to the external device, and sending a second data select signal and last data indicating the end of data transmission to the external device.

[0125] According to an embodiment of the present disclosure, an electronic device may include: a memory configured to store data; and a controller configured to send sequential data and a data selection signal to the memory, wherein the data selection signal switches twice corresponding to initial data of the sequential data and last data of the sequential data.

[0126] In the present disclosure, information transmission between the memory controller 120 and the memory 110 has been described as an example of the proposed method, but it is well known to those skilled in the art that the method can be used as a measure to reduce power consumption while transmitting information between any two entities to perform information transmission.

[0127] Although the embodiments of the present disclosure are described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and ideas of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered to be merely descriptive, rather than limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The ideas and scope of the present disclosure should be interpreted in conjunction with the attached claims, and all equivalent schemes falling within the scope of the attached claims are encompassed. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. An electronic device, comprising: A first terminal connected to a first wire and sending a read enable signal to an external device, wherein the read enable signal indicates whether data reception is possible; a second terminal connected to a second wire and transmitting a data strobe signal to the external device or receiving the data strobe signal from the external device, wherein the data strobe signal indicates the start and end of data transmission; a third terminal connected to a third wire and transmitting data to or receiving data from the external device; as well as an interface for controlling the sending of data to or the receiving of data from the external device, Wherein, the interface: sending a first read enable signal to the external device, wherein the first read enable signal indicates whether the first terminal is ready to receive data, At the same time, a first data strobe signal is received from the external device through the second terminal and first data is received from the external device through the third terminal, wherein the first data strobe signal indicates the start of data transmission, receiving subsequent data after the first data from the external device through the third terminal, and A second data strobe signal indicating an end of data transmission is received from the external device through the second terminal, and last data is received from the external device through the third terminal.

2. The electronic device according to claim 1, wherein: The interface sends a second read enable signal requesting to stop data transmission to the external device through the first terminal.

3. The electronic device according to claim 1, wherein: The interface sends the size of the data to be read to the external device through the third terminal before sending the first read enable signal.

4. The electronic device according to claim 1, wherein: The frequency of the clock used by the interface is set equal to the frequency of the clock used by the external device.

5. The electronic device according to claim 4, wherein: A clock used by the interface is synchronized with a clock used by the external device.

6. The electronic device according to claim 1, wherein: The interface: sending a third data strobe signal indicating the start of write data transmission and the first write data to the external device through the second terminal and the third terminal, sending subsequent write data after the first write data to the external device through the third terminal, and A fourth data strobe signal indicating the end of write data transmission and the last write data are transmitted to the external device through the second terminal and the third terminal.

7. The electronic device according to claim 6, wherein: The interface sends a size of data to be written to the external device before sending the third data strobe signal and the first write data.

8. An electronic device comprising: a first terminal connected to a first wire and receiving a read enable signal from an external device, the read enable signal indicating whether data reception is possible; a second terminal connected to a second wire and transmitting a data strobe signal to the external device or receiving the data strobe signal from the external device, wherein the data strobe signal indicates the start and end of data transmission; a third terminal connected to a third wire and transmitting data to or receiving data from the external device; as well as an interface for controlling the sending of data to or the receiving of data from the external device, Wherein, the interface: receiving a first read enable signal from the external device, the first read enable signal indicating whether the first terminal is ready to receive data, At the same time, a first data strobe signal is sent to the external device through the second terminal and first data is sent to the external device through the third terminal, wherein the first data strobe signal indicates the start of data transmission. sending subsequent data after the first data to the external device through the third terminal, and A second data strobe signal indicating the end of data transmission is sent to the external device through the second terminal and last data is sent to the external device through the third terminal.

9. The electronic device according to claim 8, wherein: When the interface receives a second read enable signal requesting to stop data transmission from the external device, the interface sends a second read select signal indicating the end of write data transmission and last write data to the external device through the second terminal and the third terminal.

10. The electronic device according to claim 8, wherein: The interface: before receiving the first read enable signal, receiving the size of the data to be transmitted from the external device through the third terminal, and The transmission of the first data strobe signal and the second data strobe signal is controlled so that data transmission is performed according to the size of data.

11. The electronic device according to claim 8, wherein: The frequency of the clock used by the interface is set equal to the frequency of the clock used by the external device.

12. The electronic device according to claim 11, wherein: A clock used by the interface is synchronized with a clock used by the external device.

13. The electronic device according to claim 8, wherein: The interface: receiving a third data strobe signal indicating the start of write data transmission and first write data from the external device through the second terminal and the third terminal, receiving subsequent write data subsequent to the first write data from the external device through the third terminal, and A fourth data strobe signal indicating the end of write data transmission and last write data are received from the external device through the second terminal and the third terminal.

14. The electronic device according to claim 13, wherein: The interface receives a size of data to be written from the external device before receiving the third data strobe signal and the first write data.

15. An electronic device, comprising: A first entity, performing a first function; a second entity, performing a second function; as well as a plurality of wires connected between the first entity and the second entity for data transmission, Wherein, the plurality of wires include: The first conductor transmits a read enable signal indicating whether data transmission is possible. a second conductor for transmitting a data strobe signal indicating the start and end of data transmission; and The third wire transmits data. The first entity: sending a first read enable signal to the second entity indicating whether the first wire is ready to receive data, receiving a first data strobe signal indicating the start of data transmission from the second entity through the second conductor and receiving first data from the second entity through the third conductor, receiving subsequent data subsequent to the first data from the second entity through the third wire, and receiving a second data strobe signal indicating the end of data transmission from the second entity through the second conductor and receiving last data from the second entity through the third conductor, The second entity: receiving a first read enable signal from the first entity indicating whether the first conductive line is ready to receive data, sending a first data strobe signal indicating the start of data transmission to the first entity through the second conductor and sending first data to the first entity through the third conductor, sending subsequent data after the first data to the first entity through the third wire, and A second data strobe signal indicating the end of data transmission is sent to the first entity through the second conductor and last data is sent to the first entity through the third conductor.

16. The electronic device according to claim 15, wherein: The first entity further: sending a third data strobe signal indicating the start of write data transmission and first write data to the second entity through the second wire and the third wire, sending subsequent data after the first written data to the second entity through the third wire, and A fourth data strobe signal indicating the end of write data transmission and the last write data are sent to the second entity through the second wire and the third wire.

17. The electronic device according to claim 15, wherein: The second entity further: receiving a third data strobe signal indicating the start of write data transmission and first write data from the first entity through the second wire and the third wire, receiving subsequent data subsequent to the first write data from the first entity through the third wire, and A fourth data strobe signal indicating the end of write data transmission and last write data are received from the first entity through the second wire and the third wire.

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