Display device

Abstract

Disclosed is a display device including a display panel including a plurality of pixels, a plurality of scan lines, and a scan driver. The plurality of pixels includes a first pixel, a second pixel, a third pixel, and a fourth pixel. The plurality of scanning lines include a first scanning line, a second scanning line, a third scanning line, and a fourth scanning line. The scan driver includes a plurality of stages connected to the plurality of scan lines, respectively, and outputs a plurality of scan signals. Activation periods of scanning signals of scanning lines adjacent to each other among the plurality of scanning lines do not overlap with each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0087355 filed in the Korean Intellectual Property Office on July 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device with improved display quality. Background Art

[0004] Generally, electronic devices such as smart phones, digital cameras, notebook computers, navigation systems, and smart TVs that provide images to users include a display device for displaying the images. The display device generates images and provides the generated images to the user via a display screen.

[0005] The display device includes: a display panel including a plurality of pixels for generating an image; a scan driver for applying a scan signal to the pixel; a data driver for applying a data voltage to the pixel; and a voltage generator for applying an operating voltage to the pixel. The pixel may receive the data voltage in response to the scan signal, and then may generate an image by using the data voltage and the operating voltage. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device with improved display quality.

[0007] According to an embodiment, a display device includes a display panel including a plurality of pixels, a plurality of scan lines and a scan driver. The plurality of pixels include a first pixel, a second pixel, a third pixel and a fourth pixel spaced apart from each other and arranged in a matrix configuration. The plurality of scan lines include: a first scan line including a first main line extending in a first direction and a first branch line electrically connected to the first main line and the first pixel and extending in a second direction intersecting the first direction; a second scan line including a second main line spaced apart from the first scan line in the second direction and extending in the first direction and a second branch line electrically connected to the second main line and the second pixel and extending in the second direction; a third scan line including a third main line spaced apart from the second scan line in the second direction and extending in the first direction and a third branch line electrically connected to the third main line and extending in the second direction; a fourth scan line including a fourth main line spaced apart from the third scan line in the second direction and extending in the first direction and a fourth branch line electrically connected to the fourth main line and extending in the second direction. The scan driver includes a plurality of stages respectively connected to the plurality of scan lines and outputs a plurality of scan signals. The plurality of scan lines are arranged in the order of the first scan line, the second scan line, the third scan line and the fourth scan line along the second direction. Scan lines located adjacent to each other among the plurality of scan lines receive scan signals of an active period at mutually exclusive time periods.

[0008] The display device may further include a data line extending in the second direction. The data line may be electrically connected to the first pixel, the second pixel, the third pixel, and the fourth pixel.

[0009] The third branch line may be electrically connected to the fourth pixel, and the fourth branch line may be electrically connected to the third pixel.

[0010] The third branch line may be electrically connected to the third pixel, and the fourth branch line may be electrically connected to the fourth pixel.

[0011] Each of the plurality of scan signals may have a pulse width greater than 1 horizontal period. A plurality of odd-numbered stages among the plurality of stages may be defined as a first stage group. A plurality of even-numbered stages among the plurality of stages may be defined as a second stage group. The plurality of scan signals may include a plurality of first scan signals output from the first stage group and a plurality of second scan signals output from the second stage group. The plurality of first scan signals and the plurality of second scan signals may be output alternately, respectively.

[0012] The scan driver may further include at least one dummy stage, and the at least one dummy stage may output a dummy scan signal to a next dummy stage or stages.

[0013] A 1-1 scan signal having a first activation period among the plurality of first scan signals may be applied to the first scan line. A 2-1 scan signal having a second activation period among the plurality of second scan signals may be applied to the second scan line. A 1-2 scan signal having a third activation period among the plurality of first scan signals may be applied to the third scan line, and the first activation period, the second activation period, and the third activation period are mutually exclusive time periods.

[0014] The plurality of scan signals may be output in the order of the 2-1st scan signal, the 1-1st scan signal, and the 1-2nd scan signal, and the at least one dummy stage may be connected to a first odd-numbered stage among the plurality of odd-numbered stages.

[0015] The plurality of scan signals may be output in the order of the 1-1th scan signal, the 1-2th scan signal, and the 2-1th scan signal.

[0016] The at least one dummy stage may be connected to a first even-numbered stage among the plurality of even-numbered stages. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0018] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0019] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0020] Figure 3 is a plan view of a display device according to an embodiment of the present disclosure.

[0021] Figure 4A is a diagram showing an embodiment of the present disclosure by enlarging Figure 2 FIG. 1 is a plan view of the layout of pixels of area AA′.

[0022] Figure 4B is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present disclosure.

[0023] Figure 4C is a diagram showing an embodiment of the present disclosure by enlarging and Figure 2 The area AA' corresponds to a plan view of the layout of pixels of the area.

[0024] Figure 5 is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure.

[0025] Fig. 6A is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0026] Figure 6B is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0027] Figure 6C is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0028] Fig.6D is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0029] Fig. 7A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0030] Figure 7B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0031] Fig. 8A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0032] Figure 8B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0033] Fig. 9A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0034] Fig. 9B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0035] Fig. 10A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0036] Fig. 10B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0037] Fig.11A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0038] Fig. 11B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0039] Fig.12 is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0040] FIG. 13A to FIG. 13H is a timing diagram illustrating an operation of a scan driver driven by one mode among a plurality of modes according to an embodiment of the present disclosure.

[0041] FIG. 14A to FIG. 14F is a timing diagram illustrating an operation of a scan driver driven by one mode among a plurality of modes according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In the specification, a first component (or region, layer, part, portion, etc.) being "on" a second component, being "connected" or being "coupled" to a second component refers to both the case where the first component is directly on, directly connected or coupled to the second component and the case where a third component is interposed between the first component and the second component.

[0043] The same reference numerals refer to the same components. In the drawings, for the clarity of the description of the technical content, the thickness, proportion and size of the components are exaggerated. The expression "and / or" includes one or more combinations that the relevant components can define.

[0044] Although the terms "first", "second", etc. may be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope and spirit of the present disclosure, a first component may be referred to as a second component, and similarly, the second component may be referred to as the first component. The articles "a", "one", and "the" are singular because they have a single referent, but the use of the singular in the specification should not exclude the presence of more than one referent.

[0045] In addition, the terms "below", "beneath", "on", "over", etc. are used to describe the relationship between components shown in the drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0046] It will be understood that the terms “comprises,” “includes,” “has,” etc. specify the presence of features, numbers, steps, operations, elements or components, or a combination thereof, described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements or components, or a combination thereof.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal manner.

[0048] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0050] Reference Figure 1 , the display device DD may have a plane defined by the first direction DR1 and the second direction DR2. The display device DD may have a rectangular shape having a long side extending in the first direction DR1 and a short side extending in the second direction DR2. However, this is an example, and the shape of the display device DD according to an embodiment of the present disclosure is not limited thereto. For example, the display device DD may have various shapes such as a circle or other polygons.

[0051] An upper surface of the display device DD may be referred to herein as a display surface DS. The display surface DS may have a plane defined by a first direction DR1 and a second direction DR2. An image generated by the display device DD may be provided to a user via the display surface DS.

[0052] The display surface DS may include an active area AA and a peripheral area NA adjacent to the active area AA.

[0053] The active area AA can display an image. A direction orthogonal to the display surface DS (ie, the display panel DP (see Figure 2 ) may be defined as a third direction DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each member may be identified by the third direction DR3. “In a plan view” may mean “when viewed in the third direction DR3”.

[0054] The peripheral area NA may not display an image. The peripheral area NA may surround the active area AA and may define a boundary of the display device DD printed in a predetermined color. However, the embodiment is not limited thereto. For example, the shape of the active area AA and the shape of the peripheral area NA may be designed to be related to each other. In an embodiment of the present disclosure, the peripheral area NA may be omitted.

[0055] The display device DD can be used for large electronic devices such as televisions, monitors, or external billboards. In addition, the display device DD can be used for small and medium-sized electronic devices such as personal computers (such as notebook computers or tablet computers), personal digital terminals, car navigation systems, game consoles, smart phones, or cameras. However, the above examples are provided only as embodiments, and it is obvious that the display device DD can be applied to any other electronic device without departing from the concept of the present disclosure.

[0056] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0057] Reference Figure 2 , the display device DD may include a display panel DP and a display panel driving circuit DPD. The display panel driving circuit DPD may include a scan driver SDV, a data driver DDV, and a timing controller T-CON. The display panel DP may include a plurality of pixels PX, a plurality of scan lines SO1 to SOm and SE1 to SEm, and a plurality of data lines DL1 to DLn. Each of "m" and "n" is a natural number greater than 0.

[0058] The display panel DP according to an embodiment of the present disclosure may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro light-emitting diode (LED) display panel, or a nano-LED display panel. The light-emitting element of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting element of the inorganic light-emitting display panel may include a quantum dot or a quantum rod, etc. The light-emitting element of the micro-LED display panel may include a micro-LED. The light-emitting element of the nano-LED display panel may include a nano-LED.

[0059] The plurality of scan lines SO1 to SOm and SE1 to SEm may be connected to the plurality of pixels PX and the scan driver SDV. Each of the plurality of scan lines SO1 to SOm and SE1 to SEm may extend in a first direction DR1.

[0060] The plurality of scan lines SO1 to SOm and SE1 to SEm may include a plurality of odd scan lines SO1 to SOm and a plurality of even scan lines SE1 to SEm. Each of the plurality of odd scan lines SO1 to SOm may be a scan line arranged among the odd scan lines among the plurality of scan lines. Each of the plurality of even scan lines SE1 to SEm may be a scan line arranged among the even scan lines among the plurality of scan lines. The plurality of odd scan lines SO1 to SOm and the plurality of even scan lines SE1 to SEm may be alternately spaced from each other in the second direction DR2. Each of the plurality of odd scan lines SO1 to SOm may be connected to an odd pixel of each of the plurality of pixel rows arranged in the first direction DR1. Each of the plurality of even scan lines SE1 to SEm may be connected to an even pixel of each of the plurality of pixel rows arranged in the first direction DR1.

[0061] The plurality of data lines DL1 to DLn may be connected to two adjacent pixels PX and the data driver DDV. Each of the plurality of data lines DL1 to DLn may extend in the second direction DR2. The plurality of data lines DL1 to DLn may be spaced apart from each other in the first direction DR1.

[0062] The voltage of the first power source ELVDD, the voltage of the second power source ELVSS, and the initialization voltage Vinit may be applied to the display panel DP. The voltage of the second power source ELVSS may have a lower level than the voltage of the first power source ELVDD. The voltage of the first power source ELVDD, the voltage of the second power source ELVSS, and the initialization voltage Vinit may be applied to a plurality of pixels PX.

[0063] The timing controller T-CON may receive an image signal RGB and a control signal CS from the outside (e.g., a system board). The timing controller T-CON may generate a plurality of pieces of image data DATA by converting the data format of the image signal RGB to be suitable for an interface specification with the data driver DDV. The timing controller T-CON may provide the plurality of pieces of image data DATA whose data formats are converted to the data driver DDV.

[0064] The timing controller T-CON may generate and output a first control signal CS1 and a second control signal CS2 in response to a control signal CS provided from the outside. The first control signal CS1 may be defined as a scan control signal. The second control signal CS2 may be defined as a data control signal. The first control signal CS1 may be provided to a scan driver SDV. The second control signal CS2 may be provided to a data driver DDV.

[0065] The scan driver SDV may generate a plurality of scan signals in response to the first control signal CS1. The plurality of scan signals may be applied to the plurality of pixels PX via the plurality of scan lines SO1 to SOm and SE1 to SEm.

[0066] The data driver DDV may generate a plurality of data voltages corresponding to a plurality of pieces of image data DATA in response to the second control signal CS2. The plurality of data voltages may be applied to a plurality of pixels PX via the data lines DL1 to DLn.

[0067] The plurality of pixels PX may receive a plurality of data voltages in response to the plurality of scan signals, and the plurality of pixels PX may display an image by emitting light having brightness corresponding to the plurality of data voltages.

[0068] Figure 3 is a plan view of a display device according to an embodiment of the present disclosure. Figure 3 In the description of Figure 2 The same components are described herein, and thus their description is omitted to avoid redundancy.

[0069] Reference Figure 3 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a plurality of flexible printed circuit boards FPCB, a timing controller T-CON, and a printed circuit board PCB.

[0070] A display area DA and a non-display area NDA surrounding the display area DA may be defined in the display panel DP. The display panel DP may have a rectangular shape having long sides extending in the first direction DR1 and short sides extending in the second direction DR2. However, the shape of the display panel DP is not limited thereto.

[0071] The pixel PX may be positioned in the display area DA. The scan driver SDV may be positioned in the non-display area NDA adjacent to one of the short sides of the display panel DP. A plurality of data drivers DDV may be provided. The data driver DDV may be positioned to be adjacent to the upper side of the display panel DP (as shown in FIG. Figure 2 ) is adjacent to one of the long sides of the display panel DP shown in .

[0072] The printed circuit board PCB may be positioned adjacent to the upper side of the display panel DP. The printed circuit board PCB may be connected to the display panel DP via a flexible printed circuit board FPCB. The flexible printed circuit board FPCB may be connected between the upper side of the display panel DP and the printed circuit board PCB. A plurality of data drivers DDV may be mounted on the flexible printed circuit board FPCB, respectively. Each of the plurality of data drivers DDV may include a readout chip. The readout chip may be manufactured and provided in the form of an integrated circuit chip. The readout chip may simultaneously perform a function of outputting a data voltage to the display panel DP and a function of receiving a sensing signal from the display panel DP.

[0073] A plurality of data lines DL1 to DLn may extend from the display panel DP to the flexible printed circuit board FPCB and be connected to a plurality of data drivers DDV through the flexible printed circuit board FPCB. For example, two data lines DL1 and DLn positioned at the leftmost and rightmost sides, respectively, and connected to the data drivers DDV are shown. However, a plurality of data lines may be connected to each of the data drivers DDV.

[0074] The timing controller T-CON may be manufactured in the form of an integrated circuit chip and mounted on a printed circuit board PCB.

[0075] Figure 4A is a diagram showing an embodiment of the present disclosure by enlarging Figure 2 FIG. 1 is a plan view of the layout of pixels of area AA′. Figure 4B is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present disclosure.

[0076] Reference Figure 2 , Figure 4A and Figure 4B , each of the plurality of pixels PX may include a first sub-pixel PX_R, a second sub-pixel PX_G, and a third sub-pixel PX_B. The first sub-pixel PX_R may be a pixel that emits red light. The second sub-pixel PX_G may be a pixel that emits green light. The third sub-pixel PX_B may be a pixel that emits blue light. The first sub-pixel PX_R, the second sub-pixel PX_G, and the third sub-pixel PX_B may be arranged in the second direction DR2.

[0077] Figure 4AA j-th data line DLj (hereinafter, also referred to as data line DLj) among a plurality of data lines DL1 to DLn is shown. In this case, "j" may be a natural number greater than 0. The data line DLj may include a first data line DL_R, a second data line DL_G, and a third data line DL_B. The first data line DL_R, the second data line DL_G, and the third data line DL_B may extend in the second direction DR2. The third data line DL_B, the first data line DL_R, and the second data line DL_G may be arranged in the first direction DR1.

[0078] The first data line DL_R may be electrically connected to two adjacent first subpixels PX_R in the first direction DR1. The second data line DL_G may be electrically connected to two adjacent second subpixels PX_G in the first direction DR1. The third data line DL_B may be electrically connected to two adjacent third subpixels PX_B in the first direction DR1.

[0079] According to an embodiment of the present disclosure, one data line DLj may be electrically connected to two adjacent pixels in each of a plurality of pixel rows. Compared with a case where one data line is electrically connected to one pixel in each of a plurality of pixel rows, the number of data lines DL1 to DLn output from the data driver DDV may be relatively small. The number of data lines DL1 to DLn connected to the data driver DDV may be reduced. For this reason, the size of the data driver DDV may be reduced. Therefore, the display device DD (see Figure 1 ) of the peripheral area NA (see Figure 1 ) can be reduced in area size.

[0080] The first power line PL1 may extend in the second direction DR2. A voltage of the first power source ELVDD may be supplied to the first power line PL1. The first power line PL1 may be electrically connected to the first subpixel PX_R, the second subpixel PX_G, and the third subpixel PX_B.

[0081] The initialization voltage line VL1 may extend in the second direction DR2. The initialization voltage Vinit may be supplied to the initialization voltage line VL1. The initialization voltage line VL1 may be electrically connected to the first subpixel PX_R, the second subpixel PX_G, and the third subpixel PX_B.

[0082] Figure 4AThe i-th odd scan line SOi (hereinafter, also referred to as odd scan line SOi) among a plurality of odd scan lines SO1 to SOm is shown. In this case, "i" may be a natural number greater than 0. The odd scan line SOi may extend in the first direction DR1. A portion of the odd scan line SOi may protrude in the negative second direction DR2. The odd scan line SOi may be electrically connected to a first subpixel PX_R, a second subpixel PX_G, and a third subpixel PX_B of a pixel positioned in an odd row among a plurality of pixels PX arranged in the first direction DR1. As used herein, "negative second direction DR2" refers to a direction along the second direction DR2 opposite to the direction of the arrow shown in the coordinates. The arrow representing the axis of the second direction DR2 points to the positive second direction DR2.

[0083] Figure 4A An i-th even scan line SEi (hereinafter, also referred to as an even scan line SEi) among a plurality of even scan lines SE1 to SEm is shown. The even scan line SEi may extend in the first direction DR1. A portion of the even scan line SEi may protrude in the second direction DR2. The even scan lines SE1 to SEm may be electrically connected to a first subpixel PX_R, a second subpixel PX_G, and a third subpixel PX_B positioned in one pixel in an even row among a plurality of pixels PX arranged in the first direction DR1.

[0084] Figure 4B FIG. 1 shows an equivalent circuit diagram of a first subpixel PX_R of one pixel among odd-numbered pixels arranged in the first direction DR1. Figure 4B The equivalent circuit diagram of is not limited thereto and may also be applied to the second subpixel PX_G and the third subpixel PX_B.

[0085] The first subpixel PX_R may include a pixel driving circuit PDC and a light emitting diode OLED.

[0086] For example, the pixel driving circuit PDC according to an embodiment of the present disclosure may include three transistors and one capacitor. In this way, the pixel PX including three transistors and one capacitor may be referred to as "having a 3T1C structure". However, this is an example, and the number of transistors and the number of capacitors of the pixel driving circuit PDC according to an embodiment of the present disclosure are not limited thereto.

[0087] The pixel driving circuit PDC may include a driving transistor T1 , a switching transistor T2 , a sensing transistor T3 , a capacitor Cst, and an initialization voltage line VL1 .

[0088] The light emitting diode OLED can be operated in an on state or an off state. The light emitting diode OLED may include a first electrode AE, a light emitting layer EML, and a second electrode CE. The first electrode AE ​​may be referred to as an "anode". The second electrode CE may be referred to as a "cathode".

[0089] The first electrode AE ​​may be electrically connected to a source node or a drain node of the driving transistor T1. A voltage of a second power source ELVSS may be supplied to the second electrode CE.

[0090] The driving transistor T1 may supply a driving current to the light emitting diode OLED to drive the light emitting diode OLED.

[0091] The driving transistor T1 may have a first node N1 corresponding to a source node or a drain node, a second node N2 corresponding to a gate node, and a third node N3 corresponding to a drain node or a source node. Figure 4B 1 shows a driving transistor T1 in which the first node N1 is a source node, the second node N2 is a gate node, and the third node N3 is a drain node. The source node of the driving transistor T1 may be referred to as a “source S” (see Figure 5 ). The drain node of the driving transistor T1 may be referred to as the “drain D” (see Figure 5 ). The gate node of the driving transistor T1 may be referred to as “gate G” (see Figure 5 ).

[0092] The first node N1 may be electrically connected to the first electrode AE ​​of the light emitting diode OLED. A voltage of the first power source ELVDD may be supplied to the third node N3.

[0093] The switching transistor T2 may be a transistor for transmitting the data voltage Vdata to the second node N2. The switching transistor T2 may be controlled by a first scan signal SOSi supplied to a gate node, and may be electrically connected between the second node N2 and the data line DLj. However, this is an example, and when the first subpixel PX_R according to an embodiment of the present disclosure is the first subpixel PX_R of an even pixel arranged in the first direction DR1, the switching transistor T2 may be controlled by a second scan signal supplied to a gate node.

[0094] The capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor T1. The capacitor Cst may be referred to as a “storage capacitor Cst.” The capacitor Cst may maintain a constant voltage during one frame time.

[0095] The sensing transistor T3 may be controlled by a first scan signal SOSi supplied to a gate node, and may be electrically connected between an initialization voltage line VL1 and a first node N1.

[0096] The sensing transistor T3 may be turned on to provide the initialization voltage Vinit supplied through the initialization voltage line VL1 to the first node N1 of the driving transistor T1 .

[0097] The sensing transistor T3 may be a transistor associated with a compensation function for a unique characteristic value of the driving transistor T1. The unique characteristic value of the driving transistor T1 may include, for example, a threshold voltage (Vth) and mobility, and the like.

[0098] By using the sensing transistor T3 that senses the unique characteristic value of the driving transistor T1 of each of the plurality of sub-pixels PX_R, PX_G, and PX_B, a source follower operation in which the voltage (Vs) of the first node N1 follows the voltage (Vg) of the second node N2 can be performed, and the sensing transistor T3 can sense the voltage of the first node N1 of the driving transistor T1 as a sensing voltage. A change in the threshold voltage of the driving transistor T1 can be sensed based on the sensing voltage thus sensed at this time.

[0099] According to an embodiment of the present disclosure, a unique characteristic value (threshold voltage or mobility) of the driving transistor T1 can be sensed by the sensing transistor T3 of each of the plurality of pixels PX. Brightness uniformity can be improved by compensating for the unique characteristics between the driving transistors T1. Therefore, a display device DD with improved display quality can be provided (see Figure 1 ).

[0100] Figure 4C is a diagram showing an embodiment of the present disclosure by enlarging and Figure 2 The area AA' corresponds to the plan view of the pixel layout of the area. Figure 4C In the description of Figure 4A and Figure 4B The same components are described herein, and thus their description is omitted to avoid redundancy.

[0101] Reference Figure 4C The data lines DLj-1 may include odd data lines DLaj and even data lines DLbj alternately arranged in the first direction DR1. One pixel may be disposed between the odd data lines DLaj and the even data lines DLbj. The odd data lines DLaj and the even data lines DLbj may be disposed in the non-display area NDA (see Figure 3 ) in the .

[0102] According to an embodiment of the present disclosure, the odd data lines DLaj and the even data lines DLbj may be electrically connected to the pixels, and the odd data lines DLaj and the even data lines DLbj may be connected to the pixels via the non-display area NDA (see FIG. Figure 3) is provided to the data driver DDV. Compared with the case where one data line is electrically connected to one pixel in each of a plurality of pixel rows, the number of data lines DL1 to DLn output from the data driver DDV can be relatively small. The number of data lines DL1 to DLn connected to the data driver DDV can be reduced. For this reason, the size of the data driver DDV can be reduced. Therefore, the display device DD (see Figure 1 ) of the peripheral area NA (see Figure 1 ) can be reduced in area size.

[0103] The odd data lines DLaj may include a first odd data line DL_Ra, a second odd data line DL_Ga, and a third odd data line DL_Ba.

[0104] The first odd data line DL_Ra may be electrically connected to the first subpixel PX_R of the odd pixel in one pixel row arranged in the first direction DR1. The second odd data line DL_Ga may be electrically connected to the second subpixel PX_G of the odd pixel. The third odd data line DL_Ba may be electrically connected to the third subpixel PX_B of the odd pixel.

[0105] The even data lines DLbj may include a first even data line DL_Rb, a second even data line DL_Gb, and a third even data line DL_Bb.

[0106] The first even data line DL_Rb may be electrically connected to the first subpixel PX_R of the even pixel in one pixel row arranged in the first direction DR1. The second even data line DL_Gb may be electrically connected to the second subpixel PX_G of the even pixel. The third even data line DL_Bb may be electrically connected to the third subpixel PX_B of the even pixel.

[0107] Figure 5 is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure.

[0108] Reference Figure 4B and Figure 5 , the display panel DP may include a first substrate SUB1, a pixel layer PXL, and a thin film encapsulation layer TFE.

[0109] The pixel layer PXL may be disposed on the first substrate SUB1. The pixel layer PXL may include a circuit element layer DP-CL and a display element layer DP-OLED.

[0110] The circuit element layer DP-CL may include a buffer layer BFL, first to sixth insulating layers INS1 to INS6 , transistors, and a connection electrode CNE.

[0111] The buffer layer BFL may be disposed on the first substrate SUB1. The buffer layer BFL may be an inorganic layer. The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon, amorphous silicon, or metal oxide.

[0112] The semiconductor pattern may be doped with an N-type dopant or a P-type dopant. The semiconductor pattern may include a high-doped region and a low-doped region. The conductivity of the high-doped region may be greater than the conductivity of the low-doped region. The high-doped region may operate substantially as a source electrode or a drain electrode of a transistor. The low-doped region may substantially correspond to an active region (or channel) of a transistor.

[0113] The source S, active region A, and drain D of the driving transistor T1 may be formed of a semiconductor pattern. The first insulating layer INS1 may be disposed on the semiconductor pattern. The gate G of the driving transistor T1 may be disposed on the first insulating layer INS1. The second insulating layer INS2 may be disposed on the gate G. The third insulating layer INS3 may be disposed on the second insulating layer INS2.

[0114] The connection electrode CNE may connect the driving transistor T1 to the light emitting diode OLED. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the third insulating layer INS3 and may be connected to the drain electrode D through a first contact hole CH1 defined in the first to third insulating layers INS1 to INS3.

[0115] The fourth insulating layer INS4 may be disposed on the first connection electrode CNE1. The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fourth insulating layer INS4 and the fifth insulating layer INS5.

[0116] The sixth insulating layer INS6 may be disposed on the second connection electrode CNE2. The first to sixth insulating layers INS1 to INS6 may be inorganic layers or organic layers.

[0117] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting diode OLED and a pixel defining layer PDL.

[0118] The light emitting diode OLED may include a first electrode AE ​​(or anode), a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a light emitting layer EML.

[0119] The first electrode AE ​​may be disposed on the sixth insulating layer INS6. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the sixth insulating layer INS6. A pixel defining layer PDL in which an opening PX_OP is formed over a predetermined portion of the first electrode AE ​​may be disposed on the first electrode AE ​​and the sixth insulating layer INS6.

[0120] The hole control layer HCL may be disposed on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0121] The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening PX_OP. The light emitting layer EML may include a light emitting element. The light emitting element may include an organic material and / or an inorganic material.

[0122] The electron control layer ECL may be disposed on the light emitting layer EML and the hole control layer HCL. The electron control layer ECL may include an electron transport layer and an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly disposed in the emission area PA and the non-emission area NPA.

[0123] The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed in the pixel PX (see Figure 2 )middle.

[0124] The thin film encapsulation layer TFE may be disposed on the second electrode CE to cover the pixel PX. The thin film encapsulation layer TFE may include a first encapsulation layer EN1 disposed on the second electrode CE, a second encapsulation layer EN2 disposed on the first encapsulation layer EN1, and a third encapsulation layer EN3 disposed on the second encapsulation layer EN2. Each of the first encapsulation layer EN1 and the third encapsulation layer EN3 may include an inorganic insulating layer and may protect the pixel PX from moisture / oxygen. The second encapsulation layer EN2 includes an organic insulating layer and may protect the pixel PX from foreign matter such as dust particles.

[0125] The voltage of the first power source ELVDD may be applied to the first electrode AE ​​via the driving transistor T1, and the voltage of the second power source ELVSS may be applied to the second electrode CE. Excitons may be formed by the recombination of holes and electrons injected into the light emitting layer EML. As the excitons transition to the ground state, the light emitting diode OLED may emit light.

[0126] The emission area PA and a non-emission area NPA around the emission area PA may be defined in a plane area of ​​the display panel DP. A light emitting diode OLED may be positioned in the emission area PA.

[0127] Fig. 6A is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0128] Reference Figure 2 and Fig. 6A The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, a sixth pixel PX6, a seventh pixel PX7, and an eighth pixel PX8. The plurality of pixels PX may have a shape in which the first to eighth pixels PX1 to PX8 are repeatedly arranged in the first direction DR1.

[0129] The second pixel PX2 may be spaced apart from the first pixel PX1 in the first direction DR1. The third pixel PX3 may be spaced apart from the first pixel PX1 in the second direction DR2. The fourth pixel PX4 may be spaced apart from the third pixel PX3 in the first direction DR1, and may be spaced apart from the second pixel PX2 in the second direction DR2. The fifth pixel PX5 may be spaced apart from the third pixel PX3 in the second direction DR2. The sixth pixel PX6 may be spaced apart from the fifth pixel PX5 in the first direction DR1. The seventh pixel PX7 may be spaced apart from the fifth pixel PX5 in the second direction DR2. The eighth pixel PX8 may be spaced apart from the seventh pixel PX7 in the first direction DR1, and may be spaced apart from the sixth pixel PX6 in the second direction DR2. The pixels are spaced apart from each other and arranged in a matrix configuration.

[0130] The data line DLj may extend in the second direction DR2. The data line DLj may be electrically connected to two adjacent pixels in the first direction DR1. The data line DLj may be electrically connected to the first to eighth pixels PX1 to PX8.

[0131] The plurality of scan lines SO1 to SOm and SE1 to SEm may include a plurality of odd-numbered scan lines SO1 to SOm and a plurality of even-numbered scan lines SE1 to SEm.

[0132] The plurality of odd-numbered scan lines SO1 to SOm may include a first scan line SO1, a third scan line SO2, a fifth scan line SO3, and a seventh scan line SO4.

[0133] The first scan line SO1 may include a first main line ML1 and a first branch line BL1. The first main line ML1 may extend in a first direction DR1. The first branch line BL1 may extend in a second direction DR2 from a point on the first main line ML1. The first branch line BL1 may extend in a negative second direction DR2. The first branch line BL1 may face the second branch line BL2 in the first direction DR1. The first branch line BL1 may be electrically connected to the first pixel PX1.

[0134] The third scan line SO2 may be spaced apart from the first scan line SO1, and the second scan line SE1 is interposed between the third scan line SO2 and the first scan line SO1. The third scan line SO2 may be spaced apart from the first scan line SO1 in the second direction DR2. The third scan line SO2 may include a third main line ML3 and a third branch line BL3. The third main line ML3 may extend in the first direction DR1. The third branch line BL3 may extend in the second direction DR2. The third branch line BL3 may protrude from the third main line ML3 to the fourth main line ML4 in the negative second direction DR2. The third branch line BL3 may be electrically connected to the fourth pixel PX4.

[0135] The fifth scan line SO3 may be spaced apart from the third scan line SO2, and the fourth scan line SE2 is interposed between the fifth scan line SO3 and the third scan line SO2. The fifth scan line SO3 may be spaced apart from the third scan line SO2 in the second direction DR2. The fifth scan line SO3 may include a fifth main line ML5 and a fifth branch line BL5. The fifth main line ML5 may extend in the first direction DR1. The fifth branch line BL5 may extend from a point on the fifth main line ML5 to the sixth main line ML6 in the negative second direction DR2. The fifth branch line BL5 may be electrically connected to the fifth pixel PX5.

[0136] The seventh scan line SO4 may be separated from the fifth scan line SO3, and the sixth scan line SE3 is interposed between the seventh scan line SO4 and the fifth scan line SO3. The seventh scan line SO4 may be separated from the fifth scan line SO3 in the second direction DR2. The seventh scan line SO4 may include a seventh main line ML7 and a seventh branch line BL7. The seventh main line ML7 may extend in the first direction DR1. The seventh branch line BL7 may extend in the second direction DR2. The seventh branch line BL7 may protrude from the seventh main line ML7 in the negative second direction DR2. The seventh branch line BL7 may be electrically connected to the eighth pixel PX8.

[0137] The plurality of even-numbered scan lines SE1 to SEm may include a second scan line SE1, a fourth scan line SE2, a sixth scan line SE3, and an eighth scan line SE4.

[0138] The second scan line SE1 may be spaced apart from the first scan line SO1 in the second direction DR2. The second scan line SE1 may include a second main line ML2 and a second branch line BL2. The second main line ML2 may extend in the first direction DR1. The second main line ML2 may be spaced apart from the first main line ML1, and the first pixel PX1 and the second pixel PX2 are interposed between the second main line ML2 and the first main line ML1. The second branch line BL2 may extend in the second direction DR2. The second branch line BL2 may protrude from the second main line ML2 to the first main line ML1 in the second direction DR2 without reaching the first main line ML1. The second branch line BL2 may be electrically connected to the second pixel PX2.

[0139] The parasitic capacitor may be formed between one scan line and an adjacent scan line. For example, the first parasitic capacitor CP1 may be formed between the second scan line SE1 and the first scan line SO1. The second parasitic capacitor CP2 may be formed between the second scan line SE1 and the third scan line SO2.

[0140] Unlike the embodiment of the present disclosure, the second scanning signal supplied to the second scanning line SE1 may be affected by the first scanning signal supplied to the first scanning line SO1 by the first parasitic capacitor CP1, and may be affected by the third scanning signal supplied to the third scanning line SO2 by the second parasitic capacitor CP2. For example, in the case where the level of the first scanning signal changes from the on level to the off level and the second scanning signal has the on (activated) level, the driving transistor T1 (see Figure 5 ) may be changed by the first parasitic capacitor CP1. In addition, when the level of the second scanning signal changes from the on level to the off level and the third scanning signal has the on (activation) level, the driving transistor T1 of the third pixel PX3 (see Figure 5 ) may be changed by the second parasitic capacitor CP2. That is, when the activation periods of the scan signals on the adjacently positioned scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 overlap with each other, the driving transistor T1 (see Figure 5 ) may be affected. As a result, a brightness difference may occur between the plurality of pixels PX1 to PX8 electrically connected to the plurality of scan lines SO1 to SO4 and SE1 to SE4. However, according to an embodiment of the present disclosure, activation periods of scan signals of mutually adjacent scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other at the same time. The influence of a parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ). This will be described later.

[0141] exist Fig. 6A In FIG. 1 , the parasitic capacitors CP1 and CP2 formed in the second scan line SE1 are described. However, the parasitic capacitors CP1 and CP2 according to an embodiment of the present disclosure may be formed between adjacent scan lines.

[0142] The fourth scan line SE2 may be spaced apart from the third scan line SO2 in the second direction DR2. The fourth scan line SE2 may include a fourth main line ML4 and a fourth branch line BL4. The fourth main line ML4 may extend in the first direction DR1. The fourth main line ML4 may be spaced apart from the third main line ML3, and the third pixel PX3 and the fourth pixel PX4 are interposed between the fourth main line ML4 and the third main line ML3. The fourth branch line BL4 may extend in the second direction DR2. The fourth branch line BL4 may protrude from a point on the fourth main line ML4 toward the third main line ML3 in the second direction DR2 without reaching the third main line ML3. The fourth branch line BL4 may be electrically connected to the third pixel PX3.

[0143] The sixth scan line SE3 may be separated from the fifth scan line SO3 in the second direction DR2. The sixth scan line SE3 may include a sixth main line ML6 and a sixth branch line BL6. The sixth main line ML6 may extend in the first direction DR1. The sixth main line ML6 may be separated from the fifth main line ML5, and the fifth pixel PX5 and the sixth pixel PX6 are interposed between the sixth main line ML6 and the fifth main line ML5. The sixth branch line BL6 may extend from the sixth main line ML6 to the fifth main line ML5 in the second direction DR2 without reaching the fifth main line ML5. The sixth branch line BL6 may be electrically connected to the sixth pixel PX6.

[0144] The eighth scan line SE4 may be separated from the seventh scan line SO4 in the second direction DR2. The eighth scan line SE4 may include an eighth main line ML8 and an eighth branch line BL8. The eighth main line ML8 may extend in the first direction DR1. The eighth main line ML8 may be separated from the seventh main line ML7, and the seventh pixel PX7 and the eighth pixel PX8 are interposed between the eighth main line ML8 and the seventh main line ML7. The eighth branch line BL8 may extend in the second direction DR2. The eighth branch line BL8 may protrude from the eighth main line ML8 to the seventh main line ML7 in the second direction DR2 without reaching the seventh main line ML7. The eighth branch line BL8 may be electrically connected to the seventh pixel PX7.

[0145] Figure 6B is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0146] Reference Figure 2 and Figure 6B , the plurality of pixels PX may include a first pixel PX1-1, a second pixel PX2-1, a third pixel PX3-1, a fourth pixel PX4-1, a fifth pixel PX5-1, a sixth pixel PX6-1, a seventh pixel PX7-1, and an eighth pixel PX8-1.

[0147] A plurality of odd-numbered scan lines SO1 to SOm may be included in Figure 6BThe first scan line SO1-1, the third scan line SO2-1, the fifth scan line SO3-1 and the seventh scan line SO4-1 are clearly shown.

[0148] The first scan line SO1-1 may include a first main line ML1-1 and a first branch line BL1-1 protruding from the first main line ML1-1 to the second main line ML2-1 in the negative second direction DR2. The first branch line BL1-1 may be electrically connected to the first pixel PX1-1. The first branch line BL1-1 is not electrically connected to the second main line ML2-1.

[0149] The third scan line SO2-1 may include a third main line ML3-1 and a third branch line BL3-1 protruding from the third main line ML3-1 to the fourth main line ML4-1 in the negative second direction DR2. The third branch line BL3-1 may be electrically connected to the third pixel PX3-1. The third branch line BL3-1 is not electrically connected to the fourth main line ML4-1.

[0150] The fifth scan line SO3-1 may include a fifth main line ML5-1 and a fifth branch line BL5-1 protruding from the fifth main line ML5-1 to the sixth main line ML6-1 in the negative second direction DR2. The fifth branch line BL5-1 may be electrically connected to the fifth pixel PX5-1. The fifth branch line BL5-1 is not electrically connected to the sixth main line ML6-1.

[0151] The seventh scan line SO4-1 may include a seventh main line ML7-1 and a seventh branch line BL7-1 protruding from the seventh main line ML7-1 to the eighth main line ML8-1 in the negative second direction DR2. The seventh branch line BL7-1 may be electrically connected to the seventh pixel PX7-1. The seventh branch line BL7-1 is not electrically connected to the eighth main line ML8-1.

[0152] The plurality of even-numbered scan lines SE1 to SEm may include a second scan line SE1 - 1 , a fourth scan line SE2 - 1 , a sixth scan line SE3 - 1 , and an eighth scan line SE4 - 1 .

[0153] The second scan line SE1-1 may include a second main line ML2-1 and a second branch line BL2-1 protruding from the second main line ML2-1 toward the first main line ML1-1 in the second direction DR2. The second branch line BL2-1 may be electrically connected to the second pixel PX2-1. The second branch line BL2-1 is not electrically connected to the first main line ML1-1.

[0154] The fourth scan line SE2-1 may include a fourth main line ML4-1 and a fourth branch line BL4-1 protruding from the fourth main line ML4-1 toward the third main line ML3-1 in the second direction DR2. The fourth branch line BL4-1 may be electrically connected to the fourth pixel PX4-1. The fourth branch line BL4-1 is not electrically connected to the third main line ML3-1.

[0155] The sixth scan line SE3-1 may include a sixth main line ML6-1 and a sixth branch line BL6-1 protruding from the sixth main line ML6-1 toward the fifth main line ML5-1 in the second direction DR2. The sixth branch line BL6-1 may be electrically connected to the sixth pixel PX6-1. The sixth branch line BL6-1 is not electrically connected to the fifth main line ML5-1.

[0156] The eighth scan line SE4-1 may include an eighth main line ML8-1 and an eighth branch line BL8-1 protruding from the eighth main line ML8-1 toward the seventh main line ML7-1 in the second direction DR2. The eighth branch line BL8-1 may be electrically connected to the eighth pixel PX8-1. The eighth branch line BL8-1 is not electrically connected to the seventh main line ML7-1.

[0157] Figure 6C is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0158] Reference Figure 2 and Figure 6C , the plurality of pixels PX may include a first pixel PX1-2, a second pixel PX2-2, a third pixel PX3-2, a fourth pixel PX4-2, a fifth pixel PX5-2, a sixth pixel PX6-2, a seventh pixel PX7-2, and an eighth pixel PX8-2. Figure 6C In the embodiment of FIG. 5 , the branch lines of the odd-numbered scan lines SO1 to SOm and the branch lines of the even-numbered scan lines SE1 to SEm extend in the same direction. Figure 6C In the embodiment of FIG. 5 , odd scan lines SO1 to SOm switch columns in each subsequent row. Similarly, even scan lines SE1 to SEm switch columns in each subsequent row, creating columns with a mixture of odd and even scan lines.

[0159] The plurality of odd-numbered scan lines SO1 to SOm may include Figure 6C The first scan line SO1-2, the third scan line SO2-2, the fifth scan line SO3-2 and the seventh scan line SO4-2 are clearly shown.

[0160] The first scan line SO1-2 may include a first main line ML1-2 and a first branch line BL1-2 protruding from the first main line ML1-2 in the second direction DR2. The first branch line BL1-2 may be electrically connected to the first pixel PX1-2.

[0161] The third scan line SO2-2 may include a third main line ML3-2 and a third branch line BL3-2 protruding from the third main line ML3-2 in the second direction DR2. The third branch line BL3-2 may be electrically connected to the fourth pixel PX4-2.

[0162] The fifth scan line SO3-2 may include a fifth main line ML5-2 and a fifth branch line BL5-2 protruding from the fifth main line ML5-2 in the second direction DR2. The fifth branch line BL5-2 may be electrically connected to the fifth pixel PX5-2.

[0163] The seventh scan line SO4-2 may include a seventh main line ML7-2 and a seventh branch line BL7-2 protruding from the seventh main line ML7-2 in the second direction DR2. The seventh branch line BL7-2 may be electrically connected to the eighth pixel PX8-2.

[0164] The plurality of even-numbered scan lines SE1 to SEm may include Figure 6C The second scan line SE1-2, the fourth scan line SE2-2, the sixth scan line SE3-2 and the eighth scan line SE4-2 are clearly shown.

[0165] The second scan line SE1-2 may be disposed adjacent to the first scan line SO1-2. The second scan line SE1-2 may include a second main line ML2-2 and a second branch line BL2-2 protruding from the second main line ML2-2 in the second direction DR2. The second branch line BL2-2 may be electrically connected to the second pixel PX2-2.

[0166] The fourth scan line SE2-2 may be disposed adjacent to the third scan line SO2-2. The fourth scan line SE2-2 may include a fourth main line ML4-2 ​​and a fourth branch line BL4-2 protruding from the fourth main line ML4-2 ​​in the second direction DR2. The fourth branch line BL4-2 may be electrically connected to the third pixel PX3-2.

[0167] The sixth scan line SE3-2 may be disposed adjacent to the fifth scan line SO3-2. The sixth scan line SE3-2 may include a sixth main line ML6-2 and a sixth branch line BL6-2 protruding from the sixth main line ML6-2 in the second direction DR2. The sixth branch line BL6-2 may be electrically connected to the sixth pixel PX6-2.

[0168] The eighth scan line SE4-2 may be disposed adjacent to the seventh scan line SO4-2. The eighth scan line SE4-2 may include an eighth main line ML8-2 and an eighth branch line BL8-2 protruding from the eighth main line ML8-2 in the second direction DR2. The eighth branch line BL8-2 may be electrically connected to the seventh pixel PX7-2.

[0169] Fig.6D is a schematic diagram showing a connection relationship between a plurality of pixels and a plurality of scan lines according to an embodiment of the present disclosure.

[0170] Reference Figure 2 and Fig.6D, the plurality of pixels PX may include a first pixel PX1-3, a second pixel PX2-3, a third pixel PX3-3, a fourth pixel PX4-3, a fifth pixel PX5-3, a sixth pixel PX6-3, a seventh pixel PX7-3, and an eighth pixel PX8-3. Fig.6D In the embodiment of FIG. 5 , the branch lines of the odd-numbered scan lines SO1 to SOm and the branch lines of the even-numbered scan lines SE1 to SEm extend in the same direction. Figure 6C Unlike the embodiment of the present invention, the odd-numbered scan lines SO1 to SOm are arranged in one column, and the even-numbered scan lines SE1 to SEm are arranged in another column.

[0171] The plurality of odd-numbered scan lines SO1 to SOm may include a first scan line SO1-3, a third scan line SO2-3, a fifth scan line SO3-3, and a seventh scan line SO4-3.

[0172] The first scan line SO1-3 may include a first main line ML1-3 and a first branch line BL1-3 protruding from the first main line ML1-3 in the second direction DR2. The first branch line BL1-3 may be electrically connected to the first pixel PX1-3.

[0173] The third scan line SO2-3 may include a third main line ML3-3 and a third branch line BL3-3 protruding from the third main line ML3-3 in the second direction DR2. The third branch line BL3-3 may be electrically connected to the third pixel PX3-3.

[0174] The fifth scan line SO3-3 may include a fifth main line ML5-3 and a fifth branch line BL5-3 protruding from the fifth main line ML5-3 in the second direction DR2. The fifth branch line BL5-3 may be electrically connected to the fifth pixel PX5-3.

[0175] The seventh scan line SO4-3 may include a seventh main line ML7-3 and a seventh branch line BL7-3 protruding from the seventh main line ML7-3 in the second direction DR2. The seventh branch line BL7-3 may be electrically connected to the seventh pixel PX7-3.

[0176] The plurality of even-numbered scan lines SE1 to SEm may include a second scan line SE1 - 3 , a fourth scan line SE2 - 3 , a sixth scan line SE3 - 3 , and an eighth scan line SE4 - 3 .

[0177] The second scan line SE1-3 may be disposed adjacent to the first scan line SO1-3. The second scan line SE1-3 may include a second main line ML2-3 and a second branch line BL2-3 protruding from the second main line ML2-3 in the second direction DR2. The second branch line BL2-3 may be electrically connected to the second pixel PX2-3.

[0178] The fourth scan line SE2-3 may be disposed adjacent to the third scan line SO2-3. The fourth scan line SE2-3 may include a fourth main line ML4-3 and a fourth branch line BL4-3 protruding from the fourth main line ML4-3 in the second direction DR2. The fourth branch line BL4-3 may be electrically connected to the fourth pixel PX4-3.

[0179] The sixth scan line SE3-3 may be disposed adjacent to the fifth scan line SO3-3. The sixth scan line SE3-3 may include a sixth main line ML6-3 and a sixth branch line BL6-3 protruding from the sixth main line ML6-3 in the second direction DR2. The sixth branch line BL6-3 may be electrically connected to the sixth pixel PX6-3.

[0180] The eighth scan line SE4-3 may be disposed adjacent to the seventh scan line SO4-3. The eighth scan line SE4-3 may include an eighth main line ML8-3 and an eighth branch line BL8-3 protruding from the eighth main line ML8-3 in the second direction DR2. The eighth branch line BL8-3 may be electrically connected to the eighth pixel PX8-3.

[0181] Fig. 7A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure. Figure 7B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0182] Reference Fig. 6A , Fig. 7A and Figure 7B , the scan driver SDV can operate as a shift register and can include a plurality of stages ST1a to ST1d and ST2a to ST2d that respectively provide scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4 and SES4 to a plurality of scan lines SO1, SE1, SO2, SE2, SO3, SE3, SO4 and SE4.

[0183] Each of the plurality of stages ST1a to ST1d and ST2a to ST2d may be connected to a clock line (not shown) to receive a clock signal whose phase is delayed by more than 1 horizontal period 1H from the clock line, and output a scanning signal having a pulse width PD greater than 1 horizontal period 1H to a corresponding scanning line. In this case, 1 horizontal period 1H may be 1.47 microseconds (μs). The pulse width PD may be greater than 1 horizontal period 1H and less than 2 horizontal periods. For example, the pulse width PD may have 1.8 horizontal periods.

[0184] The plurality of stages ST1a to ST1d and ST2a to ST2d may include a first stage ST1a, a second stage ST2a, a third stage ST1b, a fourth stage ST2b, a fifth stage ST1c, a sixth stage ST2c, a seventh stage ST1d, and an eighth stage ST2d.

[0185] A plurality of stages ST1a to ST1d and ST2a to ST2d may belong to a connected first stage group STG1 or a second stage group STG2. Among the plurality of stages ST1a to ST1d and ST2a to ST2d, the odd-numbered stages ST1a to ST1d may be defined as the first stage group STG1. For example, the first stage ST1a, the third stage ST1b, the fifth stage ST1c, and the seventh stage ST1d may be defined as the first stage group STG1. Among the plurality of stages ST1a to ST1d and ST2a to ST2d, the even-numbered stages ST2a to ST2d may be defined as the second stage group STG2. For example, the second stage ST2a, the fourth stage ST2b, the sixth stage ST2c, and the eighth stage ST2d may be defined as the second stage group STG2.

[0186] A plurality of stages ST1a to ST1d and ST2a to ST2d may output a plurality of scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4, respectively. Each of the plurality of scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4 may have a pulse width PD greater than 1 horizontal period 1H and less than 2 horizontal periods. For example, the pulse width PD may have 1.8 horizontal periods. The scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4 output to the output terminals of the stages ST1a to ST1d and ST2a to ST2d may be supplied to the corresponding scan lines, and may be supplied to the input terminals of the subsequent stages as the start signals of the subsequent stages at the same time.

[0187] The plurality of scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4 may include a plurality of first scan signals SOS1, SOS2, SOS3, and SOS4 output from the first stage group STG1 and a plurality of second scan signals SES1, SES2, SES3, and SES4 output from the second stage group STG2. The plurality of first scan signals SOS1, SOS2, SOS3, and SOS4 may include a 1-1st scan signal SOS1, a 1-2nd scan signal SOS2, a 1-3rd scan signal SOS3, and a 1-4th scan signal SOS4. The plurality of second scan signals SES1, SES2, SES3, and SES4 may include a 2-1st scan signal SES1, a 2-2nd scan signal SES2, a 2-3rd scan signal SES3, and a 2-4th scan signal SES4.

[0188] A plurality of first scan signals SOS1, SOS2, SOS3, and SOS4 and a plurality of second scan signals SES1, SES2, SES3, and SES4 may be output alternately, respectively. In this case, first to n-th data signals corresponding to the first to m-th scan lines are sequentially applied to the data lines based on the plurality of scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4.

[0189] The scan driver SDV may further include at least one dummy stage STDa or STDb. Fig. 7A A configuration further including two dummy stages STDa and STDb is shown.

[0190] The dummy stages STDa and STDb according to an embodiment of the present disclosure may belong to the first stage group STG1. The dummy stages STDa and STDb may include a first dummy stage STDa and a second dummy stage STDb. The first dummy stage STDa may be connected to the second dummy stage STDb. The second dummy stage STDb may be connected to the first stage ST1a. The dummy stages STDa and STDb may shift the timing at which the 1-1 scan signal SOS1 is provided.

[0191] At least one dummy stage may output a dummy scan signal to a next dummy stage or stages.

[0192] The first dummy stage STDa can be controlled by the timing controller T-CON (see Figure 2 ) receives the first start signal SSP1. The first dummy stage STDa may output a first dummy scan signal SDS1.

[0193] The second dummy stage STDb may be connected to the first dummy stage STDa. The second dummy stage STDb may receive the first dummy scan signal SDS1. The second dummy stage STDb may output the second dummy scan signal SDS2.

[0194] The first stage ST1a may be connected to the second dummy stage STDb. The first stage ST1a may receive the second dummy scan signal SDS2. The first stage ST1a may be connected to the first scan line SO1. The first stage ST1a may output a 1-1th scan signal SOS1.

[0195] The third stage ST1b may be connected to the first stage ST1a. The third stage ST1b may receive the 1-1th scan signal SOS1. The third stage ST1b may be connected to the third scan line SO2. The third stage ST1b may output the 1-2th scan signal SOS2.

[0196] The fifth stage ST1c may be connected to the third stage ST1b. The fifth stage ST1c may receive the 1-2 nd scan signal SOS2. The fifth stage ST1c may be connected to the fifth scan line SO3. The fifth stage ST1c may output the 1-3 rd scan signal SOS3.

[0197] The seventh stage ST1d may be connected to the fifth stage ST1c. The seventh stage ST1d may receive the 1st-3rd scan signal SOS3. The seventh stage ST1d may be connected to the seventh scan line SO4. The seventh stage ST1d may output the 1st-4th scan signal SOS4.

[0198] The second stage ST2a can be operated from the timing controller T-CON (see Figure 2 ) receives the second start signal SSP2. The second start signal SSP2 may be output at a different time point from the first start signal SSP1. For example, the second start signal SSP2 may be shifted from the first start signal SSP1 by 1 horizontal period 1H. The second stage ST2a may be connected to the second scan line SE1. The second stage ST2a may output the 2-1st scan signal SES1.

[0199] The fourth stage ST2b may be connected to the second stage ST2a. The fourth stage ST2b may receive the 2-1st scan signal SES1. The fourth stage ST2b may be connected to the fourth scan line SE2. The fourth stage ST2b may output the 2-2nd scan signal SES2.

[0200] The sixth stage ST2c may be connected to the fourth stage ST2b. The sixth stage ST2c may receive the 2-2 th scan signal SES2. The sixth stage ST2c may be connected to the sixth scan line SE3. The sixth stage ST2c may output the 2-3 th scan signal SES3.

[0201] The eighth stage ST2d may be connected to the sixth stage ST2c. The eighth stage ST2d may receive the 2nd-3rd scan signal SES3. The eighth stage ST2d may be connected to the eighth scan line SE4. The eighth stage ST2d may output the 2nd-4th scan signal SES4.

[0202] The 1-1 scan signal SOS1 supplied to the first scan line SO1 may be delayed by 3 horizontal periods or more compared to the 2-1 scan signal SES1 supplied to the second scan line SE1. For this reason, activation periods of scan signals on mutually adjacent scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other. For example, the activation period of the 2-1 scan signal SES1 supplied to the second scan line SE1 may not overlap with the activation periods of the 1-1 scan signal SOS1 supplied to the adjacent first scan line SO1 and the 1-2 scan signal SOS2 supplied to the adjacent third scan line SO2.

[0203] For example, the 2-1st scan signal SES1, the 1-1st scan signal SOS1, and the 1-2nd scan signal SOS2 may be output in the order of the 2-1st scan signal SES1, the 1-1st scan signal SOS1, and the 1-2nd scan signal SOS2. When the 1-1st scan signal SOS1 has a first activation period, the 2-1st scan signal SES1 has a second activation period, and the 1-2nd scan signal SOS2 has a third activation period, and the first activation period, the second activation period, and the third activation period may not overlap with each other. In other words, at a given time, no more than one scan signal of the activation scan signals SES1, SOS1, and SOS2 provided to adjacent scan lines may be activated.

[0204] One of the plurality of scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4 may be supplied to one of the plurality of scan lines SO1 to SO4 and SE1 to SE4. A next scan signal output immediately after one of the plurality of scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4, and SES4 may be supplied to another scan line spaced apart from the one scan line, and at least one intervening scan line among the other scan lines SO1 to SO4 and SE1 to SE4 is interposed between the one scan line and the another scan line.

[0205] For example, the 2-3 scan signal SES3 may be provided to the sixth scan line SE3. The 1-2 scan signal SOS2 (which is the next scan signal output immediately after the 2-3 scan signal SES3) is provided to the third scan line SO2 (which is separated from the sixth scan line SE3, and at least one scan line (e.g., scan lines SE2 and SO3) is interposed between the third scan line SO2 and the sixth scan line SE3).

[0206] Reference Figure 7B , the activation periods of one scan signal output and the next scan signal output immediately after the one scan signal may partially overlap. However, the activation periods of the scan signals output to adjacent scan lines do not overlap, and the activation period of the next scan signal may be delayed by 1 horizontal period 1H from the one scan signal. When the next scan signal is output "immediately after" a scan signal, this means that there is no activated intervening scan signal between the one scan signal and the next scan signal.

[0207] Unlike the embodiment of the present disclosure, when the activation periods of the scan signals on the scan lines adjacent to each other among the plurality of scan lines SO1 to SO4 and SE1 to SE4 overlap with each other, the driving transistor T1 (see Figure 5 ) may be affected by the kickback voltage of the signal supplied to the gate node of another adjacent drive transistor. However, according to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other, so that the scan signal of no more than one scan line among any adjacently positioned scan lines SO1 to SO4 and SE1 to SE4 is activated at a given time. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line can be reduced or prevented. The degradation of the display quality due to the kickback voltage can be prevented. Therefore, a display device DD with improved display quality can be provided (see Figure 1 ).

[0208] In addition, according to an embodiment of the present disclosure, scan lines receiving scan signals having activation periods overlapping each other may be spaced apart from each other by a predetermined minimum distance to reduce or remove the influence of parasitic capacitors CP1 and CP2. The predetermined minimum distance may be 50 μm. The scan driver SDV may be driven so that the distance between the scan lines receiving scan signals having activation periods overlapping satisfies the predetermined minimum distance. The degradation of display quality due to the kickback voltage may be prevented. Therefore, a display device DD having improved display quality may be provided (see Figure 1 ).

[0209] exist Fig. 7A and Figure 7B The operation of the scan driver SDV is described in Fig. 6A The multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1 to SOm and SE1 to SEm. However, according to an embodiment of the present disclosure, the operation of the scan driver SDV is not limited thereto. For example, Figure 7B The operation of the scan driver SDV in can be applied to Fig. 6A and Figure 6B The connection relationship between the multiple pixels PX and the multiple scanning lines SO1 to SOm and SE1 to SEm.

[0210] Fig. 8A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure. Figure 8B is a timing diagram showing the operation of the scan driver according to an embodiment of the present disclosure. Fig. 8A and Figure 8B In the description of Fig. 7A and Figure 7B The same components are described herein, and thus their description is omitted to avoid redundancy.

[0211] Reference Fig. 6A , Fig. 8A and Figure 8B , the scan driver SDV- 1 may include a plurality of stages ST1 a - 1 to ST1 d - 1 and ST2 a - 1 to ST2 d - 1 and at least one dummy stage STDa- 1 or STDb- 1 .

[0212] The plurality of stages ST1a-1 to ST1d-1 and ST2a-1 to ST2d-1 may include a first stage ST1a-1, a second stage ST2a-1, a third stage ST1b-1, a fourth stage ST2b-1, a fifth stage ST1c-1, a sixth stage ST2c-1, a seventh stage ST1d-1, and an eighth stage ST2d-1.

[0213] A plurality of stages ST1a-1 to ST1d-1 and ST2a-1 to ST2d-1 may belong to a connected first stage group STG1-1 or a second stage group STG2-1. Among the plurality of stages ST1a-1 to ST1d-1 and ST2a-1 to ST2d-1, the odd-numbered stages ST1a-1 to ST1d-1 may be defined as the first stage group STG1-1. For example, the first stage ST1a-1, the third stage ST1b-1, the fifth stage ST1c-1, and the seventh stage ST1d-1 may be defined as the first stage group STG1-1. Among the plurality of stages ST1a-1 to ST1d-1 and ST2a-1 to ST2d-1, the even-numbered stages ST2a-1 to ST2d-1 may be defined as the second stage group STG2-1. For example, the second stage ST2a-1, the fourth stage ST2b-1, the sixth stage ST2c-1, and the eighth stage ST2d-1 may be defined as the second stage group STG2-1.

[0214] The plurality of scan signals SOS1-1, SES1-1, SOS2-1, SES2-1, SOS3-1, SES3-1, SOS4-1, and SES4-1 may include a plurality of first scan signals SOS1-1, SOS2-1, SOS3-1, and SOS4-1 output from the first stage group STG1-1 and a plurality of second scan signals SES1-1, SES2-1, SES3-1, and SES4-1 output from the second stage group STG2-1. The plurality of first scan signals SOS1-1, SOS2-1, SOS3-1, and SOS4-1 may include a 1-1st scan signal SOS1-1, a 1-2nd scan signal SOS2-1, a 1-3rd scan signal SOS3-1, and a 1-4th scan signal SOS4-1. The plurality of second scan signals SES1-1, SES2-1, SES3-1, and SES4-1 may include a 2-1st scan signal SES1-1, a 2-2nd scan signal SES2-1, a 2-3rd scan signal SES3-1, and a 2-4th scan signal SES4-1.

[0215] The first stage ST1a-1 can be operated from the timing controller T-CON (see Figure 2 ) receives the first start signal SSP1. The first stage ST1a-1 may be connected to the first scan line SO1. The first stage ST1a-1 may output a 1-1th scan signal SOS1-1.

[0216] The third stage ST1b-1 may be connected to the first stage ST1a-1. The third stage ST1b-1 may receive the 1-1th scan signal SOS1-1. The third stage ST1b-1 may be connected to the third scan line SO2. The third stage ST1b-1 may output the 1-2th scan signal SOS2-1.

[0217] The fifth stage ST1c-1 may be connected to the third stage ST1b-1. The fifth stage ST1c-1 may receive the 1-2nd scan signal SOS2-1. The fifth stage ST1c-1 may be connected to the fifth scan line SO3. The fifth stage ST1c-1 may output the 1-3rd scan signal SOS3-1.

[0218] The seventh stage ST1d-1 may be connected to the fifth stage ST1c-1. The seventh stage ST1d-1 may receive the 1-3rd scan signal SOS3-1. The seventh stage ST1d-1 may be connected to the seventh scan line SO4. The seventh stage ST1d-1 may output the 1-4th scan signal SOS4-1.

[0219] The dummy stages STDa- 1 and STDb- 1 according to an embodiment of the present disclosure may belong to the second stage group STG2 - 1 .

[0220] The dummy stages STDa-1 and STDb-1 may include a first dummy stage STDa-1 and a second dummy stage STDb-1. The first dummy stage STDa-1 may be connected to the second dummy stage STDb-1. The second dummy stage STDb-1 may be connected to the second stage ST2a-1. The dummy stages STDa-1 and STDb-1 may be shifted by the timing at which the 2-1st scan signal SES1-1 is provided.

[0221] The first dummy stage STDa-1 can be controlled from the timing controller T-CON (see Figure 2 ) receives the second start signal SSP2. The first dummy stage STDa-1 may output the first dummy scan signal SDS1-1.

[0222] The second dummy stage STDb-1 may be connected to the first dummy stage STDa-1. The second dummy stage STDb-1 may receive the first dummy scan signal SDS1-1. The second dummy stage STDb-1 may output the second dummy scan signal SDS2-1.

[0223] The second stage ST2a-1 may be connected to the second dummy stage STDb-1. The second stage ST2a-1 may receive the second dummy scan signal SDS2-1. The second stage ST2a-1 may be connected to the second scan line SE1. The second stage ST2a-1 may output the 2-1st scan signal SES1-1.

[0224] The fourth stage ST2b-1 may be connected to the second stage ST2a-1. The fourth stage ST2b-1 may receive the 2-1st scan signal SES1-1. The fourth stage ST2b-1 may be connected to the fourth scan line SE2. The fourth stage ST2b-1 may output the 2-2nd scan signal SES2-1.

[0225] The sixth stage ST2c-1 may be connected to the fourth stage ST1b-1. The sixth stage ST2c-1 may receive the 2-2nd scan signal SES2-1. The sixth stage ST2c-1 may be connected to the sixth scan line SE3. The sixth stage ST2c-1 may output the 2-3rd scan signal SES3-1.

[0226] The eighth stage ST2d-1 may be connected to the sixth stage ST2c-1. The eighth stage ST2d-1 may receive the 2nd-3rd scan signal SES3-1. The eighth stage ST2d-1 may be connected to the eighth scan line SE4. The eighth stage ST2d-1 may output the 2nd-4th scan signal SES4-1.

[0227] The 2-1 scan signal SES1-1 supplied to the second scan line SE1 may be delayed by 5 horizontal periods or more compared to the 1-1 scan signal SOS1-1 supplied to the first scan line SO1. For this reason, activation periods of scan signals of mutually adjacent scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other. For example, the activation period of the 2-1 scan signal SES1-1 supplied to the second scan line SE1 may not overlap with the activation periods of the 1-1 scan signal SOS1-1 supplied to the adjacent first scan line SO1 and the 1-2 scan signal SOS2-1 supplied to the adjacent third scan line SO2.

[0228] For example, the 1-1th scan signal SOS1-1, the 1-2nd scan signal SOS2-1, and the 2-1th scan signal SES1-1 may be output in the order of the 1-1th scan signal SOS1-1, the 1-2nd scan signal SOS2-1, and the 2-1st scan signal SES1-1.

[0229] One scan signal among the plurality of scan signals SOS1-1, SES1-1, SOS2-1, SES2-1, SOS3-1, SES3-1, SOS4-1, and SES4-1 may be supplied to one scan line among the plurality of scan lines SO1 to SO4 and SE1 to SE4. A next scan signal output immediately after a scan signal among the plurality of scan signals SOS1-1, SES1-1, SOS2-1, SES2-1, SOS3-1, SES3-1, SOS4-1, and SES4-1 may be supplied to another scan line spaced apart from the one scan line, and at least one intervening scan line among the other scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 is interposed between the one scan line and the another scan line.

[0230] For example, the 1-3 scan signal SOS3-1 may be provided to the fifth scan line SO3. The 2-1 scan signal SES1-1 (which is the first signal output after the 1-3 scan signal SOS3-1) is provided to the second scan line SE1 (which is separated from the fifth scan line SO3 with at least one scan line (e.g., scan lines SE2 and SO2) interposed between the second scan line SE1 and the fifth scan line SO3).

[0231] According to an embodiment of the present disclosure, the activation periods of the scan signals on the adjacently positioned scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other. In this way, the influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0232] exist Fig. 8A and Figure 8B The operation of the scan driver SDV-1 and Fig. 6A The multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1 to SOm and SE1 to SEm. However, according to an embodiment of the present disclosure, the operation of the scan driver SDV-1 is not limited thereto. For example, Figure 8B The operation of the scan driver SDV-1 can be applied to FIG. 6A to FIG. 6D The connection relationship between the multiple pixels PX and the multiple scanning lines SO1 to SOm and SE1 to SEm.

[0233] Fig. 9A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure. Fig. 9B is a timing diagram showing the operation of the scan driver according to an embodiment of the present disclosure. Fig. 9A and Fig. 9B In the description of Fig. 7A , Figure 7B and Figure 8B The same components are described, and thus their descriptions are omitted to avoid redundancy (for example, descriptions about the first stage group STG1-2, the third stage ST1b-2, the fourth stage ST2b-2, the fifth stage ST1c-2, and the sixth stage ST2c-2 will be omitted).

[0234] Reference Fig. 6A , Fig. 9A and Fig. 9B , the scan driver SDV-2 may include a plurality of stages ST1a-2 to ST1d-2 and ST2a-2 to ST2d-2 and at least one dummy stage STDa-2, STDb-2, or STDc-2.

[0235] The plurality of dummy stages STDa- 2 , STDb- 2 , and STDc- 2 may belong to the second stage group STG2 - 2 .

[0236] The odd-numbered stages ST1a-2 to ST1d-2 may output a plurality of first scan signals SOS1-2, SOS2-2, SOS3-2, and SOS4-2, respectively. The even-numbered stages ST2a-2 to ST2d-2 may output a plurality of second scan signals SES1-2, SES2-2, SES3-2, and SES4-2, respectively.

[0237] The timing of the plurality of second scan signals SES1-2, SES2-2, SES3-2 and SES4-2 provided to the plurality of scan lines SE1 to SEm may be shifted by the plurality of dummy stages STDa-2, STDb-2 and STDc-2. The scan driver SDV-2 may control the amount of shifting by the number of dummy stages. Fig. 8A The scan driver SDV-1 shown in Fig. 8A )compared to, Fig. 9A The scan driver SDV- 2 shown in EMBODIMENT 3 may further include an additional dummy stage, and the 2-1 th scan signal SES1 - 2 may be additionally shifted.

[0238] The plurality of dummy stages STDa- 2 , STDb- 2 , and STDc- 2 may include a first dummy stage STDa- 2 , a second dummy stage STDb- 2 , and a third dummy stage STDc- 2 .

[0239] The first dummy stage STDa-2 can be controlled from the timing controller T-CON (see Figure 2 ) receives the second start signal SSP2. The first dummy stage STDa-2 may output the first dummy scan signal SDS1-2.

[0240] The second dummy stage STDb-2 may be connected to the first dummy stage STDa-2. The second dummy stage STDb-2 may receive the first dummy scan signal SDS1-2. The second dummy stage STDb-2 may output the second dummy scan signal SDS2-2.

[0241] The third dummy stage STDc-2 may be connected to the second dummy stage STDb-2. The third dummy stage STDc-2 may receive the second dummy scan signal SDS2-2. The third dummy stage STDc-2 may output the third dummy scan signal SDS3-2.

[0242] The second stage ST2a-2 may be connected to the third dummy stage STDc-2. The second stage ST2a-2 may receive the third dummy scan signal SDS3-2.

[0243] The 2-1 scan signal SES1-2 supplied to the second scan line SE1 may be delayed by 7 horizontal periods or more compared to the 1-1 scan signal SOS1-2 supplied to the first scan line SO1. For this reason, activation periods of scan signals of mutually adjacent scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other. For example, the activation period of the 2-1 scan signal SES1-2 supplied to the second scan line SE1 may not overlap with the activation periods of the 1-1 scan signal SOS1-2 supplied to the adjacent first scan line SO1 and the 1-2 scan signal SOS2-2 supplied to the adjacent third scan line SO2.

[0244] For example, the 1-1st scan signal SOS1-2, the 1-2nd scan signal SOS2-2, and the 2-1st scan signal SES1-2 may be output in the order of the 1-1st scan signal SOS1-2, the 1-2nd scan signal SOS2-2, and the 2-1st scan signal SES1-2.

[0245] One of the plurality of scan signals SOS1-2, SES1-2, SOS2-2, SES2-2, SOS3-2, SES3-2, SOS4-2, and SES4-2 may be supplied to one of the plurality of scan lines SO1 to SO4 and SE1 to SE4. A next scan signal output immediately after one of the plurality of scan signals SOS1-2, SES1-2, SOS2-2, SES2-2, SOS3-2, SES3-2, SOS4-2, and SES4-2 may be supplied to another scan line spaced apart from the one scan line, and at least one intervening scan line among the other scan lines SO1 to SO4 and SE1 to SE4 is interposed between the one scan line and the another scan line.

[0246] For example, the 1-4 scan signal SOS4-2 may be provided to the seventh scan line SO4. The 2-1 scan signal SES1-2 (which is the first signal output after the 1-4 scan signal SOS4-2) is provided to the second scan line SE1 (which is separated from the seventh scan line SO4 with at least one scan line (e.g., scan lines SO2, SE2, SO3, and SE3) interposed between the second scan line SE1 and the seventh scan line SO4).

[0247] According to an embodiment of the present disclosure, the activation periods of the scan signals on the adjacently positioned scan lines among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0248] exist Fig. 9A and Fig. 9B The operation of the scan driver SDV-2 is described in Fig. 6A The multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1 to SOm and SE1 to SEm. However, according to an embodiment of the present disclosure, the operation of the scan driver SDV-2 is not limited thereto. For example, Fig. 9B The operation of the scan driver SDV-2 can be applied to FIG. 6A to FIG. 6D The connection relationship between the multiple pixels PX and the multiple scanning lines SO1 to SOm and SE1 to SEm.

[0249] Fig. 10A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure. Fig. 10B is a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0250] Reference Figure 6C , Fig. 10A and Fig. 10B , the scan driver SDV- 3 may include a plurality of stages ST1 a - 3 to ST1 d - 3 and ST2 a - 3 to ST2 d - 3 and at least one dummy stage STDa - 3 or STDb - 3 .

[0251] The plurality of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3 may respectively output a plurality of scan signals SOS1-3, SES1-3, SOS2-3, SES2-3, SOS3-3, SES3-3, SOS4-3, and SES4-3. Each of the plurality of scan signals SOS1-3, SES1-3, SOS2-3, SES2-3, SOS3-3, SES3-3, SOS4-3, and SES4-3 may have a pulse width PDa greater than 2 horizontal periods and less than 3 horizontal periods. For example, the pulse width PDa may have 2.8 horizontal periods. The scan signals SOS1-3, SES1-3, SOS2-3, SES2-3, SOS3-3, SES3-3, SOS4-3 and SES4-3 output to the output terminals of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3 can be supplied to the corresponding scan lines and, at the same time, can be provided to the input terminals of the subsequent stages as start signals of the subsequent stages.

[0252] Each of the plurality of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3 may be connected to a clock line (not shown) to receive a clock signal whose phase is delayed by more than 2 horizontal periods from the clock line, and output a scan signal having a pulse width PDa greater than 2 horizontal periods to the corresponding scan line. In this case, 1 horizontal period 1H may be 1.47 microseconds (μs). The pulse width PDa may be greater than 2 horizontal periods and less than 3 horizontal periods. For example, the pulse width PDa may have 2.8 horizontal periods.

[0253] The plurality of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3 may include a first stage ST1a-3, a second stage ST2a-3, a third stage ST1b-3, a fourth stage ST2b-3, a fifth stage ST1c-3, a sixth stage ST2c-3, a seventh stage ST1d-3, and an eighth stage ST2d-3.

[0254] A plurality of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3 may belong to a connected first stage group STG1-3 or a second stage group STG2-3. Among the plurality of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3, the odd-numbered stages ST1a-3 to ST1d-3 may be defined as the first stage group STG1-3. For example, the first stage ST1a-3, the third stage ST1b-3, the fifth stage ST1c-3, and the seventh stage ST1d-3 may be defined as the first stage group STG1-3. Among the plurality of stages ST1a-3 to ST1d-3 and ST2a-3 to ST2d-3, the even-numbered stages ST2a-3 to ST2d-3 may be defined as the second stage group STG2-3. For example, the second stage ST2a-3, the fourth stage ST2b-3, the sixth stage ST2c-3, and the eighth stage ST2d-3 may be defined as the second stage group STG2-3.

[0255] The plurality of scan signals SOS1-3, SES1-3, SOS2-3, SES2-3, SOS3-3, SES3-3, SOS4-3, and SES4-3 may include a plurality of first scan signals SOS1-3, SOS2-3, SOS3-3, and SOS4-3 output from the first stage group STG1-3 and a plurality of second scan signals SES1-3, SES2-3, SES3-3, and SES4-3 output from the second stage group STG2-3. The plurality of first scan signals SOS1-3, SOS2-3, SOS3-3, and SOS4-3 may include a 1-1th scan signal SOS1-3, a 1-2th scan signal SOS2-3, a 1-3th scan signal SOS3-3, and a 1-4th scan signal SOS4-3. The plurality of second scan signals SES1-3, SES2-3, SES3-3, and SES4-3 may include a 2-1st scan signal SES1-3, a 2-2nd scan signal SES2-3, a 2-3rd scan signal SES3-3, and a 2-4th scan signal SES4-3.

[0256] The first stage ST1a-3 can be operated from the timing controller T-CON (see Figure 2 ) receives the first start signal SSP1a. The first stage ST1a-3 may be connected to the first scan line SO1-2. The first stage ST1a-3 may output a 1-1th scan signal SOS1-3.

[0257] The third stage ST1b-3 may be connected to the first stage ST1a-3. The third stage ST1b-3 may receive the 1-1st scan signal SOS1-3. The third stage ST1b-3 may be connected to the third scan line SO2-2. The third stage ST1b-3 may output the 1-2nd scan signal SOS2-3.

[0258] The fifth stage ST1c-3 may be connected to the third stage ST1b-3. The fifth stage ST1c-3 may receive the 1-2 nd scan signal SOS2-3. The fifth stage ST1c-3 may be connected to the fifth scan line SO3-2. The fifth stage ST1c-3 may output the 1-3 nd scan signal SOS3-3.

[0259] The seventh stage ST1d-3 may be connected to the fifth stage ST1c-3. The seventh stage ST1d-3 may receive the 1-3rd scan signal SOS3-3. The seventh stage ST1d-3 may be connected to the seventh scan line SO4-2. The seventh stage ST1d-3 may output the 1-4th scan signal SOS4-3.

[0260] The dummy stages STDa- 3 and STDb- 3 according to an embodiment of the present disclosure may belong to the second stage group STG2 - 3 .

[0261] The dummy stages STDa-3 and STDb-3 may include a first dummy stage STDa-3 and a second dummy stage STDb-3. The first dummy stage STDa-3 may be connected to the second dummy stage STDb-3. The second dummy stage STDb-3 may be connected to the second stage ST2a-3. The dummy stages STDa-3 and STDb-3 may be shifted by the timing at which the 2-1st scan signal SES1-3 is provided.

[0262] The first dummy stage STDa-3 can be controlled from the timing controller T-CON (see Figure 2 ) receives the second start signal SSP2a. The second start signal SSP2a may be output at a different time point from the first start signal SSP1a. For example, the second start signal SSP2a may be a signal shifted by 1 horizontal period 1H from the first start signal SSP1a. The first dummy stage STDa-3 may output the first dummy scan signal SDS1-3.

[0263] The second stage ST2a-3 may be connected to the second dummy stage STDb-3. The second stage ST2a-3 may receive the second dummy scan signal SDS2-3. The second stage ST2a-3 may be connected to the second scan line SE1-2. The second stage ST2a-3 may output the 2-1st scan signal SES1-3.

[0264] The fourth stage ST2b-3 may be connected to the second stage ST2a-3. The fourth stage ST2b-3 may receive the 2-1st scan signal SES1-3. The fourth stage ST2b-3 may be connected to the fourth scan line SE2-2. The fourth stage ST2b-3 may output the 2-2nd scan signal SES2-3.

[0265] The sixth stage ST2c-3 may be connected to the fourth stage ST2b-3. The sixth stage ST2c-3 may receive the 2-2nd scan signal SES2-3. The sixth stage ST2c-3 may be connected to the sixth scan line SE3-2. The sixth stage ST2c-3 may output the 2-3rd scan signal SES3-3.

[0266] The eighth stage ST2d-3 may be connected to the sixth stage ST2c-3. The eighth stage ST2d-3 may receive the 2nd-3rd scan signal SES3-3. The eighth stage ST2d-3 may be connected to the eighth scan line SE4-2. The eighth stage ST2d-3 may output the 2nd-4th scan signal SES4-3.

[0267] The 2-1 scan signal SES1-3 supplied to the second scan line SE1-2 may be delayed by 5 horizontal periods or more compared to the 1-1 scan signal SOS1-3 supplied to the first scan line SO1-2. For this reason, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1-2 to SO4-2 and SE1-2 to SE4-2 may not overlap with each other. For example, the activation period of the 2-1 scan signal SES1-3 supplied to the second scan line SE1-2 may not overlap with the activation periods of the 1-1 scan signal SOS1-3 supplied to the adjacent first scan line SO1-2 and the 1-2 scan signal SOS2-3 supplied to the adjacent third scan line SO2-2.

[0268] For example, the 1-1 scan signal SOS1-3, the 1-2 scan signal SOS2-3, and the 2-1 scan signal SES1-3 may be output in the order of the 1-1 scan signal SOS1-3, the 1-2 scan signal SOS2-3, and the 2-1 scan signal SES1-3. When the 1-1 scan signal SOS1-3 has a first activation period, the 2-1 scan signal SES1-3 has a second activation period, and the 1-2 scan signal SOS2-3 has a third activation period, the first activation period may at least partially overlap with the third activation period, but the second activation period may not overlap with the first activation period or the third activation period.

[0269] One of the plurality of scan signals SOS1-3, SES1-3, SOS2-3, SES2-3, SOS3-3, SES3-3, SOS4-3, and SES4-3 may be supplied to one of the plurality of scan lines SO1-2 to SO4-2 and SE1-2 to SE4-2. Another scan signal output immediately after one of the plurality of scan signals SOS1-3, SES1-3, SOS2-3, SES2-3, SOS3-3, SES3-3, SOS4-3, and SES4-3 may be supplied to another scan line spaced apart from the one scan line, and at least one intervening scan line among the other scan lines SO1-2 to SO4-2 and SE1-2 to SE4-2 is interposed between the one scan line and the another scan line.

[0270] For example, the 1-3 scan signal SOS3-3 may be provided to the fifth scan line SO3-2. The 2-1 scan signal SES1-3 (which is continuously output after the 1-3 scan signal SOS3-3) is provided to the second scan line SE1-2 (which is separated from the fifth scan line SO3-2 with at least one scan line (e.g., scan lines SE2-2 and SO2-2) interposed between the second scan line SE1-2 and the fifth scan line SO3-2).

[0271] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1-2 to SO4-2 and SE1-2 to SE4-2 may not overlap with each other. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0272] exist Fig. 10A and Fig. 10B The operation of the scan driver SDV-3 is described in Figure 6C The multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1 to SOm and SE1 to SEm. However, according to an embodiment of the present disclosure, the operation of the scan driver SDV-3 is not limited thereto. For example, Fig. 10B The operation of the scan driver SDV-3 can be applied to Figure 6C and Fig.6D The connection relationship between the multiple pixels PX and the multiple scanning lines SO1 to SOm and SE1 to SEm.

[0273] Fig.11A is a schematic block diagram of a scan driver according to an embodiment of the present disclosure. Fig. 11Bis a timing diagram illustrating the operation of a scan driver according to an embodiment of the present disclosure.

[0274] Reference Fig. 6A , Fig.11A and Fig. 11B , the scan driver SDV-4 may include a plurality of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4 and ST2a-4 to ST2d-4 that respectively provide scan signals SOS11-4, SES1-4, SOS21-4, SES2-4, SOS12-4, SES3-4, SOS22-4 and SES4-4 to a plurality of scan lines SO1, SE1, SO2, SE2, SO3, SE3, SO4 and SE4 and a plurality of dummy stages STDa-4, STDb-4, STDc-4 and STDd-4.

[0275] The plurality of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4 and ST2a-4 to ST2d-4 may include a first stage ST11a-4, a second stage ST2a-4, a third stage ST12a-4, a fourth stage ST2b-4, a fifth stage ST11b-4, a sixth stage ST2c-4, a seventh stage ST12b-4 and an eighth stage ST2d-4.

[0276] A plurality of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4, and ST2a-4 to ST2d-4 may belong to a connected first stage group STG1-4 or a second stage group STG2-4. Among the plurality of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4, and ST2a-4 to ST2d-4, odd-numbered stages ST11a-4, ST11b-4, ST12a-4, and ST12b-4 may be defined as a first stage group STG1-4. For example, a first stage ST11a-4, a third stage ST12a-4, a fifth stage ST11b-4, and a seventh stage ST12b-4 may be defined as a first stage group STG1-4.

[0277] The first stage group STG1-4 may be defined as a 1-1 stage group STG11 and a 1-2 stage group STG12. The 1-1 stage group STG11 may include some odd stages among the odd stages ST11a-4, ST11b-4, ST12a-4, and ST12b-4. For example, the 1-1 stage group STG11 may include the first stage ST11a-4 and the fifth stage ST11b-4. The 1-2 stage group STG12 may include other odd stages among the odd stages ST11a-4, ST11b-4, ST12a-4, and ST12b-4. For example, the 1-2 stage group STG12 may include the third stage ST12a-4 and the seventh stage ST12b-4.

[0278] Among the plurality of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4, and ST2a-4 to ST2d-4, the even-numbered stages ST2a-4 to ST2d-4 may be defined as a second stage group STG2-4. For example, the second stage ST2a-4, the fourth stage ST2b-4, the sixth stage ST2c-4, and the eighth stage ST2d-4 may be defined as a second stage group STG2-4.

[0279] A plurality of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4, and ST2a-4 to ST2d-4 may respectively output a plurality of scan signals SOS11-4, SES1-4, SOS21-4, SES2-4, SOS12-4, SES3-4, SOS22-4, and SES4-4. Each of the plurality of scan signals SOS11-4, SES1-4, SOS21-4, SES2-4, SOS12-4, SES3-4, SOS22-4, and SES4-4 may have a pulse width PDa greater than 2 horizontal periods and less than 3 horizontal periods. For example, the pulse width PDa may have 2.8 horizontal periods. The scan signals SOS11-4, SES1-4, SOS21-4, SES2-4, SOS12-4, SES3-4, SOS22-4 and SES4-4 output to the output terminals of stages ST11a-4, ST11b-4, ST12a-4, ST12b-4 and ST2a-4 to ST2d-4 can be supplied to the corresponding scan lines and, at the same time, can be provided to the input terminals of the subsequent stages as start signals of the subsequent stages.

[0280] The plurality of scan signals SOS11-4, SES1-4, SOS21-4, SES2-4, SOS12-4, SES3-4, SOS22-4 and SES4-4 may include a plurality of first scan signals SOS11-4, SOS12-4, SOS21-4 and SOS22-4 output from the first stage group STG1-4 and a plurality of second scan signals SES1-4, SES2-4, SES3-4 and SES4-4 output from the second stage group STG2-4.

[0281] The plurality of first scan signals SOS11-4, SOS12-4, SOS21-4, and SOS22-4 may include a plurality of first sub-scanning signals SOS11-4 and SOS12-4 output from the 1-1 stage group STG11 and a plurality of second sub-scanning signals SOS21-4 and SOS22-4 output from the 1-2 stage group STG12.

[0282] The plurality of first sub-scanning signals SOS11-4 and SOS12-4 may include a 1-1th scan signal SOS11-4 and a 1-3th scan signal SOS12-4. The plurality of second sub-scanning signals SOS21-4 and SOS22-4 may include a 1-2th scan signal SOS21-4 and a 1-4th scan signal SOS22-4.

[0283] The plurality of second scan signals SES1 - 4 , SES2 - 4 , SES3 - 4 , and SES4 - 4 may include a 2-1st scan signal SES1 - 4 , a 2-2nd scan signal SES2 - 4 , a 2-3rd scan signal SES3 - 4 , and a 2-4th scan signal SES4 - 4 .

[0284] A plurality of first scan signals SOS11-4, SOS12-4, SOS21-4, and SOS22-4 and a plurality of second scan signals SES1-4, SES2-4, SES3-4, and SES4-4 may be output alternately, respectively. In this case, first to n-th data signals corresponding to the first to m-th scan lines are sequentially applied to the data lines based on the plurality of scan signals SOS11-4, SES1-4, SOS21-4, SES2-4, SOS12-4, SES3-4, SOS22-4, and SES4-4.

[0285] Some of the dummy stages STDa-4, STDb-4, STDc-4, and STDd-4 may belong to the 1-2 stage group STG12, and other dummy stages of the dummy stages STDa-4, STDb-4, STDc-4, and STDd-4 may belong to the second stage group STG2-4. The dummy stages STDa-4, STDb-4, STDc-4, and STDd-4 may include a first dummy stage STDa-4, a second dummy stage STDb-4, a third dummy stage STDc-4, and a fourth dummy stage STDd-4.

[0286] The first dummy stage STDa-4 may be connected to the second dummy stage STDb-4. The second dummy stage STDb-4 may be connected to the third stage ST12a-4. The first dummy stage STDa-4 and the second dummy stage STDb-4 may be shifted by the timing at which the 1-2 nd scan signal SOS21-4 is supplied.

[0287] The third dummy stage STDc-4 may be connected to the fourth dummy stage STDd-4. The fourth dummy stage STDd-4 may be connected to the second stage ST2a-4. The third dummy stage STDc-4 and the fourth dummy stage STDd-4 may be shifted by the timing at which the 2-1st scan signal SES1-4 is supplied.

[0288] The first stage ST11a-4 can be controlled by the timing controller T-CON (see Figure 2 ) receives a 1-1th start signal SSP11a. The first stage ST11a-4 may be connected to the first scan line SO1. The first stage ST11a-4 may output a 1-1th scan signal SOS11-4.

[0289] The fifth stage ST11b-4 may be connected to the first stage ST11a-4. The fifth stage ST11b-4 may receive a 1-1st scan signal SOS11-4. The fifth stage ST11b-4 may be connected to a fifth scan line SO3. The fifth stage ST11b-4 may output a 1-3rd scan signal SOS12-4.

[0290] The first dummy stage STDa-4 can be controlled from the timing controller T-CON (see Figure 2 ) receives the 1-2 start signal SSP12a. However, this is an example. For example, the method of receiving the 1-2 start signal SSP12a according to the embodiment of the present disclosure is not limited thereto. For example, the 1-2 start signal SSP12a may be received from one of the stages included in the 1-1 stage group STG11. The first dummy stage STDa-4 may output the first dummy scan signal SDS1-4.

[0291] The second dummy stage STDb-4 may be connected to the first dummy stage STDa-4. The second dummy stage STDb-4 may receive the first dummy scan signal SDS1-4. The second dummy stage STDb-4 may output the second dummy scan signal SDS2-4.

[0292] The third stage ST12a-4 may be connected to the second dummy stage STDb-4. The third stage ST12a-4 may receive the second dummy scan signal SDS2-4. The third stage ST12a-4 may be connected to the third scan line SO2. The third stage ST12a-4 may output the 1-2 nd scan signal SOS21-4.

[0293] The seventh stage ST12b-4 may be connected to the third stage ST12a-4. The seventh stage ST12b-4 may receive the 1-2 nd scan signal SOS21-4. The seventh stage ST12b-4 may be connected to the seventh scan line SO4. The seventh stage ST12b-4 may output the 1-4 th scan signal SOS22-4.

[0294] The third dummy stage STDc-4 can be controlled from the timing controller T-CON (see Figure 2 ) receives the second start signal SSP2a. The third dummy stage STDc-4 may output a third dummy scan signal SDS3-4.

[0295] The fourth dummy stage STDd-4 may be connected to the third dummy stage STDc-4. The fourth dummy stage STDd-4 may receive the third dummy scan signal SDS3-4. The fourth dummy stage STDd-4 may output the fourth dummy scan signal SDS4-4.

[0296] The second stage ST2a-4 may be connected to the fourth dummy stage STDd-4. The second stage ST2a-4 may receive the fourth dummy scan signal SDS4-4. The second stage ST2a-4 may be connected to the second scan line SE1. The second stage ST2a-4 may output the 2-1st scan signal SES1-4.

[0297] The fourth stage ST2b-4 may be connected to the second stage ST2a-4. The fourth stage ST2b-4 may receive the 2-1st scan signal SES1-4. The fourth stage ST2b-4 may be connected to the fourth scan line SE2. The fourth stage ST2b-4 may output the 2-2nd scan signal SES2-4.

[0298] The sixth stage ST2c-4 may be connected to the fourth stage ST2b-4. The sixth stage ST2c-4 may receive the 2-2nd scan signal SES2-4. The sixth stage ST2c-4 may be connected to the sixth scan line SE3. The sixth stage ST2c-4 may output the 2-3rd scan signal SES3-4.

[0299] The eighth stage ST2d-4 may be connected to the sixth stage ST2c-4. The eighth stage ST2d-4 may receive the 2nd-3rd scan signal SES3-4. The eighth stage ST2d-4 may be connected to the eighth scan line SE4. The eighth stage ST2d-4 may output the 2nd-4th scan signal SES4-4.

[0300] The 2-1 scan signal SES1-4 supplied to the second scan line SE1 may be delayed by 5 horizontal periods or more compared to the 1-1 scan signal SOS11-4 supplied to the first scan line SO1. The 1-2 scan signal SOS21-4 supplied to the third scan line SO2 may be delayed by 10 horizontal periods or more compared to the 1-1 scan signal SOS11-4 supplied to the first scan line SO1. For this reason, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap. For example, the activation period of the 2-1 scan signal SES1-4 supplied to the second scan line SE1 may not overlap with the activation periods of the 1-1 scan signal SOS11-4 supplied to the adjacent first scan line SO1 and the 1-2 scan signal SOS21-4 supplied to the adjacent third scan line SO2.

[0301] For example, the 1-1 scan signal SOS11-4, the 1-2 scan signal SOS21-4, and the 2-1 scan signal SES1-4 may be output in the order of the 1-1 scan signal SOS11-4, the 2-1 scan signal SES1-4, and the 1-2 scan signal SOS21-4. When the 1-1 scan signal SOS11-4 has a first activation period, the 2-1 scan signal SES1-4 has a second activation period, and the 1-2 scan signal SOS21-4 has a third activation period, the first activation period, the second activation period, and the third activation period may not overlap with each other.

[0302] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO4 and SE1 to SE4 may not overlap with each other. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0303] exist Fig.11A and Fig. 11B The operation of the scan driver SDV-4 is described in Fig. 6A The multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1 to SOm and SE1 to SEm. However, according to an embodiment of the present disclosure, the operation of the scan driver SDV-4 is not limited thereto. For example, Fig. 11B The operation of the scan driver SDV-4 can be applied to Fig. 6A and Figure 6B The connection relationship between the multiple pixels PX and the multiple scanning lines SO1 to SOm and SE1 to SEm.

[0304] Fig.12 is a schematic block diagram of a scan driver according to an embodiment of the present disclosure.

[0305] Reference Fig. 6A and Fig.12 , the scan driver SDV-5 can operate as a shift register and can include multiple stages (for example, multiple stages ST1a to ST1c and ST2a to ST2c) that provide scan signals SOS1, SES1, SOS2, SES2, SOS3, SES3, SOS4 and SES4 to multiple scan lines SO1, SE1, SO2, SE2, SO3, SE3, SO4 and SE4, respectively.

[0306] Each of the plurality of stages ST1a to ST1c and ST2a to ST2c may be connected to a clock line (not shown) to receive a clock signal whose phase is delayed by more than 1 horizontal period from the clock line and output a scanning signal having a pulse width greater than 1 horizontal period to a corresponding scanning line. At this time, 1 horizontal period may be 1.47 μs, and the pulse width may be 1.8 horizontal periods.

[0307] The plurality of stages ST1a to ST1c and ST2a to ST2c may include a first stage ST1a, a second stage ST2a, a third stage ST1b, a fourth stage ST2b, a fifth stage ST1c, and a sixth stage ST2c.

[0308] A plurality of stages ST1a to ST1c and ST2a to ST2c may belong to a connected first stage group STG1-5 or a second stage group STG2-5. Among the plurality of stages ST1a to ST1c and ST2a to ST2c, the odd-numbered stages ST1a to ST1c may be defined as the first stage group STG1-5. For example, the first stage ST1a, the third stage ST1b, and the fifth stage ST1c may be defined as the first stage group STG1-5. Among the plurality of stages ST1a to ST1c and ST2a to ST2c, the even-numbered stages ST2a to ST2c may be defined as the second stage group STG2-5. For example, the second stage ST2a, the fourth stage ST2b, and the sixth stage ST2c may be defined as the second stage group STG2-5.

[0309] The plurality of stages ST1a to ST1c and ST2a to ST2c may output a plurality of scan signals SS1, SS2, SS3, SS4, SS5, and SS6, respectively. The scan signals SS1, SS2, SS3, SS4, SS5, and SS6 output to the output terminals of the stages ST1a to ST1c and ST2a to ST2c may be supplied to corresponding scan lines and may be supplied to input terminals of subsequent stages as start signals of the subsequent stages at the same time.

[0310] The plurality of scan signals SS1, SS2, SS3, SS4, SS5, and SS6 may include a plurality of first scan signals SS1, SS3, and SS5 output from the first stage group STG1-5 and a plurality of second scan signals SS2, SS4, and SS6 output from the second stage group STG2-5. The plurality of first scan signals SS1, SS3, and SS5 may include a 1-1st scan signal SS1, a 1-2nd scan signal SS3, and a 1-3rd scan signal SS5. The plurality of second scan signals SS2, SS4, and SS6 may include a 2-1st scan signal SS2, a 2-2nd scan signal SS4, and a 2-3rd scan signal SS6.

[0311] A plurality of first scan signals SS1, SS3 and SS5 and a plurality of second scan signals SS2, SS4 and SS6 may be output alternately, respectively. In this case, first to nth data signals corresponding to the first to mth scan lines are sequentially applied to the data lines based on the plurality of scan signals SS1 to SS6.

[0312] The second stage ST1a can be operated from the timing controller T-CON (see Figure 2 ) receives the first start signal SSP1. The first stage ST1a may output a 1-1th scan signal SS1.

[0313] The third stage ST1b may be connected to the first stage ST1a. The third stage ST1b may receive the 1-1th scan signal SS1. The third stage ST1b may output the 1-2th scan signal SS3.

[0314] The fifth stage ST1c may be connected to the third stage ST1b. The fifth stage ST1c may receive the 1-2 nd scan signal SS3. The fifth stage ST1c may output the 1-3 rd scan signal SS5.

[0315] The second stage ST2a can be operated from the timing controller T-CON (see Figure 2 ) receives the second start signal SSP2. The second start signal SSP2 may be output at a different time point from the first start signal SSP1. For example, the second start signal SSP2 may be a signal shifted by 1 horizontal period from the first start signal SSP1. The second stage ST2a may output the 2-1st scan signal SS2.

[0316] The fourth stage ST2b may be connected to the second stage ST2a. The fourth stage ST2b may receive the 2-1st scan signal SS2. The fourth stage ST2b may output the 2-2nd scan signal SS4.

[0317] The sixth stage ST2c may be connected to the fourth stage ST2b. The sixth stage ST2c may receive the 2-2nd scan signal SS4. The sixth stage ST2c may output the 2-3rd scan signal SS6.

[0318] When observed on the time axis, the scan driver SDV-5 can shift the 1-1 scan signal SS1, the 2-1 scan signal SS2, the 1-2 scan signal SS3, the 2-2 scan signal SS4, the 1-3 scan signal SS5, and the 2-3 scan signal SS6 in sequence by 1 horizontal period, and can output the shifted result. At this time, the 2-1 scan signal SS2 can be defined as being continuously output after the 1-1 scan signal SS1. The 1-2 scan signal SS3 can be defined as being continuously output after the 2-1 scan signal SS2. The 2-2 scan signal SS4 can be defined as being continuously output after the 1-2 scan signal SS3. The 1-3 scan signal SS5 can be defined as being continuously output after the 2-2 scan signal SS4. The 2-3 scan signal SS6 can be defined as being continuously output after the 1-3 scan signal SS5.

[0319] The scan driver SDV-5 can be electrically connected to the six pixels PX of one data line (see Figure 3 ) grouping to provide a scanning signal. However, this is an example. For example, the number of pixels included in a group according to an embodiment of the present disclosure is not limited thereto. For example, the number of pixels included in a group according to an embodiment of the present disclosure may be four or more.

[0320] The order of driving the first pixel PX1 to the sixth pixel PX6 may be defined as a plurality of patterns. For example, one of the plurality of patterns may be driven in the order of the third pixel PX3, the sixth pixel PX6, the second pixel PX2, the fifth pixel PX5, the fourth pixel PX4 and the first pixel PX1. This will be described later.

[0321] The scan driver SDV-5 can drive the plurality of pixels PX in units of six pixels by using each of the plurality of patterns as one cycle period (see Figure 3 ). In other words, the scan driver SDV-5 can drive the plurality of pixels PX while repeating one mode among the plurality of modes or mixing at least two modes among the plurality of modes.

[0322] The pixels may be arranged along an N-th line extending in the first direction DR1. In this case, "N" is a natural number greater than zero.

[0323] The scan line may extend along the (N+1)th line spaced apart from the Nth line in the negative second direction DR2 and extending in the first direction DR1. The next scan line may extend along the (N+2)th line spaced apart from the (N+1)th line in the negative second direction DR2 and extending in the first direction DR1.

[0324] Other pixels may be arranged along the (N+3)th line spaced apart from the (N+2)th line in the negative second direction DR2 and extending in the first direction DR1. The scan line may extend along the (N+4)th line spaced apart from the (N+3)th line in the negative second direction DR2 and extending in the first direction DR1.

[0325] The scan line may extend along the (N-1)th line spaced apart from the Nth line in the positive second direction DR2 and extending in the first direction DR1. The next scan line may extend along the (N-2)th line spaced apart from the (N-1)th line in the second direction DR2 and extending in the first direction DR1.

[0326] Other pixels may be arranged along the (N-3)th line spaced apart from the (N-2)th line in the second direction DR2 and extending in the first direction DR1. The next scan line may extend along the (N-4)th line spaced apart from the (N-3)th line in the second direction DR2 and extending in the first direction DR1.

[0327] In this case, the first scan signal output after outputting the scan signal for driving one of the pixels PX arranged on the Nth line may be output from the scan line extending along the front line of the (N-2)th line and the rear line of the (N+2)th line. For example, different scan signals may be output from the scan line extending along the (N+4)th line or the scan line extending along the (N-4)th line.

[0328] For example, the third pixel PX3 and the fourth pixel PX4 may be arranged along the Nth line. The first scan signal output after the scan signal for driving the third pixel PX3 is output may be output from the sixth scan line SE3 extending from the next scan line of the fifth scan line SO3 extending from the (N+2)th line. The next scan signal output continuously after the scan signal for driving the fourth pixel PX4 is output may be output from the first scan line SO1 extending from the previous scan line of the second scan line SE1 extending from the (N-2)th line.

[0329] In other words, when the scan driver SDV-5 outputs a scan signal and a next scan signal output after the scan signal, at least one scan line may be set between the scan line for providing the next scan signal and the scan line for providing the scan signal. For example, when the scan signal for driving the third pixel PX3 is output via the fourth scan line SE2, the scan signal output continuously after the scan signal may be output at the sixth scan line SE3. At this time, at least one scan line SO3 may be positioned between the fourth scan line SE2 and the sixth scan line SE3. Alternatively, when the scan signal for driving the fourth pixel PX4 is output via the third scan line SO2, the next scan signal output continuously after the scan signal may be output at the first scan line SO1. At this time, at least one scan line SE1 may be positioned between the first scan line SO1 and the third scan line SO2.

[0330] FIG. 13A to FIG. 13H is a timing diagram illustrating an operation of a scan driver driven by one mode among a plurality of modes according to an embodiment of the present disclosure.

[0331] The plurality of modes may include a first mode, a second mode, a third mode, a fourth mode, a fifth mode, a sixth mode, a seventh mode, and an eighth mode having different driving orders. FIG. 13A to FIG. 13H It is shown that the plurality of modes include 8 modes including the first mode to the eighth mode. However, the number of modes according to the embodiment of the present disclosure is not limited thereto. For example, the number of modes can be provided in a variety of ways as long as the display quality degradation caused by the kickback voltage can be prevented.

[0332] Reference Fig. 6A , Fig.12 and Fig.13A Each of the plurality of scan signals SS1 to SS6 may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0333] The first mode among the plurality of modes may be driven in the order of the third pixel PX3 , the sixth pixel PX6 , the second pixel PX2 , the fifth pixel PX5 , the fourth pixel PX4 , and the first pixel PX1 .

[0334] The first stage ST1a may output a 1-1th scan signal SS1. The first stage ST1a may be connected to the fourth scan line SE2. The 1-1th scan signal SS1 may be provided to the fourth scan line SE2. The third pixel PX3 may be driven in response to the 1-1th scan signal SS1.

[0335] The second stage ST2a may output a 2-1st scan signal SS2. The second stage ST2a may be connected to the sixth scan line SE3. The 2-1st scan signal SS2 may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 2-1st scan signal SS2.

[0336] The third stage ST1b may output a 1-2 th scan signal SS3. The third stage ST1b may be connected to the second scan line SE1. The 1-2 th scan signal SS3 may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 1-2 th scan signal SS3.

[0337] The fourth stage ST2b may output a 2-2nd scan signal SS4. The fourth stage ST2b may be connected to the fifth scan line SO3. The 2-2nd scan signal SS4 may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 2-2nd scan signal SS4.

[0338] The fifth stage ST1c may output the 1-3rd scan signal SS5. The fifth stage ST1c may be connected to the third scan line SO2. The 1-3rd scan signal SS5 may be provided to the third scan line SO2. The fourth pixel PX4 may be driven in response to the 1-3rd scan signal SS5.

[0339] The sixth stage ST2c may output a 2-3rd scan signal SS6. The sixth stage ST2c may be connected to the first scan line SO1. The 2-3rd scan signal SS6 may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 2-3rd scan signal SS6.

[0340] Unlike the embodiment of the present disclosure, the second scanning signal supplied to the second scanning line SE1 may be affected by the first scanning signal supplied to the first scanning line SO1 by the first parasitic capacitor CP1, and may be affected by the third scanning signal supplied to the third scanning line SO2 by the second parasitic capacitor CP2. For example, when the second scanning signal has an on-level, in the case where the level of the first scanning signal is simultaneously changed from the on-level to the off-level, the driving transistor T1 (see Figure 5 ) may be changed by the first parasitic capacitor CP1. In addition, when the third scanning signal has an on-level, in the case where the level of the second scanning signal is simultaneously changed from the on-level to the off-level, the driving transistor T1 (see Figure 5 ) may be changed by the second parasitic capacitor CP2. That is, when the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 overlap with each other at the same time, the driving transistor T1 (see Figure 5 ) may be affected. As a result, a brightness difference may occur between the plurality of pixels PX1 to PX6 electrically connected to the plurality of scan lines SO1 to SO3 and SE1 to SE3. However, according to an embodiment of the present disclosure, activation periods of scan signals of mutually adjacent scan lines among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other at the same time. The influence of a parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. A decrease in display quality due to a kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0341] Reference Fig. 6A , Fig.12 and Fig. 13B Each of the plurality of scan signals SS1a to SS6a may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0342] The second mode among the plurality of modes may be driven in the order of the sixth pixel PX6 , the second pixel PX2 , the fourth pixel PX4 , the first pixel PX1 , the fifth pixel PX5 , and the third pixel PX3 .

[0343] The first stage ST1a may output a 1-1th scan signal SS1a. The first stage ST1a may be connected to the sixth scan line SE3. The 1-1th scan signal SS1a may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 1-1th scan signal SS1a.

[0344] The second stage ST2a may output a 2-1st scan signal SS2a. The second stage ST2a may be connected to the second scan line SE1. The 2-1st scan signal SS2a may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 2-1st scan signal SS2a.

[0345] The third stage ST1b may output a 1-2nd scan signal SS3a. The third stage ST1b may be connected to the fourth scan line SE2. The 1-2nd scan signal SS3a may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 1-2nd scan signal SS3a.

[0346] The fourth stage ST2b may output a 2-2nd scan signal SS4a. The fourth stage ST2b may be connected to the first scan line SO1. The 2-2nd scan signal SS4a may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 2-2nd scan signal SS4a.

[0347] The fifth stage ST1c may output the 1-3rd scan signal SS5a. The fifth stage ST1c may be connected to the fifth scan line SO3. The 1-3rd scan signal SS5a may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 1-3rd scan signal SS5a.

[0348] The sixth stage ST2c may output a 2-3rd scan signal SS6a. The sixth stage ST2c may be connected to the third scan line SO2. The 2-3rd scan signal SS6a may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 2-3rd scan signal SS6a.

[0349] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other at the same time. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0350] Reference Fig. 6A , Fig.12 and Fig. 13C Each of the plurality of scan signals SS1b to SS6b may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0351] The third mode among the plurality of modes may be driven in the order of the second pixel PX2 , the fourth pixel PX4 , the sixth pixel PX6 , the third pixel PX3 , the first pixel PX1 , and the fifth pixel PX5 .

[0352] The first stage ST1a may output a 1-1th scan signal SS1b. The first stage ST1a may be connected to the second scan line SE1. The 1-1th scan signal SS1b may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 1-1th scan signal SS1b.

[0353] The second stage ST2a may output a 2-1st scan signal SS2b. The second stage ST2a may be connected to the fourth scan line SE2. The 2-1st scan signal SS2b may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 2-1st scan signal SS2b.

[0354] The third stage ST1b may output a 1-2nd scan signal SS3b. The third stage ST1b may be connected to the sixth scan line SE3. The 1-2nd scan signal SS3b may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 1-2nd scan signal SS3b.

[0355] The fourth stage ST2b may output a 2-2nd scan signal SS4b. The fourth stage ST2b may be connected to the third scan line SO2. The 2-2nd scan signal SS4b may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 2-2nd scan signal SS4b.

[0356] The fifth stage ST1c may output the 1st-3rd scan signal SS5b. The fifth stage ST1c may be connected to the first scan line SO1. The 1st-3rd scan signal SS5b may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 1st-3rd scan signal SS5b.

[0357] The sixth stage ST2c may output a 2-3rd scan signal SS6b. The sixth stage ST2c may be connected to the fifth scan line SO3. The 2-3rd scan signal SS6b may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 2-3rd scan signal SS6b.

[0358] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other. In this way, the influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0359] Reference Fig. 6A , Fig.12 and Fig.13D Each of the plurality of scan signals SS1c to SS6c may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0360] A fourth mode among the plurality of modes may be driven in the order of the second pixel PX2 , the fourth pixel PX4 , the sixth pixel PX6 , the first pixel PX1 , the fifth pixel PX5 , and the third pixel PX3 .

[0361] The first stage ST1a may output a 1-1th scan signal SS1c. The first stage ST1a may be connected to the second scan line SE1. The 1-1th scan signal SS1c may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 1-1th scan signal SS1c.

[0362] The second stage ST2a may output a 2-1st scan signal SS2c. The second stage ST2a may be connected to the fourth scan line SE2. The 2-1st scan signal SS2c may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 2-1st scan signal SS2c.

[0363] The third stage ST1b may output a 1-2nd scan signal SS3c. The third stage ST1b may be connected to the sixth scan line SE3. The 1-2nd scan signal SS3c may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 1-2nd scan signal SS3c.

[0364] The fourth stage ST2b may output a 2-2nd scan signal SS4c. The fourth stage ST2b may be connected to the first scan line SO1. The 2-2nd scan signal SS4c may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 2-2nd scan signal SS4c.

[0365] The fifth stage ST1c may output a 1-3rd scan signal SS5c. The fifth stage ST1c may be connected to the fifth scan line SO3. The 1-3rd scan signal SS5c may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 1-3rd scan signal SS5c.

[0366] The sixth stage ST2c may output a 2-3rd scan signal SS6c. The sixth stage ST2c may be connected to the third scan line SO2. The 2-3rd scan signal SS6c may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 2-3rd scan signal SS6c.

[0367] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other. In this way, the influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0368] Reference Fig. 6A , Fig.12 and Fig.13EEach of the plurality of scan signals SS1d to SS6d may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0369] A fifth mode among the plurality of modes may be driven in the order of the fifth pixel PX5 , the third pixel PX3 , the first pixel PX1 , the fourth pixel PX4 , the sixth pixel PX6 , and the second pixel PX2 .

[0370] The first stage ST1a may output a 1-1th scan signal SS1d. The first stage ST1a may be connected to the fifth scan line SO3. The 1-1th scan signal SS1d may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 1-1th scan signal SS1d.

[0371] The second stage ST2a may output a 2-1st scan signal SS2d. The second stage ST2a may be connected to the third scan line SO2. The 2-1st scan signal SS2d may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 2-1st scan signal SS2d.

[0372] The third stage ST1b may output a 1-2nd scan signal SS3d. The third stage ST1b may be connected to the first scan line SO1. The 1-2nd scan signal SS3d may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 1-2nd scan signal SS3d.

[0373] The fourth stage ST2b may output a 2-2nd scan signal SS4d. The fourth stage ST2b may be connected to the fourth scan line SE2. The 2-2nd scan signal SS4d may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 2-2nd scan signal SS4d.

[0374] The fifth stage ST1c may output the 1-3rd scan signal SS5d. The fifth stage ST1c may be connected to the sixth scan line SE3. The 1-3rd scan signal SS5d may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 1-3rd scan signal SS5d.

[0375] The sixth stage ST2c may output a 2nd-3rd scan signal SS6d. The sixth stage ST2c may be connected to the second scan line SE1. The 2nd-3rd scan signal SS6d may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 2nd-3rd scan signal SS6d.

[0376] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0377] Reference Fig. 6A , Fig.12 and Fig.13F Each of the plurality of scan signals SS1e to SS6e may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0378] A sixth mode among the plurality of modes may be driven in the order of the fifth pixel PX5 , the third pixel PX3 , the first pixel PX1 , the sixth pixel PX6 , the second pixel PX2 , and the fourth pixel PX4 .

[0379] The first stage ST1a may output a 1-1th scan signal SS1e. The first stage ST1a may be connected to the fifth scan line SO3. The 1-1th scan signal SS1e may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 1-1th scan signal SS1e.

[0380] The second stage ST2a may output a 2-1st scan signal SS2e. The second stage ST2a may be connected to the third scan line SO2. The 2-1st scan signal SS2e may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 2-1st scan signal SS2e.

[0381] The third stage ST1b may output a 1-2nd scan signal SS3e. The third stage ST1b may be connected to the first scan line SO1. The 1-2nd scan signal SS3e may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 1-2nd scan signal SS3e.

[0382] The fourth stage ST2b may output a 2-2nd scan signal SS4e. The fourth stage ST2b may be connected to the sixth scan line SE3. The 2-2nd scan signal SS4e may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 2-2nd scan signal SS4e.

[0383] The fifth stage ST1c may output the 1st-3rd scan signal SS5e. The fifth stage ST1c may be connected to the second scan line SE1. The 1st-3rd scan signal SS5e may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 1st-3rd scan signal SS5e.

[0384] The sixth stage ST2c may output a 2-3rd scan signal SS6e. The sixth stage ST2c may be connected to the fourth scan line SE2. The 2-3rd scan signal SS6e may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 2-3rd scan signal SS6e.

[0385] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0386] Reference Fig. 6A , Fig.12 and Figure 13G Each of the plurality of scan signals SS1f to SS6f may have a pulse width greater than 1 horizontal period 1H and less than 2 horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0387] A seventh mode among the plurality of modes may be driven in the order of the third pixel PX3 , the first pixel PX1 , the fifth pixel PX5 , the second pixel PX2 , the fourth pixel PX4 , and the sixth pixel PX6 .

[0388] The first stage ST1a may output a 1-1th scan signal SS1f. The first stage ST1a may be connected to the third scan line SO2. The 1-1th scan signal SS1f may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 1-1th scan signal SS1f.

[0389] The second stage ST2a may output a 2-1st scan signal SS2f. The second stage ST2a may be connected to the first scan line SO1. The 2-1st scan signal SS2f may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 2-1st scan signal SS2f.

[0390] The third stage ST1b may output a 1-2nd scan signal SS3f. The third stage ST1b may be connected to the fifth scan line SO3. The 1-2nd scan signal SS3f may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 1-2nd scan signal SS3f.

[0391] The fourth stage ST2b may output a 2-2nd scan signal SS4f. The fourth stage ST2b may be connected to the second scan line SE1. The 2-2nd scan signal SS4f may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 2-2nd scan signal SS4f.

[0392] The fifth stage ST1c may output the 1-3rd scan signal SS5f. The fifth stage ST1c may be connected to the fourth scan line SE2. The 1-3rd scan signal SS5f may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 1-3rd scan signal SS5f.

[0393] The sixth stage ST2c may output a 2-3rd scan signal SS6f. The sixth stage ST2c may be connected to the sixth scan line SE3. The 2-3rd scan signal SS6f may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 2-3rd scan signal SS6f.

[0394] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other. The influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0395] Reference Fig. 6A , Fig.12 and Fig.13H Each of the plurality of scan signals SS1g to SS6g may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0396] An eighth mode among the plurality of modes may be driven in the order of the first pixel PX1 , the fifth pixel PX5 , the third pixel PX3 , the sixth pixel PX6 , the fourth pixel PX4 , and the second pixel PX2 .

[0397] The first stage ST1a may output a 1-1th scan signal SS1g. The first stage ST1a may be connected to the first scan line SO1. The 1-1th scan signal SS1g may be provided to the first scan line SO1. The first pixel PX1 may be driven in response to the 1-1th scan signal SS1g.

[0398] The second stage ST2a may output a 2-1st scan signal SS2g. The second stage ST2a may be connected to the fifth scan line SO3. The 2-1st scan signal SS2g may be provided to the fifth scan line SO3. The fifth pixel PX5 may be driven in response to the 2-1st scan signal SS2g.

[0399] The third stage ST1b may output a 1-2nd scan signal SS3g. The third stage ST1b may be connected to the third scan line SO2. The 1-2nd scan signal SS3g may be provided to the third scan line SO2. The third pixel PX3 may be driven in response to the 1-2nd scan signal SS3g.

[0400] The fourth stage ST2b may output a 2-2nd scan signal SS4g. The fourth stage ST2b may be connected to the sixth scan line SE3. The 2-2nd scan signal SS4g may be provided to the sixth scan line SE3. The sixth pixel PX6 may be driven in response to the 2-2nd scan signal SS4g.

[0401] The fifth stage ST1c may output the 1-3rd scan signal SS5g. The fifth stage ST1c may be connected to the fourth scan line SE2. The 1-3rd scan signal SS5g may be provided to the fourth scan line SE2. The fourth pixel PX4 may be driven in response to the 1-3rd scan signal SS5g.

[0402] The sixth stage ST2c may output a 2nd-3rd scan signal SS6g. The sixth stage ST2c may be connected to the second scan line SE1. The 2nd-3rd scan signal SS6g may be provided to the second scan line SE1. The second pixel PX2 may be driven in response to the 2nd-3rd scan signal SS6g.

[0403] According to an embodiment of the present disclosure, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines SO1 to SO3 and SE1 to SE3 may not overlap with each other. In this way, the influence of the parasitic capacitor formed between one scan line and another adjacent scan line may be reduced or prevented. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0404] exist Fig.13A and Fig. 13B The operation of the scan driver SDV-5 is described in Fig. 6AThe multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1 to SO3 and SE1 to SE3. However, according to the embodiment of the present disclosure, the operation of the scan driver SDV-5 is not limited thereto. For example, FIG. 13A to FIG. 13H The operation of the scan driver SDV-5 can be applied to Fig. 6A and Figure 6B The connection relationship between multiple pixels PX and multiple scanning lines SO1 to SO3 and SE1 to SE3.

[0405] FIG. 14A to FIG. 14F is a timing diagram illustrating an operation of a scan driver driven by one mode among a plurality of modes according to an embodiment of the present disclosure.

[0406] The plurality of modes may include a 1-1th mode, a 2-1th mode, a 3-1th mode, a 4-1th mode, a 5-1th mode, and a 6-1th mode having different driving orders. FIG. 14A to FIG. 14F The plurality of modes are shown to include 6 modes including the 1-1th mode to the 6-1th mode. However, the number of modes according to the embodiments of the present disclosure is not limited thereto. For example, the number of modes may be provided in a variety of ways as long as the display quality degradation caused by the kickback voltage can be prevented.

[0407] Reference Figure 6C , Fig.12 and Fig.14A Each of the plurality of scan signals SS1-1 to SS6-1 may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0408] The 1-1th mode among the plurality of modes may be driven in the order of the fourth pixel PX4 - 2 , the sixth pixel PX6 - 2 , the second pixel PX2 - 2 , the fifth pixel PX5 - 2 , the first pixel PX1 - 2 , and the third pixel PX3 - 2 .

[0409] The first stage ST1a may output a 1-1th scan signal SS1-1. The first stage ST1a may be connected to the fourth scan line SE2-2. The 1-1th scan signal SS1-1 may be provided to the fourth scan line SE2-2. The fourth pixel PX4-2 may be driven in response to the 1-1th scan signal SS1-1.

[0410] The second stage ST2a may output a 2-1st scan signal SS2-1. The second stage ST2a may be connected to the sixth scan line SE3-2. The 2-1st scan signal SS2-1 may be provided to the sixth scan line SE3-2. The sixth pixel PX6-2 may be driven in response to the 2-1st scan signal SS2-1.

[0411] The third stage ST1b may output a 1-2nd scan signal SS3-1. The third stage ST1b may be connected to the second scan line SE1-2. The 1-2nd scan signal SS3-1 may be provided to the second scan line SE1-2. The second pixel PX2-2 may be driven in response to the 1-2nd scan signal SS3-1.

[0412] The fourth stage ST2b may output a 2-2nd scan signal SS4-1. The fourth stage ST2b may be connected to the fifth scan line SO3-2. The 2-2nd scan signal SS4-1 may be provided to the fifth scan line SO3-2. The fifth pixel PX5-2 may be driven in response to the 2-2nd scan signal SS4-1.

[0413] The fifth stage ST1c may output a 1-3rd scan signal SS5-1. The fifth stage ST1c may be connected to the first scan line SO1-2. The 1-3rd scan signal SS5-1 may be provided to the first scan line SO1-2. The first pixel PX1-2 may be driven in response to the 1-3rd scan signal SS5-1.

[0414] The sixth stage ST2c may output a 2-3rd scan signal SS6-1. The sixth stage ST2c may be connected to the third scan line SO2-2. The 2-3rd scan signal SS6-1 may be provided to the third scan line SO2-2. The third pixel PX3-2 may be driven in response to the 2-3rd scan signal SS6-1.

[0415] According to an embodiment of the present disclosure, scan lines receiving scan signals having activation periods overlapping each other may be spaced apart from each other by a predetermined distance or more to reduce or eliminate parasitic capacitors CP1 and CP2 (see Fig. 6A ). The predetermined interval may be 50 μm. The scan driver SDV-5 may be driven so that the distance between the scan lines whose activation periods of the scan signals overlap each other at the same time satisfies the predetermined interval or a larger interval. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0416] Reference Figure 6C , Fig.12 and Fig. 14B Each of the plurality of scan signals SS1-2 to SS6-2 may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0417] The 2-1th mode among the plurality of modes may be driven in the order of the fourth pixel PX4 - 2 , the sixth pixel PX6 - 2 , the second pixel PX2 - 2 , the third pixel PX3 - 2 , the fifth pixel PX5 - 2 , and the first pixel PX1 - 2 .

[0418] The first stage ST1a may output a 1-1th scan signal SS1-2. The first stage ST1a may be connected to the fourth scan line SE2-2. The 1-1th scan signal SS1-2 may be provided to the fourth scan line SE2-2. The fourth pixel PX4-2 may be driven in response to the 1-1th scan signal SS1-2.

[0419] The second stage ST2a may output a 2-1st scan signal SS2-2. The second stage ST2a may be connected to the sixth scan line SE3-2. The 2-1st scan signal SS2-2 may be provided to the sixth scan line SE3-2. The sixth pixel PX6-2 may be driven in response to the 2-1st scan signal SS2-2.

[0420] The third stage ST1b may output a 1-2nd scan signal SS3-2. The third stage ST1b may be connected to the second scan line SE1-2. The 1-2nd scan signal SS3-2 may be provided to the second scan line SE1-2. The second pixel PX2-2 may be driven in response to the 1-2nd scan signal SS3-2.

[0421] The fourth stage ST2b may output a 2-2nd scan signal SS4-2. The fourth stage ST2b may be connected to the third scan line SO2-2. The 2-2nd scan signal SS4-2 may be provided to the third scan line SO2-2. The third pixel PX3-2 may be driven in response to the 2-2nd scan signal SS4-2.

[0422] The fifth stage ST1c may output a 1-3rd scan signal SS5-2. The fifth stage ST1c may be connected to the fifth scan line SO3-2. The 1-3rd scan signal SS5-2 may be provided to the fifth scan line SO3-2. The fifth pixel PX5-2 may be driven in response to the 1-3rd scan signal SS5-2.

[0423] The sixth stage ST2c may output a 2-3rd scan signal SS6-2. The sixth stage ST2c may be connected to the first scan line SO1-2. The 2-3rd scan signal SS6-2 may be provided to the first scan line SO1-2. The first pixel PX1-2 may be driven in response to the 2-3rd scan signal SS6-2.

[0424] According to an embodiment of the present disclosure, scan lines receiving scan signals having activation periods overlapping each other may be spaced apart from each other by a predetermined distance or more to reduce or eliminate parasitic capacitors CP1 and CP2 (see Fig. 6A). The predetermined interval may be 50 μm. The scan driver SDV-5 may be driven so that the distance between the scan lines receiving the scan signals having activation periods overlapping each other satisfies the predetermined minimum interval. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD with improved display quality may be provided (see Figure 1 ).

[0425] Reference Figure 6C , Fig.12 and Fig. 14C Each of the plurality of scan signals SS1-3 to SS6-3 may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0426] The 3-1st mode among the plurality of modes may be driven in the order of the sixth pixel PX6 - 2 , the second pixel PX2 - 2 , the fourth pixel PX4 - 2 , the fifth pixel PX5 - 2 , the first pixel PX1 - 2 , and the third pixel PX3 - 2 .

[0427] The first stage ST1a may output a 1-1th scan signal SS1-3. The first stage ST1a may be connected to the sixth scan line SE3-2. The 1-1th scan signal SS1-3 may be provided to the sixth scan line SE3-2. The sixth pixel PX6-2 may be driven in response to the 1-1th scan signal SS1-3.

[0428] The second stage ST2a may output a 2-1st scan signal SS2-3. The second stage ST2a may be connected to the second scan line SE1-2. The 2-1st scan signal SS2-3 may be provided to the second scan line SE1-2. The second pixel PX2-2 may be driven in response to the 2-1st scan signal SS2-3.

[0429] The third stage ST1b may output a 1-2nd scan signal SS3-3. The third stage ST1b may be connected to the fourth scan line SE2-2. The 1-2nd scan signal SS3-3 may be provided to the fourth scan line SE2-2. The fourth pixel PX4-2 may be driven in response to the 1-2nd scan signal SS3-3.

[0430] The fourth stage ST2b may output a 2-2nd scan signal SS4-3. The fourth stage ST2b may be connected to the fifth scan line SO3-2. The 2-2nd scan signal SS4-3 may be provided to the fifth scan line SO3-2. The fifth pixel PX5-2 may be driven in response to the 2-2nd scan signal SS4-3.

[0431] The fifth stage ST1c may output a 1-3rd scan signal SS5-3. The fifth stage ST1c may be connected to the first scan line SO1-2. The 1-3rd scan signal SS5-3 may be provided to the first scan line SO1-2. The first pixel PX1-2 may be driven in response to the 1-3rd scan signal SS5-3.

[0432] The sixth stage ST2c may output a 2-3rd scan signal SS6-3. The sixth stage ST2c may be connected to the third scan line SO2-2. The 2-3rd scan signal SS6-3 may be provided to the third scan line SO2-2. The third pixel PX3-2 may be driven in response to the 2-3rd scan signal SS6-3.

[0433] According to an embodiment of the present disclosure, scan lines receiving scan signals having activation periods overlapping each other may be spaced apart from each other by a predetermined distance or more to reduce or eliminate parasitic capacitors CP1 and CP2 (see Fig. 6A ). The predetermined minimum distance may be 50 μm. The scan driver SDV-5 may be driven so that the distance between the scan lines receiving the scan signals having overlapping activation periods satisfies the predetermined minimum interval. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD having improved display quality may be provided (see Figure 1 ).

[0434] Reference Figure 6C , Fig.12 and Fig.14D Each of the plurality of scan signals SS1-4 to SS6-4 may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0435] The 4-1st mode among the plurality of modes may be driven in the order of the fifth pixel PX5-2, the first pixel PX1-2, the third pixel PX3-2, the sixth pixel PX6-2, the second pixel PX2-2, and the fourth pixel PX4-2.

[0436] The first stage ST1a may output a 1-1th scan signal SS1-4. The first stage ST1a may be connected to the fifth scan line SO3-2. The 1-1th scan signal SS1-4 may be provided to the fifth scan line SO3-2. The fifth pixel PX5-2 may be driven in response to the 1-1th scan signal SS1-4.

[0437] The second stage ST2a may output a 2-1st scan signal SS2-4. The second stage ST2a may be connected to the first scan line SO1-2. The 2-1st scan signal SS2-4 may be provided to the first scan line SO1-2. The first pixel PX1-2 may be driven in response to the 2-1st scan signal SS2-4.

[0438] The third stage ST1b may output a 1-2nd scan signal SS3-4. The third stage ST1b may be connected to the third scan line SO2-2. The 1-2nd scan signal SS3-4 may be provided to the third scan line SO2-2. The third pixel PX3-2 may be driven in response to the 1-2nd scan signal SS3-4.

[0439] The fourth stage ST2b may output a 2-2nd scan signal SS4-4. The fourth stage ST2b may be connected to the sixth scan line SE3-2. The 2-2nd scan signal SS4-4 may be provided to the sixth scan line SE3-2. The sixth pixel PX6-2 may be driven in response to the 2-2nd scan signal SS4-4.

[0440] The fifth stage ST1c may output a 1-3rd scan signal SS5-4. The fifth stage ST1c may be connected to the second scan line SE1-2. The 1-3rd scan signal SS5-4 may be provided to the second scan line SE1-2. The second pixel PX2-2 may be driven in response to the 1-3rd scan signal SS5-4.

[0441] The sixth stage ST2c may output a 2-3rd scan signal SS6-4. The sixth stage ST2c may be connected to the fourth scan line SE2-2. The 2-3rd scan signal SS6-4 may be provided to the fourth scan line SE2-2. The fourth pixel PX4-2 may be driven in response to the 2-3rd scan signal SS6-4.

[0442] According to an embodiment of the present disclosure, scan lines receiving scan signals having activation periods overlapping each other may be spaced apart from each other by a predetermined distance or more to reduce or eliminate parasitic capacitors CP1 and CP2 (see Fig. 6A ). The predetermined minimum distance may be 50 μm. The scan driver SDV-5 may be driven so that the distance between the scan lines receiving the scan signals having overlapping activation periods satisfies the predetermined minimum distance. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD having improved display quality may be provided (see Figure 1 ).

[0443] Reference Figure 6C , Fig.12 and Fig.14EEach of the plurality of scan signals SS1-5 to SS6-5 may have a pulse width greater than 1 horizontal period 1H and less than 2 horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0444] The 5-1st mode among the plurality of modes may be driven in the order of the third pixel PX3 - 2 , the fifth pixel PX5 - 2 , the first pixel PX1 - 2 , the fourth pixel PX4 - 2 , the sixth pixel PX6 - 2 , and the second pixel PX2 - 2 .

[0445] The first stage ST1a may output a 1-1th scan signal SS1-5. The first stage ST1a may be connected to the third scan line SO2-2. The 1-1th scan signal SS1-5 may be provided to the third scan line SO2-2. The third pixel PX3-2 may be driven in response to the 1-1th scan signal SS1-5.

[0446] The second stage ST2a may output a 2-1st scan signal SS2-5. The second stage ST2a may be connected to the fifth scan line SO3-2. The 2-1st scan signal SS2-5 may be provided to the fifth scan line SO3-2. The fifth pixel PX5-2 may be driven in response to the 2-1st scan signal SS2-5.

[0447] The third stage ST1b may output a 1-2nd scan signal SS3-5. The third stage ST1b may be connected to the first scan line SO1-2. The 1-2nd scan signal SS3-5 may be provided to the first scan line SO1-2. The first pixel PX1-2 may be driven in response to the 1-2nd scan signal SS3-5.

[0448] The fourth stage ST2b may output a 2-2nd scan signal SS4-5. The fourth stage ST2b may be connected to the fourth scan line SE2-2. The 2-2nd scan signal SS4-5 may be provided to the fourth scan line SE2-2. The fourth pixel PX4-2 may be driven in response to the 2-2nd scan signal SS4-5.

[0449] The fifth stage ST1c may output a 1-3rd scan signal SS5-5. The fifth stage ST1c may be connected to the sixth scan line SE3-2. The 1-3rd scan signal SS5-5 may be provided to the sixth scan line SE3-2. The sixth pixel PX6-2 may be driven in response to the 1-3rd scan signal SS5-5.

[0450] The sixth stage ST2c may output a 2-3rd scan signal SS6-5. The sixth stage ST2c may be connected to the second scan line SE1-2. The 2-3rd scan signal SS6-5 may be provided to the second scan line SE1-2. The second pixel PX2-2 may be driven in response to the 2-3rd scan signal SS6-5.

[0451] According to an embodiment of the present disclosure, scan lines receiving scan signals having activation periods overlapping each other may be spaced apart from each other by a predetermined minimum distance to reduce or eliminate parasitic capacitors CP1 and CP2 (see Fig. 6A ). The predetermined minimum distance may be 50 μm. The scan driver SDV-5 may be driven so that the distance between the scan lines receiving the scan signals having overlapping activation periods satisfies the predetermined minimum distance. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD having improved display quality may be provided (see Figure 1 ).

[0452] Reference Figure 6C , Fig.12 and Fig.14F Each of the plurality of scan signals SS1-6 to SS6-6 may have a pulse width greater than one horizontal period 1H and less than two horizontal periods. For example, the pulse width may have 1.8 horizontal periods.

[0453] The 6-1th mode among the plurality of modes may be driven in the order of the third pixel PX3 - 2 , the fifth pixel PX5 - 2 , the first pixel PX1 - 2 , the sixth pixel PX6 - 2 , the second pixel PX2 - 2 , and the fourth pixel PX4 - 2 .

[0454] The first stage ST1a may output a 1-1th scan signal SS1-6. The first stage ST1a may be connected to the third scan line SO2-2. The 1-1th scan signal SS1-6 may be provided to the third scan line SO2-2. The third pixel PX3-2 may be driven in response to the 1-1th scan signal SS1-6.

[0455] The second stage ST2a may output a 2-1st scan signal SS2-6. The second stage ST2a may be connected to the fifth scan line SO3-2. The 2-1st scan signal SS2-6 may be provided to the fifth scan line SO3-2. The fifth pixel PX5-2 may be driven in response to the 2-1st scan signal SS2-6.

[0456] The third stage ST1b may output a 1-2nd scan signal SS3-6. The third stage ST1b may be connected to the first scan line SO1-2. The 1-2nd scan signal SS3-6 may be provided to the first scan line SO1-2. The first pixel PX1-2 may be driven in response to the 1-2nd scan signal SS3-6.

[0457] The fourth stage ST2b may output a 2-2nd scan signal SS4-6. The fourth stage ST2b may be connected to the sixth scan line SE3-2. The 2-2nd scan signal SS4-6 may be provided to the sixth scan line SE3-2. The sixth pixel PX6-2 may be driven in response to the 2-2nd scan signal SS4-6.

[0458] The fifth stage ST1c may output the 1-3rd scan signal SS5-6. The fifth stage ST1c may be connected to the second scan line SE1-2. The 1-3rd scan signal SS5-6 may be provided to the second scan line SE1-2. The second pixel PX2-2 may be driven in response to the 1-3rd scan signal SS5-6.

[0459] The sixth stage ST2c may output a 2-3rd scan signal SS6-6. The sixth stage ST2c may be connected to the fourth scan line SE2-2. The 2-3rd scan signal SS6-6 may be provided to the fourth scan line SE2-2. The fourth pixel PX4-2 may be driven in response to the 2-3rd scan signal SS6-6.

[0460] According to an embodiment of the present disclosure, scan lines receiving scan signals having overlapping activation periods may be spaced apart from each other by a predetermined minimum distance to reduce or eliminate parasitic capacitors CP1 and CP2 (see Fig. 6A ). The predetermined minimum distance may be 50 μm. The scan driver SDV-5 may be driven so that the distance between the scan lines receiving the scan signals having overlapping activation periods satisfies the predetermined minimum distance. The degradation of the display quality due to the kickback voltage may be prevented. Therefore, a display device DD having improved display quality may be provided (see Figure 1 ).

[0461] exist Fig.14A and Fig. 14B The operation of the scan driver SDV-5 is described in Figure 6C The multiple pixels PX in Figure 2 ) and the connection relationship between the plurality of scan lines SO1-2 to SO3-2 and SE1-2 to SE3-2. However, according to an embodiment of the present disclosure, the operation of the scan driver SDV-5 is not limited thereto. For example, Fig.14A and Fig. 14B The operation of the scan driver SDV-5 can be applied to Figure 6C and Fig.6D The connection relationship between multiple pixels PX and multiple scanning lines SO1-2 to SO3-2 and SE1-2 to SE3-2.

[0462] Although the embodiments of the present disclosure are described for illustrative purposes, it will be understood by those skilled in the art that various modifications and substitutions may be made without departing from the scope and spirit of the present disclosure as disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0463] According to an embodiment of the present disclosure, one data line can be electrically connected to two adjacent pixels in each of a plurality of pixel rows. Compared with a case where one data line is electrically connected to one pixel in each of a plurality of pixel rows, the number of data lines output from a data driver can be relatively small. The number of data lines connected to the data driver can be reduced. As a result, the size of the data driver can be reduced. Therefore, the area size of the peripheral area of ​​the display device can be reduced.

[0464] In addition, as described above, the activation periods of the scan signals of the scan lines adjacent to each other among the plurality of scan lines may not overlap with each other. In this way, the influence of the parasitic capacitor formed between one scan line and another adjacent scan line can be reduced or prevented. The degradation of the display quality due to the kickback voltage can be prevented. Therefore, a display device with improved display quality can be provided.

[0465] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein: The display device comprises: The display panel includes a plurality of pixels, a plurality of scanning lines and a scanning driver. Wherein, the plurality of pixels include: first pixels, second pixels, third pixels, and fourth pixels that are spaced apart from each other and arranged in a matrix configuration, Wherein, the plurality of scan lines include: a first scanning line including a first main line extending in a first direction and a first branch line electrically connected to the first main line and the first pixel and extending in a second direction intersecting the first direction; a second scan line including a second main line spaced apart from the first scan line in the second direction and extending in the first direction, and a second branch line electrically connected to the second main line and the second pixel and extending in the second direction; a third scanning line including a third main line spaced apart from the second scanning line in the second direction and extending in the first direction and a third branch line electrically connected to the third main line and extending in the second direction; a fourth scan line, comprising a fourth main line spaced apart from the third scan line in the second direction and extending in the first direction, and a fourth branch line electrically connected to the fourth main line and extending in the second direction, wherein the scan driver comprises a plurality of stages respectively connected to the plurality of scan lines and outputs a plurality of scan signals, and the plurality of scan lines are arranged in the order of the first scan line, the second scan line, the third scan line and the fourth scan line along the second direction, and Among the plurality of scan lines, the scan lines positioned adjacent to each other receive scan signals of an activation period at mutually exclusive time periods.

2. The display device according to claim 1, wherein: The display device further includes: data lines extending in the second direction, The data line is electrically connected to the first pixel, the second pixel, the third pixel and the fourth pixel.

3. The display device according to claim 1, wherein: The third branch line is electrically connected to the fourth pixel, and Wherein, the fourth branch line is electrically connected to the third pixel.

4. The display device according to claim 1, wherein: The third branch line is electrically connected to the third pixel, and Wherein, the fourth branch line is electrically connected to the fourth pixel.

5. The display device according to claim 1, wherein: Each of the plurality of scanning signals has a pulse width greater than 1 horizontal period, wherein a plurality of odd-numbered stages among the plurality of stages are defined as a first stage group, wherein a plurality of even-numbered stages among the plurality of stages are defined as a second stage group, wherein the plurality of scanning signals include a plurality of first scanning signals output from the first stage group and a plurality of second scanning signals output from the second stage group, and The plurality of first scanning signals and the plurality of second scanning signals are output alternately.

6. The display device according to claim 5, wherein: The scan driver further includes at least one dummy stage, and The at least one dummy stage outputs a dummy scan signal to the next dummy stage or the next stage.

7. The display device according to claim 6, wherein: A 1-1th scanning signal having a first activation period among the plurality of first scanning signals is applied to the first scanning line, wherein a 2-1 scan signal having a second activation period among the plurality of second scan signals is applied to the second scan line, wherein the 1st-2nd scanning signal having a third activation period among the plurality of first scanning signals is applied to the third scanning line, and The first activation period, the second activation period and the third activation period are mutually exclusive time periods.

8. The display device according to claim 7, wherein: The plurality of scanning signals are output in the order of the 2-1 scanning signal, the 1-1 scanning signal, and the 1-2 scanning signal, and The at least one dummy stage is connected to a first odd-numbered stage among the plurality of odd-numbered stages.

9. The display device according to claim 7, wherein: The plurality of scanning signals are output in the order of the 1-1 scanning signal, the 1-2 scanning signal, and the 2-1 scanning signal.

10. The display device according to claim 9, wherein: The at least one dummy stage is connected to a first even-numbered stage among the plurality of even-numbered stages.

Images