Self-detection circuit and storage device

Abstract

The present application discloses a self-test circuit and a storage device, wherein the storage device includes a storage circuit, a control circuit, and a self-test circuit, wherein the self-test circuit is coupled between the control circuit and the storage circuit, and the self-test circuit includes a built-in self-test module and a built-in self-test interface; wherein the built-in self-test module is connected to the control circuit via the built-in self-test interface and a first custom bus, and the built-in self-test module is configured to receive a test instruction from the control circuit via the first custom bus and the built-in self-test interface, perform a self-test operation based on the test instruction to detect damaged storage cells in the storage circuit, generate corresponding bad pixel information, and store it in the storage circuit. In this way, the self-test circuit of the present application can automatically test the damaged storage cells in the storage circuit for bad pixels, reduce external operations, and obtain bad pixel information in the storage circuit in real time, and has a high degree of automation, generalization, and parallelization.

Description

Technical Field

[0001] The present application relates to the field of memory repair technology, and in particular to a self-detection circuit and a storage device. Background Art

[0002] In the manufacturing process of random access memory (RAM), especially dynamic random access memory (DRAM), there are problems such as short circuit or open circuit of word line (WL) in the row direction, short circuit or open circuit of bit line (BL) in the column direction, or damage of memory cell (MC).

[0003] Furthermore, as DRAM process technology continues to shrink and storage capacity continues to increase, failed cells are inevitable within mass-produced DRAM chips. Consequently, the requirements for DRAM repair are becoming increasingly demanding. Furthermore, with the continuous development of artificial intelligence, the demand for high computing power is increasing in more and more scenarios. Hybrid bonding technology can effectively bond logic and memory wafers together, significantly increasing data access bandwidth. Therefore, in such scenarios, a real-time repair method is needed to meet the complex and ever-changing repair scenarios. Summary of the Invention

[0004] In order to solve the above problems, the present application provides a self-detection circuit and a storage device to solve the above problems.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a self-detection circuit, the self-detection circuit is coupled between the control circuit and the storage circuit, the self-detection circuit includes a built-in self-test module and a built-in self-test interface; wherein, the built-in self-test module is connected to the control circuit through the built-in self-test interface and a first custom bus, the built-in self-test module is configured to receive test instructions from the control circuit through the first custom bus and the built-in self-test interface, perform self-test operations based on the test instructions to detect damaged storage cells in the storage circuit, generate corresponding bad pixel information and store it in the storage circuit.

[0006] In some embodiments, a built-in self-test module includes at least one built-in self-test sub-module, a storage circuit includes at least one storage die, each built-in self-test sub-module corresponds to a corresponding storage die, and each storage die includes a first storage sub-module and a second storage sub-module; in response to at least one built-in self-test sub-module performing a self-test operation on a first storage sub-module in its corresponding storage die based on a test instruction, the built-in self-test sub-module detects a damaged storage cell in the first storage sub-module, generates corresponding bad pixel information, and stores the bad pixel information in the second storage sub-module in the corresponding storage die, wherein , the first storage submodule serves as a test storage submodule for self-test, and the second storage submodule serves as a test result storage submodule for self-test; in response to at least one built-in self-test submodule performing a self-test operation on the second storage submodule in its corresponding storage grain based on a test instruction, the built-in self-test submodule detects damaged storage cells in the second storage submodule, generates corresponding bad pixel information and stores the bad pixel information in the first storage submodule in the corresponding storage grain, wherein the second storage submodule serves as a test storage submodule for self-test, and the first storage submodule serves as a test result storage submodule for self-test.

[0007] In some embodiments, each built-in self-test sub-module includes a general configuration unit, a process selection unit, a timing generation unit, and a bad pixel detection unit. The general configuration unit is configured to connect to the control circuit to receive test instructions and configure test items and schedule test functions based on the test instructions; the process selection unit is configured to connect to the general configuration unit. The process selection unit selects the corresponding test item and starts the corresponding sub-state machine based on the configuration information of the test item and the scheduling information of the test function in the general configuration unit; the timing generation unit is configured to connect to the general configuration unit and the process selection unit. The timing generation module generates the corresponding logic control timing based on the sub-state machine in the process selection module, and the built-in self-test sub-module performs the self-test operation of the corresponding test item based on the logic control timing; the bad pixel detection unit is configured to connect to the general configuration unit and the timing generation unit. The bad pixel detection unit detects damaged storage cells in the corresponding storage die based on the self-test operation of the test item and generates bad pixel information.

[0008] In some embodiments, the bad pixel detection unit includes a check subunit, a bad pixel information generation subunit, a bad pixel information generation subunit, and a bad pixel information write-back subunit. The check subunit is configured to connect to the general configuration unit and the timing generation unit. The check unit determines whether the written and read data of the storage cell in the corresponding storage die are consistent based on the self-test operation of the test item and generates a corresponding check result. The bad pixel information generation subunit is configured to connect to the check subunit. The bad pixel information generation subunit determines whether the corresponding storage cell is damaged based on the check result and generates corresponding bad pixel information to mark the damaged storage cell. The bad pixel information write-back subunit is configured to connect to the bad pixel information generation subunit. The bad pixel information write-back subunit is configured to write the bad pixel information to the test result storage submodule in the corresponding storage die. The bad pixel information reading subunit is configured to read the bad pixel information stored in the test result storage submodule in the corresponding storage die and feed back the bad pixel information to the control circuit so that the control circuit performs redundancy mapping repair based on the bad pixel information.

[0009] In some embodiments, the general configuration unit includes a test function configuration register group, multiple instruction configuration register groups, a data type selection register group, and other configuration register groups. The test function configuration register group is used to store the configuration of each test item based on the test instruction; the multiple instruction configuration register groups are used to store the relevant information of each test item; the data type selection register group is used to store different types of test data so that the corresponding test data can be selectively output when executing any test item; and the other configuration register groups are used to store other non-common test items.

[0010] In some embodiments, the process selection unit includes multiple sub-state machines, which are connected one-to-one with the register groups in the general configuration unit, and are used to perform self-test operations of corresponding test items based on the start signal and obtaining relevant information of the test items in the register group.

[0011] In some embodiments, the self-detection circuit also includes a memory operation processing circuit, which is connected to the control circuit and the storage circuit, wherein the memory operation processing circuit performs memory operations based on user instruction information transmitted from the control circuit, and the memory operations include write operations and read operations.

[0012] In some embodiments, the memory operation processing circuit includes a user interface, a command decoding module, an addressing module with a redundant mapping replacement function, an error correction coding module, a port physical layer module, and an error correction decoding module. The user interface is connected to the control circuit via a second custom bus; the command decoding module is connected to the user interface; the addressing module with a redundant mapping replacement function is connected to the user interface; the error correction coding module is connected to the user interface; the port physical layer module is connected to the command decoding module, the addressing module, the error correction coding module, and the storage circuit; the error correction decoding module is connected to the storage circuit and the user interface; wherein, in response to the memory operation being a write operation, the user interface receives corresponding user instruction information from the control circuit via the second custom bus; the command decoding module parses the command information in the user instruction information transmitted from the user interface; the addressing module with a redundant mapping replacement function determines whether to perform redundant mapping replacement based on the bad pixel information detected by the self-test operation and the addressing information in the user instruction information transmitted from the user interface, and performs the corresponding addressing operation; the error correction coding module performs error correction coding on the data information in the user instruction information transmitted from the user interface; the port physical layer module is used to Generate corresponding timing control signals to write the error-corrected encoded data information into the corresponding storage unit of the storage circuit corresponding to the addressing operation in a timely manner based on the parsed command information; in response to the memory operation being a read operation, the user interface receives corresponding user instruction information from the control circuit through the second custom bus; the command decoding module parses the command information in the user instruction information transmitted from the user interface; the addressing module with redundant mapping replacement function determines whether to perform redundant mapping replacement based on the bad pixel information detected by the self-test operation and the addressing information in the user instruction information transmitted from the user interface, and performs the corresponding addressing operation; the port physical layer module is used to generate corresponding timing control signals; in response to the timing control signals, the storage circuit reads out the data information in the storage unit corresponding to the addressing operation based on the parsed command information; the error correction decoding module performs error correction decoding on the read data information and outputs it through the user interface and the second custom bus.

[0013] In some embodiments, a built-in self-test module is connected to a memory operation processing circuit to multiplex the memory operation processing circuit to perform a self-test operation; wherein, when performing the self-test operation, the built-in self-test module completes the initialization configuration of the test item based on the test instruction, the command decoding module parses the test write command of the configured test item, the addressing module with a redundant mapping replacement function executes the addressing operation of the test item corresponding to the test write command, the error correction coding module performs error correction coding on the test data of the test item, and the port physical layer module is used to generate a corresponding timing control signal to write the test data into the storage unit corresponding to the addressing operation based on the parsed test write command in a timely manner. Complete the write operation in the self-test operation; the command decoding module also parses the test read commands of the configured test items in sequence, the addressing module with redundant mapping replacement function executes the addressing operation of the test read command corresponding to the test item, the port physical layer module is used to generate the corresponding timing control signal, the storage circuit reads out the test data of the storage unit corresponding to the addressing operation based on the parsed test read command, the error correction decoding module performs error correction decoding on the read test data, and transmits the read test data to the built-in self-test module, so that the built-in self-test module compares the written test data with the read test data to determine whether the storage unit of the storage circuit is a damaged storage unit.

[0014] In some embodiments, the self-detection circuit further includes a path switching module, which is switchably connected between the error correction decoding module and the user interface or the built-in self-test module. When performing a memory operation, the path switching module is connected to the user interface to be configured to perform a read operation in the memory operation; when performing a self-test operation, the path switching module is connected to the built-in self-test module to be configured to perform a read operation of the self-test operation.

[0015] In some embodiments, the self-detection circuit further includes: a test interface, connected to a built-in self-test module, and communicating with the outside world through a test pin, wherein a test machine can connect the test interface and the built-in self-test module through the test pin to control the built-in self-test module to perform functional testing.

[0016] In some embodiments, a test instruction sent by a control circuit is received in a broadcast manner, wherein the test instruction sent in the broadcast manner contains address information of a selected built-in self-test sub-module. Based on the address information in the test instruction sent in the broadcast manner, the built-in self-test sub-module of the corresponding address is selected, and a self-test operation is performed on the corresponding storage chip based on the test instruction.

[0017] In some embodiments, the address information in the test instruction includes first address information and second address information; in response to the first address information being a preset value, a built-in self-test sub-module matching the second address information is selected, and a self-test operation is performed on the corresponding storage grain based on the test instruction; in response to the first address information being a non-preset value, multiple built-in self-test sub-modules whose addresses are not greater than the first address information are selected, and self-test operations are respectively performed on the corresponding storage grains based on the test instruction.

[0018] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a storage device, which includes a control circuit, a storage circuit and the self-detection circuit of any of the above embodiments.

[0019] In some embodiments, the control circuit and the processing circuit are integrated into the same logic die, and the memory circuit is integrated into the memory die; the logic die and the memory die are integrated together in three dimensions.

[0020] Different from the prior art, the storage device of the present application includes a storage circuit, a control circuit and a self-detection circuit. The self-detection circuit of the present application includes a built-in self-test module and a built-in self-test interface. The self-detection circuit of the present application can configure relevant test items through the built-in self-test interface, and can perform self-test operations on the storage circuit through the built-in self-test module to detect damaged storage cells in the storage circuit, generate corresponding bad pixel information and store it. Through the above method, the self-detection circuit of the present application can automatically test the damaged storage cells in the storage circuit for bad pixels, reduce external operations, and obtain bad pixel information in the storage circuit in real time, and the degree of automation, generalization and parallelization are all high. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0022] Figure 1 This is a schematic structural diagram of the first embodiment of the storage device of the present application;

[0023] Figure 2 is a structural diagram of the second embodiment of the storage device of the present application;

[0024] Figure 3 This is a schematic diagram of the structure of an embodiment of the built-in self-test submodule of the present application;

[0025] Figure 4 This is a structural diagram of an embodiment of a general configuration unit of the present application;

[0026] Figure 5 This is a structural diagram of an embodiment of the combination of the general configuration unit and the process selection unit of the present application;

[0027] Figure 6 is a structural diagram of the third embodiment of the storage device of the present application;

[0028] Figure 7 is a structural diagram of a fourth embodiment of the storage device of the present application;

[0029] Figure 8 It is a structural diagram of the fifth embodiment of the storage device of the present application.

[0030] Description of symbols: storage device 100, control circuit 10, self-test circuit 20, built-in self-test interface 21, built-in self-test module 22, built-in self-test sub-module 23, general configuration unit 231, test function configuration register group 2311, instruction configuration register group 2312, data type selection register group 2313, other configuration register group 2314, process selection unit 232, timing generation unit 233, bad pixel detection unit 234, check sub-unit 2341, bad pixel information generation sub-unit Element 2342, bad pixel information write-back subunit 2343, bad pixel information reading subunit 2344, memory operation processing circuit 24, user interface 241, command decoding module 242, addressing module 243 with redundant mapping replacement function, error correction coding module 244, port physical layer module 245, error correction decoding module 246, path switching module 247, storage circuit 30, storage grain 31, first storage submodule 311, second storage submodule 312, test interface 40, test machine 50. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] In the manufacturing process of random access memory (RAM), especially dynamic random access memory (DRAM), there are problems such as short circuit or open circuit of word line (WL) in the row direction, short circuit or open circuit of bit line (BL) in the column direction, or damage of memory cell (MC).

[0034] Furthermore, as DRAM process technology continues to shrink and storage capacity continues to increase, failed cells are inevitable within mass-produced DRAM chips. Consequently, the requirements for DRAM repair are becoming increasingly demanding. Furthermore, with the continuous development of artificial intelligence, the demand for high computing power is increasing in more and more scenarios. Hybrid bonding technology can effectively bond logic and memory wafers together, significantly increasing data access bandwidth. Therefore, in such scenarios, a real-time repair method is needed to meet the complex and ever-changing repair scenarios.

[0035] In order to solve the above problems, this application first proposes a storage device. Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the storage device of this application. Figure 1 As shown, the storage device 100 of this embodiment includes a storage circuit 30 , a control circuit 10 and a self-detection circuit 20 .

[0036] The self-test circuit 20 is coupled between the control circuit 10 and the storage circuit 30, and the self-test circuit 20 includes a built-in self-test module 22 and a built-in self-test interface 21; wherein, the built-in self-test module 22 is connected to the control circuit 10 via the built-in self-test interface 21 and a first custom bus, and the built-in self-test module 22 is configured to receive test instructions from the control circuit 10 via the first custom bus and the built-in self-test interface 21, perform self-test operations based on the test instructions to detect damaged storage cells in the storage circuit 30, generate corresponding bad pixel information and store it in the storage circuit 30.

[0037] In this embodiment, the control circuit 10 can be a microcontroller unit (CU) or a central processing unit (CPU). The storage circuit 30 includes multiple word lines (WL), multiple pairs of complementary bit lines (target bit line BL and complementary bit line BL#) and multiple storage cells, wherein each storage cell is connected to a word line WL and a pair of complementary bit lines (target bit line BL and complementary bit line BL#). Each storage cell includes an access switch and a storage capacitor. The storage capacitor represents logical "1" and "0" by the amount of charge stored in it, or the high and low voltage difference across the storage capacitor. The on and off of the access switch determines whether the information stored in the storage capacitor is allowed or prohibited to be read and rewritten. When a word line, a complementary bit line or a storage cell is short-circuited or open-circuited, it will cause read and write data errors.

[0038] At this time, the control circuit 10 sends a test instruction to the self-detection circuit 20, and the self-detection circuit 20 can perform a self-test operation on the storage circuit 30 based on the test instruction to detect damaged storage cells in the storage circuit 30, generate corresponding bad pixel information and store it in the storage circuit 30.

[0039] Among them, the built-in self-test interface 21 in the self-detection circuit 20 can be connected to the control circuit 10 via the first custom bus to receive test instructions issued by the control circuit 10. The built-in self-test interface 21 can also perform control-related decoding operations and internal register group configuration operations to configure the test-related register group, thereby further improving the built-in self-test process. When the built-in self-test module 22 receives the test instruction via the first custom bus and the built-in self-test interface 21, the built-in self-test module 22 can perform self-test operations based on the test instruction to detect damaged storage cells in the storage circuit 30, generate corresponding bad pixel information, and store it in the storage circuit 30. In this embodiment, the built-in self-test module 22 is the main control part of the entire self-test process, and can complete the selection and implementation of test items and control the data flow during the built-in self-test process. It will not be described in detail here. The detailed description of the built-in self-test module 22 is shown below.

[0040] Different from the prior art, the storage device 100 of the present application includes a storage circuit 30, a control circuit 10 and a self-detection circuit 20. In the self-detection circuit 20 of the present application, the self-detection circuit 20 includes a built-in self-test module 22 and a built-in self-test interface 21. The self-detection circuit 20 of the present application can configure relevant test items through the built-in self-test interface 21, and can perform self-test operations on the storage circuit 30 through the built-in self-test module 22 to detect damaged storage cells in the storage circuit 30, generate corresponding bad pixel information and store it. In the above manner, the self-detection circuit 20 of the present application can automatically test the damaged storage cells in the storage circuit 30, reduce external operations, and obtain the bad pixel information in the storage circuit 30 in real time, and the degree of automation, generalization and parallelization are all high.

[0041] Optionally, see Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the storage device of this application. Figure 2 As shown, the built-in self-test module 22 in the storage device 100 of this embodiment includes at least one built-in self-test sub-module 23, and the storage circuit 30 includes at least one storage grain 31. Each built-in self-test sub-module 23 corresponds to a corresponding storage grain 31, and each storage grain 31 includes a first storage sub-module 311 and a second storage sub-module 312.

[0042] like Figure 2 As shown, in this embodiment, when the built-in self-test sub-module 23 performs a self-test operation on the first storage sub-module 311 in its corresponding storage chip 31 based on the test instruction, the built-in self-test sub-module 23 can detect the damaged storage unit in the first storage sub-module 311, generate corresponding bad pixel information and store the bad pixel information in the second storage sub-module 312 in the corresponding storage chip 31. In this process, the first storage sub-module 311 serves as a test storage sub-module for self-test, and the second storage sub-module 312 serves as a test result storage sub-module for self-test.

[0043] After the sub-test operation on the first storage sub-module 311 is completed and the bad pixel information of the first storage sub-module 311 is stored in the control circuit 10, the built-in self-test sub-module 23 can be used to perform a self-test operation on the second storage sub-module 312 in the corresponding storage grain 31 based on the test instruction. The built-in self-test sub-module 23 can detect the damaged storage unit in the second storage sub-module 312, generate corresponding bad pixel information and store the bad pixel information in the first storage sub-module 311 in the corresponding storage grain 31. At this time, in this process, the second storage sub-module 312 serves as a test storage sub-module for self-test, and the first storage sub-module 311 serves as a test result storage sub-module for self-test.

[0044] Among them, in the above process, if the built-in self-test submodule 23 is used to perform self-test on the first storage submodule 311, the bad pixel information of the self-test is stored in the second storage submodule 312. Considering that the second storage submodule 312 has not been repaired at this time and there may be bad pixels on it, it is necessary to perform multiple backup processing on the same bad pixel information. When extracting the bad pixel information, it is also necessary to perform multiple voting to ensure the accuracy of the bad pixel information. Similarly, the self-test of the second storage submodule 312 can also be performed as described above.

[0045] Compared to the prior art, the built-in self-test module 22 of this embodiment can include multiple built-in self-test sub-modules 23, and the storage circuit 30 can also include multiple memory chips 31. Each built-in self-test sub-module 23 corresponds to a corresponding memory chip 31, and each memory chip 31 includes a first storage sub-module 311 and a second storage sub-module 312. One of the first storage sub-module 311 and the second storage sub-module 312 is used as a test storage sub-module for the self-test, and the other of the first storage sub-module 311 and the second storage sub-module 312 is used to store the test results of the self-test. This configuration eliminates the need for additional storage logic and fully utilizes the resources of the storage circuit 30.

[0046] Alternatively, as Figure 3 As shown, in this embodiment, the self-test circuit 20 can receive the test instructions sent by the control circuit 10 in a broadcast manner, wherein the test instructions sent in the broadcast manner contain the address information of the selected built-in self-test sub-module 23. Based on the address information in the test instructions sent in the broadcast manner, the built-in self-test sub-module 23 of the corresponding address is selected, and a self-test operation is performed on the corresponding storage chip 31 based on the test instructions.

[0047] That is, in this embodiment, the built-in self-test submodule 23 can be controlled to access the corresponding memory chip 31 by broadcasting. All built-in self-test submodules 23 on the bus can receive the broadcast, and only the built-in self-test submodule 23 specified by the address can execute the command. Figure 3 As shown, the control circuit 10 accesses different built-in self-test sub-modules 23 via broadcasting. Each built-in self-test sub-module 23 is connected to a corresponding memory die 31, thereby accessing the corresponding memory die 31. Each memory die 31 includes a first memory sub-module 311 and a second memory sub-module 312. In other embodiments, the control circuit 10 may also use other wireless communication methods to communicate with the built-in self-test sub-modules 23, as long as they can accomplish the aforementioned functions. This is not a limitation here.

[0048] Compared with the prior art, in this embodiment, a control circuit 10 can simultaneously test multiple storage dies 31 in the storage circuit 30 by broadcasting an address, which can effectively save area and is beneficial to the testing of large-capacity storage circuits 30.

[0049] Optionally, in this embodiment, the address information in the test instruction includes first address information and second address information; in response to the first address information being a preset value, the built-in self-test sub-module 23 matching the second address information is selected, and a self-test operation is performed on the corresponding storage grain 31 based on the test instruction; in response to the first address information being a non-preset value, multiple built-in self-test sub-modules 23 whose addresses are not greater than the first address information are selected, and self-test operations are respectively performed on the corresponding storage grains 31 based on the test instruction.

[0050] For example, in one application scenario, when the control circuit 10 implements simultaneous testing of multiple storage dies 31 in the storage circuit 30 by broadcasting an address, each built-in self-test sub-module 23 has independent address information. For example, the address information of the built-in self-test sub-module 23 with a serial number of 1 can be set to 0, and the address information of the built-in self-test sub-module 23 with a serial number of 1023 can be set to 10'd1023.

[0051] Each piece of address information includes first and second address information. In this embodiment, the second address information can be set as mask_id, and the second address information can be set as add_id. In this embodiment, the bit width of add_id and mask_id can be set to 10 bits. The add_id is used to match a single piece of address information, that is, to match a single built-in self-test submodule 23, and the mask_id is used to match multiple pieces of address information, that is, to match multiple built-in self-test submodules 23.

[0052] For example, when mask_id[9:0] = 10'h0 and add_id[9:0] = 0, the built-in self-test sub-module 23 with the first address information of 0 and the serial number of 1 is selected. When mask_id[9:0] = 10'h0 and add_id[9:0] = 10'h3ff, the built-in self-test sub-module 23 with the first address information of 0 and the serial number of 1023 is selected. That is, only when the first address information mask_id is a preset value does the second address information add_id take effect, and in this case, the built-in self-test sub-module 23 matching the second address information add_id is selected.

[0053] When mask_id[9:0] = 10'h001 and add_id[9:0] = 0, the built-in self-test sub-module 23 with serial number 1 and the built-in self-test sub-module 23 with serial number 2 corresponding to mask_id are selected. When mask_id[9:0] = 10'h007 and add_id[9:0] = 10'h0, the eight built-in self-test sub-modules 23 with serial numbers 1 to 8 corresponding to mask_id are selected. That is, when the first address information mask_id is not a preset value, the first address information mask_id takes effect, and the first address information add_id does not take effect. In this case, multiple built-in self-test sub-modules 23 with addresses not greater than the first address information are selected.

[0054] Optionally, see Figure 3 , Figure 3 This is a schematic diagram of the structure of an embodiment of the built-in self-test submodule of the present application. Figure 3 As shown, in this embodiment, the BIST sub-module 23 includes a general configuration unit 231 , a process selection unit 232 , a timing generation unit 233 and a bad pixel detection unit 234 .

[0055] The general configuration unit 231 is configured to connect to the control circuit 10 to receive test instructions and configure test items and schedule test functions based on the test instructions. The process selection unit 232 is configured to connect to the general configuration unit 231. Based on the test item configuration information and test function scheduling information in the general configuration unit 231, the process selection unit 232 selects the corresponding test item and starts the corresponding sub-state machine. In this embodiment, the test items include but are not limited to read and write operations and overvoltage testing.

[0056] The timing generation unit 233 is configured to connect the general configuration unit 231 and the process selection unit 232. The timing generation module generates the corresponding logic control timing based on the sub-state machine in the process selection module, and the built-in self-test sub-module 23 performs the self-test operation of the corresponding test item based on the logic control timing.

[0057] The bad pixel detection unit 234 is configured to connect the general configuration unit 231 and the timing generation unit 233 . The bad pixel detection unit 234 detects damaged memory cells in the corresponding memory die 31 based on the self-test operation of the test item and generates bad pixel information.

[0058] The built-in self-test (BIST) submodule 23 is essentially a purely digital circuit combination of a set of registers and a sub-state machine. In this embodiment, the universal configuration unit 231 within the BIST submodule 23 contains multiple registers, enabling real-time configuration of test items within the BIST submodule 23 via the control circuit 10 and the first custom bus. Therefore, compared to the prior art, the BIST submodule 23 of this embodiment can add arbitrary test items in any scenario, meeting diverse application scenarios and improving the adaptability of the storage device 100.

[0059] Alternatively, as Figure 3 As shown, the bad pixel detection unit 234 in this embodiment includes a check subunit 2341 , a bad pixel information generation subunit 2342 , a bad pixel information write-back subunit 2343 and a bad pixel information reading subunit 2344 .

[0060] Among them, the check subunit 2341 is configured to connect the general configuration unit 231 and the timing generation unit 233, and the check unit determines whether the write and read data of the storage unit in the corresponding storage grain 31 are consistent based on the self-test operation of the test item, and generates a corresponding check result; the bad pixel information generation subunit 2342 is configured to connect the check subunit 2341, and the bad pixel information generation subunit 2342 determines whether the corresponding storage unit is damaged based on the check result, and generates corresponding bad pixel information to mark the damaged storage unit; the bad pixel information write-back subunit 2343 is configured to connect the bad pixel information generation subunit 2342, and the bad pixel information write-back subunit 2343 is configured to write the bad pixel information to the test result storage submodule in the corresponding storage grain 31; the bad pixel information reading subunit 2344 is configured to read the bad pixel information stored in the test result storage submodule in the corresponding storage grain 31, and feed back the bad pixel information to the control circuit 10, so that the control circuit 10 performs redundant mapping repair based on the bad pixel information.

[0061] In this embodiment, the check sub-unit 2341 is a judgment unit. For example, when performing a bad point test on the first storage sub-module 311, a full write-0 operation can be performed on the first storage sub-module 311. After the write operation is completed, the storage cell data in the first storage sub-module 311 is read, and the data in the storage cell is compared with the written data. If the data read out of a storage cell in the first storage sub-module 311 is not 0, the storage cell under the address may be damaged, and the address corresponding to the storage cell is the verification result. The bad pixel information generating subunit 2342 is a marking unit. The bad pixel information generating subunit 2342 obtains the verification result in the verification subunit 2341 and then performs re-verification and marks the damaged storage unit; the bad pixel information writing back subunit 2343 writes back the bad pixel address (i.e., bad pixel information) in the bad pixel information generating subunit 2342 to the second storage submodule 312. As mentioned above, considering that there may also be bad pixels in the second storage submodule 312, the bad pixel information writing back subunit 2343 needs to perform multiple backup processes on the bad pixel information when writing back the bad pixel information to the second storage submodule 312, that is, a bad pixel information is stored multiple times in the second storage submodule 312. When the bad pixel information write-back sub-unit 2343 completes the above operation, the bad pixel information reading sub-unit 2344 can start working at this time, read the bad pixel information in the second storage sub-module 312, and send it to the control circuit 10 for storage, so that the control circuit 10 calculates the repair information of the first storage sub-module 311 according to the embedded software algorithm, that is, performs redundant mapping repair.

[0062] Optionally, see Figure 4 , Figure 4 This is a schematic diagram of the structure of an embodiment of the general configuration unit of the present application. Figure 4 As shown, in this embodiment, the general configuration unit 231 includes a test function configuration register group 2311 , multiple instruction configuration register groups 2312 , a data type selection register group 2313 , and an other configuration register group 2314 .

[0063] Among them, the test function configuration register group 2311 is used to store the configuration of each test item based on the test instruction; the multiple instruction configuration register group 2312 is used to store the relevant information of each test item; the data type selection register group 2313 is used to store different types of test data, so as to selectively output the corresponding test data when executing any test item; other configuration register groups are used to store other non-common test items.

[0064] As mentioned above, in this embodiment, the general configuration unit 231 includes multiple register groups, and the control circuit 10 can configure and schedule the register groups in real time through the first custom bus. In this embodiment, the general configuration unit 231 includes n+3 register groups (n=1, 2, 3, ...), each of which can be 32 bits in size or can be independently sized. It includes at least one test function configuration register group 2311, n instruction configuration register groups 2312, a data type selection register group 2313, and an other configuration register group 2314. Figure 4 As shown, register group 0 is the test function configuration register group 2311, which contains test function configuration functions, primarily determining test items, test chip selection, and data path selection. Register groups 1 through n are instruction configuration register groups 2312, where the instruction code portion represents the function implementation to be tested. In this embodiment, based on the test flow required by the memory die 31, the test flow is broken down into smallest flow units, which are then encapsulated into instructions in the instruction configuration register group 2312. Each instruction in each instruction configuration register group 2312 has its own independent flow control, address control, data control, voltage control, and timing control. Register group n+1 is the data type selection register group 2313 within the entire test flow. This register group primarily selects different test data types during the read and write processes of the memory die 31, selectively outputting corresponding test data when executing any test item. Register group n+2 is the other configuration register group 2314, which primarily stores other less commonly used test items and can enable different test paths during certain test conditions.

[0065] Compared with the shortcomings of the prior art of fixed hardware implementation, inflexible algorithm, and inability to change after design, the storage device 100 in this embodiment can configure the registers in the general configuration unit 231 in the built-in self-test sub-module 23 in real time through the control circuit 10, thereby realizing real-time detection of the storage grain 31 and intermittent inspection during use for real-time repair, thereby improving the performance of the storage device 100 and enabling it to meet complex application scenarios.

[0066] Optionally, see Figure 5 , Figure 5 This is a structural diagram of an embodiment of the combination of the general configuration unit and the process selection unit of the present application. Figure 5 As shown, the process selection unit 232 includes multiple sub-state machines, which are connected one-to-one with the register groups in the general configuration unit 231, and are used to perform self-test operations of corresponding test items based on the start signal and the relevant information of the test items in the register group.

[0067] In this embodiment, whether a sub-state machine is activated is based on an activation signal from the test function configuration register group 2311. When the activation signal sent by the test function configuration register group 2311 to the sub-state machine is set to logic 1, the sub-state machine of the process selection unit 232 begins to activate. After the sub-state machine is activated, the corresponding sub-state machine sequentially reads the data information from register groups 1 to n, and activates the corresponding sub-state machine based on the instruction code and related information read from the register group. In this embodiment, the sub-state machine is also implemented according to the function of the minimum test process unit, which is configurable.

[0068] Based on the above implementation, in other embodiments, the present application can write different instruction codes and related information into registers 1 to n according to the actual test items and the test process. Finally, a start signal is written to register group 0 (i.e., test function configuration register group 2311) to start the state machine, and the test process can be implemented in sequence.

[0069] In one application scenario, the built-in self-test submodule 23 is required to perform bad pixel detection on the memory die 31. The first step is to use a sub-state machine to write all-0 data to the even bit line address of the memory die 31. In this case, it is necessary to use an instruction configuration register group 2312 (for example, register group 1). The instruction code in the instruction configuration register group 2312 is set to the write operation instruction code, the process control is set to write to all bit lines of the memory die 31, the address configuration is set to the first address 0 and the cumulative step mode is set to +2 mode, the data control configuration is set to all 0s, the voltage configuration is set to universal voltage, and the timing control configuration is set to universal timing. Through the above operations, the sub-state machine corresponding to register group 1 can implement the operation of writing all-0 data to the even bit line address of the memory die 31.

[0070] After the write-all-0 operation is completed, the data in the memory die 31 needs to be read. This requires another instruction configuration register group 2312 (e.g., register group 2). The instruction code of this instruction configuration register group 2312 is set to the read operation instruction code, the process control is set to read all bit lines of the memory die 31, the address configuration is set to the first address 0 and the cumulative step mode is set to +2 mode, the data control is configured to all 0s, the voltage is configured to a universal voltage, and the timing control is configured to universal timing. Through the above operations, the sub-state machine corresponding to register group 2 can implement the operation of reading all 0 data from the even bit line address in the memory die 31. If the data of the storage cell at a certain address is not 0 during the read process, the address of the storage cell is recorded as a bad pixel. In subsequent operations, the bad pixel information is written to the non-test memory die 31.

[0071] Through the above-mentioned method, in this embodiment, the storage device 100 of the present application can utilize the control circuit 10 to control the register group in the built-in self-test submodule 23, so that the test process can be changed according to different test requirements under different test environments, and has good adaptability and real-time performance. In addition, in this embodiment, during the self-test process, the instruction code and related configuration information are split according to the minimum test unit, so that a highly configurable self-test process can be realized with higher stability.

[0072] Optionally, see Figure 6 , Figure 6 This is a schematic diagram of the structure of the third embodiment of the storage device of this application. Figure 1 The storage device 100 is based on Figure 6 As shown, the self-detection circuit 20 of this embodiment further includes a memory operation processing circuit 24 .

[0073] like Figure 6 As shown, the memory operation processing circuit 24 is connected to the control circuit 10 and the storage circuit 30 , wherein the memory operation processing circuit 24 performs memory operations based on user instruction information transmitted from the control circuit 10 , and the memory operations include write operations and read operations.

[0074] Optionally, see Figure 7 , Figure 7 This is a schematic diagram of the structure of the fourth embodiment of the storage device of this application. Figure 7 As shown, the memory operation processing circuit 24 of this embodiment includes a user interface 241, a command decoding module 242, an addressing module 243 with a redundant mapping replacement function, an error correction coding module 244, a port physical layer module 245 and an error correction decoding module 246.

[0075] like Figure 7 As shown, in this embodiment, the user interface 241 is connected to the control circuit 10 through a second customized bus; the command decoding module 242 is connected to the user interface 241; the addressing module 243 with redundant mapping replacement function is connected to the user interface 241; the error correction coding module 244 is connected to the user interface 241; the port physical layer module 245 is connected to the command decoding module 242, the addressing module, the error correction coding module 244 and the storage circuit 30; and the error correction decoding module 246 is connected to the storage circuit 30 and the user interface 241.

[0076] In this embodiment, the user interface 241 is primarily an interface for users to access the storage circuit 30. The command decoding module 242 is used to perform operations such as judging, decoding, and arbitrating user commands. The addressing module 243, which has a redundant mapping replacement function, is used to replace the mapping of the redundant units (Redundancy) in the storage circuit 30 to the damaged word lines or bit lines. This module is composed of registers, and the user needs to write the repair information obtained by the repair algorithm into this module after the word test is completed. The function of the error correction coding module 244 is to add coding bits to the original data bits, which can decode and reconstruct the erroneous data, thereby completing the error correction function of the erroneous data. This module completes the error correction code (ECC) encoding function of the input data. The ECC is implemented by adding bits to the original data bits, and the added bits are used to reconstruct the erroneous data. The error correction decoding module 246 is used to complete the decoding function of the coded data to achieve error correction of the erroneous data.

[0077] The port physical layer module 245 is used to control the timing of all interface signals in the storage circuit 30. It contains some configurable registers, which can be used to configure timing for specific needs during the self-test process. The storage circuit 30 is a memory chip. Unlike general-purpose memory, this storage circuit 30 does not include a general random access memory timing interface, but rather a specially customized interface. This improves the speed at which logic slices access the storage circuit 30 and increases the chip's capacity density.

[0078] Among them, when the memory operation is a write operation, the user interface 241 receives the corresponding user instruction information from the control circuit 10 through the second custom bus; the command decoding module 242 parses the command information in the user instruction information transmitted by the user interface 241; the addressing module 243 with a redundant mapping replacement function determines whether to perform redundant mapping replacement based on the bad pixel information detected by the self-test operation and the addressing information in the user instruction information transmitted by the user interface 241, and performs the corresponding addressing operation; the error correction coding module 244 performs error correction coding on the data information in the user instruction information transmitted by the user interface 241; the port physical layer module 245 is used to generate a corresponding timing control signal to write the error-corrected encoded data information into the corresponding storage unit of the storage circuit 30 corresponding to the addressing operation in a timely manner based on the parsed command information.

[0079] When the memory operation is a read operation, the user interface 241 receives corresponding user instruction information from the control circuit 10 through the second custom bus; the command decoding module 242 parses the command information in the user instruction information transmitted by the user interface 241; the addressing module 243 with redundant mapping replacement function determines whether to perform redundant mapping replacement based on the bad pixel information detected by the self-test operation and the addressing information in the user instruction information transmitted by the user interface 241, and performs the corresponding addressing operation; the port physical layer module 245 is used to generate a corresponding timing control signal; corresponding to the timing control signal, the storage circuit 30 reads out the data information in the storage unit corresponding to the addressing operation based on the parsed command information; the error correction decoding module 246 performs error correction decoding on the read data information and outputs it through the user interface 241 and the second custom bus.

[0080] That is, Figure 7 As shown, the storage device 100 of this embodiment includes two ways of accessing the storage circuit 30 . The first way is for a user to access the storage circuit 30 and complete normal read, write and refresh operations on the storage circuit 30 .

[0081] When the user performs a write operation or a read operation on the storage circuit 30, that is, the memory operation is a write operation or a read operation, the data flow is specifically as follows:

[0082] When the user writes to the storage circuit 30, the user controls the user interface 241 through the second custom bus. The user interface 241 sends the user command through line ⑧ to the command decoding module 242. The command decoding module 242 decodes the user command and sends it through line 8. The user interface 241 sends the address information corresponding to the user instruction to the addressing module 243 with redundant mapping replacement function through line 9. The addressing module obtains the repair mapping address based on the address information and the repair mapping address relationship, and sends it to the port physical layer module 245 through line 3. The user interface 241 sends the data information corresponding to the user instruction to the error correction coding module 244 through line 10. The error correction coding module 244 completes the encoding of the data information, and then sends it to the port physical layer module 245 through line 3. The data is sent to the port physical layer module 245 , which generates the interface control timing required by the storage circuit 30 based on the above user instruction and the corresponding address information and data information, thereby completing the writing of the storage unit data in the storage circuit 30 .

[0083] When the user performs a read operation on the storage circuit 30, the user controls the user interface 241 through the second custom bus. The user interface 241 sends the user command through line ⑧ to the command decoding module 242. The command decoding module 242 decodes the user command and sends it through line 8. The interface is sent to the port physical layer module 245. The user interface 241 sends the address information corresponding to the user instruction to the addressing module 243 with redundant mapping replacement function via line 9. The addressing module obtains the repair mapping address based on the address information and the relationship between the repair mapping address, and sends it to the port physical layer module 245 via line 3. The port physical layer module 245 generates the interface control timing required by the storage circuit 30 based on the above-mentioned read user instruction and the corresponding address information. The output data of the storage circuit 30 is sent to the error correction decoding module 246 via line 5 for data decoding, and then the data is decoded by using lines 6 and 7. The second customized bus feeds back to the user interface 241 and the control circuit 10 , thereby completing the reading of the storage unit data in the storage circuit 30 .

[0084] Alternatively, as Figure 7 As shown, in this embodiment, the built-in self-test module 22 is connected to the memory operation processing circuit 24 to multiplex the memory operation processing circuit 24 to perform self-test operations.

[0085] Among them, when performing the self-test operation, the built-in self-test module 22 completes the initialization configuration of the test item based on the test instruction, the command decoding module 242 parses the test write command of the configured test item, the addressing module 243 with the redundant mapping replacement function performs the addressing operation of the test item corresponding to the test write command, the error correction coding module 244 performs error correction coding on the test data of the test item, and the port physical layer module 245 is used to generate the corresponding timing control signal to write the test data into the storage unit corresponding to the addressing operation based on the parsed test write command in time to complete the write operation in the self-test operation; the command decoding module 242 also decodes the test data in time in time. The test read command of the configured test item is analyzed, and the addressing module 243 with a redundant mapping replacement function performs the addressing operation of the test read command corresponding to the test item. The port physical layer module 245 is used to generate a corresponding timing control signal. The storage circuit 30 reads out the test data of the storage unit corresponding to the addressing operation based on the analyzed test read command. The error correction decoding module 246 performs error correction decoding on the read test data and transmits the read test data to the built-in self-test module 22, so that the built-in self-test module 22 compares the written test data with the read test data to determine whether the storage unit of the storage circuit 30 is a damaged storage unit.

[0086] That is, Figure 7 As shown, in the storage device 100 of this embodiment, the second path for accessing the storage circuit 30 is for the built-in self-test module 22 to access the storage circuit 30 to complete functions such as reading, writing, refreshing, bad pixel detection and aging test on the storage circuit 30, thereby obtaining the bad pixel location of the storage circuit 30 to calculate repair information.

[0087] When the built-in self-test module 22 performs testing and bad pixel detection on the storage circuit 30, the data flow is as follows:

[0088] The control circuit 10 sends a test instruction to the built-in self-test interface 21 via a first custom bus. The built-in self-test interface 21 sends the test instruction to the built-in self-test module 22 via line ①. The built-in self-test module 22 completes the initial configuration of the test item based on the test instruction. The built-in self-test module 22 sends the test write instruction to the command decoding module 242. The command decoding module 242 parses the test write command of the configured test item. In addition, the built-in self-test module 22 also sends the address information corresponding to the test write instruction to the addressing module 243 with redundant mapping replacement function. The addressing module performs the addressing operation corresponding to the test write command of the test item. The error correction coding module 244 performs error correction coding on the test data of the test item. The port physical layer module 245 receives the test instruction, the address signal corresponding to the test instruction, and the test data, and generates corresponding timing control signals. Based on the parsed test write command, the test data is written to the storage unit corresponding to the addressing operation in a timely manner, thereby completing the write operation in the self-test operation. In addition, during this process, since bad pixels need to be tested, the built-in self-test module 22 can complete the write operation in the self-test operation of the storage circuit 30 without going through the error correction coding module 244.

[0089] After the built-in self-test module 22 completes the test write instruction, it needs to read the data of the storage unit in the storage circuit 30. The process of sending the test read instruction and the address information corresponding to the test read instruction is the same as the operation of the test write instruction. The difference is that the test read instruction does not need to send data to the storage circuit 30. After receiving the parsed test read command, the storage circuit 30 needs to read out the test data of the storage unit corresponding to the addressing operation and send it to the error correction decoding module 246 via line 5. The error correction decoding module 246 performs error correction decoding on the read test data and transmits the read test data to the built-in self-test module 22 via lines 6 and 7, so that the built-in self-test module 22 compares the written test data with the read test data to determine whether the storage unit of the storage circuit 30 is a damaged storage unit.

[0090] Alternatively, as Figure 7 As shown, in this embodiment, the self-test circuit 20 further includes a path switching module 247 , which is switchably connected between the error correction decoding module 246 and the user interface 241 or the built-in self-test module 22 .

[0091] For example, when the self-detection circuit 20 performs a memory operation, the path switching module 247 is connected to the user interface 241 to be configured to perform a read operation in the memory operation; when the self-detection circuit 20 performs a self-test operation, the path switching module 247 is connected to the built-in self-test module 22 to be configured to perform a read operation of the self-test operation.

[0092] Alternatively, as Figure 7 As shown, in this embodiment, the self-test circuit 20 further includes a test interface 40, which is connected to the built-in self-test module 22 and communicates with the outside world through a test pin. A test machine 50 can connect the test interface 40 and the built-in self-test module 22 through the test pin to control the built-in self-test module 22 to perform functional testing.

[0093] like Figure 7 As shown, the test machine 50 is connected to the test interface 40 through the test pin, and the test interface 40 is connected to the test interface 40 through the line Connected to the built-in self-test module 22, the tester 50 can connect to the test interface 40 and the built-in self-test module 22 via the test pins of the storage device 100 to control the built-in self-test module 22 to perform functional tests and also perform wafer tests on the storage circuit 30. In this embodiment, by providing the test interface 40, the method for the tester 50 to access the storage circuit 30 is retained, and a test backdoor is established to facilitate subsequent testing.

[0094] Different from the prior art, the storage device 100 of the present application includes a storage circuit 30, a control circuit 10 and a self-detection circuit 20. In the self-detection circuit 20 of the present application, the self-detection circuit 20 includes a built-in self-test module 22 and a built-in self-test interface 21. The self-detection circuit 20 of the present application can configure relevant test items through the built-in self-test interface 21, and can perform self-test operations on the storage circuit 30 through the built-in self-test module 22 to detect damaged storage cells in the storage circuit 30, generate corresponding bad pixel information and store it. In the above manner, the self-detection circuit 20 of the present application can automatically test the damaged storage cells in the storage circuit 30, reduce external operations, and obtain the bad pixel information in the storage circuit 30 in real time, and the degree of automation, generalization and parallelization are all high.

[0095] Optionally, this application further proposes a storage device, see Figure 8 , Figure 8 This is a schematic diagram of the structure of the fifth embodiment of the storage device of this application. Figure 8 As shown, the storage device 100 of this embodiment includes a control circuit 10 , a storage circuit 30 , and the self-detection circuit 20 of any of the above embodiments.

[0096] The storage device 100 of this embodiment may be a random access memory, including but not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM), or a pseudo static random access memory (Pseudo SRAM, PSRAM).

[0097] Optionally, based on the above embodiment, in this embodiment, if Figure 8 As shown, the control circuit 10 and the self-test circuit 20 can be integrated into the same logic die, and the memory circuit 30 can be integrated into at least one memory die. The logic die and the at least one memory die are three-dimensionally integrated using techniques such as hybrid bonding. That is, the logic die is an independent control logic die, and is packaged with the at least one memory die through three-dimensional bonding to form a memory chip. In other embodiments, the logic die can also be provided as an independent chip, which is not limited here.

[0098] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0099] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A self-detection circuit, characterized in that: The self-test circuit is coupled between the control circuit and the storage circuit, and the self-test circuit includes a built-in self-test module and a built-in self-test interface; The built-in self-test module is connected to the control circuit via the built-in self-test interface and a first custom bus, and is configured to receive a test instruction from the control circuit via the first custom bus and the built-in self-test interface, perform a self-test operation based on the test instruction to detect damaged storage cells in the storage circuit, generate corresponding bad pixel information, and store the bad pixel information in the storage circuit; The built-in self-test module includes at least one built-in self-test sub-module, the storage circuit includes at least one storage die, each of the built-in self-test sub-module corresponds to a corresponding storage die, and each storage die includes a first storage sub-module and a second storage sub-module; In response to at least one of the built-in self-test sub-modules performing a self-test operation on the first storage sub-module in the corresponding storage die based on the test instruction, the built-in self-test sub-module detects damaged storage cells in the first storage sub-module, generates corresponding bad pixel information, and stores the bad pixel information in the second storage sub-module in the corresponding storage die, wherein the first storage sub-module serves as a test storage sub-module for the self-test, and the second storage sub-module serves as a test result storage sub-module for the self-test; In response to at least one of the built-in self-test sub-modules performing a self-test operation on the second storage sub-module in the corresponding storage grain based on the test instruction, the built-in self-test sub-module detects damaged storage cells in the second storage sub-module, generates corresponding bad pixel information and stores the bad pixel information to the first storage sub-module in the corresponding storage grain, wherein the second storage sub-module serves as a test storage sub-module for self-testing, and the first storage sub-module serves as a test result storage sub-module for self-testing.

2. The self-detection circuit according to claim 1, wherein: Each of the built-in self-test submodules comprises: a general configuration unit, configured to connect to the control circuit to receive the test instruction, and configure test items and schedule test functions based on the test instruction; a process selection unit, configured to be connected to the general configuration unit, the process selection unit selecting a corresponding test item and starting a corresponding sub-state machine based on the configuration information of the test item and the scheduling information of the test function in the general configuration unit; a timing generation unit, configured to connect the general configuration unit and the process selection unit, the timing generation module generating a corresponding logic control timing based on the sub-state machine in the process selection unit, and the built-in self-test submodule performing a self-test operation of the corresponding test item based on the logic control timing; The bad pixel detection unit is configured to connect the general configuration unit and the timing generation unit, and the bad pixel detection unit detects damaged storage cells in the corresponding storage die based on the self-test operation of the test item to generate the bad pixel information.

3. The self-detection circuit according to claim 2, characterized in that: The bad pixel detection unit includes: a check subunit, configured to connect the general configuration unit and the timing generation unit, the check subunit determining whether the written data and the read data of the storage cell in the corresponding storage die are consistent based on the self-test operation of the test item, and generating a corresponding check result; a bad pixel information generating subunit, configured to be connected to the verification subunit, the bad pixel information generating subunit determining whether a corresponding storage unit is damaged based on the verification result, and generating corresponding bad pixel information to mark the damaged storage unit; a bad pixel information write-back subunit, configured to be connected to the bad pixel information generating subunit, and configured to write the bad pixel information into the test result storage submodule in the corresponding storage die; The bad pixel information reading subunit is configured to read the bad pixel information stored in the test result storage submodule in the corresponding storage die, and feed back the bad pixel information to the control circuit so that the control circuit performs redundant mapping repair based on the bad pixel information.

4. The self-detection circuit according to claim 2, wherein: The general configuration unit includes: A test function configuration register group, used for storing the configuration of each test item based on the test instruction; A plurality of instruction configuration register groups, used for storing relevant information of each of the test items; A data type selection register group, used to store different types of test data, so as to selectively output corresponding test data when executing any of the test items; Other configuration register groups are used to store other uncommon test items.

5. The self-detection circuit according to claim 2, wherein: The process selection unit includes: A plurality of sub-state machines are connected to the register groups in the general configuration unit in a one-to-one correspondence, and are used to execute the self-test operation of the corresponding test items based on the start signal and the relevant information of the test items in the register group.

6. The self-detection circuit according to claim 1, wherein: The self-detection circuit further includes: a memory operation processing circuit connected to the control circuit and the storage circuit, wherein the memory operation processing circuit performs memory operations based on user instruction information transmitted from the control circuit, and the memory operations include write operations and read operations.

7. The self-detection circuit according to claim 6, characterized in that: The memory operation processing circuit includes: a user interface connected to the control circuit via a second custom bus; A command decoding module connected to the user interface; An addressing module with a redundant mapping replacement function, connected to the user interface; an error correction coding module, connected to the user interface; A port physical layer module, connecting the command decoding module, the addressing module, the error correction coding module and the storage circuit; an error correction decoding module, connected to the storage circuit and the user interface; In response to the memory operation being a write operation, the user interface receives the corresponding user instruction information from the control circuit via the second custom bus; the command decoding module parses the command information in the user instruction information transmitted by the user interface; the addressing module with a redundant mapping replacement function determines whether to perform redundant mapping replacement based on the bad pixel information detected by the self-test operation and the addressing information in the user instruction information transmitted by the user interface, and performs the corresponding addressing operation; the error correction coding module performs error correction coding on the data information in the user instruction information transmitted by the user interface; and the port physical layer module is used to generate a corresponding timing control signal to sequentially write the error-corrected encoded data information into the corresponding storage unit of the storage circuit corresponding to the addressing operation based on the parsed command information; In response to the memory operation being a read operation, the user interface receives the corresponding user instruction information from the control circuit through the second custom bus; the command decoding module parses the command information in the user instruction information transmitted from the user interface; the addressing module with redundant mapping replacement function determines whether to perform redundant mapping replacement and performs corresponding addressing operations based on the bad pixel information detected by the self-test operation and the addressing information in the user instruction information transmitted from the user interface; the port physical layer module is used to generate a corresponding timing control signal; corresponding to the timing control signal, the storage circuit reads out the data information in the storage unit corresponding to the addressing operation based on the parsed command information; the error correction decoding module performs error correction decoding on the read data information and outputs it through the user interface and the second custom bus.

8. The self-detection circuit according to claim 7, characterized in that: The built-in self-test module is connected to the memory operation processing circuit to multiplex the memory operation processing circuit to perform the self-test operation; Wherein, when executing the self-test operation, the built-in self-test module completes the initialization configuration of the test item based on the test instruction, the command decoding module parses the test write command of the configured test item, the addressing module with redundant mapping replacement function executes the addressing operation of the test item corresponding to the test write command, the error correction coding module performs error correction coding on the test data of the test item, and the port physical layer module is used to generate a corresponding timing control signal to write the test data into the storage unit corresponding to the addressing operation based on the parsed test write command in time to complete the write operation in the self-test operation; the command decoding module also parses the test write command in sequence. The configured test read command of the test item, the addressing module with redundant mapping replacement function performs the addressing operation of the test item corresponding to the test read command, the port physical layer module is used to generate a corresponding timing control signal, the storage circuit reads out the test data of the storage unit corresponding to the addressing operation based on the parsed test read command, the error correction decoding module performs error correction decoding on the read test data, and transmits the read test data to the built-in self-test module, so that the built-in self-test module compares the written test data with the read test data to determine whether the storage unit of the storage circuit is a damaged storage unit.

9. The self-detection circuit according to claim 8, characterized in that: The self-detection circuit further includes: A path switching module is switchably connected between the error correction decoding module and the user interface or the built-in self-test module. When the memory operation is performed, the path switching module is connected to the user interface to be configured to perform a read operation in the memory operation; when the self-test operation is performed, the path switching module is connected to the built-in self-test module to be configured to perform a read operation of the self-test operation.

10. The self-detection circuit according to claim 6, wherein: The self-detection circuit further includes: A test interface is connected to the built-in self-test module and communicates with the outside world through a test pin, wherein a test machine can connect the test interface and the built-in self-test module through the test pin to control the built-in self-test module to perform functional testing.

11. The self-detection circuit according to claim 1, wherein: The test instruction sent by the control circuit is received in a broadcast manner, wherein the test instruction sent in the broadcast manner contains address information of the selected built-in self-test sub-module, based on the address information in the test instruction sent in the broadcast manner, the built-in self-test sub-module of the corresponding address is selected, and a self-test operation is performed on the corresponding storage grain based on the test instruction.

12. The self-detection circuit according to claim 11, characterized in that: The address information in the test instruction includes first address information and second address information; In response to the first address information being a preset value, the built-in self-test submodule matching the second address information is selected, and a self-test operation is performed on the corresponding memory die based on the test instruction; In response to the first address information being a non-preset value, a plurality of the built-in self-test sub-modules having addresses not greater than the first address information are selected, and self-test operations are respectively performed on the corresponding memory dies based on the test instruction.

13. A storage device, characterized in that: include: control circuit; storage circuits; and The self-detection circuit according to any one of claims 1 to 12.

14. The storage device according to claim 13, wherein: The control circuit and the self-detection circuit are integrated into the same logic die, and the storage circuit is integrated into at least one storage die; the logic die and the storage die are integrated together in three dimensions.

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