Miniaturized radio frequency signal recording and playback system

Abstract

The invention relates to a miniaturized radio frequency signal recording and playback system, which comprises a bottom plate, a core plate stacked on the bottom plate, a high-integration radio frequency transceiving unit and a storage unit which are arranged on the bottom plate, and a central processing unit, a programmable logic unit and a cache unit which are arranged on the core plate, when the system records the radio frequency signal, the digital radio frequency signal processed in the high-speed cache unit is converted into a signal file in a file format through the central processing unit, and the signal file is stored in the storage unit according to a scheduling strategy so as to complete recording of the radio frequency signal; after the central processing unit caches signal files in the storage unit to the high-speed cache unit according to a scheduling strategy, the signal files are processed by the programmable logic unit and the high-integration radio frequency receiving and transmitting unit, and the high-integration radio frequency receiving and transmitting unit transmits radio frequency signals to complete playback. The system can realize high-frequency-band coverage, high-bandwidth signal processing and stable signal playback in a small volume.

Description

Technical Field

[0001] The present application relates to the field of electronic measurement technology, and in particular to a miniaturized radio frequency signal recording and playback system. Background Art

[0002] In modern wireless communication systems, the development of RF signal recording and playback systems is to meet the growing demand for wireless communication performance evaluation, protocol verification and system optimization. The traditional RF signal recording and playback system has the limitation of large size, making it difficult to apply in space-constrained scenarios. Especially in the fields of drone payload and portable testing, the large size of traditional equipment makes it inflexible and not portable enough.

[0003] Users are increasingly demanding portability and flexibility, but traditional RF signal recording and playback systems perform poorly in this regard. To address this problem, the design of miniaturized RF signal recording and playback systems faces technical challenges, including achieving high-frequency band coverage, high-bandwidth signal processing, and stable signal playback in a small volume. Traditional technologies have difficulty balancing these requirements in miniaturized RF signal recording and playback systems, so new technical means are needed to overcome these challenges.

[0004] In addition, miniaturized devices also face higher requirements in terms of efficient signal processing and playback. This means that advanced signal processing and playback technologies need to be integrated within a limited volume to ensure that ideal performance is still provided in a small size. Summary of the invention

[0005] Based on this, it is necessary to provide a miniaturized RF signal recording and playback system that can achieve portability while having stable performance in order to address the above technical problems.

[0006] A miniaturized radio frequency signal recording and playback system, the system is arranged on a base plate and a core board stacked on the base plate, the system comprises a highly integrated radio frequency transceiver unit and a storage unit arranged on the base plate, and a central processing unit, a programmable logic unit and a cache unit arranged on the core board;

[0007] When the system is recording radio frequency signals:

[0008] The central processor sends a signal acquisition instruction to the highly integrated radio frequency transceiver unit;

[0009] The highly integrated radio frequency transceiver unit collects radio frequency signals according to the signal collection instruction, performs modulation and demodulation processing on the collected radio frequency signals to obtain digital radio frequency signals, and sends the digital radio frequency signals to the programmable logic unit;

[0010] The programmable logic unit performs digital signal processing on the digitized radio frequency signal and caches the processed digitized radio frequency signal in the cache unit;

[0011] The central processor converts the processed digital radio frequency signal in the cache unit into a signal file in a file format, and stores the signal file in the storage unit according to the scheduling strategy to complete the recording of the radio frequency signal;

[0012] When the system plays back the radio frequency signal: the central processor caches the signal file in the storage unit to the cache unit according to the scheduling strategy, and then the programmable logic unit and the highly integrated radio frequency transceiver unit process the signal, and the highly integrated radio frequency transceiver unit sends the radio frequency signal to complete the playback;

[0013] The scheduling strategies include efficient cache overflow response strategy, interrupt service program strategy, data efficient processing strategy, real-time enhancement strategy and resource utilization optimization strategy.

[0014] In one embodiment, when storing the signal file to the storage unit according to the scheduling strategy:

[0015] Determine whether interrupt service program optimization is needed based on the current status, performance requirements, and interrupt processing efficiency, and execute the interrupt processing code if necessary;

[0016] If the interrupt service program does not need to be optimized, then determine whether the data processing algorithm needs to be optimized based on the data analysis characteristics, and if necessary, execute the efficient data processing algorithm;

[0017] If data processing algorithm optimization is not required, determine whether practical optimization is required based on the data reuse status. If necessary, set a suitable data update frequency and update the data content.

[0018] If practical optimization is not required, determine whether resource utilization optimization is required based on resource usage status. If necessary, use resource utilization optimization strategy to optimize resources.

[0019] If not necessary, the signal file is directly stored in the storage unit.

[0020] In one embodiment, when the processed digitized radio frequency signal is cached in the cache unit, the cache unit is dynamically expanded or reduced by using a cache area dynamic adjustment mechanism according to the flow change of the data to be cached.

[0021] In one embodiment, the central processing unit is equipped with a Linux operating system;

[0022] In the Linux operating system, an optdev library for simplifying software interface development is included, and the optdev library supports multiple backends, including a Local backend and a Network backend;

[0023] The Local backend directly interacts with the Linux kernel through the sysfs virtual file system;

[0024] The Network backend is connected to the FTP Server via a network, wherein the FTP Server acts as a transit station, creates an optdev context using the Local backend, and shares it with the Network backend using optdev.

[0025] In one embodiment, the highly integrated RF transceiver unit collects and plays back RF signals with a frequency band of 75MHz-6GHz and a signal bandwidth of 200MHz through a RF interface unit disposed on the bottom board.

[0026] In one embodiment, the system further includes a satellite navigation unit and a clock unit disposed on the bottom plate, for sensing real-time position and time information of the system.

[0027] In one embodiment, the system includes a control unit arranged on a base plate, and the control unit is respectively connected to the core board, the highly integrated radio frequency transceiver unit, the clock unit, the satellite navigation unit and the storage unit;

[0028] The control unit receives control instructions from the host computer through the control interface arranged on the bottom board, converts the instructions into a form understandable by each unit and sends it to the relevant unit, and sends the data received from each unit to the host computer through the control interface;

[0029] The control interface includes a Gigabit Ethernet interface, a serial port interface and a GPIO interface.

[0030] In one embodiment, the storage unit includes a pluggable solid state disk.

[0031] In one embodiment, the system is fixed in a cavity of a rectangular protective shell with a size of 105 mm×26 mm×120 mm and a weight of 0.85 kg.

[0032] The above-mentioned miniaturized RF signal recording and playback system includes a core board arranged on a base plate and stacked on the base plate, including a highly integrated RF transceiver unit and a storage unit arranged on the base plate, and a central processing unit, a programmable logic unit and a cache unit arranged on the core board. When the system records the RF signal, the central processing unit converts the processed digitized RF signal in the cache unit into a signal file in a file format and stores the signal file in the storage unit according to the scheduling strategy to complete the recording of the RF signal, or when playing back, the central processing unit caches the signal file in the storage unit to the cache unit according to the scheduling strategy, and then processes it by the programmable logic unit and the highly integrated RF transceiver unit, and the highly integrated RF transceiver unit sends the RF signal to complete the playback. The system can achieve high-frequency band coverage, high-bandwidth signal processing and stable signal playback in a small volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a structural block diagram of a miniaturized radio frequency signal recording and playback system in one embodiment;

[0034] Figure 2 A schematic diagram of a scheduling strategy flow in one embodiment;

[0035] Figure 3 A schematic diagram of a process flow of an efficient cache overflow response strategy in one embodiment;

[0036] Figure 4 A schematic diagram of a lean process for interruption services in an embodiment;

[0037] Figure 5 A schematic diagram of a DMA data transmission process in one embodiment;

[0038] Figure 6 A schematic diagram of the architecture of a Linux operating system installed on a central processing unit in one embodiment;

[0039] Figure 7 A schematic diagram of a framework of a miniaturized radio frequency signal recording and playback system architecture in one embodiment. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] In this embodiment, if Figure 1As shown, a miniaturized radio frequency signal recording and playback system is provided, which is arranged on a base plate and a core board stacked on the base plate. The system includes a highly integrated radio frequency transceiver unit and a storage unit arranged on the base plate, and a central processing unit, a programmable logic unit and a cache unit arranged on the core board.

[0042] Among them, when the system records the radio frequency signal: the central processing unit sends a signal acquisition instruction to the highly integrated radio frequency transceiver unit, the highly integrated radio frequency transceiver unit acquires the radio frequency signal according to the signal acquisition instruction, and modulates and demodulates the acquired radio frequency signal to obtain a digital radio frequency signal, and sends it to the programmable logic unit, the programmable logic unit performs digital signal processing on the digital radio frequency signal, and caches the processed digital radio frequency signal in the cache unit. Then, the central processing unit converts the processed digital radio frequency signal in the cache unit into a signal file in a file format, and stores the signal file in the storage unit according to the scheduling strategy to complete the recording of the radio frequency signal.

[0043] Among them, when the system plays back the RF signal: the central processor caches the signal file in the storage unit to the cache unit according to the scheduling strategy, and then the programmable logic unit and the highly integrated RF transceiver unit process it, and the highly integrated RF transceiver unit sends the RF signal to complete the playback.

[0044] In this embodiment, the scheduling strategy includes an efficient cache overflow response strategy, an interrupt service program strategy, a data efficient processing strategy, a real-time enhancement strategy, and a resource utilization optimization strategy.

[0045] In this embodiment, the highly integrated RF transceiver unit collects and replays RF signals with a frequency band of 75MHz-6GHz and a signal bandwidth of 200MHz through a RF interface unit arranged on the bottom board. The RF interface unit is used to process two input analog signals and output analog signals to adapt to the highly integrated RF transceiver unit.

[0046] Furthermore, the highly integrated RF transceiver unit can use a dual-channel RF transceiver chip to complete signal acquisition and transmission within the frequency band of 75MHz to 6GHz. Taking single-channel signal acquisition as an example, in a dual-channel RF transceiver chip, the analog signal (i.e., RF signal) enters the analog-to-digital conversion chip in the dual-channel RF transceiver chip through the RF interface unit, and then passes through its built-in LNA. The built-in local oscillator (LO) completes the zero intermediate frequency conversion of the analog signal, and then the I / Q modulation module completes the phase conversion to obtain the I / Q two-way signal output, and then the ADC completes the sampling, and the final I / Q two-way signal is output to the central processor in the core board after passing through the FIR filter.

[0047] Specifically, the dual-channel RF transceiver chip includes a built-in low noise amplifier (LNA) and a local oscillator (LO). The LNA is used to amplify the received signal, and the LO is used for zero intermediate frequency conversion. The maximum transmission bandwidth is 200MHz, and the maximum reception bandwidth is 200MHz. It provides 2-way reception and 2-way transmission. The addition of an RF amplifier to the transmission link improves linearity, and the addition of a low noise amplifier to the receiving link can effectively reduce input noise and improve the sensitivity of the receiver, and provide an external reference clock input function. Among them, the sampling rate and bit width of the ADC are 245.76MS / s, 16 bits for IQ sampling in single channel and 122.88MS / s, 16 bits for IQ sampling in dual channel. Among them, FIR filtering is a selective FIR filtering of the sampled I / Q signals to further optimize the signal quality.

[0048] In this embodiment, the core board uses a core control chip, which integrates a quad-core Arm Cortex-A53 processor, a dual-core Arm Cortex-R5F real-time processor processing system (PS) part, i.e., a central processing unit, a traditional field programmable gate array (FPGA) logic component PL part, i.e., a programmable logic unit, and a cache unit. PS is responsible for exchanging data with the programmable logic to ensure the normal operation of the system. PL implements customized hardware functions, such as accelerating specific cache functions, to improve system performance and flexibility. The cache unit completes the caching of the transmission signal of the high-frequency transceiver unit to improve data access speed and system performance.

[0049] In this embodiment, the cache unit includes 4GB DDR4 mounted on the PL part, and 4GB DDR4 mounted on the PL part.

[0050] In this embodiment, the data path between the PS and the PL is mainly a general AXI Memory interface, and the PS / PL mainly exchanges large blocks of data through the DDR of the PS.

[0051] In this embodiment, the DDR of the core board PS and the DDR of the PL two-level cache, together with the storage unit of the baseboard, form a three-level storage and playback signal data storage system. The use of the two-level cache and the storage unit scheduling strategy are different from those in the traditional operating system because of the characteristics of the signal data stream, such as large file size, continuous storage playback requirements, etc.

[0052] Furthermore, the signal data stream collected and stored comes from the highly integrated RF transceiver unit, first in the DDR cache of the PL, then moved to the DDR cache of the PS through DMA, and then processed by the PS to generate a data file, which is stored in the storage unit according to a certain scheduling strategy. However, the signal data stream in playback first reads the signal data file in the storage unit to the DDR cache of the PS according to a certain scheduling strategy, and then moves it to the DDR cache of the PL through DMA, and is sent to the highly integrated RF transceiver unit after being processed by the PL logic.

[0053] Since the signal data files of the storage unit have large data volumes and high data transmission rate requirements, storage unit scheduling faces more stringent requirements than traditional operating systems. However, the predictability of signal data file storage and playback provides convenience for storage unit scheduling. Compared with the unpredictable disk requests of traditional operating systems, signal data files have obvious sequentiality when storing and playing back files, which increases the predictability of requests. Signal data file storage and playback place special requirements on storage unit scheduling, mainly because of the need to continuously and uninterruptedly store and play back high-speed signal data streams with large file sizes. This requires that the storage unit scheduling strategy can effectively manage storage unit access, reduce access time, and ensure continuous data transmission. Traditional access scheduling mechanisms, such as first-come, first-served (FCFS) or shortest seek time first (SSTF), are not suitable for the needs of signal data file storage and playback because they do not take into account the continuity and real-time requirements of data streams. Specific data stream-based scheduling optimization mechanisms are designed here, such as Figure 2 As shown, this ensures that signal data can be accurately stored and played back in the required time and sequence.

[0054] Furthermore, a comprehensive scheduling optimization mechanism has been built for the efficient management and optimization of data flow. Its core focuses on the refined regulation of data cache management, supplemented by comprehensive optimization of interrupt handling, data processing algorithms, real-time response and resource utilization, in order to accurately meet the high standards of signal data file storage and playback.

[0055] In this embodiment, when the signal file is stored in the storage unit according to the scheduling strategy:

[0056] Determine whether interrupt service program optimization is needed based on the current status, performance requirements, and efficiency of interrupt processing. If necessary, execute the interrupt processing code. If interrupt service program optimization is not needed, determine whether data processing algorithm optimization is needed based on data analysis characteristics. If necessary, execute an efficient data processing algorithm. If data processing algorithm optimization is not needed, determine whether practicality optimization is needed based on the data reuse status. If necessary, set a suitable data update frequency and update the data content. If practicality optimization is not needed, determine whether resource utilization optimization is needed based on the resource usage status. If necessary, use a resource utilization optimization strategy to optimize resources. If not necessary, directly store the signal file in the storage unit.

[0057] Specifically, the basis for judging whether to optimize the interrupt service routine (ISR) is usually based on multiple factors, which are directly related to the current state of the system, performance requirements, and the efficiency of interrupt processing. The key factors for judgment include interrupt frequency, interrupt processing time, system load, interrupt priority, and resource usage. Among them, the current state includes: if the interrupt frequency generated by a certain interrupt source is very high, and the processing time of these interrupts is relatively long, then it may affect the overall response time and performance of the system. In this case, it is particularly important to optimize the interrupt service routine to reduce the interrupt processing time. Interrupt processing time includes: directly measuring or estimating the execution time of the interrupt processing function. If the processing time is too long, it may block the execution of other interrupts or tasks, resulting in a slow system response. At this time, optimizing the interrupt service routine to reduce the processing time is a reasonable choice. System load includes: the current load of the system is also an important factor in judging whether to optimize the interrupt service routine. If the system is already in a high load state and interrupt processing further increases the load, then optimizing interrupt processing to improve the overall system performance is particularly necessary. Interrupt priority includes: different interrupt sources may have different priorities. For high-priority interrupts, their processing efficiency has a more significant impact on system performance. Therefore, for high-priority interrupts, it may be necessary to pay more attention to their processing efficiency and optimize them accordingly. Resource usage includes: CPU, memory and other resources may be used during interrupt processing. If resource usage is tight and interrupt processing occupies a large amount of resources, it is also necessary to optimize the interrupt service program to reduce resource consumption.

[0058] In this embodiment, when the processed digitized radio frequency signal is cached in the cache unit, the cache unit is dynamically expanded or reduced by using a cache area dynamic adjustment mechanism according to the flow change of the data to be cached.

[0059] Specifically, the intelligent cache dynamic expansion strategy effectively copes with the changing challenges of data traffic with its excellent flexibility. When the system detects in real time that the data memory exceeds the preset high threshold (4GB), it responds quickly, uses advanced prediction algorithms to dynamically calculate the required cache capacity growth, and automatically performs the expansion operation. This process ensures that in high-load scenarios, the system can have sufficient cache resources to support efficient data processing and avoid performance bottlenecks.

[0060] In this embodiment, the prediction algorithm uses time series to calculate the required cache growth, which mainly involves the analysis and prediction of time series data. Time series data is a series of data points arranged in chronological order, which reflects the change of a phenomenon over time. In the calculation of cache growth, we can use time series analysis to predict the cache demand in the future period of time, so as to determine the cache growth.

[0061] In this embodiment, a cache growth calculation step based on time series analysis is also provided: first, it is necessary to collect historical data on cache usage, which should include cache usage at different time points, such as cache usage per day, per hour or per minute, and the collected data is sorted in chronological order to form time series data. Through time series analysis, the trend of cache usage over time is identified. This can be achieved by drawing a time series graph, calculating a moving average or performing trend fitting. According to the results of the time series analysis, a suitable prediction model is selected to predict future cache usage. On the contrary, when the data memory falls back to the set low threshold (200MB), the system shows its intelligent reduction. It will intelligently release part of the cache resources based on the actual utilization of the current cache resources and future data processing forecasts to achieve optimal resource configuration and utilization. This reverse regulation not only helps to reduce unnecessary costs, but also further improves the overall efficiency and stability of the system.

[0062] This two-way adjustment mechanism of the intelligent cache dynamic expansion strategy not only significantly improves the utilization efficiency of cache resources, but also greatly enhances the adaptability and resilience of the system. It enables the system to maintain efficient and stable operation under various load conditions. Through this intelligent dynamic adjustment, we provide solid support for the ever-changing data processing needs and ensure the continuous high availability and excellent performance of the system.

[0063] Specifically, efficient cache overflow response strategy: To address the risk of cache overflow, we have designed an efficient cache management strategy. When the cache is close to full, the system will trigger an intelligent overflow processing mechanism to discard the oldest or less important data first to make room for new data. This process strictly follows the principles of data priority and integrity protection to ensure that critical data is not lost, while reducing the risk of performance degradation or crash caused by cache overflow. The process is as follows: Figure 3 shown.

[0064] In this embodiment, the discardable data includes: the oldest data: according to the creation time or update time of the data, the data that first enters the cache is often the most likely to be discarded. This is because the data may no longer be the latest, or its information value has decreased over time. Data with low access rate: if some data is stored in the cache for a long time but is rarely accessed, they may be regarded as unimportant. The retention of such data not only takes up valuable cache space, but also may affect the overall efficiency of the cache. Data that is easy to retrieve: if the data can be easily retrieved from the original data source and the retrieval cost is low, then the data can be discarded first when the cache overflows. Implement different cache strategies: such as LRU (least recently used), LFU (least frequently used), FIFO (first in, first out), etc. Each strategy has its applicable scenario, and the appropriate strategy can be selected according to specific needs to determine which data should be discarded. Customization according to business needs: in some cases, customized priorities can be set for data according to specific business needs. In this way, when the cache overflows, the system can decide which data should be retained and which data should be discarded according to these priorities.

[0065] Specifically, the interrupt service program is streamlined: by finely configuring the interrupt priority, it ensures that key interrupts can be responded to quickly and efficiently, effectively avoiding interrupt conflicts and delays. At the same time, the interrupt service program is slimmed down to reduce unnecessary calculations and waiting time, further improving the system's response speed and execution efficiency. Figure 4 shown.

[0066] Furthermore, the interrupt priority needs to identify all interrupt sources in the system, which may come from external devices, internal timers, system anomalies, etc. The interrupt sources are classified and initially divided according to their functions, importance and urgency. A priority is set for each interrupt source, and the priority depends on the importance, urgency and impact of the interrupt event on the system.

[0067] Furthermore, priority setting can be implemented through software or hardware. The software method usually arranges a priority query program before the interrupt service program, while the hardware method uses a priority queuing circuit or a dedicated interrupt controller. Allow high-priority interrupts to interrupt the execution of low-priority interrupts during the service process to achieve interrupt nesting. Slim down the interrupt service program to reduce unnecessary calculation and waiting time and ensure the efficiency of the interrupt processing process. Optimize the execution path and data processing logic of the interrupt service program to improve the execution efficiency of the program.

[0068] The main object of interrupt priority division is the various interrupt sources in the system. These interrupt sources are prioritized according to urgency, criticality, frequency, and processing time.

[0069] Specifically, the efficiency of data processing algorithms: In order to speed up the data processing process, DMA (direct memory access) technology is used to reduce CPU intervention and improve data transmission and processing speed. The DMA data transmission process is as follows: Figure 5 In addition, complex data processing logic is moved to the main program or background task to avoid time-consuming operations in the interrupt service program, thus ensuring the timeliness and efficiency of interrupt processing.

[0070] Furthermore, the entire process begins with the CPU executing a series of instructions to test the device status and configure the DMA controller, including setting the device number, the memory start address, and the amount of data to be transferred. Subsequently, when the peripheral is ready for data transmission, it will initiate a request to the DMA controller. After obtaining bus control, the DMA controller directly takes over the data bus and address bus to transfer data between the peripheral and the memory. For each word transferred, the DMA controller updates the address counter and word counter until the preset amount of data is reached. After the data transfer is completed, the DMA controller notifies the CPU via an interrupt, and the CPU responds to the interrupt and performs subsequent processing, including verifying the correctness of the data and deciding the next step. Finally, the DMA controller releases bus control to the CPU so that it can continue to perform other tasks. The entire process effectively reduces the burden on the CPU and improves the efficiency of data transmission.

[0071] Specifically, real-time enhancement strategies include: meeting real-time requirements, analyzing data sensitivity, setting second-level updates for high-frequency trading data, and low-frequency updates for trend data. After formulating the strategy, dynamically adjust the update frequency according to system load and data changes to optimize resource utilization and ensure real-time response. Also, reduce unnecessary data read and write operations, implement data caching strategies, store high-frequency access data in memory, reduce the number of I / O times for disks and remote storage, and reduce latency. At the same time, batch processing technology is used to merge small write operations, and database batch write optimization is used to improve write efficiency. In addition, according to the principle of on-demand loading, only the currently required data is processed to avoid unnecessary memory and CPU consumption, thereby improving the overall processing efficiency of the system.

[0072] Specifically, resource utilization is optimized: In terms of resource management, a refined scheduling strategy is implemented to ensure that system resources are efficiently and reasonably allocated and utilized. Through the coordinated optimization of cache management, data processing, interrupt response and other links, the maximum benefit of resource utilization is achieved, resource waste and conflicts are reduced, and the overall operating efficiency and stability of the system are improved.

[0073] In this embodiment, the central processing unit is equipped with a Linux operating system, in which an optdev library for simplifying software interface development is included, and the optdev library supports multiple backends, including Local backend and Network backend. Among them, Local backend directly interacts with the Linux kernel through the sysfs virtual file system. Network backend is connected to the FTP Server through the network, wherein the FTP Server acts as a transit station, uses Local backend to create an optdev context, and shares it with the Network backend using optdev.

[0074] Specifically, a highly customized and tailored embedded Linux operating system is deployed inside the core board, which is designed to provide advanced software functions and performance. The Linux operating system provides a powerful abstraction layer that hides the details of the underlying hardware, allowing developers to focus on application development without having to pay too much attention to the details at the hardware level. By using mechanisms such as the device tree to describe the hardware structure of the system, it is easier to manage and configure hardware resources. The Linux kernel provides rich device driver support, including drivers for various peripherals and sensors. This makes it easier for the software architecture to interact and communicate with various hardware devices. The embedded Linux system provides powerful network support, including the TCP / IP protocol stack and the implementation of various network protocols. The software architecture can use these functions to easily communicate with external devices or networks to achieve data transmission and remote control. The modular design of the Linux system allows developers to easily add or remove functional modules as needed to meet the needs of different application scenarios. Developers can use Linux's package management tools to install and manage the required software packages, thereby achieving flexible configuration and expansion of system functions. The Linux operating system has been developed and tested for a long time and has performed well in stability and reliability. When the software architecture runs in a Linux environment, it can benefit from the stability and reliability of Linux, thereby improving the stability and reliability of the system.

[0075] In this embodiment, the software architecture of the Linux operating system installed in the central processing unit is as follows: Figure 4 As shown in the figure, optdev is a library developed to simplify Linux software interface development. It provides developers with a simple and complete programming interface by abstracting the details of the underlying hardware. The design of this abstraction layer not only reduces the difficulty of development and improves development efficiency, but also enhances the portability and maintainability of the software. The design idea of ​​optdev library embodies the software engineering principle of "encapsulating complexity and simplifying interfaces".

[0076] In this embodiment, the optdev library supports multiple backends, including Local backend and Network backend. This design enables the library to flexibly adapt to different application scenarios.

[0077] Furthermore, the Local backend directly interacts with the Linux kernel through the sysfs virtual file system, realizing the abstraction and management of key functions such as PS-side applications, module clocks, AD / DA, DMA, and interrupt drivers. This design allows developers to easily interact with the underlying hardware without having to pay attention to the underlying details, thus greatly improving the efficiency and maintainability of software development.

[0078] Furthermore, the Network backend is connected to the FTP Server through the network. As a transit station, the FTP Server uses the Local backend to create an optdev context and shares it to the Networkbackend using optdev, thereby realizing the connection to any client application on the server. This network-based architecture allows the module to easily communicate and exchange data with the external environment, providing convenience for remote management and control of the system. The module supports interaction with the host computer software on the Windows side, and realizes the transmission of instructions and data through network links. This cross-platform compatibility enables the module to be seamlessly integrated in different operating system environments, providing users with a more flexible and convenient operating experience.

[0079] In this embodiment, the storage unit uses two M.2 interfaces, both supporting NVMe (PCIe3.0×4), and can install two 2280 M.2 solid-state drives to form a storage unit with a maximum capacity of 8TB, and a storage speed of up to 1Gbps / s, which is difficult to match with traditional storage solutions. This design enables the storage unit to handle a large number of data-intensive tasks, such as video editing, scientific computing, etc.

[0080] Furthermore, two 2280-size M.2 SSDs supported by the NVMe (PCIe3.0×4) protocol are inserted into the two M.2 interfaces of the storage unit to achieve a high-density storage solution while maintaining the flexibility of the interface. Users can choose different M.2 SSDs to build their own storage system according to their needs. Users can perform initialization settings, including RAID configuration and partition settings, to ensure that the storage unit works as required. Subsequently, users can save files, applications, and data in the storage unit to take full advantage of its high-speed NVMe storage performance.

[0081] Specifically, the storage unit includes a pluggable solid-state drive. This modular design allows users to add or replace M.2 solid-state drives through simple plug-in operations, thereby easily expanding or upgrading storage capacity. At the same time, this design not only reduces maintenance costs, but also improves the maintainability of the system. Using the NVMe (PCIe3.0×4) protocol, it provides a high-speed data transmission channel, which greatly improves the speed of data storage and retrieval. The storage unit supports flexible capacity expansion. Users can install two 2280-size M.2 solid-state drives to a maximum capacity of 8TB. ​​It has a wide range of applications, including personal computers, servers, embedded systems, and other fields, providing high-performance, high-capacity storage solutions for various application scenarios.

[0082] Furthermore, the storage unit has a built-in RAID configuration function, which improves the redundancy and reliability of data. Users can choose the appropriate RAID level according to their needs to protect data and avoid data loss caused by a single hard drive failure. The capacity expansion method is simple and easy, and users can easily add or replace M.2 solid-state drives according to their needs without the need for professional tools. Through this storage unit, users can enjoy a high-performance, high-capacity storage experience, while also having convenient capacity expansion and flexible application scenario applicability.

[0083] In this embodiment, the storage unit provides a high-speed, large-capacity and flexible storage solution through the above configuration. The NVMe protocol is adopted to achieve high-speed data transmission and significantly improve work efficiency. It supports a maximum capacity of 8TB to meet diverse storage needs, and the capacity can be expanded through simple operations. The built-in RAID configuration function enhances data security and protects user data from hardware failures. At the same time, the modular design makes expansion and maintenance simple and fast, improving the user experience.

[0084] In this embodiment, the system further includes a satellite navigation unit and a clock unit disposed on the bottom plate, for sensing the real-time position and time information of the system.

[0085] In this embodiment, the satellite navigation unit integrates ubox's UBX-M8030 parallel GNSS IC, which can receive signals from multiple satellite systems such as GPS, GLONASS, Beidou and QZSS, providing wide coverage and higher positioning reliability around the world. Not only does it provide positioning functions, it also integrates a low phase noise 30.72MHz system reference oscillator, which is constrained by GNSS, precise and jitter-free time pulses, which is a unique innovation in applications that require high-precision time synchronization.

[0086] Furthermore, the workflow of the satellite navigation unit includes: first, signal reception, accurate positioning of position and time through GNSS constraints and high-sensitivity signal acquisition. The system also generates jitter-free time pulses and supports single-satellite timing, which can provide accurate time and position information even when only one satellite is visible. This breaks through the traditional GNSS positioning's dependence on multiple satellite signals and improves the system's flexibility and adaptability. At the same time, it is also designed that the satellite navigation unit has the function of automatically maintaining the current state when the signal is interrupted, ensuring that the system can quickly reposition when the signal is restored, reducing data interruption and repositioning time caused by signal loss.

[0087] In this embodiment, the satellite navigation unit provides high-precision, multi-system and multi-band positioning capabilities, ensuring wide coverage and reliability around the world, generating stable and jitter-free time pulses to meet the needs of high-precision time synchronization. It also has high-sensitivity signal acquisition and single-satellite timing functions to adapt to complex environments; the automatic hold mechanism reduces the impact of signal interruptions and improves system continuity and user experience.

[0088] In this embodiment, the clock unit switches the 30.72 MHz reference signal provided by the satellite navigation unit, or the local 100 MHz reference oscillator, or the external input 100 MHz reference signal to meet different signal acquisition and playback requirements.

[0089] Furthermore, the clock unit is a key system component whose workflow and role are designed to provide flexible clock synchronization and signal source selection. First, users can select reference signals from multiple sources, including a 30.72MHz signal from a satellite navigation unit, a local 100MHz reference oscillator, or an externally input 100MHz reference signal. This multi-source selection ensures the flexibility of the clock unit in different application scenarios. Through hardware switching circuits or control logic, the clock unit can switch to the user-selected reference signal source in real time.

[0090] After selection, the clock unit may divide or adjust the reference signal to meet different signal acquisition and playback requirements. This ensures that the clock frequency is consistent with the system requirements and provides stable and accurate clock synchronization for the entire system. Finally, the clock unit outputs the selected and processed clock signal as the clock synchronization reference for other modules in the system.

[0091] The role of the clock unit is not only to provide flexibility in signal sources and clock synchronization, but also to adapt to different application requirements. Through multi-source selection, frequency division and frequency rectification, the clock unit can be flexibly applied to a variety of systems and devices to ensure the system's operational stability and high performance.

[0092] Specifically, the clock unit has a clock source backup function, which can switch to other available signal sources when a reference signal source fails, thereby enhancing the reliability and anti-interference of the system, which is an innovation in the design of the clock unit.

[0093] In this embodiment, the clock unit improves the system adaptability and flexibility, and meets different needs through multi-source switching and flexible processing. It optimizes system performance, reduces timing errors, and improves response speed. It enhances system reliability, ensures continuous operation through clock source backup, reduces costs and complexity, and improves product competitiveness through integrated design, laying a solid foundation for future technology upgrades and expansions.

[0094] In this embodiment, the system further includes a control unit disposed on the base plate, and the control unit is respectively connected to the core board, the highly integrated radio frequency transceiver unit, the clock unit, the satellite navigation unit, and the storage unit. The control unit receives control instructions from the host computer through a control interface disposed on the base plate, converts the instructions into a form understandable to each unit and sends the instructions to the relevant unit, and sends the data received from each unit to the host computer through the control interface.

[0095] Specifically, the control interface is used to interconnect with the baseboard, exchange instructions and data, and control the acquisition and playback of its signals.

[0096] Furthermore, the control interface plays a key role as a bridge between the baseboard and the host computer, mainly including Gigabit Ethernet, serial port and GPIO and other interfaces. First, the physical connection is achieved through Gigabit Ethernet, and the host computer can communicate with the baseboard through network protocols such as TCP / IP or UDP. At the same time, the baseboard needs to be configured with an IP address to establish communication. The serial port interface uses physical connection methods such as UART or RS-232, and parameters such as baud rate and data frame format need to be negotiated to ensure stable serial communication. The GPIO interface achieves communication by defining the input and output states of the pins, and the level logic needs to be negotiated to ensure the correct transmission of information.

[0097] In this embodiment, in terms of command interaction: the baseboard and the host computer transmit commands and data through Gigabit Ethernet or serial port, and a clear communication protocol needs to be defined, including command format, data format, etc. After receiving the command, the baseboard parses it and performs corresponding operations, which may involve control algorithms, data processing, etc. In the data interaction stage, the data format needs to be defined to ensure that the host computer correctly understands and processes the data sent by the baseboard. After receiving the data from the host computer, the baseboard parses and processes it, which may include operations such as storage, display, and sensor data acquisition.

[0098] In the entire workflow of the miniaturized RF signal recording and playback system, an error detection mechanism needs to be implemented to ensure the accurate transmission of instructions and data, including checksum, CRC check, etc. When an error is found, the baseboard sends error information to the host computer so that the host computer can process or correct it accordingly. At the same time, the baseboard can send current status information to the host computer through the control interface, including operating status, sensor status, etc., so as to monitor the working status of the baseboard in real time. This overall process ensures effective interaction and control between the host computer and the baseboard.

[0099] In this embodiment, the system also includes a power supply unit and a corresponding power interface arranged on the base plate. Among them, the power interface is a DC interface, a DC power plug suitable for the device is selected, and the specification requirements are defined, including parameters such as rated voltage and maximum current. The design of the power supply unit focuses on supporting 12V DC input, integrating power management circuits to ensure the stability and safety of external power input, and adding filtering and voltage stabilization circuits to ensure clean and stable power output. In the physical connection stage, a matching connector is selected, and the corresponding cable is designed to reduce resistance loss to ensure that the physical connection is firm and reliable.

[0100] like Figure 5 The figure shows the overall block diagram of the miniaturized RF signal recording and playback system. The system adopts a dual-module stacking structure design, and different functional layers are connected through layer indirect plug-ins. The hardware platform is based on the SOC architecture, in which the SOC is responsible for coordinating various communication and data interaction interfaces, such as NVMe, network, RS2322, etc. The hardware platform has two M.2 interfaces, which can support the expansion and installation of two NVMe protocol M.2 solid-state drives to achieve high-speed recording and playback of signal data. The main technical indicators include: frequency range: 75MHz-6GHz; acquisition bandwidth: single channel 200MHz, dual channel 100MHz; playback bandwidth: single channel 200MHz, dual channel 100MHz, power supply: 12V DC.

[0101] In this embodiment, the miniaturized radio frequency signal recording and playback system is fixed in a cavity of a rectangular protective shell with a size of 105 mm×26 mm×120 mm and a weight of 0.85 kg.

[0102] In this embodiment, the miniaturized RF signal recording and playback system supports massive data acquisition and storage, signal playback, and arbitrary signal generation, and is configured with three software, namely, signal acquisition and storage control software, signal quick browsing and analysis software, and complex electromagnetic signal generation software.

[0103] Specifically, the functions of the signal acquisition and storage control software interface include: signal spectrum display and waterfall chart display during acquisition and playback; acquisition and playback function status display, memory remaining capacity display; acquisition function start / end, acquisition time control; acquisition bandwidth control: you can select the bandwidth and sampling rate used when acquiring signals, so as to optimize the memory usage efficiency; playback function start / end; playback parameter setting, progress display, etc.

[0104] Specifically, the specific functions of the signal quick browsing and analysis software interface include a graphical interface to display the spectrum diagram and time-frequency diagram of the collected data, quickly browse the entire data to find the signal location of interest; data file cutting and extraction; and transfer of collected data to other standard file formats.

[0105] Specifically, the signals simulated and generated in the complex electromagnetic signal generation software include radar pulse signals and analog / digital modulated communication signals. The corresponding signals can be generated according to user-defined parameters and directly output through the analog signal output port. Specific functions include: analog signal generation: CW, AM, FM; digital modulation sample signal generation: BPSK, QPSK, DQPSK, π / 4DQPSK, 8PSK, Star-16QAM, Star-32QAM, QAM 16, QAM 32, QAM 64, QAM128, QAM256; radar pulse signal generation: single carrier frequency, positive linear frequency modulation, negative linear frequency modulation, V-type frequency modulation, inverted V-type frequency modulation, 2 / 3 / 4 / 5 / 7 / 11 / 13-bit Barker code, etc.; support for superposition generation of different styles of signals; support for users to edit signal parameters arbitrarily; support for user-defined waveform output.

[0106] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0107] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A miniaturized radio frequency signal recording and playback system, characterized in that: The system is arranged on a base plate and a core board stacked on the base plate, and the system includes a highly integrated radio frequency transceiver unit and a storage unit arranged on the base plate, and a central processing unit, a programmable logic unit and a cache unit arranged on the core board; When the system is recording radio frequency signals: The central processor sends a signal acquisition instruction to the highly integrated radio frequency transceiver unit; The highly integrated radio frequency transceiver unit collects radio frequency signals according to the signal collection instruction, performs modulation and demodulation processing on the collected radio frequency signals to obtain digital radio frequency signals, and sends the digital radio frequency signals to the programmable logic unit; The programmable logic unit performs digital signal processing on the digitized radio frequency signal and caches the processed digitized radio frequency signal in the cache unit; The central processor converts the processed digital radio frequency signal in the cache unit into a signal file in a file format, and stores the signal file in the storage unit according to the scheduling strategy to complete the recording of the radio frequency signal; When the system plays back the radio frequency signal: the central processor caches the signal file in the storage unit to the cache unit according to the scheduling strategy, and then the programmable logic unit and the highly integrated radio frequency transceiver unit process the signal, and the highly integrated radio frequency transceiver unit sends the radio frequency signal to complete the playback; The scheduling strategies include efficient cache overflow response strategy, interrupt service program strategy, data efficient processing strategy, real-time enhancement strategy and resource utilization optimization strategy.

2. The miniaturized radio frequency signal recording and playback system according to claim 1, characterized in that: When storing the signal file in the storage unit according to the scheduling strategy: Determine whether interrupt service program optimization is needed based on the current status, performance requirements, and interrupt processing efficiency, and execute the interrupt processing code if necessary; If the interrupt service program does not need to be optimized, then determine whether the data processing algorithm needs to be optimized based on the data analysis characteristics, and if necessary, execute the efficient data processing algorithm; If data processing algorithm optimization is not required, determine whether practical optimization is required based on the data reuse status. If necessary, set a suitable data update frequency and update the data content. If practical optimization is not required, determine whether resource utilization optimization is required based on resource usage status. If necessary, use resource utilization optimization strategy to optimize resources. If not necessary, the signal file is directly stored in the storage unit.

3. The miniaturized radio frequency signal recording and playback system according to claim 1, characterized in that: When the processed digitized radio frequency signal is cached in the cache unit, the cache unit is dynamically expanded or reduced by using a cache area dynamic adjustment mechanism according to the flow change of the data to be cached.

4. The miniaturized radio frequency signal recording and playback system according to claim 1, characterized in that: The central processing unit is equipped with a Linux operating system; In the Linux operating system, an optdev library for simplifying software interface development is included, and the optdev library supports multiple backends, including a Local backend and a Network backend; The Local backend directly interacts with the Linux kernel through the sysfs virtual file system; The Network backend is connected to the FTP Server via a network, wherein the FTP Server acts as a transit station, creates an optdev context using the Local backend, and shares it with the Network backend using optdev.

5. The miniaturized radio frequency signal recording and playback system according to any one of claims 1 to 4, characterized in that: The highly integrated radio frequency transceiver unit realizes the collection and playback of radio frequency signals with a frequency band of 75MHz-6GHz and a signal bandwidth of 200MHz through a radio frequency interface unit arranged on the bottom plate.

6. The miniaturized radio frequency signal recording and playback system according to claim 5, characterized in that: The system further comprises a satellite navigation unit and a clock unit arranged on the bottom plate, which are used for sensing the real-time position and time information of the system.

7. The miniaturized radio frequency signal recording and playback system according to claim 6, characterized in that: The system includes a control unit arranged on a base plate, and the control unit is respectively connected to the core board, the highly integrated radio frequency transceiver unit, the clock unit, the satellite navigation unit and the storage unit; The control unit receives control instructions from the host computer through the control interface arranged on the bottom plate, converts the instructions into a form understandable to each unit and sends it to the relevant unit, and sends the data received from each unit to the host computer through the control interface; The control interface includes a Gigabit Ethernet interface, a serial port interface and a GPIO interface.

8. The miniaturized radio frequency signal recording and playback system according to claim 7, characterized in that: The storage unit includes a pluggable solid state disk.

9. The miniaturized radio frequency signal recording and playback system according to claim 8, characterized in that: The system is fixed in a cavity of a rectangular protective shell with a size of 105 mm×26 mm×120 mm and a weight of 0.85 kg.

Images