Processor verification system and method

Abstract

The present application discloses a processor verification system and method, including a monitoring component and a storage component; the storage component is used to store verification use cases; the verification use cases include multiple nodes; the verification use cases are used to trigger the target processor to write node data corresponding to the node to the target memory when the target processor executes any node of the verification use case, and the node data represents the state of the target processor when the node of the verification use case is executed; the monitoring component is used to monitor the node data of the target processor.

Description

Technical Field

[0001] The present application relates to the field of verification technology, and in particular to a processor verification system and method. Background Art

[0002] To verify the proper functioning of an electronic device's processor, it's necessary to perform processor verification. One method involves having the processor execute pre-programmed verification tests. A verification platform collects data from the processor during the execution of these tests and analyzes this data to determine whether the processor successfully executes the tests, thereby verifying its proper functioning.

[0003] In related technologies, the verification platform obtains the data to be analyzed by monitoring the processor's input / output pins (such as GPIO pins) and processor registers. This method collects a small amount of data and is difficult to meet analysis requirements. Summary of the Invention

[0004] To this end, this application discloses the following technical solutions:

[0005] A first aspect of the present application provides a processor verification system, comprising a monitoring component and a storage component;

[0006] The storage component is used to store verification use cases;

[0007] The verification case includes a plurality of nodes;

[0008] The verification case is used to trigger the target processor to write node data corresponding to any node of the verification case to the target memory when the target processor executes the verification case, wherein the node data represents the state of the target processor when the node of the verification case is executed;

[0009] The monitoring component is used to monitor the node data of the target processor.

[0010] Optionally, monitoring the node data of the target processor includes:

[0011] When detecting that the node data is updated, obtaining the updated node data;

[0012] The updated node data is output.

[0013] Optionally, monitoring the node data of the target processor includes:

[0014] determining target node data among a plurality of node data of the target processor;

[0015] The target node data of the target processor is monitored.

[0016] Optionally, determining the target node data from the plurality of node data of the target processor includes:

[0017] The target node data is determined from the plurality of node data of the target processor according to a user operation instruction.

[0018] Optionally, monitoring target node data of the target processor includes:

[0019] Determining a target storage address of the target node data;

[0020] Data stored at a target storage address of the target memory is monitored.

[0021] Optionally, the target processor includes a first target processor and a second target processor;

[0022] The monitoring of the node data of the target processor includes:

[0023] When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor;

[0024] The associated second node data is output.

[0025] Optionally, the node data also includes interaction data, which is data transmitted between the first processor and the second processor when executing to the corresponding node of the verification use case.

[0026] Optionally, the monitoring component is further used to:

[0027] Update the nodes included in the verification case.

[0028] A second aspect of the present application provides a processor verification method, comprising:

[0029] Executing a verification case based on a target processor, the verification case including a plurality of nodes;

[0030] When the target processor executes any of the nodes of the verification case, the target memory writes node data corresponding to the node, where the node data represents the state of the target processor when the node of the verification case is executed;

[0031] The node data of the target processor is monitored.

[0032] Optionally, the target processor includes a first target processor and a second target processor;

[0033] The monitoring of the node data of the target processor includes:

[0034] When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor;

[0035] The associated second node data is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0037] Figure 1 This is a schematic diagram of the structure of a processor verification system provided by an embodiment of the present application;

[0038] Figure 2 This is a schematic diagram of writing node data provided by an embodiment of the present application;

[0039] Figure 3 This is a flowchart of a processor verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] This embodiment provides a processor verification system, see Figure 1 The system may include a monitoring component 102 and a storage component 101 .

[0042] The storage component 101 is used to store verification use cases;

[0043] The verification use case includes multiple nodes;

[0044] The verification use case is used to trigger the target processor to write node data corresponding to the node to the target memory when the target processor executes to any node of the verification use case, and the node data represents the state of the target processor when the node of the verification use case is executed;

[0045] The monitoring component 102 is used to monitor the node data of the target processor.

[0046] The monitoring component 102 can be connected to the target storage, thereby monitoring data in the target storage based on the connection.

[0047] The target processor may include a central processing unit (CPU) of an electronic device, and the verification case may include a first verification case for CPU execution. The first verification case may include a CPU-executable computer program (which may be called a C program) developed entirely based on the C language, and may also include data required for the execution of the computer program.

[0048] The verification case program may include multiple pre-set nodes. For example, for the first verification case, the first verification case program may include but is not limited to the following nodes:

[0049] The node that enters the C main function, the node that enters the Handler, the node that completes the IP register configuration, and the node that ends the C program execution.

[0050] The target processor may also include an intellectual property (IP) core of the electronic device. The verification case may include a second verification case for executing the IP core. The second verification case may include a UVM / SV program executable by the IP core and data required to execute the program. UVM stands for Universal Verification Methodology, and SV (SystemVerilog) stands for a hardware description and verification language.

[0051] For the second verification case, the procedure of the second verification case may include but is not limited to the following nodes:

[0052] Nodes that monitor whether the processor has finished configuring the IP registers, nodes that determine whether the IP core can start working, nodes that wait for interrupts to be cleared, nodes that jump out of the while loop, nodes that wait for operations, and nodes that notify the processor.

[0053] Each of the above nodes may include a number of computer instructions edited by a corresponding programming language. When these computer instructions are executed by a target processor, the target processor will access the target memory of the electronic device to which it belongs, and then write the collected node data corresponding to the node into the target memory.

[0054] The node data corresponding to each node may be the same or different, and which node data a node corresponds to may be specified in the computer instructions contained in the node.

[0055] Taking the target processor as a CPU as an example, during the verification process, the CPU can load a first verification case from the storage component and execute the C program contained in the first verification case. Assuming that the verification case includes a node that completes the IP register configuration, each time the CPU configures the IP register, it can execute the computer instructions contained in the node, thereby collecting the node data corresponding to the node, and writing the collected node data into the target memory for storage.

[0056] The monitoring component can monitor the node data stored in the target memory regularly or irregularly based on verification requirements, so that relevant verification engineers can analyze the node data to determine whether the various functions of the target processor are normal during the verification process.

[0057] The beneficial effect of this embodiment is that, in this embodiment, the processor can write node data reflecting the processor status into the target memory when executing the verification use case, and analyze the function of the processor by monitoring the node data of the target memory. Compared with the related technology of collecting data through input / output pins and registers, this embodiment can use the larger storage space of the target memory to collect larger and more comprehensive node data, thereby providing better data support for subsequent analysis of the processor function.

[0058] In this embodiment, the target memory and the storage component can be two different modules. The storage component can be a disk, hard disk or other module capable of storing data included in the verification system of this embodiment for storing verification use cases. The target memory can be any storage medium for storing data in the system to which the target processor belongs (that is, the system to be verified), including but not limited to the disk, hard disk, memory stick, etc. of the system.

[0059] As an example, when the verification system of this embodiment verifies a target processor installed in a server, the target memory may be a memory bar of the server.

[0060] The benefits of the verification system of this embodiment monitoring node data through the target memory are:

[0061] Any computer system necessarily contains several memories. These memories can generally be read and written in a common way, and reading and writing data in these memories generally does not affect the functions of the system's processors. Therefore, when using it, you only need to connect the monitoring component to the memory of the system being verified, and you can use the monitoring component to verify the target processor of the verified system;

[0062] In contrast, registers and GPIO pins vary significantly across computer systems, and reading and writing registers and GPIO pins may affect the normal operation of the target processor in the system. Therefore, when verifying a target processor through registers or GPIO pins in related technologies, it is obvious that the GPIO pins and registers in the system being verified must be configured accordingly.

[0063] It can be seen that the verification system of this embodiment can be conveniently used to verify the target processors of various different computer systems, while the verification solution through registers or GPIO pins needs to rely on a specific computer system. Therefore, the verification system of this embodiment has higher portability and can be applied to the verification of multiple computer systems.

[0064] The target processor can collect and write node data to the target memory in a variety of ways. As an example, the target processor can encapsulate the collected node data into a node data packet according to a certain format and write the node data packet to the target memory.

[0065] As an example, a node data packet may include 32 bits of data as shown in Table 1, wherein the meaning and default value of each part of the data are as shown in Table 1.

[0066]

[0067] Taking the node data packet shown in Table 1 as an example, when the target processor executes a node, it can determine whether the processor has just entered the main function of the C program. If so, the 0th bit of the node data packet is determined to be 1. If not, the 0th bit of the node data packet is determined to be 0. Similarly, the target processor can respectively determine whether the register of the current IP core is configured, whether the program jumps out of the wait state, whether the program jumps out of the while loop, whether the IP core in the system starts working, and whether the processor has completed executing the main function. Based on the determination results, bits 1 to 3, bit 24, and bit 31 of the node data packet are configured, and the interrupt number and exception number of the processor (if interrupts and exceptions exist) are obtained as the data of bits 4 to 23 of the node data packet. The data of bits 24 to 30 are set to 0, thereby obtaining a node data packet. The target processor can then write the node data packet to the target memory.

[0068] Optionally, for any node, the node data corresponding to the node may include other data in addition to the data defined in Table 1.

[0069] As some examples, the node data of a node may include data sent by the target processor to other processors and / or received from other processors. For example, when the target processor is a CPU, the node data of a node may include data sent by the CPU to other IP cores in the system when executing at the node, as well as data sent by other IP cores to the CPU.

[0070] As other examples, the node data of a node may include various data obtained by the target processor executing the program contained in the verification case, such as the processing result data output by the program at the end of the execution of the program, the intermediate data generated during the execution of the program, etc.

[0071] During the execution of the verification use case by the target processor, the target processor may execute to the same node multiple times. Each time the target processor executes to a node, the target processor may write a node data corresponding to the node. In the target memory, the same node may correspond to multiple node data.

[0072] For example, during the execution of the verification use case, the CPU may execute the node entering the Handler multiple times in succession. Each time the CPU executes the node, it writes a copy of the node data of the node to the target memory (for example, writes a node data packet corresponding to the node). Correspondingly, the target memory may contain multiple copies of node data corresponding to the node entering the Handler.

[0073] In a computer system, a handler can be understood as a program responsible for handling specific tasks or events. This handler can perform corresponding operations based on input parameters or events. For example, an operating system may have interrupt handlers and event handlers. When a hardware interrupt event occurs, the target processor can enter the interrupt handler to handle the hardware interrupt event. When a user interaction operation event occurs, the target processor can enter the event handler to handle the user interaction operation.

[0074] The monitoring component 102 may monitor the node data of the target processor in the following manner:

[0075] When detecting that the node data is updated, the updated node data is obtained;

[0076] Output the updated node data.

[0077] Monitoring that the node data is updated may include monitoring that new node data is added to the target storage. In this case, the updated node data may include the new node data.

[0078] As an example, when the monitoring component detects a node data packet corresponding to a new node entering the Handler in the target memory, the monitoring component can read the node data packet from the target memory and output the node data packet as updated node data.

[0079] Monitoring that node data is updated may also include monitoring that new node data different from the original node data in the target memory is written into the target memory. In this case, the updated node data may include the new node data different from the original node data in the target memory.

[0080] As an example, when the monitoring component detects a new node data packet corresponding to a node entering the Handler in the target memory, it can compare this new node data packet with the node data packet corresponding to the node entering the Handler previously written by the target processor. If the two are inconsistent, it is determined that the node data corresponding to the node entering the Handler is updated, and the new node data packet is obtained as the updated node data.

[0081] Monitoring that the node data is updated may also include monitoring that new node data different from the original node data in the target memory is written into the target memory, and the target data contained in the new node data is different from the target data contained in the original node data.

[0082] The target data may be a specific portion of the node data. In conjunction with the example in Table 1, a portion of the node data written to the memory by the target processor may be a node data packet shown in Table 1, and the target data may be bits 12 to 19 of the node data packet, i.e., the hexadecimal data representing the interrupt number (in hexadecimal) entering the interrupt handler.

[0083] Combined with the above example, if a node data packet corresponding to a new node entering the Handler is monitored in the target memory, and it is determined that the target data in this new node data packet is different from the target data in the node data packet of the node entering the Handler written last time, that is, the data of the 12th to 19th bits of the two node data packets are different, then it is determined that the node data corresponding to the node entering the Handler is updated. At this time, the monitoring component can obtain this new node data packet as the updated node data.

[0084] The monitoring component can output the updated node data in a variety of ways. For example, the monitoring component can print the updated node data as an electronic document or a paper document, or the monitoring component can display the updated node data on a display screen.

[0085] In some embodiments, when the monitoring component outputs updated node data, it may output only a portion of the updated node data. For example, using the node data packet shown in Table 1, the monitoring component may output only bits 12 to 19 of the updated node data packet. The monitoring component may determine which data in the node data packet to output based on user input.

[0086] In some optional embodiments, in order to reduce power consumption of the monitoring component, the monitoring component may monitor only a portion of the node data when monitoring the node data. In other words, the monitoring component may:

[0087] determining target node data among a plurality of node data of a target processor;

[0088] Monitor target node data of the target processor.

[0089] In the above embodiment, the monitoring component can determine at least one target node from the multiple nodes included in the verification use case, and use the node data written when the target processor executes the target node as the target node data. Then, the monitoring component can only monitor whether the target node data is updated, and output the updated target node data when it is detected that the target node data is updated.

[0090] As an example, assuming that the monitoring component determines that the node that has completed the IP register configuration is the target node, the monitoring component can only monitor whether the node data of the node that has completed the IP register configuration in the target memory is updated, and output the updated node data of the node that has completed the IP register configuration when the update is detected, and the node data of other nodes will not be monitored and output.

[0091] The monitoring component can determine the target node data in the following ways:

[0092] Target node data is determined among a plurality of node data of a target processor according to a user operation instruction.

[0093] In this embodiment, when determining the target node, the monitoring component can prompt the user to enter one or more node identifiers, or prompt the user to select one or more node identifiers from multiple node identifiers, and then determine the node corresponding to the node identifier entered or selected by the user as the target node, and then determine the node data corresponding to the target node as the target node data.

[0094] Exemplarily, when determining the target node, the user can select node identifier 3 representing the node that has completed the IP register configuration. Thus, the monitoring component can determine that the target node is the node that has completed the IP register configuration and use the node data corresponding to the target node as the target node data.

[0095] In some optional embodiments, several storage addresses for storing node data can be pre-specified in the target memory, each storage address corresponds to a node of the verification use case, and each time the target processor executes a node, the obtained node data of the node can be written into the storage address corresponding to the node for storage.

[0096] For example, see Figure 2 In the target memory, storage address 1 to storage address N can be specified, which correspond to nodes 1 to node N of the verification use case in sequence. When the target processor executes the verification use case, when it executes to node 1, it obtains node data 1 corresponding to node 1 and writes node data 1 to storage address 1. When it executes to node 2, it obtains node data 2 corresponding to node 2 and writes node data 2 to storage address 2, and so on.

[0097] Based on the above storage method, when monitoring target node data, the monitoring component can:

[0098] Determine the target storage address of the target node data;

[0099] Data stored at a target storage address of a target memory is monitored.

[0100] For example, after determining that the target node is node 4, the monitoring component can detect in real time whether the node data at storage address 4 in the target memory is updated. If it is detected that the node data at storage address 4 is updated, the updated node data stored in storage address 4 is obtained and output.

[0101] Optionally, the monitoring component can also be used to:

[0102] Update the nodes included in the verification case.

[0103] In this embodiment, the monitoring component can display the program included in the verification use case based on the user operation, so that the user can add or delete a node at any position in the program.

[0104] For any existing node in the verification use case, the monitoring component can display the computer instructions contained in the node on the display screen, allowing the user to add, delete or modify the computer instructions in the node as needed.

[0105] In some optional embodiments, the target processor may include a first target processor and a second target processor;

[0106] When monitoring the node data of the target processor, the monitoring component can be used to:

[0107] When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor;

[0108] Output the associated second node data.

[0109] As some examples, the first target processor may be a CPU and the second target processor may be an IP core.

[0110] If there are two nodes with a dependency relationship between the first verification case executed by the first target processor and the second verification case executed by the second target processor, that is, there is a dependency relationship between the first node of the first verification case and the second node of the second verification case, then it can be considered that the first node data corresponding to the first node and the second node data corresponding to the second node are associated.

[0111] In this embodiment, if the first node and the second node are both related to a specific portion of data, it can be considered that there is a dependency relationship between the first node and the second node. Exemplarily, in the following cases, it can be considered that there is a dependency relationship between the first node and the second node:

[0112] When the first target processor executes the first node of the first verification case, it sends specific data to the second target processor. When the second target processor executes the second node of the second verification case, it processes the specific data sent by the first target processor.

[0113] In this embodiment, the monitoring component can analyze the node data written by the first target processor and the node data written by the second target processor to determine which node data are related to each other. For example, if node data A written by the first target processor and node data B written by the second target processor both contain data C, and data C is data sent from the first target processor to the second target processor, or from the second target processor to the first target processor, in this case, it can be determined that there is a dependency relationship between the node corresponding to node data A and the node corresponding to node data B, and node data A and node data B are related to each other.

[0114] Alternatively, the monitoring component may determine which node data are related to each other based on the dependencies between nodes pre-set by the user.

[0115] Optionally, the target memory can store multiple second node data written by the second target processor multiple times. When it is detected that the first node data written by the first target processor is updated, the monitoring component can obtain the data associated with the updated first node from the target memory, and output the second node data written by the second target processor most recently.

[0116] In the above embodiment, the monitoring component may output the second node data and the updated first node data together.

[0117] This embodiment also provides a processor verification method, see Figure 3 , is a flowchart of the method, which may include the following steps.

[0118] S301, executing a verification case based on a target processor, where the verification case includes multiple nodes.

[0119] S302 , when the target processor executes any node of the verification use case, the target memory writes node data corresponding to the node, where the node data represents the state of the target processor when executing the node of the verification use case.

[0120] S303: Monitor the node data of the target processor.

[0121] Optionally, the target processor includes a first target processor and a second target processor;

[0122] Monitors the target processor's node data, including:

[0123] When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor.

[0124] The implementation of the processor verification method of this embodiment can refer to the working principle of the aforementioned processor verification system, which will not be described in detail.

[0125] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0126] For the convenience of description, the above systems or devices are described as being divided into various modules or units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0127] Through the description of the above embodiments, it can be seen that those skilled in the art can clearly understand that the present application can be implemented by means of software plus the necessary general hardware platform. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments of the present application or certain parts of the embodiments.

[0128] Finally, it should be noted that, in this document, relational terms such as first, second, third, and fourth are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0129] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A processor verification system comprising a monitoring component and a storage component; The storage component is used to store verification use cases; The verification case includes a plurality of nodes, and the plurality of nodes correspond to a plurality of stages when the verification case is executed; The verification case is used to trigger the target processor to write node data corresponding to any node of the verification case to the target memory when the target processor executes the verification case, wherein the node data represents the state of the target processor when the node of the verification case is executed; The monitoring component is used to monitor the node data of the target processor; The target processor includes a first target processor and a second target processor, the first target processor and the second target processor are of different types, and the type of the verification case executed by the first target processor is different from the type of the verification case executed by the second target processor; The verification case executed by the first target processor includes a first node, the verification case executed by the second target processor includes a second node, the first node and the second node have a dependency relationship, and the node data includes first node data corresponding to the first node and second node data corresponding to the second node; The node data also includes interaction data, which is data transmitted between the first target processor and the second target processor when executing to the corresponding node of the verification use case.

2. The system according to claim 1, wherein monitoring the node data of the target processor comprises: When detecting that the node data is updated, obtaining the updated node data; The updated node data is output.

3. The system according to claim 1, wherein monitoring the node data of the target processor comprises: determining target node data among a plurality of node data of the target processor; The target node data of the target processor is monitored.

4. The system according to claim 3, wherein determining the target node data from the plurality of node data of the target processor comprises: The target node data is determined from the plurality of node data of the target processor according to a user operation instruction.

5. The system according to claim 3, wherein monitoring target node data of the target processor comprises: Determining a target storage address of the target node data; Data stored at a target storage address of the target memory is monitored.

6. The system according to claim 1, wherein monitoring the node data of the target processor comprises: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; The associated second node data is output.

7. The system according to claim 1, wherein the monitoring component is further configured to: Update the nodes included in the verification case.

8. A processor verification method, comprising: Executing a verification case based on a target processor, the verification case including a plurality of nodes, the plurality of nodes corresponding to a plurality of stages when the verification case is executed; When the target processor executes any of the nodes of the verification case, the target memory writes node data corresponding to the node, where the node data represents the state of the target processor when the node of the verification case is executed; monitoring the node data of the target processor; The target processor includes a first target processor and a second target processor, the first target processor and the second target processor are of different types, and the type of the verification case executed by the first target processor is different from the type of the verification case executed by the second target processor; The verification case executed by the first target processor includes a first node, the verification case executed by the second target processor includes a second node, the first node and the second node have a dependency relationship, and the node data includes first node data corresponding to the first node and second node data corresponding to the second node; The node data also includes interaction data, which is data transmitted between the first target processor and the second target processor when executing to the corresponding node of the verification use case.

9. The method according to claim 8, wherein monitoring the node data of the target processor comprises: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; The associated second node data is output.

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