A hardware implementation method for single-root virtualization of RDMA network cards supporting Ethernet

Abstract

The present invention relates to a hardware implementation method for single-root virtualization of an Ethernet-supported RDMA network card, comprising: offsetting input read and write addresses using offset information; performing TLP header framing on requester_id information using VF configuration information; performing TLP header framing and interrupt number assignment on the requester_id information; maintaining the req_queue register of the rcq descriptor using the qp_num register and the destination MAC register using the dest_mac register; forwarding the obtained destination MAC address and queue number information using the destination MAC address and reporting the corresponding queue number information. The present invention has minimal changes to data and control paths, low resource consumption, flexible resource allocation, and extremely high flexibility and compatibility.

Description

Technical Field

[0001] The present invention relates to the technical field of network card virtualization, and in particular to a hardware implementation method for single-root virtualization of an Ethernet-supported RDMA network card. Background Art

[0002] With the rapid development of technologies such as artificial intelligence, cloud computing, and distributed computing, the scale and data volume of data centers have increased significantly, creating enormous data transmission demands for the distributed and parallel processing of big data applications. However, traditional TCP / IP (Transmission Control Protocol / Internet Protocol) technology, when handling large-scale data transmission, consumes a large amount of server resources and memory bus bandwidth due to the need to pass through the operating system and software layers. This in turn places a heavy burden on the CPU (Central Processing Unit) and memory. This is especially serious when there is a mismatch between network bandwidth, processor speed, and memory bandwidth, which exacerbates network latency.

[0003] To address this issue, Remote Direct Memory Access (RDMA) technology has been introduced and widely used in modern data centers. Leveraging CPU bypass and zero-copy mechanisms, RDMA effectively reduces data transmission latency, significantly alleviating CPU load and memory bandwidth bottlenecks, thereby improving bandwidth utilization. Through RDMA, applications can directly read and write to the virtual memory of a remote server, bypassing the complex processing at the operating system and software levels. The core advantages of RDMA technology include extremely low transmission latency, high throughput, and minimal dependence on CPU resources. This technology provides an efficient I / O channel, particularly well-suited for big data applications, enabling fast and efficient data transmission and processing, significantly improving overall performance and efficiency within the data center. RDMA technology excels particularly in handling large-scale parallel computing and data analysis tasks, providing crucial technical support and optimization solutions for the high-performance computing needs of modern data centers. In summary, RDMA technology not only improves data transmission efficiency and responsiveness, but also reduces system resource consumption, making it an indispensable key technology in modern data centers, bringing significant performance improvements and operational efficiency to various data-intensive application scenarios.

[0004] Therefore, a standard Ethernet-compatible RDMA network card offers significant advantages in terms of performance, latency, throughput, CPU load, compatibility, flexibility, simplified network architecture, and data center optimization. It can operate seamlessly in standard network environments while leveraging the advantages of RDMA in scenarios requiring high-performance network transmission. This dual functionality enables more flexible network infrastructure design and deployment, adapting to diverse application requirements and network environments. Furthermore, using a standard Ethernet- and RDMA-compatible network card allows multiple applications to be supported on the same network infrastructure, reducing the procurement and maintenance costs of disparate network hardware. This simplifies network architecture and reduces management complexity while ensuring high performance and reliability. These advantages not only improve network transmission efficiency and performance but also provide more flexible and efficient solutions for complex and diverse application scenarios. By effectively leveraging the characteristics of this network card, data transmission and processing capabilities within a network environment can be significantly optimized, meeting the demands of modern high-performance computing and data centers.

[0005] Furthermore, hardware-based virtualization currently primarily utilizes the single-root virtualization standard. Single-root I / O Virtualization (SR-IOV) is a hardware virtualization technology widely researched and applied in academia and industry, primarily used to improve the performance and efficiency of I / O devices in virtualized environments. In traditional software virtualization, network packets must pass through the host operating system's network protocol stack, incurring additional CPU overhead and transmission latency. In contrast, SR-IOV allows virtual functions (VFs) to directly access the hardware resources of physical devices, bypassing these intermediary layers and achieving performance levels close to those of the hardware itself. This is particularly important for applications requiring high throughput, low latency, and large-scale data transfer. The core concept of SR-IOV technology is to virtualize a single physical I / O device (such as a network interface card or storage controller) into multiple virtual functions (VFs) through hardware-level support. These VFs can be directly assigned to virtual machines or containers, each with its own independent PCI configuration space and DMA (Direct Memory Access) engine. The basic functions of physical devices are managed and controlled by physical functions (PFs), which are responsible for allocating and reclaiming VFs and providing management interfaces. SR-IOV technology uses a hardware-level resource isolation mechanism to ensure that data and resources between different VFs are completely isolated, preventing data leakage and conflicts. SR-IOV technology also supports the dynamic creation and destruction of VFs, allowing administrators to flexibly configure and allocate device resources to different virtual machines or containers based on actual needs. This flexibility makes resource management more efficient and can support the expansion needs of large-scale data centers and cloud computing environments. With the rapid development of emerging technologies such as big data, artificial intelligence, and cloud computing, the demand for efficient, flexible, and scalable data center solutions continues to increase. As a technology based on hardware virtualization, SR-IOV can provide a solid technical foundation and support for future technological development, helping the academic community achieve more innovative results in fields such as high-performance computing and large-scale data processing.

[0006] In summary, hardware-implemented single-root virtualization and RDMA-capable Ethernet network cards offer exceptional flexibility and compatibility, improving data center performance and efficiency, meeting the high-performance demands of virtualized environments, reducing system resource consumption and costs, enhancing security and isolation, and providing essential technical support for future technological development. This makes them highly promising and valuable in academic research, industrial applications, and large-scale computing environments.

[0007] However, hardware-based implementation of single-root virtualization on Ethernet RDMA-capable network cards presents the challenge of requiring modifications to existing control and data paths, introducing new hardware processing delays. This can also significantly increase resource consumption, making it less suitable for resource-constrained hardware development platforms. Summary of the Invention

[0008] In order to solve the above problems existing in the prior art, the present invention provides a hardware implementation method for single-root virtualization of an RDMA network card supporting Ethernet.

[0009] According to a first aspect of an embodiment of the present invention, a method for hardware implementation of single-root virtualization of an Ethernet-supported RDMA network card is provided, the method comprising:

[0010] Maintain the offset register through the VF_offset register to obtain the offset information;

[0011] By allocating MMIO resources using the offset information, the input read and write addresses are offset to achieve allocation and isolation of MMIO resources of PF and VF;

[0012] Maintain the requester_id register of the tlp header through the VF_config register to obtain VF configuration information;

[0013] By allocating DMA resources using the VF configuration information and performing TLP header framing on the requester_id information, the DMA resources of the PF and the VF are allocated and isolated;

[0014] Maintaining the requester_id register of the tlp header through the requester_id register to obtain the requester_id information;

[0015] By using the requester_id information to allocate interrupt resources, framing the requester_id information into a tlp header and allocating an interrupt number, the interrupt resources of the PF and the VF are allocated and isolated;

[0016] The req_queue register of the rcq descriptor is maintained through the qp_num register, and the destination MAC register is maintained through the dest_mac register to obtain the destination MAC address for forwarding RX traffic and the queue number information for calling the RQ queue;

[0017] The message is forwarded through the destination MAC address and the corresponding queue number information is reported, so as to achieve correct forwarding and splitting of the RX traffic of the PF and the VF and reporting of the queue number.

[0018] Optionally, allocating MMIO resources by using the offset information to offset the input read and write addresses includes:

[0019] After the read / write address is input, whether it is VF is determined based on the device function number carried by the read / write address;

[0020] When the read / write address is a VF, determining whether the read / write address is within a processable range of the VF;

[0021] When the read / write address is not within the processable range, discarding the read / write address;

[0022] When the read / write address is within the processable range, the read / write address is offset according to the corresponding preset offset value and output, so as to achieve allocation and isolation of MMIO resources of PF and VF.

[0023] Optionally, the VF configuration information includes: VF_en and VF_function; the VF_en is a 1-bit register, when the flag bit is 1, it indicates that the VF is enabled, when the flag bit is 0, it indicates that the VF is not enabled, and the initial value is 0; the VF_function is an 8-bit register, indicating the device function number corresponding to the VF, and the initial value is 0.

[0024] Optionally, allocating DMA resources by using the VF configuration information and performing TLP header framing on the requester_id information includes:

[0025] Obtain the first VF enable bit in the VF configuration information corresponding to the standard Ethernet mode;

[0026] When the first VF enable bit is not pulled high, the device function number corresponding to the PF is used as the information for TLP header framing;

[0027] When the first VF enable bit is pulled high, the device function number corresponding to the VF is used as the information for TLP header framing;

[0028] The device function number, which is used as information for tlp header framing, is output to the DMA engine and the framing module of the tlp header, so as to allocate and isolate the DMA resources of the PF and the VF.

[0029] Optionally, allocating DMA resources by using the VF configuration information and performing TLP header framing on the requester_id information further includes:

[0030] Get the second VF enable bit in the VF configuration information corresponding to the RDMA mode;

[0031] When the second VF enable bit is not pulled high, the device function number of the PF is used as the information for TLP header framing;

[0032] When the second VF enable bit is pulled high, the device function number corresponding to the VF is used as the information for TLP header framing;

[0033] The device function number, which is used as information for tlp header framing, is output to the DMA engine and the framing module of the tlp header, so as to allocate and isolate the DMA resources of the PF and the VF.

[0034] Optionally, allocating interrupt resources by using the requester_id information, framing the requester_id information into a tlp header, and allocating an interrupt number, includes:

[0035] Determine whether the interrupt is a VF interrupt based on the device function number in the requester_id information;

[0036] If the interrupt is not a VF interrupt, the interrupt number corresponding to the interrupt and the PF pcie device function number in the requester_id information are output to the PF interrupt processing module, and the first tlp data returned by the PF interrupt processing module is obtained;

[0037] If the interrupt is a VF interrupt, the interrupt number corresponding to the interrupt and the PCIe device function number of the VF in the requester_id information are output to the VF interrupt processing module, and the second TLP data returned by the VF interrupt processing module is obtained;

[0038] Output valid data of the first TLP data or the second TLP data to allocate and isolate interrupt resources of the PF and the VF.

[0039] Optionally, forwarding the packet according to the destination MAC address and reporting corresponding queue number information includes:

[0040] When the destination MAC address is the MAC address of the PF, forward the first queue number information corresponding to the message and the PF to the PF port, and report the first queue number information to the queue management module;

[0041] When the destination MAC address is the MAC address of the VF, the second queue number information corresponding to the message and the VF is forwarded to the VF port, and the second queue number information is reported to the queue management module.

[0042] According to a second aspect of an embodiment of the present invention, there is provided a hardware implementation device for single-root virtualization of an RDMA network card supporting Ethernet, the device comprising:

[0043] A first information acquisition module is configured to maintain an offset register through a VF_offset register to obtain offset information;

[0044] A first resource allocation module is configured to allocate MMIO resources by utilizing the offset information and offset the input read and write addresses to achieve allocation and isolation of MMIO resources of PFs and VFs;

[0045] The second information acquisition module is used to maintain the requester_id register of the tlp header through the VF_config register to obtain VF configuration information;

[0046] A second resource allocation module is configured to allocate DMA resources by utilizing the VF configuration information and perform TLP header framing on the requester_id information to achieve allocation and isolation of DMA resources between the PF and the VF;

[0047] A third information acquisition module is used to maintain the requester_id register of the tlp header through the requester_id register to obtain the requester_id information;

[0048] a third resource allocation module, configured to allocate interrupt resources by utilizing the requester_id information, perform tlp header framing and interrupt number allocation on the requester_id information, so as to allocate and isolate the interrupt resources of the PF and the VF;

[0049] The fourth information acquisition module is used to maintain the req_queue register of the rcq descriptor through the qp_num register and the destination MAC register through the dest_mac register to obtain the destination MAC address for forwarding RX traffic and the queue number information for calling the RQ queue;

[0050] The information processing module is used to forward the message through the destination MAC address and report the corresponding queue number information, so as to correctly forward and split the RX traffic of the PF and the VF and report the queue number.

[0051] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, comprising: a processor; a memory for storing instructions executable by the processor;

[0052] The processor is configured to: execute the executable instructions to implement the steps of the hardware implementation method for single-root virtualization of an RDMA network card supporting Ethernet as described in any one of the embodiments of the first aspect above.

[0053] According to a fourth aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which computer program instructions are stored. When the program instructions are executed by a processor, the steps of the hardware implementation method for single-root virtualization of an RDMA network card supporting Ethernet described in the first aspect of the present invention are implemented.

[0054] The technical solution provided by the present invention can have the following beneficial effects:

[0055] Through the above technical solution, SR-IOV virtualization can be implemented through hardware means. Compared with traditional software virtualization, it does not cause additional CPU overhead and transmission delay, improves the performance and efficiency of I / O devices in the virtualized environment, and at the same time, by using the offset idea to allocate MMIO resources, it is possible to achieve the allocation of MMIO resources with minimal changes to the data and control paths. By calling existing signals, such as the function number and destination MAC address of the PCIe device, the allocation of DMA and interrupt resources and the forwarding of RX traffic are achieved using fewer hardware resources. The present invention has the effects of minimal changes to the data and control paths, low resource consumption, high isolation, flexible resource allocation, and basically no introduction of new hardware processing delays. It has extremely high flexibility and compatibility and has important application prospects and practical value in academic research, industrial applications and large-scale computing environments.

[0056] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0058] Figure 1 The present invention is a flowchart showing a method for hardware implementation of single-root virtualization of an Ethernet-supporting RDMA network card according to an exemplary embodiment.

[0059] Figure 2 It is a system framework diagram according to an exemplary embodiment.

[0060] Figure 3 The flowchart shows a method for allocating and isolating MMIO resources of PFs and VFs according to an exemplary embodiment.

[0061] Figure 4 is a schematic diagram showing a VF_config register format according to an exemplary embodiment.

[0062] Figure 5 The flowchart shows a method for allocating and isolating DMA resources of PF and VF according to an exemplary embodiment.

[0063] Figure 6 The flowchart shows another method of allocating and isolating DMA resources of PF and VF according to an exemplary embodiment.

[0064] Figure 7 The flowchart shows a method for allocating and isolating interruption resources of PFs and VFs according to an exemplary embodiment.

[0065] Figure 8 The flowchart shows a method for allocating and isolating interruption resources of PFs and VFs according to an exemplary embodiment.

[0066] Figure 9 The present invention is a block diagram showing a hardware implementation device for a single-root virtualization RDMA network card supporting Ethernet according to an exemplary embodiment.

[0067] Figure 10 The present invention is a block diagram of an electronic device showing a hardware implementation method for supporting Ethernet RDMA network card single root virtualization according to an exemplary embodiment. DETAILED DESCRIPTION

[0068] Figure 1 FIG. 1 is a flowchart of a method for implementing single-root virtualization hardware of an Ethernet-supporting RDMA network card according to an exemplary embodiment. Figure 1 As shown, the method may include the following steps:

[0069] S101. Maintain the offset register through the VF_offset register to obtain offset information.

[0070] S102 : Allocate MMIO resources by using the offset information and offset the input read and write addresses to achieve allocation and isolation of MMIO resources of the PF and VF.

[0071] Figure 2is a system framework diagram according to an exemplary embodiment, and the present invention can be applied to the system, such as Figure 2 As shown, the system may include PEIe IP, MMIO resource allocation module, interrupt resource allocation module, DMA resource allocation module, queue management module, QPC module, RDMA IP module, interface module, RX module, RX (receive side) traffic forwarding module, TX (transmit side) module and MAC (media access control) module;

[0072] It's understandable that PCIe IP can be generated through software. When generating IP, ensure that single-root virtualization and interrupts are enabled. In the MMIO resource allocation module, the VF_offset register (VF offset register) maintains the offset register (offset register) related to MMIO resource allocation, providing offset information for MMIO resource allocation. Through MMIO resource allocation, read and write addresses are offset according to this offset information, thereby allocating and isolating MMIO resources for PFs and virtual functions (VFs).

[0073] Optionally, S102 may include:

[0074] After the read / write address is input, it is determined whether it is VF based on the device function number carried in the read / write address;

[0075] When the read / write address is VF, it is determined whether the read / write address is within the processable range of VF;

[0076] When the read / write address is not within the processable range, the read / write address is discarded;

[0077] When the read / write address is within the processable range, the read / write address is offset and output according to the corresponding preset offset value to achieve allocation and isolation of MMIO resources of PF and VF.

[0078] In one embodiment, Figure 3 FIG. 1 is a flow chart showing allocation and isolation of MMIO resources of PF and VF according to an exemplary embodiment. Figure 3 As shown, there can be multiple processable intervals. When the read / write address is not in processable interval 1, it is determined whether the read / write address is in processable interval 2. When the read / write address is not in any processable interval, the read / write address is discarded. When the read / write address is in any processable interval, the read / write address is offset according to the corresponding preset offset value and output, so as to realize the allocation and isolation of MMIO resources of PF and VF.

[0079] S103: Maintain the requester_id register of the tlp header through the VF_config register to obtain VF configuration information.

[0080] Optionally, Figure 4 This is a schematic diagram of the VF_config register format according to an exemplary embodiment. VF configuration information may include: VF_en and VF_function; VF_en is a 1-bit register. When the flag bit is 1, it indicates that the VF is enabled. When the flag bit is 0, it indicates that the VF is disabled. The initial value is 0; VF_function is an 8-bit register that indicates the first device function number corresponding to the VF. The initial value is 0.

[0081] S104: Allocate DMA resources by using the VF configuration information and perform TLP header framing on the requester_id information to achieve allocation and isolation of DMA resources for the PF and VF.

[0082] It is understood that the DMA resource allocation module can perform tlp header framing on the requester_id information according to the information provided by the VF_config register, thereby allocating and isolating DMA resources of the physical function (PF) and the virtual function (VF);

[0083] In addition, the queue management module can maintain the five queue states of the corresponding network interface: transmission, transmission completion, reception, reception completion, and event queue. In this embodiment, it is also used to store the VF_config configuration information required for DMA resource allocation when the standard Ethernet card side hardware implements single-root virtualization;

[0084] It is worth mentioning that the RMDA IP module is used to implement the RMDA function and the QPC module is placed in this module. The QPC module is subordinate to the RDMA IP module used to implement the RDMA function and is used to maintain queue information for the network protocol stack module to frame and send RoCEV2 frames / Ethernet frames. In this embodiment, it is also used to store the VF_config configuration information required for DMA resource allocation when the RDMA network card side hardware implements single-root virtualization.

[0085] In one embodiment, an interface module is created, and the queue management module is connected to the RMDA ip containing the QPC module and placed in the interface module.

[0086] Optionally, S104 may include:

[0087] Obtain the first VF enable bit in the VF configuration information corresponding to the standard Ethernet mode;

[0088] When the first VF enable bit is not pulled high, the device function number corresponding to the PF is used as the information for TLP header framing;

[0089] When the first VF enable bit is pulled high, the device function number corresponding to the VF is used as the information for TLP header framing;

[0090] The device function number, which is used as the information for TLP header framing, is output to the DMA engine and the TLP header framing module to allocate and isolate DMA resources for PF and VF.

[0091] In one embodiment, Figure 5 FIG. 1 is a flow chart showing how to allocate and isolate DMA resources of PF and VF according to an exemplary embodiment. Figure 5 As shown, in the standard Ethernet mode, the first VF enable bit in the VF configuration information written by the driver into the register in the standard Ethernet IP logic is obtained from the queue management module, and the device function number corresponding to the PF or the device function number corresponding to the VF is selected according to the specific situation of the first VF enable bit to perform TLP header (transaction layer data packet header) framing information.

[0092] Optionally, S104 may further include:

[0093] Get the second VF enable bit in the VF configuration information corresponding to the RDMA mode;

[0094] When the second VF enable bit is not pulled high, the PF device function number is used as the information for TLP header framing;

[0095] When the second VF enable bit is pulled high, the device function number corresponding to the VF is used as the information for TLP header framing;

[0096] The device function number, which is used as the information for TLP header framing, is output to the DMA engine and the TLP header framing module to allocate and isolate DMA resources for PF and VF.

[0097] In one embodiment, Figure 6 FIG. 1 is another flow chart showing another method of allocating and isolating DMA resources of PF and VF according to an exemplary embodiment. Figure 6 As shown, in RDMA mode, the first VF enable bit in the VF configuration information written by the driver into the register in the RDMA IP logic is obtained from the QPC (Queue Pair Context) module, and the device function number corresponding to the PF or the device function number corresponding to the VF is selected according to the specific situation of the first VF enable bit for TLP header framing information.

[0098] S105. Maintain the requester_id register of the tlp header through the requester_id register to obtain requester_id information.

[0099] S106 , allocating interrupt resources by using the requester_id information, framing the requester_id information into a tlpheader, and allocating an interrupt number, so as to achieve allocation and isolation of the interrupt resources of the PF and VF.

[0100] It can be understood that the interrupt resource allocation module can perform tlp header framing and interrupt number allocation on the requester_id (requester number) information according to the information provided by the requester_id register through interrupt resource allocation, thereby allocating and isolating the interrupt resources of the physical function (PF) and the virtual function (VF).

[0101] Optionally, S106 may include:

[0102] Determine whether the interrupt is a VF interrupt based on the device function number in the requester_id information;

[0103] If the interrupt is not a VF interrupt, the interrupt number corresponding to the interrupt and the PF pcie device function number in the requester_id information are output to the PF interrupt processing module, and the first tlp data returned by the PF interrupt processing module is obtained;

[0104] If the interrupt is a VF interrupt, the interrupt number corresponding to the interrupt and the VF pcie device function number in the requester_id information are output to the VF interrupt processing module, and the second tlp data returned by the VF interrupt processing module is obtained;

[0105] Output valid data in the first TLP data or the second TLP data to allocate and isolate interrupt resources of PF and VF.

[0106] In one embodiment, Figure 7 FIG. 1 is a flow chart showing how to allocate and isolate interrupt resources for PF and VF according to an exemplary embodiment. Figure 7 As shown, the interrupt is determined to be a PF interrupt or a VF interrupt, and then the corresponding PCIe device function number is output to the corresponding interrupt processing module. Then, the TLP data returned by the corresponding module is obtained, and the valid data in the first TLP data or the second TLP data is output to realize the allocation and isolation of the interrupt resources of the PF and VF.

[0107] S107. Maintain the req_queue (request queue) register of the rcq (receive completion queue) descriptor through the qp_num (queue number) register, and maintain the destination MAC register through the dest_mac register to obtain the destination MAC address for forwarding RX traffic and the queue number information for calling the RQ queue.

[0108] It is understood that the RX module can manage the receive data path, including receiving messages returned by the MAC, dequeuing and retrieving DMA descriptors, receiving DMA data packets, writing back DMA data, recording and writing back completed DMA enqueues, and processing PTP timestamps. In this embodiment, it is used to connect the eSwitch module and the interface module;

[0109] The eSwitch module, namely the RX traffic forwarding module, can maintain the req_queue register of the rcq descriptor through the qp_num register and the destination MAC register through the dest_mac register, providing the destination MAC information for the forwarding of RX traffic and the queue number information for calling the RQ queue. Through RX traffic forwarding, packets are forwarded according to the destination MAC and reported according to the corresponding queue number, thereby achieving correct forwarding and splitting of RX traffic of physical functions (PFs) and virtual functions (VFs) and reporting of queue numbers;

[0110] The TX module manages the transmit data path, including delivering messages to the MAC module, dequeuing and retrieving DMA descriptors, transferring DMA data and packets, recording and writing back completed enqueues via DMA, and handling timestamps.

[0111] The MAC module can provide functions such as addressing mechanism, data frame construction, data error checking, transmission control, and providing a standard data interface to the network layer.

[0112] S108 : Forward the message by the destination MAC address and report the corresponding queue number information, so as to correctly forward and split the RX traffic of PF and VF and report the queue number.

[0113] Optionally, S108 may include:

[0114] When the destination MAC address is the MAC address of the PF, the packet and the first queue number information corresponding to the PF are forwarded to the PF port, and the first queue number information is reported to the queue management module;

[0115] When the destination MAC address is the MAC address of the VF, the second queue number information corresponding to the message and the VF is forwarded to the VF port, and the second queue number information is reported to the queue management module.

[0116] In one embodiment, Figure 8 FIG. 1 is a flow chart showing how to allocate and isolate interrupt resources for PF and VF according to an exemplary embodiment. Figure 8 As shown, by judging whether the destination MAC address belongs to a virtual function, the packet is forwarded and the corresponding queue number information is reported, so as to achieve correct forwarding and splitting of the PF and VF RX traffic and queue number reporting.

[0117] The present invention provides a hardware implementation method for Ethernet-supported RDMA network cards with single-root virtualization. This method enables SR-IOV virtualization through hardware. Compared to traditional software virtualization, it does not incur additional CPU overhead or transmission delays, thereby improving the performance and efficiency of I / O devices in virtualized environments. Furthermore, it is compatible with both standard Ethernet and RDMA network cards, providing a seamless experience in various environments.

[0118] This invention implements MMIO resource allocation through an offset concept, achieving MMIO resource allocation with minimal changes to the data and control paths. Simultaneously, by invoking existing signals, such as the device function number and destination MAC address, it uses fewer hardware resources to implement DMA and interrupt resource allocation, as well as RX traffic forwarding. This approach offers the advantages of minimal changes to the data and control paths, low resource consumption, high isolation, flexible resource allocation, and virtually no new hardware processing delays. Furthermore, this invention achieves both standard Ethernet compatibility and RDMA support within the same network card, while also implementing single-root virtualization capabilities based on hardware. This approach offers significant flexibility and compatibility, can improve data center performance and efficiency, and meet the high-performance requirements of virtualized environments. It holds significant application prospects and practical value in academic research, industrial applications, and large-scale computing environments.

[0119] Figure 9 FIG. 1 is a block diagram of a hardware implementation device for implementing Ethernet RDMA network card single root virtualization according to an exemplary embodiment. Figure 9 As shown, the apparatus 900 may include:

[0120] A first information acquisition module 901 is configured to maintain an offset register through a VF_offset register to obtain offset information;

[0121] A first resource allocation module 902 is configured to allocate MMIO resources by using offset information and offset the input read and write addresses to achieve allocation and isolation of MMIO resources for PFs and VFs;

[0122] The second information acquisition module 903 is used to maintain the requester_id register of the tlp header through the VF_config register to obtain VF configuration information;

[0123] The second resource allocation module 904 is configured to allocate DMA resources by using VF configuration information and perform TLP header framing on the requester_id information to achieve allocation and isolation of DMA resources between PF and VF;

[0124] The third information acquisition module 905 is used to maintain the requester_id register of the tlp header through the requester_id register to obtain the requester_id information;

[0125] The third resource allocation module 906 is configured to allocate interrupt resources by using the requester_id information, framing the requester_id information into a TLP header, and allocating interrupt numbers, so as to allocate and isolate interrupt resources for PFs and VFs.

[0126] The fourth information acquisition module 907 is used to maintain the req_queue register of the rcq descriptor through the qp_num register and the destination MAC register through the dest_mac register to obtain the destination MAC address for forwarding RX traffic and the queue number information for calling the RQ queue;

[0127] The information processing module 908 is used to forward packets according to the destination MAC address and report the corresponding queue number information, so as to correctly forward and split the RX traffic of PF and VF and report the queue number.

[0128] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0129] Figure 10 1 is a block diagram of an electronic device for supporting a hardware implementation method of a single-root virtualization RDMA network card for Ethernet according to an exemplary embodiment. Figure 10 As shown, the electronic device 1000 may include: a processor 1001 and a memory 1002 .

[0130] The processor 1001 is used to control the overall operation of the electronic device 1000 to complete all or part of the steps in the aforementioned method for hardware implementation of single-root virtualization of an Ethernet-supported RDMA network card. The memory 1002 is used to store various types of data to support the operation of the electronic device 1000. This data may include, for example, instructions for any application or method operating on the electronic device 1000, as well as application-related data such as contact data, sent and received messages, images, audio, video, and the like. The memory 1002 can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0131] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided. When executed by a processor, the program instructions implement the steps of the aforementioned method for implementing single-root virtualization hardware for an Ethernet-supporting RDMA network card. For example, the computer-readable storage medium may be the aforementioned memory 1002 including the program instructions. The program instructions may be executed by the processor 1001 of the electronic device 1000 to implement the aforementioned method for implementing single-root virtualization hardware for an Ethernet-supporting RDMA network card.

[0132] In another exemplary embodiment, a computer program product is also provided, which includes a computer program that can be executed by a programmable device, and has a code portion for executing the above-mentioned hardware implementation method of single-root virtualization of an Ethernet-supporting RDMA network card when executed by the programmable device.

[0133] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the scope of protection of the present invention.

[0134] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0135] In addition, the various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A hardware implementation method for single-root virtualization of an Ethernet RDMA network card, characterized in that: The method comprises: Maintain the offset register through the VF_offset register to obtain the offset information; By allocating MMIO resources using the offset information, the input read and write addresses are offset to achieve allocation and isolation of MMIO resources of PF and VF; Maintain the requester_id register of the tlp header through the VF_config register to obtain VF configuration information; By allocating DMA resources using the VF configuration information and performing TLP header framing on the requester_id information, the DMA resources of the PF and the VF are allocated and isolated; Maintaining the requester_id register of the tlp header through the requester_id register to obtain the requester_id information; By allocating interrupt resources using the requester_id information, framing the tlpheader and allocating the interrupt number for the requester_id information, the interrupt resources of the PF and the VF are allocated and isolated; The req_queue register of the rcq descriptor is maintained through the qp_num register, and the destination MAC register is maintained through the dest_mac register to obtain the destination MAC address for forwarding RX traffic and the queue number information for calling the RQ queue; The message is forwarded through the destination MAC address and the corresponding queue number information is reported, so as to achieve correct forwarding and splitting of the RX traffic of the PF and the VF and reporting of the queue number.

2. The method for implementing single-root virtualization hardware of an Ethernet-supported RDMA network card according to claim 1, wherein: The allocating MMIO resources by utilizing the offset information to offset the input read and write addresses includes: After the read / write address is input, whether it is VF is determined based on the device function number carried by the read / write address; When the read / write address is a VF, determining whether the read / write address is within a processable range of the VF; When the read / write address is not within the processable range, discarding the read / write address; When the read / write address is within the processable range, the read / write address is offset according to the corresponding preset offset value and output, so as to achieve allocation and isolation of MMIO resources of PF and VF.

3. The method for implementing single-root virtualization hardware of an Ethernet-supported RDMA network card according to claim 1, wherein: The VF configuration information includes: VF_en and VF_function; the VF_en is a 1-bit register, when the flag bit is 1, it indicates that the VF is enabled, when the flag bit is 0, it indicates that the VF is not enabled, and the initial value is 0; the VF_function is an 8-bit register, indicating the device function number corresponding to the VF, and the initial value is 0.

4. The method for implementing single-root virtualization hardware of an Ethernet-supported RDMA network card according to claim 3, wherein: The allocating DMA resources by using the VF configuration information and performing TLP header framing on the requester_id information includes: Obtain the first VF enable bit in the VF configuration information corresponding to the standard Ethernet mode; When the first VF enable bit is not pulled high, the device function number corresponding to the PF is used as the information for TLP header framing; When the first VF enable bit is pulled high, the device function number corresponding to the VF is used as the information for TLP header framing; The device function number, which is used as information for tlp header framing, is output to the DMA engine and the framing module of the tlp header, so as to allocate and isolate the DMA resources of the PF and the VF.

5. The method for implementing single-root virtualization hardware of an Ethernet-supported RDMA network card according to claim 1, wherein: The method of allocating DMA resources by using the VF configuration information and performing TLP header framing on the requester_id information further includes: Get the second VF enable bit in the VF configuration information corresponding to the RDMA mode; When the second VF enable bit is not pulled high, the device function number of the PF is used as the information for TLP header framing; When the second VF enable bit is pulled high, the device function number corresponding to the VF is used as the information for TLP header framing; The device function number, which is used as information for tlp header framing, is output to the DMA engine and the framing module of the tlp header, so as to allocate and isolate the DMA resources of the PF and the VF.

6. The method for implementing single-root virtualization hardware of an Ethernet-supported RDMA network card according to claim 1, wherein: The method of allocating interrupt resources by utilizing the requester_id information, framing the tlpheader and allocating the interrupt number for the requester_id information, includes: Determine whether the interrupt is a VF interrupt based on the device function number in the requester_id information; If the interrupt is not a VF interrupt, the interrupt number corresponding to the interrupt and the PF pcie device function number in the requester_id information are output to the PF interrupt processing module, and the first tlp data returned by the PF interrupt processing module is obtained; If the interrupt is a VF interrupt, the interrupt number corresponding to the interrupt and the PCIe device function number of the VF in the requester_id information are output to the VF interrupt processing module, and the second TLP data returned by the VF interrupt processing module is obtained; Output valid data of the first TLP data or the second TLP data to allocate and isolate interrupt resources of the PF and the VF.

7. The method for implementing single-root virtualization hardware of an Ethernet-supported RDMA network card according to claim 1, wherein: The forwarding of the message by the destination MAC address and reporting the corresponding queue number information includes: When the destination MAC address is the MAC address of the PF, forward the first queue number information corresponding to the message and the PF to the PF port, and report the first queue number information to the queue management module; When the destination MAC address is the MAC address of the VF, the second queue number information corresponding to the message and the VF is forwarded to the VF port, and the second queue number information is reported to the queue management module.

8. A hardware implementation device for single-root virtualization of an Ethernet RDMA network card, characterized in that: The device comprises: A first information acquisition module is configured to maintain an offset register through a VF_offset register to obtain offset information; A first resource allocation module is configured to allocate MMIO resources by utilizing the offset information and offset the input read and write addresses to achieve allocation and isolation of MMIO resources of PFs and VFs; The second information acquisition module is used to maintain the requester_id register of the tlp header through the VF_config register to obtain VF configuration information; A second resource allocation module is configured to allocate DMA resources by utilizing the VF configuration information and perform TLP header framing on the requester_id information to achieve allocation and isolation of DMA resources between the PF and the VF; A third information acquisition module is used to maintain the requester_id register of the tlp header through the requester_id register to obtain the requester_id information; a third resource allocation module, configured to allocate interrupt resources by utilizing the requester_id information, perform tlp header framing and interrupt number allocation on the requester_id information, so as to allocate and isolate the interrupt resources of the PF and the VF; The fourth information acquisition module is used to maintain the req_queue register of the rcq descriptor through the qp_num register and the destination MAC register through the dest_mac register to obtain the destination MAC address for forwarding RX traffic and the queue number information for calling the RQ queue; The information processing module is used to forward the message through the destination MAC address and report the corresponding queue number information, so as to correctly forward and split the RX traffic of the PF and the VF and report the queue number.

9. An electronic device, characterized in that: include: a memory having a computer program stored thereon; A processor is configured to execute the computer program in the memory to implement the steps of the hardware implementation method for single-root virtualization of an Ethernet-supporting RDMA network card according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method for hardware implementation of single-root virtualization of an Ethernet-supporting RDMA network card are implemented as described in any one of claims 1-7.

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