Method for improving fault tolerance efficiency based on soft topology of quantum chip

Abstract

The application relates to a method for improving fault tolerance efficiency based on a soft topology of a quantum chip, wherein the method comprises the following steps: determining quantum bit requirements of quantum circuit operations in a quantum circuit; allocating an activation time interval to each quantum bit based on the quantum bit requirements, and designing a control pulse sequence; and evolving each quantum bit in the activation time interval according to the control pulse sequence to realize a dynamic quantum circuit. By constructing a soft topology, i.e., quantum bits generate and release quantum bits according to model calculation activation time, dynamically activate and close quantum bits, reduce the time of quantum bits exposed to environmental noise, reduce decoherence and error rate, and improve the fault tolerance of quantum computing as a whole, thereby improving the reliability of quantum computing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of quantum computing, and in particular to a method for improving fault tolerance efficiency based on soft topology of quantum chips. BACKGROUND

[0002] Quantum computing is becoming a research hotspot in the global technology field due to its potential in solving complex computing problems. However, quantum computers face many challenges in practical implementation. Quantum bits, as the basic unit of quantum computing, are easily affected by environmental noise and decoherence. Due to the characteristics of quantum superposition and entanglement, any minor disturbance can lead to loss or error propagation of quantum information. The error rate and fault tolerance of quantum bits are key problems that need to be solved. SUMMARY

[0003] Therefore, the present disclosure proposes a method for improving fault tolerance efficiency based on soft topology of quantum chips.

[0004] The present disclosure constructs a soft topology structure of dynamically generating quantum bits, i.e., quantum bits are generated and released on demand according to computing requirements, reducing the time they are exposed to environmental noise and the risk of decoherence, and the physical error rate of quantum bits is also reduced. The overall fault tolerance of quantum computing is improved. When the soft topology structure is combined with quantum error correction codes, the reduction of the physical error rate enables the error correction codes to function more effectively, further improving the reliability of logical quantum bits.

[0005] According to an aspect of the present disclosure, a method for improving fault tolerance efficiency based on soft topology of quantum chips is provided, comprising:

[0006] determining quantum bit requirements of quantum circuit operations in a quantum circuit;

[0007] allocating an activation time interval for each quantum bit based on the quantum bit requirements, and designing a control pulse sequence;

[0008] evolving each quantum bit in the activation time interval according to the control pulse sequence to realize a dynamic quantum circuit.

[0009] In one possible implementation, when determining quantum bit requirements of quantum circuit operations in a quantum circuit, the method comprises: obtaining each quantum gate operation in the quantum circuit; and determining quantum bit requirements of each quantum gate operation.

[0010] In one possible implementation, when allocating an activation time interval for each quantum bit, the activation time interval is calculated based on a trained time-varying quantum bit activation model.

[0011] In a possible implementation, within the activation time interval, each qubit evolves according to the control pulse sequence, and the method further comprises:

[0012] Outside the activation time interval, each qubit remains in a ground state or an isolated state.

[0013] In a possible implementation, the training of the trained time-varying qubit activation model comprises:

[0014] allocating an activation time and a shutdown time for each qubit in the quantum circuit, wherein the time interval between the activation time and the shutdown time is the activation time interval allocated to the qubit;

[0015] defining a qubit activation function, designing a control pulse sequence, each qubit evolving in state according to the control pulse, and calculating the physical error rate of evolution;

[0016] predicting the minimum activation time, the number of gates, the circuit depth, the number of qubits, the physical error rate, and other parameters;

[0017] calculating a loss function according to the parameters, minimizing the loss function to update the parameters, and inputting the quantum circuit for multiple training to find the optimal parameters.

[0018] In a possible implementation, calculating the physical error rate of evolution further comprises: a logical error rate and an overall physical error rate;

[0019] For each qubit, the physical error rate of each qubit is calculated according to the activation time of each qubit;

[0020] For a system of multiple qubits, the overall physical error rate of the system is calculated according to the physical error rate of a single qubit;

[0021] The logical error rate is obtained according to the quantum error correction code and the physical error rate of a single qubit.

[0022] In a possible implementation, the fault tolerance efficiency is evaluated by comparing the logical error rate with the system preset requirement;

[0023] Adjusting the qubit activation time according to the evaluation result of fault tolerance efficiency.

[0024] According to another aspect of the present disclosure, a system for improving fault tolerance efficiency based on a soft topology of a quantum chip is provided, comprising: an analysis module, an allocation module;

[0025] The analysis module is configured to determine the qubit requirement in the quantum circuit.

[0026] The allocation module is configured to allocate an activation time interval to each qubit based on the qubit requirement, and design a control pulse sequence;

[0027] Each qubit evolves according to the control pulse sequence in the activation time interval, and a dynamic quantum circuit is realized.

[0028] According to another aspect of the present disclosure, a device for improving fault tolerance efficiency based on a quantum chip soft topology is provided, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to execute the above method.

[0029] According to another aspect of the present disclosure, a non-volatile computer readable storage medium having computer program instructions stored thereon is provided, wherein the computer program instructions are executed by a processor to implement the above method.

[0030] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0032] Figure 1 A flowchart of a method for improving fault tolerance efficiency based on a quantum chip soft topology according to an embodiment of the present application is shown;

[0033] Figure 2 A quantum bit soft topology diagram according to an embodiment of the present application is shown;

[0034] Figure 3 A quantum bit soft topology diagram according to an embodiment of the present application is shown;

[0035] Figure 4 A schematic diagram of a QFT circuit before optimization according to an embodiment of the present application is shown;

[0036] Figure 5 A schematic diagram of a QFT circuit after optimization according to an embodiment of the present application is shown;

[0037] Figure 6 A comparison diagram of probability distribution of a soft topology and an original topology according to an embodiment of the present application is shown;

[0038] Figure 7 A comparison diagram of logical error rate with code distance according to an embodiment of the present application is shown;

[0039] Figure 8A comparison diagram of fault tolerance efficiency between the soft topology structure and the original topology structure of the embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] Various exemplary embodiments, features and aspects of the present disclosure will be explained in detail below with reference to the accompanying drawings. The same reference numbers in different drawings denote the same or similar elements / function. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0041] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0042] In addition, for the purpose of better illustrating the present disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details, which are provided for the purpose of illustration and not limitation. In some instances, methods, means, elements and circuits well known to those skilled in the art are not described in detail in order to avoid obscuring the present disclosure.

[0043] The scheme of the present application is to execute in a quantum computing device based on a soft topology structure, in order to calculate the specific implementation as follows.

[0044] Embodiment 1

[0045] Figure 1 A flowchart of a method for improving fault tolerance efficiency of a quantum chip-based soft topology structure according to an embodiment of the present application is shown. The method of the present embodiment includes the following steps:

[0046] Step S100: Determine the quantum bit requirement of quantum circuit operation in the quantum circuit. The quantum circuit refers to the model of quantum computing based on the soft topology structure, which represents the quantum logic circuit that operates on the quantum bit in the abstract concept. The quantum circuit operation in the quantum circuit includes quantum gate operation, measurement operation, entanglement operation, etc. In this step, the quantum bit requirement of all operations of the quantum circuit currently being executed is calculated. The quantum bit requirement refers to the quantum bit required for each quantum gate operation when executing the quantum circuit operation, and the quantum bit requirement required for different operations is also different.

[0047] Step S200: Assign an activation time interval to each quantum bit based on the quantum bit requirement, and design a control pulse sequence. The activation time interval is the interval between the activation time and the shutdown time, and the control pulse sequence is obtained according to the activation function, and the activation function a i(t) is a function of time t, ti,on and ti,off are the activation and deactivation time of the quantum bit qi, respectively, the activation time interval is allocated to each quantum bit in this step, ensuring that the quantum bit is in the active state when it needs to participate in the operation. The value of the activation function is 1, indicating that the quantum bit is in the active state; the value of the activation function is 0, indicating that the quantum bit is in the inactive state, including the ground state and the isolation state, reducing the exposure time of the quantum bit to reduce the influence of decoherence.

[0048] Step S300: Each quantum bit in the activation time interval evolves according to the control pulse sequence to realize a dynamic quantum circuit. The control pulse sequence refers to the control signal of the quantum bit, which controls the quantum bit to evolve in a predetermined quantum operation. By applying a pulse modulation signal to the quantum bit, the interaction and state modification between quantum bits are realized, and then dynamic quantum computing is realized.

[0049] When determining the quantum bit requirement of the quantum circuit operation in the quantum circuit, the following steps are included: obtaining each quantum gate operation in the quantum circuit; determining the quantum bit requirement of each quantum gate operation. Since the quantum bit topology relationship of the real hardware may not match the calculation route structure of the quantum logic circuit, the high-level quantum gate is decomposed into basis gate operations that can be supported by the quantum computing device based on the soft topology structure of the present application. Based on the decomposed quantum gate operation, the quantum bit requirement of each gate operation is determined.

[0050] Considering the topology and connectivity of the device, the logical quantum bit is mapped to the physical quantum bit, and the activation time interval is calculated based on the trained time-varying quantum bit activation model. The training steps of the trained time-varying quantum bit activation model include:

[0051] Each quantum bit in the quantum circuit is allocated an activation time and a deactivation time, wherein the time interval between the activation time and the deactivation time is the activation time interval allocated to the quantum bit;

[0052] Define a quantum bit activation function and design a control pulse sequence, each quantum bit evolves according to the control pulse, and the physical error rate of evolution is calculated; the control pulse sequence refers to the control signal of the quantum bit, which is used to realize the interaction between quantum bits. Since it is difficult for physical devices to couple all quantum bits when executing, necessary SWAP gates are inserted to ensure the connectivity of the quantum computing device. The SWAP gate is used to exchange the execution order of two quantum bits during evolution.

[0053] Predict the minimum activation time, gate number, circuit depth, quantum bit number, physical error rate and other parameters;

[0054] According to the parameters, a loss function is calculated, the loss function is minimized to update the parameters, and the input quantum circuit is trained multiple times to find the optimal parameters.

[0055] Based on the time-varying qubit activation model trained according to the above steps, when a new quantum circuit is input, the activation time and the shutdown time of each qubit in the quantum circuit are calculated according to the optimized parameters, and the activation time interval of each qubit is allocated. Based on the activation time and the shutdown time of the qubit, the activation function of the qubit is defined, and the control pulse sequence is designed according to the activation function, so that each qubit in the quantum circuit evolves according to the control pulse.

[0056] The quantum computing soft topology based on the time-varying qubit activation model (TDQA) realizes the on-demand generation and release of qubits. Physically, the hardware of qubits may always exist, but in actual operation, the qubits at the corresponding positions on the time axis are activated only when needed, so that the qubits in the quantum circuit participate in the calculation only when needed, and enter the idle or isolated state when not needed, thereby reducing the time for which the qubits are exposed to environmental noise and improving the fault tolerance of quantum computing.

[0057] In the activation time interval, each qubit evolves according to the control pulse sequence; in the set activation time and shutdown time interval, the qubit is in an activated state; and in other time outside the activation time and shutdown time interval, the qubit is in a non-activated state. In the activation time interval, each qubit performs a corresponding predetermined gate operation, and when not in the activation time interval, each qubit remains in a predetermined ground state or isolated state.

[0058] After each qubit in the quantum circuit evolves according to the control pulse, the physical error rate of each qubit is calculated according to the activation time of each qubit; in the quantum computing process, quantum gate operations and measurement operations and other steps will introduce errors, which will gradually accumulate with the increase of the calculation depth. The physical error rate refers to the error rate generated by each operation in the quantum physical circuit, which is subject to the physical implementation, manipulation method and environmental noise mechanism of quantum computing.

[0059] For a system of multiple qubits, the overall physical error rate of the system is calculated according to the physical error rate of a single qubit.

[0060] The logical error rate is obtained according to the quantum error correction code and the physical error rate of a single quantum bit. The error correction code can be adjusted according to the actual application environment, and specific parameters are not limited in the present application. The fault-tolerant efficiency is evaluated by comparing the logical error rate with the system preset requirement; and the quantum bit activation time is adjusted according to the evaluation result of the fault-tolerant efficiency.

[0061] Specifically, first, all quantum circuit operations in the quantum circuit are determined, including quantum gates, measurements, and entanglements. The quantum bit requirements in all quantum operations are analyzed, and the activation interval is allocated based on the quantum bit requirements. First, the high-level quantum gate is decomposed into the basis gate set supported by the target device. Since the quantum bit topology relationship of the real hardware may not match the structure of the required logical quantum bit topology circuit, it is difficult to couple all quantum bits during execution, therefore, the topology structure and connectivity of the physical device are considered, and necessary SWAP gates are inserted in the circuit to meet the connection limit between physical bits, so as to map the logical quantum bits to the physical quantum bits.

[0062] As shown in Figure 2 and Figure 3 , the topology graph of the original topology structure of the quantum bit is Figure 2 . Figure 3 The dynamic topology graph of the soft topology structure of the quantum bit is

[0063] The red part in the figure represents the quantum bit in the active state, and the green part represents the quantum bit in the inactive state. In the original topology structure, all quantum bits are in the active state at the beginning of the circuit. In the soft topology structure proposed in the present application, the quantum bits are not all activated, but are activated and released on demand. The quantum bits that do not participate in quantum computing at the current time are kept in the ground state or isolated state to reduce the time of quantum bits exposed to environmental noise.

[0064] It should be noted that the figure shown is only an exemplary illustration of an embodiment of the present application, and the actual topology structure is not limited to a mesh structure, but can be any topology structure, which is not specifically limited in the present application.

[0065] The activation time interval is calculated based on the time-varying quantum bit activation model. The training steps of the time-varying quantum bit activation model are as follows: under the premise of equivalent calculation, the total number of gates, depth, number of quantum bits, and physical error rate are minimized:

[0066]

[0067] Wherein, G represents the number of gate operations, i.e. the number of circuit gates; D represents the circuit depth; Q represents the number of quantum bits; Pphys represents the physical error rate; ti,on represents the activation time of the corresponding quantum bit; ti,off represents the closing time of the corresponding quantum bit.

[0068] The form of the loss function is as follows:

[0069]

[0070] wherein, is a weight parameter, by adjusting the importance of different optimization objectives to meet the function L minimization, reduce the gate operation number, depth, number of qubits, physical error rate and activation time.

[0071] For each qubit qi, according to the algorithm steps, the activation time interval [ti,on and ti,off] is allocated, which ensures that the qubit is in an active state when it needs to participate in the operation.

[0072]

[0073] wherein: ti,on and ti,off are the activation and off time of qubit qi, respectively.

[0074] According to the activation function a i (t), the control pulse sequence is designed to minimize the interference on adjacent qubits.

[0075] During the activation period, the qubits evolve according to the predetermined quantum operation, including performing quantum gate operations, participating in entanglement, etc.

[0076] When not in the activation time interval, the qubits remain in the ground state or isolated state to reduce the influence of decoherence

[0077] A large amount of quantum circuit data is input to obtain a trained time-varying qubit activation model (i.e. a deep learning model), and the optimal parameters are found through the trained time-varying qubit activation model, i.e. under the premise of equivalent calculation, the total gate number, depth, number of qubits and physical error rate are minimized, the depth and gate number of the circuit are reduced, and the execution efficiency and reliability are improved. The method of using a deep learning model to find the optimal solution is a conventional technical means in the technical field of the present application, and will not be described in detail in the present application.

[0078] In an embodiment of the present application, a quantum Fourier transform (QFT) calculation of 4 qubits is performed. As shown in Figure 4 The QFT circuit under the original topology before optimization contains multiple gate operations: Hadamard gate, phase gate P(π / 2), phase gate P(π / 4) and phase gate P(π / 8). Four qubits (q0, q1, q2, q3) are in working state at the same time, and finally they are measured at the end of the circuit.

[0079] AsFigure 5 In the optimized soft topology QFT circuit, the quantum bits perform different operations at different times, rather than simultaneously at all times. The measurement of the quantum bits is not the last measurement, but there are intermediate measurements, indicating that the quantum bits in the soft topology are activated on demand.

[0080] For the exposure time Ti of each quantum bit qi, the following calculation method is used:

[0081]

[0082] By controlling ti,on and ti,off, the exposure time of the quantum bit is adjusted:

[0083]

[0084] where the physical error rate Pphys,i is related to the exposure time Ti of the quantum bit, the environmental decoherence rate ℷ, ℷ = 1 / T2, and T2 is the coherence time. The coherence time is directly measured by other physical devices, and the measurement of the coherence time is a conventional technical means in the art, which will not be described in detail in this application.

[0085] For a system of N quantum bits, the physical error rates of all quantum bits are accumulated to obtain the total physical error rate:

[0086]

[0087] According to the physical error rate and the calculation requirement, a suitable quantum error correction code and code distance are selected. Using the quantum error correction code, the relationship between the logical error rate plog and the physical error rate is:

[0088]

[0089] where A is a constant related to the specific implementation of the error correction code. Preferably, in a specific embodiment of the present application, it is preset to 0.1. By comparing the logical error rate Plog with the system requirement, it is evaluated whether the fault tolerance meets the demand. According to the evaluation result, the activation time of the quantum bit and the error correction code parameters are adjusted to optimize the system performance.

[0090] Pth is the fault tolerance threshold of the error correction code, and d is the code distance of the error correction code, representing the number of errors that can be corrected. Preferably, in a specific embodiment of the present application, Pth is set to 1%, and d is set to 5; it should be noted that the error correction code and the code distance can be adjusted according to the actual superconducting quantum bit, and are not specifically limited.

[0091] The total error rate of each calculation is minimized, and the exposure time T is reduced according to the physical error rate calculation formula:

[0092]

[0093] The reduction of exposure time T will reduce Pphys. So that the physical error rate is lower than the threshold error rate, the error correction code can work effectively, and the logical error rate is exponentially reduced by appropriately increasing the code distance d under the condition of meeting the error correction condition. Wherein, the threshold error rate depends on the selection of the error correction code and the nature of the environmental noise.

[0094] In an embodiment of the present application, the original topology and the soft topology process the same quantum circuit, and the operation time and error rate of the original topology and the soft topology of the same equivalent quantum computation are compared as shown in the following table:

[0095]

[0096] The operation time of the original topology is 10 μs, the operation time of the soft topology is 2 μs, the exposure time of the quantum bit is shortened by 5 times, and the physical error rate is also reduced accordingly.

[0097] Specifically, the physical error rates of the original topology and the soft topology are calculated respectively:

[0098] The physical error rate of the original topology is:

[0099] The physical error rate of the soft topology is:

[0100] Since Pphys,soft=0.40%<pth=1%, by reducing the exposure time, the physical error rate is reduced below the threshold error rate, and the quantum error correction code can effectively correct errors. The physical error rate of quantum computation based on the soft topology is also reduced by 4.95 times.

[0101] The logical error rate is calculated according to the physical error rate:

[0102] The logical error rate of the original topology is:

[0103] The logical error rate of the soft topology is:

[0104] Based on the soft topology proposed in the present application, the logical error rate of the same quantum circuit is reduced from 77.61% to 0.64%, which is reduced by 121.58 times.

[0105] All quantum bits in the original topology quantum circuit are in the active state at the beginning, the quantum bit exposure time is long, and the error rate cannot be effectively reduced. While the quantum bits in the soft topology quantum circuit of the present application are generated and released on demand, by reducing the time of quantum bits exposed to the environment, the overall error rate of each calculation is significantly reduced.

[0106] The experimental measurement results before and after optimization show that Figure 6 The circuit before and after optimization has the same probability distribution, indicating that the adjusted soft topology structure has the same function as the original topology structure.

[0107] In the case of the same code distance, the soft topology structure and the hard topology structure are compared in terms of logical error rate. The logical error rates of different code distances d (5, 7, 9, 13, 19, 21, 29) are calculated and compared. By increasing the code distance d, the logical error rate Plog can be reduced, and the error correction effect can be improved. Figure 7 The schematic diagram of the logical error rate changing with the code distance is shown in the figure. In the case of the same code distance, the soft topology structure can further reduce the logical error rate compared with the hard topology structure, and the reliability of quantum computing is improved.

[0108] The above examples show that the quantum bits of the soft topology structure are generated on demand, rather than being in working state at the same time when the circuit starts.

[0109] According to another aspect of the present disclosure, a system for improving fault tolerance efficiency based on a soft topology structure of a quantum chip is also provided, comprising: an analysis module, an allocation module;

[0110] The analysis module is configured to determine the quantum bit requirement of quantum circuit operations in the quantum circuit;

[0111] The allocation module is configured to allocate an activation time interval for each quantum bit based on the quantum bit requirement, and design a control pulse sequence;

[0112] Each quantum bit evolves according to the control pulse sequence within the activation time interval, realizing a dynamic quantum circuit.

[0113] In order to quantify the fault tolerance capability of the system in a noisy environment, a fault tolerance efficiency formula is defined to represent the fault tolerance performance of the quantum bit under a specific exposure time:

[0114]

[0115] Wherein, η is the fault tolerance efficiency of the system, and the higher the value, the stronger the fault tolerance capability;

[0116] α is the noise factor, representing the strength of the quantum bit exposed to environmental noise, and is preset as α = 2000S-1 (coherence time is 500 microseconds), and texposed is the time of the quantum bit exposed to noise;

[0117] In the original hard topology structure (hereinafter referred to as hard topology structure), the quantum bit is exposed to environmental noise for a long time, so the fault tolerance efficiency is low:

[0118]

[0119] In the soft topology of the present application, the quantum bits are exposed to environmental noise for a shorter time, so the fault tolerance rate is higher:

[0120]

[0121] The soft topology significantly improves the fault tolerance efficiency by reducing the exposure time of quantum bits to environmental noise.

[0122] As Figure 8 The comparison of the fault tolerance efficiency of the soft topology and the hard topology is shown. The dashed part Soft Topology represents the fault tolerance efficiency of the on-demand generated soft topology at different time steps, and the fluctuation is relatively stable and the overall fault tolerance efficiency range is maintained between 0.8-1.0. It should be noted that the hard topology is only used to describe the quantum computing original topology that is contrasted with the quantum computing soft topology of the present application, and cannot be understood as an indicated technical feature.

[0123] The solid part Origin Topology represents the fault tolerance efficiency of the fixed generated hard topology at different time steps, and the overall fault tolerance efficiency range is between 0.4-0.6. The gray area is the difference in fault tolerance efficiency between the soft topology and the hard topology. In most time steps, the soft topology is better than the hard topology, and the soft topology proposed in the present application can significantly improve the accuracy and reliability of quantum computing.

[0124] Further, according to another aspect of the present disclosure, a device for improving fault tolerance efficiency based on a soft topology of a quantum chip is also provided. The device for improving fault tolerance efficiency based on a soft topology of a quantum chip according to the embodiments of the present disclosure includes a processor and a memory for storing processor-executable instructions. Wherein, the processor is configured to implement the method described in any of the preceding embodiments when executing the executable instructions. It should be noted here that the number of processors can be one or more. The processor and the memory can be connected through a bus or through other means, which is not limited here.

[0125] The memory, as a computer readable storage medium, can be used to store software programs, computer executable programs and various modules, such as programs or modules corresponding to the method for improving fault tolerance efficiency based on a soft topology of a quantum chip according to the embodiments of the present disclosure. The processor executes the software programs or modules stored in the memory, thereby performing various functional applications and data processing of the device for improving fault tolerance efficiency based on a soft topology of a quantum chip.

[0126] According to another aspect of the present disclosure, there is also provided a non-transitory computer readable storage medium having computer program instructions stored thereon, the computer program instructions, when executed by a processor, implement the method of improving fault tolerance efficiency based on soft topology of quantum chip according to any of the preceding aspects.

[0127] Embodiments of the present disclosure have been described above, with the understanding that these descriptions are exemplary only, and are not intended to be exhaustive or to limit the embodiments disclosed to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen and described in order to best explain the principles of various embodiments and their practical application and to thereby enable others skilled in the art to best utilize the embodiments disclosed herein. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

Claims

1. A method for improving fault tolerance efficiency based on a soft topology of a quantum chip, characterized in that, The method comprises the following steps: determining the quantum bit requirement of quantum circuit operations in a quantum circuit, the quantum circuit operations comprising quantum gate operations, measurement operations and entanglement operations, the quantum bit requirement referring to the quantum bits required for each quantum gate operation when performing the quantum circuit operations, and the quantum bit requirements required by different operations being different; allocating an activation time interval for each quantum bit in an optimized time-varying quantum bit activation model based on the quantum bit requirement, and designing a control pulse sequence, the control pulse sequence being a control signal for the quantum bits; evolving each quantum bit in the activation time interval according to the control pulse sequence to realize a dynamic quantum circuit; wherein, in the activation time interval, each quantum bit is in an activated state, i.e., performs a predetermined gate operation, and outside the activation time interval, each quantum bit is in a non-activated state, i.e., remains in a ground state or an isolated state; further comprising: calculating the physical error rate of a single quantum bit according to the activation time of each quantum bit; for a system of multiple quantum bits, accumulating the physical error rates of all single quantum bits to obtain the overall physical error rate of the system; calculating the logical error rate according to the quantum error correction code and the overall physical error rate; evaluating the fault tolerance efficiency by comparing the logical error rate with the system preset requirement; adjusting the quantum bit activation time and the error correction code parameters according to the evaluation result of the fault tolerance efficiency to optimize the system performance; the training steps of the optimized time-varying quantum bit activation model comprise: allocating an activation time and an off time for each quantum bit in the quantum circuit, wherein the time interval between the activation time and the off time is the activation time interval allocated for the quantum bit; defining a quantum bit activation function, designing a control pulse sequence, each quantum bit evolving in a state according to the control pulse, and calculating the physical error rate of the evolution; under the premise of equivalent calculation, constructing an objective function based on the purposes of predicting the minimum activation time, the number of gates, the circuit depth, the number of quantum bits and the physical error rate, the objective function being in the following form: min(f(G,D,Q,Pphys,ti,on,ti,off)); wherein, G is the number of gates, D is the circuit depth, Q is the number of quantum bits, Pphys is the physical error rate, ti,on is the activation time of the corresponding quantum bit, and ti,off is the off time of the corresponding quantum bit; constructing a loss function according to the objective function, updating the parameters by minimizing the loss function, inputting the quantum circuit multiple times to find the optimal parameters, realizing the optimization of the dynamic quantum circuit in the form of soft topology, and the loss function being in the following form: L(G,D,Q,Pphys)=αG+βD+γQ+δPphys+ε*ti,on+ζ*ti,off; wherein, α, β, γ, δ, ε, ζ are weight parameters, G is the number of gates, D is the circuit depth, Q is the number of quantum bits, Pphys is the physical error rate, ti,on is the activation time of the corresponding quantum bit, and ti,off is the off time of the corresponding quantum bit.

2. The method for improving fault tolerance efficiency of soft topology based on quantum chip according to claim 1, characterized in that, The method comprises the following steps: acquiring quantum bit requirements of quantum circuit operations in a quantum circuit; The method comprises the following steps: acquiring quantum bit requirements of quantum circuit operations in a quantum circuit; 3. A system for improving fault tolerance efficiency based on soft topology of quantum chips, characterized in that, The method comprises the following steps: The method comprises the following steps: The analysis module is configured to determine quantum bit requirements of quantum circuit operations in a quantum circuit, wherein the quantum circuit operations comprise quantum gate operations, measurement operations and entanglement operations, and the quantum bit requirements refer to quantum bit requirements of each quantum gate operation when the quantum circuit operations are performed, and the quantum bit requirements required by different operations are different; The allocation module is configured to allocate an activation time interval for each quantum bit in an optimized time-varying quantum bit activation model based on the quantum bit requirements, design a control pulse sequence, and the control pulse sequence is a control signal of a quantum bit; Each quantum bit evolves according to the control pulse sequence in the activation time interval, and a dynamic quantum circuit is realized; wherein each quantum bit is in an activated state, that is, performs a predetermined gate operation, in the activation time interval, and is in a non-activated state, that is, remains in a ground state or an isolated state, outside the activation time interval; further comprising: calculating a physical error rate of a single quantum bit according to the activation time of each quantum bit; for a system of multiple quantum bits, accumulating physical error rates of all single quantum bits to obtain a total physical error rate of the system; calculating a logical error rate according to a quantum error correction code and the total physical error rate; evaluating fault tolerance efficiency by comparing the logical error rate with a system preset requirement; adjusting quantum bit activation time and error correction code parameters according to the evaluation result of fault tolerance efficiency to optimize system performance; The training steps of the optimized time-varying quantum bit activation model comprise: allocating an activation time and an off time for each quantum bit in the quantum circuit, wherein a time interval between the activation time and the off time is the activation time interval allocated for the quantum bit; defining a quantum bit activation function, designing a control pulse sequence, each quantum bit evolving according to the control pulse, and calculating a physical error rate of evolution; under the premise of equivalent calculation, constructing a target function based on the purposes of predicting the minimum activation time, the number of gates, the circuit depth, the number of quantum bits and the physical error rate, and the target function is as follows: min(f(G,D,Q,Pphys,ti,on,ti,off)); wherein G is the number of gates, D is the circuit depth, Q is the number of quantum bits, Pphys is the physical error rate, ti,on is the activation time of the corresponding quantum bit, and ti,off is the off time of the corresponding quantum bit; constructing a loss function according to the target function, updating the parameters by minimizing the loss function, inputting the quantum circuit multiple times to find the optimal parameters, realizing the optimization of the dynamic quantum circuit in the form of soft topology, and the loss function is as follows: L(G,D,Q,Pphys)=αG+βD+γQ+δPphys+ε*ti,on+ζ*ti,off; wherein a, b, g, d, e, z are weight parameters, G is the number of gates, D is the circuit depth, Q is the number of qubits, Pphys is the physical error rate, ti,on is the time to activate the corresponding qubit, ti,off is the time to deactivate the corresponding qubit.

4. An apparatus for improving fault tolerance efficiency based on soft topology of quantum chips, characterized in that, Comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the method of any one of claims 1-2 when executing the executable instructions.

5. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein, The computer program instructions implement the method of any one of claims 1-2 when executed by a processor.

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