Shift register device

Abstract

The shift register device comprises a serial input end, a shift pulse input end and a first output end, the shift register device comprises a shift register unit. The shift register unit is coupled with the serial input end, the shift pulse input end and the first output end; the shift register unit is configured to perform shift operation on an input signal of the serial input end in response to a clock signal of the shift pulse input end. According to the shift register device provided by the embodiment of the invention, the variable-bit shift register device is realized based on the shift register unit, and compared with the prior art, through the structural design of the shift register unit, the shift operation on the data can be realized by using fewer hardware resources, and the shift register device has the advantages that the complexity of the shift register device is reduced. Therefore, the problem of shortage of hardware resources when the shift register is used on a hardware platform with limited resources is solved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit design, and in particular to a shift register device. Background Art

[0002] In the field of integrated circuit design, most of the current shift register designs adopt a design concept based on various types of trigger structures: a single trigger stores one bit of binary data, and a serial shift can be formed by connecting the output of the trigger to the input of the next trigger.

[0003] The common shift register design at present is usually composed of multiple D flip-flops. The structure of this shift register based on D flip-flops is relatively simple and easy to implement. However, a D flip-flop is composed of two D latches, and it takes 4 NAND gate circuit units to implement a D latch, and a NAND gate circuit uses 4 transistor resources. Therefore, 32 transistors are required to implement a basic unit of a D flip-flop. According to estimates, the D flip-flop-based solution requires at least 256 transistor resources to implement an 8-bit shift register, which consumes more hardware resources and is difficult to implement on a hardware platform with limited resources. Summary of the invention

[0004] Based on the above situation of the prior art, an object of an embodiment of the present invention is to provide a shift register device, and to solve the problems of the prior art, a shift register device with lower resource consumption is provided.

[0005] To achieve the above object, according to one aspect of the present invention, a shift register device is provided, the shift register device comprising a serial input terminal, a shift pulse input terminal and a first output terminal;

[0006] The shift register device comprises a shift register unit; the shift register unit is coupled to the serial input terminal, the shift pulse input terminal and the first output terminal; the shift register unit is configured to perform a shift operation on the input signal of the serial input terminal in response to a clock signal of the shift pulse input terminal;

[0007] The shift register unit includes a first shift circuit and a second shift circuit; the first shift circuit includes a first latch circuit and a first drive circuit, the input end of the first drive circuit is the input end of the shift register unit, the control end of the first drive circuit is coupled to the shift pulse input end, and the input and output ends of the first latch circuit are coupled to the output end of the first drive circuit; the second shift circuit includes a second latch circuit and a second drive circuit, the input end of the second drive circuit is coupled to the output end of the first drive circuit, the control end of the second drive circuit is coupled to the shift pulse input end, and the input and output ends of the second latch circuit are the output end of the shift register unit and are coupled to the output end of the second drive circuit.

[0008] Further, the shift register device comprises a plurality of shift register units, and the number of the plurality of shift register units is the same as the maximum number of shift bits of the shift register device;

[0009] The multiple shift register units are connected in series in sequence, the output end of the previous shift register unit is connected to the input end of the next shift register unit, the input end of the first shift register unit is coupled to the serial input end, and the output end of the last shift register unit is coupled to the first output end.

[0010] Furthermore, the output end of each of the shift register units constitutes a parallel output end of the shift register device, and the parallel output end parallel-shifts and outputs the input signal of the serial input end.

[0011] Further, the clock signal includes a first level signal and a second level signal; the first level signal and the second level signal have different levels;

[0012] When the clock signal is a first level signal, the shift register unit reads a signal from an input end of the shift register unit; when the clock signal is a second level signal, the shift register unit outputs a signal from an output end of the shift register unit.

[0013] Furthermore, the first level signal and the second level signal constitute a clock signal of one cycle;

[0014] When the clock signal is a second level signal in each cycle,

[0015] The lowest bit of the output signal of the parallel output terminal is the same as the input signal in the same cycle, and is shifted to the adjacent high bit in the next cycle.

[0016] Furthermore, the first driving circuit controls the output and input of the first driving circuit to be turned on in response to a first level signal at the control terminal; the second driving circuit controls the output and input of the second driving circuit to be turned on in response to a second level signal at the control terminal.

[0017] Furthermore, when the output terminal and the input terminal of the first driving circuit are turned on, the input and output terminals of the first latch circuit read the input terminal signal of the first driving circuit;

[0018] When the output terminal and the input terminal of the second driving circuit are turned on, the input and output terminals of the second latch circuit read the input terminal signal of the second driving circuit.

[0019] Furthermore, the first latch circuit and the second latch circuit are dual inverter structures;

[0020] The dual inverter structure includes a first inverter and a second inverter;

[0021] The input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the output end of the first inverter; the input end of the first inverter is the input / output end of the first latch circuit or the input / output end of the second latch circuit.

[0022] Further, at least one of the first driving circuit and the second driving circuit is a three-state gate structure;

[0023] The tri-state gate structure includes a third inverter and a tri-state gate circuit;

[0024] The output end of the third inverter is connected to the input end of the three-state gate circuit, the input end of the third inverter is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the three-state gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the three-state gate circuit is the control end of the first drive circuit, and the second control port of the three-state gate circuit is the control end of the second drive circuit.

[0025] Further, at least one of the first driving circuit and the second driving circuit is a first transmission gate structure;

[0026] The first transmission gate structure includes a source follower and a transmission gate circuit;

[0027] The output end of the source follower is connected to the input end of the transmission gate circuit; the input end of the source follower is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the transmission gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the transmission gate circuit is the control end of the first drive circuit, and the second control port of the transmission gate circuit is the control end of the second drive circuit.

[0028] Further, at least one of the first driving circuit and the second driving circuit is a second transmission gate structure;

[0029] The second transmission gate structure includes a fourth inverter, a fifth inverter and a transmission gate circuit;

[0030] The output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the transmission gate circuit, the input end of the fourth inverter is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the transmission gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the transmission gate circuit is the control end of the first drive circuit, and the second control port of the transmission gate circuit is the control end of the second drive circuit.

[0031] In summary, an embodiment of the present invention provides a shift register device, including a serial input terminal, a shift pulse input terminal and a first output terminal; the shift register device includes a shift register unit; the shift register unit couples the serial input terminal, the shift pulse input terminal and the first output terminal; the shift register unit is configured to perform a shift operation on the input signal of the serial input terminal in response to a clock signal of the shift pulse input terminal. The shift register device provided by the embodiment of the present invention realizes a shift register device with a variable number of bits based on the shift register unit therein, and through the structural design of the shift register unit, compared with the prior art, it is possible to realize the shift operation on data with less hardware resources, thereby solving the problem of tight hardware resources when using shift registers on a hardware platform with limited resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of a shift register for realizing 4-bit data shifting in the prior art;

[0033] Figure 2 is a schematic diagram of the overall structure of a shift register device provided by an embodiment of the present invention;

[0034] Figure 3 is a structural schematic diagram of a shift register device consisting of two shift register units provided in an embodiment of the present invention;

[0035] Figure 4 is a schematic structural diagram of a latch circuit with a dual inverter structure provided by an embodiment of the present invention;

[0036] Figure 5 is a schematic structural diagram of a driving circuit of a tri-state gate structure provided by an embodiment of the present invention;

[0037] Figure 6 is a schematic structural diagram of a driving circuit of a first transmission gate structure provided by an embodiment of the present invention;

[0038] Figure 7 4 is a schematic diagram of the structure of a driving circuit of a second transmission gate structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0040] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in one or more embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0041] The common shift register design currently usually uses multiple D flip-flops. Figure 1 A schematic diagram of the shift register structure for implementing 4-bit data shift is shown in FIG. Figure 1As shown, the shift register includes four D flip-flops, namely the first D flip-flop 1011, the second D flip-flop 1012, the third D flip-flop 1013 and the fourth D flip-flop 1014. The output ports of the four D flip-flops are connected to the input port of the next one in sequence, and the same clock signal CLK is used as the shift pulse. The input port of the first D flip-flop 1011 is the serial input port D of the shift register, the output port of the fourth D flip-flop 1014 is the serial output port Q of the shift register, and the output ports Q0-Q4 of the four D flip-flops are used as parallel output ports of the shift register. The shift function logic implemented is shown in Table 1:

[0042] Table 1 Shift register shift function logic table composed of 4 D flip-flops

[0043]

[0044] It can be seen from Table 1 that when the rising edge of the shift pulse CLK arrives, the signal input from the serial input port D flows through the connection path between the D flip-flops, and the D flip-flops are converted from the current state to the next state. It can be seen from Table 1 that after 4 shift pulses, the serial input signal stored in the register can be converted into a parallel shift output. Similarly, if 4-bit parallel data is placed in the 4 D flip-flops of the shift register, and then 4 shift pulses are added continuously, the 4-bit data in the shift register will be output serially from the serial output port Q. It takes 32 transistors to realize a basic unit of a D flip-flop through the above structure. It is estimated that the D flip-flop-based solution requires at least 256 transistor resources to realize an 8-bit shift register, which consumes more hardware resources and is difficult to implement on a hardware platform with limited resources.

[0045] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings. In view of the above problems of the prior art, an embodiment of the present invention provides a shift register device with lower resource consumption. Figure 2 FIG. 4 shows a schematic diagram of the overall structure of the shift register device provided by an embodiment of the present invention. Figure 2 As shown, the shift register device includes a serial input terminal D, a shift pulse input terminal CLK and a first output terminal Q. The shift register device includes a shift register unit 101, which is coupled to the serial input terminal D, the shift pulse input terminal CLK and the first output terminal Q; the shift register unit 101 is configured to perform a shift operation on an input signal of the serial input terminal D in response to a clock signal of the shift pulse input terminal CLK.

[0046] According to some optional embodiments, the shift register unit 101 may be one or more, and the number of the shift register units 101 is related to the number of shift bits of the shift register device. Specifically, the number of the shift register units 101 is the same as the maximum number of shift bits of the shift register device. When there is one shift register unit 101, the shift register device can implement a shift operation with a shift number of 1, i.e., 1 bit, on the input data of the serial input terminal D. When there are N shift register units 101, the shift register device can implement a shift operation with a maximum shift number of N, i.e., N bits, on the input data of the serial input terminal D, where N is a natural number greater than 1.

[0047] The shift register device provided in this embodiment of the present invention is a shift register circuit based on a driving circuit. By using a simple latch circuit to latch data, the data storage function can be realized with less hardware resources. Adjacent latch circuits are connected by a driving circuit to realize data transmission between different latch circuits. In order to realize the edge triggering function, adjacent driving circuits use opposite level triggering methods. Figure 2 , the basic principle of the shift register device based on the driving circuit provided by the embodiment of the present invention is introduced by taking the structure of a 1-bit serial shift register device. Figure 2 1 shows a schematic diagram of the structure of a shift register device composed of a single shift register unit 101. The shift register device composed of a single shift register unit 101 can implement a shift operation with a shift bit of 1. Figure 2As shown, the shift register unit 101 includes a first shift circuit and a second shift circuit; the first shift circuit includes a first latch circuit 1021 and a first drive circuit 1031, the input end of the first drive circuit 1031 is the input end D of the shift register unit 101, the control end of the first drive circuit 1031 is coupled to the shift pulse input end CLK, and the input and output ends of the first latch circuit 1021 are coupled to the output end of the first drive circuit 1031; the second shift circuit includes a second latch circuit 1022 and a second drive circuit 1032, the input end of the second drive circuit 1032 is coupled to the output end of the first drive circuit 1031, the control end of the second drive circuit 1032 is coupled to the shift pulse input end CLK, the input and output ends of the second latch circuit 1022 are the output end Q of the shift register unit 101, and are also coupled to the output end of the second drive circuit 1032. The first latch circuit 1021 and the second latch circuit 1022 are used to latch data, and the first drive circuit 1031 and the second drive circuit 1032 are used to control the data accessed in the first latch circuit 1021 and the second latch circuit 1022. The shift register unit 101 performs a shift operation of 1 on the input signal of the serial input terminal D in response to the clock signal of the shift pulse input terminal CLK. The clock signal includes a first level signal and a second level signal, and the first level signal and the second level signal have different levels, for example, a low level signal and a high level signal, respectively. When the clock signal is a first level signal, the shift register unit 101 reads a signal from the input terminal D of the shift register unit 101; when the clock signal is a second level signal, the shift register unit 101 outputs a signal from the output terminal Q of the shift register unit 101. The driving circuit is a level-controlled switch. Therefore, in order to realize the edge-triggered function, the adjacent driving circuits use opposite trigger levels. In this embodiment, the first driving circuit 1031 controls the output and input of the first driving circuit 1031 to be turned on in response to the first level signal (e.g., low-level trigger) of the control end; the second driving circuit 1032 controls the output and input of the second driving circuit 1032 to be turned on in response to the second level signal (e.g., high-level trigger) of the control end. When the output and input of the first driving circuit 1031 are turned on, the input and output of the first latch circuit 1021 read the input signal of the first driving circuit 1031; when the output and input of the second driving circuit 1032 are turned on, the input and output of the second latch circuit 1022 read the input signal of the second driving circuit 1032. That is, when the clock signal of the shift pulse input terminal CLK is at a low level, the first driving circuit 1031 is turned on. Due to its strong driving capability, the first latch circuit 1021 can read the data of the input port of the first driving circuit 1031 at the current moment. At this time, the second driving circuit 1032 is in a high impedance state, so the data stored in the second latch circuit 1022 will not change.When the clock signal of the shift pulse input terminal CLK is at a high level, the first drive circuit 1031 is in a high impedance state, and the first drive circuit 1031 latches the data read when the clock signal is at a low level. At this time, the second drive circuit 1032 is turned on, and the second latch circuit 1022 reads the data currently latched by the first latch circuit 1021. Figure 2 In the structure shown, the first latch circuit 1021 and the first drive circuit 1031 are connected with the second latch circuit 1022 and the second drive circuit 1032 to realize the function of a rising edge triggered D flip-flop. Figure 2 The structure implements a 1-bit shift operation of serial data.

[0048] When there are multiple shift register units, the multiple shift register units are connected in series in sequence, the output end of the previous shift register unit is connected to the input end of the next shift register unit, the input end of the first shift register unit is coupled to the serial input end, and the output end of the last shift register unit is coupled to the first output end. In the shift register device composed of multiple shift register units, the output end of each shift register unit constitutes the parallel output end of the shift register device, and the parallel output end shifts and outputs the input signal of the serial input end in parallel. The clock signal includes a first level signal and a second level signal, and the first level signal and the second level signal constitute a clock signal of one cycle; in each cycle, when the clock signal is a second level signal, the lowest bit of the output signal of the parallel output end is the same as the input signal in the same cycle, and is shifted to the adjacent high bit in the next cycle. Figure 3 , a schematic diagram of the structure of a shift register device composed of two shift register units is shown in FIG. The shift register device composed of two shift register units can implement a shift operation with a maximum shift number of 2. Figure 3As shown, the shift register device includes a first shift register unit 102 and a second shift register unit 103, the first shift register unit 102 and the second shift register unit 103 are connected in series in sequence, and the structures of the first shift register unit 102 and the second shift register unit 103 are the same as the structure of the shift register unit 101 involved in the above embodiment. The first shift register unit 102 includes a third shift circuit and a fourth shift circuit, the third shift circuit includes a third latch circuit 1023 and a third drive circuit 1033, and the fourth shift circuit includes a fourth latch circuit 1024 and a fourth drive circuit 1034; the second shift register unit 103 includes a fifth shift circuit and a sixth shift circuit, the fifth shift circuit includes a fifth latch circuit 1025 and a fifth drive circuit 1035, and the sixth shift circuit includes a sixth latch circuit 1026 and a sixth drive circuit 1036. The input end of the first shift register unit 102 is coupled to the serial input end D, and the output end of the second shift register unit 103 is coupled to the first output end Q. The output Q0 of the first shift register unit 102 and the output Q1 of the second shift register unit 103 constitute the parallel output end Q0Q1 of the shift register device. This embodiment can realize the shift function of 2-bit data by connecting two shift register units in series. The basic principle and shift process of data shifting are the same as the basic principle and shift process of the shift register device composed of a single shift register unit 101 in the above embodiment. In each cycle, when the clock signal is a second level signal (for example, a high level signal), the lowest bit of the output signal Q0Q1 of the parallel output end is the same as the input signal in the same cycle, and is shifted to the adjacent high bit in the next cycle. In the second cycle, the output signal of the first output end Q is the same as the input signal of the previous cycle.

[0049] Based on the above basic principles, the function of a shift register device for multi-bit data can be realized by connecting multiple shift register unit structures in series. Table 2 shows a shift function logic table of a shift register device composed of four shift register units connected in series. According to the contents of the above embodiments, in a shift register device composed of four shift register units connected in series, each shift register unit includes two latch circuits. Therefore, the shift register device with four shift register units includes eight latch circuits, namely the first latch circuit to the eighth latch circuit, which can realize a shift operation with a maximum shift number of 4 bits. During operation, in response to the clock signal of the shift pulse input terminal CLK, the data of each latch and the data output by the parallel output terminal are shown in Table 2.

[0050] Table 2 Shift function logic table of a shift register device composed of four shift register units connected in series

[0051]

[0052]

[0053] The latch circuit and the drive circuit in the shift register device based on the drive circuit provided by the embodiment of the present invention have a variety of design forms, which can consume less hardware resources to realize the design of the same functional circuit module, and help alleviate the problem of hardware resource shortage when using the shift register on a hardware platform with limited resources. According to some optional embodiments, the latch circuit can be a dual inverter structure. Figure 4 The schematic diagram of the structure of the latch circuit of the dual inverter structure is shown in FIG. Figure 4 As shown, the dual inverter structure includes a first inverter and a second inverter, the first inverter includes a first NMOS transistor MN1 and a first PMOS transistor MP1, and the second inverter includes a second NMOS transistor MN2 and a second PMOS transistor MP2. The input end of the first inverter (the gate of the first NMOS transistor MN1 and the first PMOS transistor MP1) is connected to the output end of the second inverter (the drain of the second NMOS transistor MN2 and the second PMOS transistor MP2), and the connection point is QX; the input end of the second inverter (the gate of the second NMOS transistor MN2 and the second PMOS transistor MP2) is connected to the output end of the first inverter (the drain of the first NMOS transistor MN1 and the first PMOS transistor MP1), and the connection point is / QX, QX is the input and output end of the latch circuit, and according to the structure of the shift register device in the above embodiment, it is connected to the output end of the previous stage driving circuit and the input end of the next stage driving circuit. Among them, QX and / QX are opposite levels. When the previous stage driving circuit outputs a high level, due to its strong driving ability, Figure 4 The QX terminal in is pulled high to a high level, the first NMOS transistor MN1 is turned on, / QX is pulled low to a low level, and the second PMOS transistor MP2 is turned on, and the QX terminal level continues to be pulled high, and the data enters a high-level latched state. Similarly, when the output of the previous stage driving circuit is a low level, the first PMOS transistor MP1 and the second NMOS transistor MN2 are turned on, the first NMOS transistor MN1 and the second PMOS transistor MP2 are turned off, and the data enters a low-level latched state. This latch circuit structure only needs to use 4 transistor resources, which saves half of the hardware resources compared to the conventional latch circuit structure using a NAND gate.

[0054] According to some optional embodiments, at least one of the first drive circuit and the second drive circuit is a three-state gate structure. The three-state gate structure includes a third inverter and a three-state gate circuit, the output end of the third inverter is connected to the input end of the three-state gate circuit, the input end of the third inverter is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the three-state gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the three-state gate circuit is the control end of the first drive circuit, and the second control port of the three-state gate circuit is the control end of the second drive circuit. Figure 5 The schematic diagram of the driving circuit of the three-state gate structure is shown in FIG. Figure 5 As shown, the third inverter includes a third NMOS transistor MN3 and a third PMOS transistor MP3, and the three-state gate circuit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5 connected in sequence, that is, the source of the fourth PMOS transistor MP4 is connected to the power supply VDD, the drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, the drain of the fifth PMOS transistor MP5 is connected to the drain of the fourth NMOS transistor MN4, the source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5, and the source of the fifth NMOS transistor MN5 is connected to the ground. Among them, the output end of the third inverter (the drain of the third NMOS transistor MN3 and the third PMOS transistor MP3) is connected to the input end of the tri-state gate circuit (the gate of the fifth NMOS transistor MN5 and the fourth PMOS transistor MP4), and the input end of the third inverter (the gate of the third NMOS transistor MN3 and the third PMOS transistor MP3) is the data input port A of the tri-state gate structure. When forming a driving circuit, the input end is the input end of the first driving circuit or the input end of the second driving circuit. The gate of the fifth PMOS transistor MP5 is the first control port S of the tri-state gate circuit, and the gate of the fourth NMOS transistor MN4 is the second control port of the tri-state gate circuit. The first control port S and the second control port input a pair of opposite level signals. When forming a driving circuit, the first control port S is the control end of the first driving circuit, and the second control port is the control end of the second driving circuit, both of which are coupled to the shift pulse input end, and the effective driving levels of the control end of the first driving circuit and the control end of the second driving circuit are opposite. The output end of the tri-state gate circuit (the drains of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4) is the data output port B. When constituting a driving circuit, the output end is the output end of the first driving circuit or the output end of the second driving circuit.

[0055] In this three-state gate structure, when the signal input to the first control port S is at a high level and the signal input to the second control port / S is at a low level, the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 are turned off, and the data cannot be transmitted to the output port B. At this time, the drive circuit is in a high impedance state. When the signal input to the first control port S is at a low level and the signal input to the second control port / S is at a high level, the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 are turned on, and the drive circuit is in a conductive state. When the signal input to the data input port A is at a low level, after passing through the third inverter, the intermediate signal Y is at a high level, the fourth PMOS transistor MP4 is turned off, and the fifth NMOS transistor MN5 is turned on. If the drive circuit is turned on, the output port B is at a low level. When the data input port A is at a high level, after passing through the third inverter, the intermediate signal Y is at a low level, the fourth PMOS transistor MP4 is turned on, and the fifth NMOS transistor MN5 is turned off. If the drive circuit is turned on, the output port B is at a high level. Compared to Figure 4 For the latch circuit in the drive circuit, a larger transistor is needed to ensure that the output has a stronger driving capability and can latch the output data into the subsequent latch circuit. Figure 5 The driving circuit shown uses the hardware resources of 6 transistors. A driving circuit and a latch circuit can realize the function of a level-triggered D latch. The hardware structure of the driving circuit plus the latch circuit needs to be built using 10 transistors, and the structure of the D latch needs 16 transistors to be built. It is estimated that the solution based on the driving circuit requires about 160 transistor resources to realize an 8-bit (bit) shift register circuit. Compared with the structure of the conventional shift register based on the D flip-flop, the shift register device based on the driving circuit of the embodiment of the present invention can save about 3 / 8 of the hardware resource consumption, reducing the resource pressure when realizing the shift register on a hardware platform with limited resources.

[0056] According to some optional embodiments, at least one of the first driving circuit and the second driving circuit is a first transmission gate structure. Figure 6 The schematic diagram of the structure of the driving circuit of the first transmission gate structure is shown in FIG. Figure 6As shown, the first transmission gate structure includes a source follower and a transmission gate circuit, the source follower includes a sixth NMOS transistor MN6 and a first resistor R1, the transmission gate circuit includes a seventh PMOS transistor MP7 and a seventh NMOS transistor MN7, and the source and drain of the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are interconnected to form a bidirectional transmission gate. The output end of the source follower (the connection end of the source of the sixth NMOS transistor MN6 and the first resistor R1) is connected to the input end of the transmission gate circuit; when the first transmission gate structure is used to form a driving circuit, the input end C of the source follower (the gate of the sixth NMOS transistor MN6) is the input end of the first driving circuit or the input end of the second driving circuit, the output end D of the transmission gate circuit is the output end of the first driving circuit or the output end of the second driving circuit, the first control port S1 of the transmission gate circuit (the gate of the seventh PMOS transistor MP7) is the control end of the first driving circuit, and the second control port / S1 of the transmission gate circuit (the gate of the seventh NMOS transistor MN7) is the control end of the second driving circuit, both of which are coupled to the shift pulse input end, and the effective driving levels of the control end of the first driving circuit and the control end of the second driving circuit are opposite. The first control port S1 and the second control port / S1 input a pair of opposite level signals. When the signal input to the first control port S1 is at a high level and the signal input to the second control port / S1 is at a low level, the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are cut off, and the source follower output data Z cannot be transmitted to the output terminal D. At this time, the drive circuit is in a high impedance state; when the signal input to the first control port S1 is at a low level and the signal input to the second control port / S1 is at a high level, the seventh PMOS transistor MP7 and the seventh NMOS transistor MN7 are turned on, and the drive circuit is in a conductive state. When the input terminal C is at a high level, after passing through the source follower, the source follower output data Z is at a high level. If the drive circuit is turned on, the output terminal D is at a high level. When the input terminal C is at a low level, after passing through the source follower, the source follower output data Z is at a low level. If the drive circuit is turned on, the output terminal D is at a low level. Figure 5 Compared with the embodiment, Figure 6 The driving circuit implemented by the embodiment structure can further reduce the consumption of hardware resources.

[0057] According to some optional embodiments, at least one of the first driving circuit and the second driving circuit is a second transmission gate structure. Figure 7 The schematic diagram of the structure of the driving circuit of the second transmission gate structure is shown in FIG. Figure 7As shown, the second transmission gate structure includes a fourth inverter, a fifth inverter and a transmission gate circuit; wherein the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the transmission gate circuit, the input end of the fourth inverter is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the transmission gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port S1 of the transmission gate circuit is the control end of the first drive circuit, the second control port / S1 of the transmission gate circuit is the control end of the second drive circuit, both are coupled to the shift pulse input end, and the effective drive levels of the control end of the first drive circuit and the control end of the second drive circuit are opposite. In this embodiment, the structures of the fourth inverter and the fifth inverter are the same as the third inverter structure involved in the above embodiment, as shown in FIG. Figure 7 As shown, the fourth inverter includes an eighth PMOS transistor MP8 and an eighth NMOS transistor MN8, and the fifth inverter includes a ninth PMOS transistor MP9 and a ninth NMOS transistor MN9. The transmission gate circuit structure is the same as the transmission gate circuit structure involved in the above embodiment, such as Figure 7 As shown, the transmission gate circuit includes a tenth PMOS transistor MP10 and a tenth NMOS transistor MN10. The working principles of each inverter and transmission gate circuit are similar to those of the inverter and transmission gate circuit involved in the above embodiments, and their repeated description will be omitted here.

[0058] In summary, an embodiment of the present invention relates to a shift register device, comprising a serial input terminal, a shift pulse input terminal and a first output terminal; the shift register device comprises a shift register unit; the shift register unit couples the serial input terminal, the shift pulse input terminal and the first output terminal; the shift register unit is configured to perform a shift operation on the input signal of the serial input terminal in response to a clock signal of the shift pulse input terminal. The shift register device provided by the embodiment of the present invention realizes a shift register device with a variable number of bits based on the setting of the shift register unit therein, and through the structural design of the shift register unit, compared with the prior art, it is possible to realize the shift operation on data with less hardware resources, thereby solving the problem of tight hardware resources when using shift registers on a hardware platform with limited resources.

[0059] It should be understood that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present invention (including claims) is limited to these examples; under the idea of ​​the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of one or more embodiments of the present invention as described above, which are not provided in detail for the sake of simplicity. The above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the scope of protection of the present invention. In addition, the claims attached to the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the attached claims, or the equivalent forms of such scope and boundaries.

Claims

1. A shift register device, characterized in that: The shift register device comprises a serial input terminal, a shift pulse input terminal and a first output terminal; The shift register device comprises a shift register unit; the shift register unit is coupled to the serial input terminal, the shift pulse input terminal and the first output terminal; the shift register unit is configured to perform a shift operation on the input signal of the serial input terminal in response to a clock signal of the shift pulse input terminal; The shift register unit includes a first shift circuit and a second shift circuit; the first shift circuit includes a first latch circuit and a first drive circuit, the input end of the first drive circuit is the input end of the shift register unit, the control end of the first drive circuit is coupled to the shift pulse input end, and the input and output ends of the first latch circuit are coupled to the output end of the first drive circuit; the second shift circuit includes a second latch circuit and a second drive circuit, the input end of the second drive circuit is coupled to the output end of the first drive circuit, the control end of the second drive circuit is coupled to the shift pulse input end, and the input and output ends of the second latch circuit are the output end of the shift register unit and are coupled to the output end of the second drive circuit.

2. The device according to claim 1, characterized in that The shift register device comprises a plurality of shift register units, and the number of the plurality of shift register units is the same as the maximum number of shift bits of the shift register device; The multiple shift register units are connected in series in sequence, the output end of the previous shift register unit is connected to the input end of the next shift register unit, the input end of the first shift register unit is coupled to the serial input end, and the output end of the last shift register unit is coupled to the first output end.

3. The device according to claim 2, characterized in that The output end of each shift register unit constitutes a parallel output end of the shift register device, and the parallel output end performs parallel shifting and outputting of the input signal of the serial input end.

4. The device according to any one of claims 1 to 3, characterized in that: The clock signal includes a first level signal and a second level signal; the first level signal and the second level signal have different levels; When the clock signal is a first level signal, the shift register unit reads a signal from an input end of the shift register unit; when the clock signal is a second level signal, the shift register unit outputs a signal from an output end of the shift register unit.

5. The device according to claim 4, characterized in that The first level signal and the second level signal constitute a clock signal of one cycle; When the clock signal is a second level signal in each cycle, The lowest bit of the output signal of the parallel output terminal is the same as the input signal in the same cycle, and is shifted to the adjacent high bit in the next cycle.

6. The device according to claim 5, characterized in that The first driving circuit controls the output and input of the first driving circuit to be turned on in response to a first level signal at the control terminal; the second driving circuit controls the output and input of the second driving circuit to be turned on in response to a second level signal at the control terminal.

7. The device according to claim 6, characterized in that: When the output terminal and the input terminal of the first driving circuit are turned on, the input and output terminals of the first latch circuit read the input terminal signal of the first driving circuit; When the output terminal and the input terminal of the second driving circuit are turned on, the input and output terminals of the second latch circuit read the input terminal signal of the second driving circuit.

8. The device according to any one of claims 1 to 3, characterized in that: The first latch circuit and the second latch circuit are dual inverter structures; The dual inverter structure includes a first inverter and a second inverter; The input end of the first inverter is connected to the output end of the second inverter, and the input end of the second inverter is connected to the output end of the first inverter; the input end of the first inverter is the input / output end of the first latch circuit or the input / output end of the second latch circuit.

9. The device according to any one of claims 1 to 6, characterized in that: At least one of the first driving circuit and the second driving circuit is a three-state gate structure; The tri-state gate structure includes a third inverter and a tri-state gate circuit; The output end of the third inverter is connected to the input end of the three-state gate circuit, the input end of the third inverter is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the three-state gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the three-state gate circuit is the control end of the first drive circuit, and the second control port of the three-state gate circuit is the control end of the second drive circuit.

10. The device according to any one of claims 1 to 6, characterized in that: At least one of the first driving circuit and the second driving circuit is a first transmission gate structure; The first transmission gate structure includes a source follower and a transmission gate circuit; The output end of the source follower is connected to the input end of the transmission gate circuit; the input end of the source follower is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the transmission gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the transmission gate circuit is the control end of the first drive circuit, and the second control port of the transmission gate circuit is the control end of the second drive circuit.

11. The device according to any one of claims 1 to 6, characterized in that: At least one of the first driving circuit and the second driving circuit is a second transmission gate structure; The second transmission gate structure includes a fourth inverter, a fifth inverter and a transmission gate circuit; The output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the input end of the transmission gate circuit, the input end of the fourth inverter is the input end of the first drive circuit or the input end of the second drive circuit, the output end of the transmission gate circuit is the output end of the first drive circuit or the output end of the second drive circuit, the first control port of the transmission gate circuit is the control end of the first drive circuit, and the second control port of the transmission gate circuit is the control end of the second drive circuit.

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