Display device and mobile electronic device including the same

Abstract

The invention relates to a mobile electronic device and a display device. The display device may include a substrate, a driving element layer disposed on the substrate, and a light emitting element layer disposed on the driving element layer. The light emitting element layer may include: a pixel defining layer including a plurality of openings defining a plurality of pixels, respectively; a first electrode disposed in each of the plurality of pixels and including a first portion covered by the pixel defining layer and a second portion extending from the first portion and corresponding to an opening of each of the plurality of pixels; and an intermediate layer covering the second portion of the first electrode in the opening of each of the plurality of pixels, covering the pixel defining layer between adjacent pixels among the plurality of pixels, and including an electrically disconnected portion corresponding to a heating wiring.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0089153 filed in the Korean Intellectual Property Office on July 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a mobile electronic device including the display device. Background Art

[0004] A wearable device in the form of glasses or helmets is being developed that forms a focus at a shorter distance from the user's eyes. For example, the wearable device may be a head-mounted display (HMD) or augmented reality (AR) glasses. Such a wearable device provides an AR image or a virtual reality (VR) image to the user.

[0005] Wearable devices such as HMD or AR glasses may need to have a display specification of at least 2000 pixels per inch (PPI) so that users can use the wearable device for a long time without dizziness. To this end, organic light emitting diode on silicon (OLEDoS) technology is proposed, which can be a small, high-resolution organic light emitting display device. OLEDoS is a technology for placing an organic light emitting diode (OLED) on a semiconductor wafer substrate, and a complementary metal oxide semiconductor (CMOS) can be set on the semiconductor wafer substrate.

[0006] Since the distance between pixels in a display panel to which OLEDoS technology is applied may be reduced, unexpected leakage current may be generated between adjacent pixels. The leakage current may be generated by some conductive layers of an intermediate layer provided between a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode). The leakage current may be the cause of color crosstalk between adjacent pixels. Summary of the invention

[0007] Various aspects of the present disclosure provide a display device and a mobile electronic device including the display device, in which at least a portion of an intermediate layer disposed between a pixel electrode and a common electrode can be electrically disconnected between adjacent pixels (i.e., adjacent pixels) to prevent leakage current and color crosstalk.

[0008] According to an embodiment of the present disclosure, a display device may include: a substrate; a driving element layer disposed on the substrate; and a light-emitting element layer disposed on the driving element layer. The light-emitting element layer may include: a pixel defining layer including a plurality of openings respectively defining a plurality of pixels; a first electrode disposed in each of the plurality of pixels and including a first portion covered by the pixel defining layer and a second portion extending from the first portion and corresponding to one of the plurality of openings; a heating wiring disposed on the upper surface of the pixel defining layer to surround at least a portion of each of the plurality of openings; a connecting electrode connecting the heating wiring and the first portion of the first electrode through a contact hole penetrating the pixel defining layer; an intermediate layer covering the second portion of the first electrode and the pixel defining layer disposed between adjacent pixels among the plurality of pixels, the intermediate layer including an electrically disconnected portion corresponding to the heating wiring in a plan view; and a second electrode, the second electrode being continuous and covering a portion of the intermediate layer disposed in a corresponding one of the plurality of openings in each of the plurality of pixels, and covering a portion of the intermediate layer and the heating wiring disposed between the adjacent pixels among the plurality of pixels.

[0009] The driving element layer may include a Joule heating driver disposed to correspond to a non-display area of ​​the substrate and configured to sequentially supply a heating scan signal to a plurality of heating scan wirings disposed in a display area of ​​the substrate.

[0010] The driving element layer may further include a switching circuit, which is arranged to correspond to the non-display area of ​​the substrate, and the switching circuit is configured to supply a Joule heating voltage to a plurality of heating voltage supply wirings arranged in the display area of ​​the substrate in synchronization with the timing at which the Joule heating driver outputs the heating scanning signal.

[0011] The switch circuit may include a plurality of switch transistors electrically connected one-to-one to the plurality of heating voltage supply wirings, and each of the plurality of switch transistors may be turned on in response to a heating control signal and configured to output the Joule heating voltage when turned on.

[0012] The heating control signal may be synchronized with the heating scanning signal.

[0013] The plurality of heating voltage supply wirings may cross the plurality of heating scanning wirings.

[0014] The driving element layer may also include a pixel driving circuit, which is arranged in the display area of ​​the substrate to correspond to each of the multiple pixels, and the pixel driving circuit may include: a driving transistor, which supplies a specified driving current to a first node electrically connected to the first electrode based on a data signal input from a data line; and a heating transistor, which is turned on in response to the heating scanning signal input from the multiple heating scanning wirings, and supplies the Joule heating voltage input from the multiple heating voltage supply wirings to the first node when turned on.

[0015] The heating wiring may be configured to receive the Joule heating voltage via the first electrode and the connection electrode.

[0016] The resistance of the heating wiring may be greater than each of the resistance of the first electrode and the resistance of the connection electrode.

[0017] The intermediate layer may include at least one conductive layer, the at least one conductive layer including a portion electrically disconnected at a position corresponding to the heating wiring, and the at least one conductive layer may include a layer selected from a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer and a P-type doping layer.

[0018] In a plan view, the heating wiring may surround each of the plurality of openings in the pixel defining layer, and the heating wiring may include an open slit region opened in a specific lateral direction.

[0019] The intermediate layer and the second electrode may be continuous without being electrically disconnected at a position corresponding to the open slit region.

[0020] According to an embodiment of the present disclosure, a mobile electronic device may include a display panel, the display panel may include: a substrate; a driving element layer disposed on the substrate; and a light-emitting element layer disposed on the driving element layer. The light-emitting element layer may include: a pixel defining layer including a plurality of openings respectively defining a plurality of pixels; a first electrode disposed in each of the plurality of pixels and including a first portion covered by the pixel defining layer and a second portion extending from the first portion and corresponding to one of the plurality of openings; a heating wiring disposed on an upper surface of the pixel defining layer to surround at least a portion of each of the plurality of openings; a connecting electrode connecting the heating wiring and the first portion of the first electrode through a contact hole penetrating the pixel defining layer; an intermediate layer covering the second portion of the first electrode and the pixel defining layer disposed between adjacent pixels among the plurality of pixels, the intermediate layer including an electrically disconnected portion corresponding to the heating wiring in a plan view; and a second electrode, the second electrode being continuous and covering a portion of the intermediate layer disposed in a corresponding one of the plurality of openings in each of the plurality of pixels, and covering a portion of the intermediate layer and the heating wiring disposed between the adjacent pixels among the plurality of pixels.

[0021] The driving element layer may include a Joule heating driver disposed to correspond to a non-display area of ​​the substrate and configured to sequentially supply a heating scan signal to a plurality of heating scan wirings disposed in a display area of ​​the substrate.

[0022] The driving element layer may further include a switching circuit, which is arranged to correspond to the non-display area of ​​the substrate, and the switching circuit is configured to supply a Joule heating voltage to a plurality of heating voltage supply wirings arranged in the display area of ​​the substrate in synchronization with the timing of the Joule heating driver outputting the heating scanning signal.

[0023] The switch circuit may include a plurality of switch transistors electrically connected one-to-one to the plurality of heating voltage supply wirings, and each of the plurality of switch transistors may be turned on in response to a heating control signal and configured to output the Joule heating voltage when turned on.

[0024] The heating control signal may be synchronized with the heating scanning signal.

[0025] The plurality of heating voltage supply wirings may cross the plurality of heating scanning wirings.

[0026] The driving element layer may also include a pixel driving circuit, which is arranged in the display area of ​​the substrate to correspond to each of the multiple pixels, and the pixel driving circuit may include: a driving transistor, which supplies a specified driving current to a first node electrically connected to the first electrode based on a data signal input from a data line; and a heating transistor, which is turned on in response to the heating scanning signal input from the multiple heating scanning wirings, and supplies the Joule heating voltage input from the multiple heating voltage supply wirings to the first node when turned on.

[0027] The heating wiring may be configured to receive the Joule heating voltage via the first electrode and the connection electrode.

[0028] However, aspects of the present disclosure may not be limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become more apparent and easier to understand from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a perspective view of a display device according to an embodiment;

[0031] Figure 2 is a plan view of a display panel according to an embodiment;

[0032] Figure 3 is a schematic block diagram configuration of a display device according to an embodiment;

[0033] Figure 4 is a schematic block diagram configuration of a Joule heating driver and a switching circuit according to an embodiment;

[0034] Figure 5 is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment;

[0035] Figure 6 is a schematic cross-sectional view of a portion of a display panel of a display device according to an embodiment;

[0036] Figure 7 is a cross-sectional view schematically showing a stacked structure of a light emitting element according to an embodiment;

[0037] Figure 8 is a cross-sectional view schematically showing a stacked structure of a light emitting element according to an embodiment;

[0038] Fig. 9is a schematic plan view of a portion of a display area of ​​a display panel according to an embodiment;

[0039] Fig.10 It is schematically shown Fig. 9 A cross-sectional view of the cross-sectional structure of adjacent pixels shown in ;

[0040] Fig.11 It shows the manufacturing Fig. 9 A flowchart of a method for displaying a panel as shown in ;

[0041] Figures 12 to 15 are schematic cross-sectional views sequentially illustrating a method of manufacturing a display panel according to an embodiment;

[0042] Fig.16 Shows Fig. 9 The heating wiring shown in the embodiment includes an open slit area in a specific lateral direction of each pixel;

[0043] Fig.17 It shows the manufacturing Fig.16 A flowchart of a method for displaying a panel as shown in ;

[0044] Figures 18 to 21 are schematic cross-sectional views sequentially illustrating a method of manufacturing a display panel according to an embodiment; and

[0045] Fig. 22 is an example view of a wearable device including a display device according to an embodiment. DETAILED DESCRIPTION

[0046] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. "Embodiment" and "implementation" used herein are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0047] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter referred to as "elements" independently or collectively) can be combined, separated, interchanged and / or rearranged without departing from the concept of the present invention.

[0048] The use of cross hatching and / or shadows in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shadows does not convey or indicate a preference or requirement for a specific material, material performance, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performances, etc. of the elements. Furthermore, in the accompanying drawings, the size and relative size of the elements may be enlarged for clarity and / or descriptive purposes. In the case where the embodiments can be implemented in different ways, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals and / or reference characters represent the same elements.

[0049] In the case where an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, in the case where an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. Furthermore, the first direction DR1, the second direction DR2 and the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the X-axis, the Y-axis and the Z-axis), and the first direction DR1, the second direction DR2 and the third direction DR3 may be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2 and the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0050] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms "first", "second", etc. can be used in this article to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0052] Spatially relative terms such as "under," "below," "below," "down," "above," "over (throughout)," "up," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and to describe the relationship of one element to another (or other) elements shown in the drawings. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, elements or features described as "under" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the term "under" may encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or oriented in other orientations), and as such, the spatially relative terms used herein are interpreted accordingly.

[0053] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "one (kind / person)" and "the (the)" are also intended to include plural forms. In addition, in the case of use in this specification, the terms "comprises, comprising" and / or "includes, including" indicate the presence of stated features, integral bodies, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or combinations thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and are not terms of degree, and as such, the terms "substantially", "about" and other similar terms are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0054] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shapes of the views due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments disclosed herein need not be construed as being limited to the shapes of the particular zones shown, but rather include deviations in shapes, such as those caused by manufacturing. In this manner, the zones shown in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and as such, need not be intended to limit the shapes of these zones.

[0055] According to the convention in the art, some embodiments are described and shown in the accompanying drawings with respect to functional blocks, components and / or modules. It will be understood by those skilled in the art that these blocks, components and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.), and these blocks, components and / or modules can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, components and / or modules are implemented by microprocessors or other similar hardware, blocks, components and / or modules can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and blocks, components and / or modules can be optionally driven by firmware and / or software. It is also conceivable that each block, each component and / or each module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and related circuit systems) for performing other functions. In addition, without departing from the scope of the inventive concept, each block, each component and / or each module of some embodiments can be physically divided into two or more interacting and discrete blocks, components and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, components and / or modules of some embodiments may be physically combined into more complex blocks, components and / or modules.

[0056] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the context of the present disclosure, and should not be interpreted in an ideal or overly formal sense.

[0057] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device 10 according to the embodiment.

[0059] Reference Figure 1The display device 10 can be applied to portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)). For example, the display device 10 can be applied as a display component of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices (such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs)).

[0060] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having short sides in the first direction DR1 and long sides in the second direction DR2. The display device 10 may have a planar shape similar to a quadrilateral having long sides in the first direction DR1 and short sides in the second direction DR2. Figure 1 , the third direction DR3 represents a normal direction DR3 perpendicular to the plane defined by the first direction DR1 and the second direction DR2. Each corner where the short side intersects the long side may be rounded with a curvature (e.g., a predetermined or selectable curvature), or may be a right angle. The planar shape of the display device 10 may not be limited to a quadrilateral shape, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0061] The display device 10 may include a display panel 110 , a circuit board 120 , and a power supply part 130 .

[0062] The display panel 110 may be a semiconductor wafer substrate 200 (see Figure 2 ) as a display panel 110 as a base substrate. The display panel 110 may include a main area MA and a sub area SBA.

[0063] The main area MA may include pixels PX (see Figure 3 ) and a non-display area NDA disposed around the display area DA. The non-display area NDA may be an area other than the display area DA in the main area MA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 110 may include a pixel driving circuit PC (see Figure 5 ), the pixel driving circuit PC includes a switching element.

[0064] Light emitting element LEL (see Figure 6 ) may include but may not be limited to at least one of an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, and a micro light emitting diode.

[0065] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 110. The non-display area NDA may include fan-out lines extending from lines (e.g., gate lines, data lines, and emission control lines) of the display area DA, and fan-out lines and a display driving circuit 210 (see FIG. Figure 2 ) is connected to a display pad component (not shown).

[0066] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a main pad part electrically connected to the circuit board 120. Alternatively, the sub-area SBA may be omitted, and the main pad part may be provided in the non-display area NDA.

[0067] The circuit board 120 may be attached to the main pad part of the display panel 110 using an anisotropic conductive film (ACF). Leads of the circuit board 120 may be electrically connected to the main pad part of the display panel 110. The circuit board 120 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0068] The power supply component 130 may be provided on the circuit board 120 to supply a power supply voltage to the display driving circuit 210 and the display panel 110. The power supply component 130 may generate a driving voltage and supply the driving voltage to the driving voltage line. For example, the driving voltage may include a high potential voltage ( Figure 5 The first driving voltage ELVDD) and the low potential voltage ( Figure 5 of the second driving voltage ELVSS).

[0069] Figure 2 is a plan view of a display panel 110 according to an embodiment.

[0070] Reference Figure 2 , the display panel 110 may be an organic light emitting diode on silicon (OLEDoS) panel using a semiconductor wafer substrate as a base substrate. For example, the display panel 110 may include a substrate 200, and the substrate 200 may be a semiconductor wafer substrate. In the present disclosure, the substrate may be, but is not necessarily, referred to as a "semiconductor substrate", "semiconductor wafer substrate" or "wafer".

[0071] According to an embodiment, the pixel driving circuit PC (see Figure 5 ) and a display driving circuit 210 for controlling the pixel driving circuit PC may be disposed on the front surface 201 of the substrate 200. The pixel driving circuit PC may be disposed in the display area DA in conjunction with the pixel PX (see Figure 3 ) of the light-emitting element LEL (see Figure 6The display driving circuit 210 may be disposed in the non-display area NDA and may drive the pixel driving circuit PC.

[0072] Pixel drive circuit PC (see Figure 5 ) and the display driving circuit 210 may be formed on a driving element layer 601 (see Figure 6 ). The driving element layer 601 may include, for example, an N-type metal oxide semiconductor field effect transistor (MOSFET) and / or a P-type MOSFET. In the present disclosure, the driving element layer 601 (see Figure 6 ) may but need not necessarily be referred to as a “MOSFET layer”, “CMOS layer”, “transistor layer” or “backplane layer”.

[0073] Figure 3 The display device 10 according to the embodiment (see Figure 1 ) is a schematic block diagram configuration.

[0074] Reference Figure 3 And combined with Figure 1 , Figure 2 and Figure 6 , the display device 10 includes a display driving circuit 210 embedded in the display panel 110. The display driving circuit 210 may be formed in a driving element layer 601 disposed on the front surface 201 of the substrate 200. The display driving circuit 210 may include a timing controller 310, a gate driver 320, an emission control driver 330, and a data driver 340, but the present disclosure may not be limited thereto. Although not shown, the display driving circuit 210 may also include a memory (e.g., a one-time programmable (OTP) memory), an interface circuit (e.g., an I / F circuit), an image processing circuit (e.g., a logic circuit), and / or a gamma processing circuit.

[0075] The display area DA of the display panel 110 may include a plurality of pixels PX arranged in a matrix form. Each of the plurality of pixels PX may be electrically connected to a first driving voltage line VDL, a second driving voltage line VSL, a gate line GL, an emission control line EML, and a data line DL.

[0076] The first driving voltage line VDL may supply the first driving voltage ELVDD (see FIG. 1 ) input from the power supply part 130 to the pixel PX. Figure 5 The second driving voltage line VSL may supply the second driving voltage ELVSS (see FIG. 1 ) input from the power supply part 130 to the pixel PX. Figure 5 The gate line GL may supply gate signals GR and GW (see FIG. 1 ) input from the gate driver 320 to the pixel PX. Figure 5). The emission control line EML may supply the pixel PX with an emission control signal EM input from the emission control driver 330. The data line DL may supply the pixel PX with an analog data voltage input from the data driver 340.

[0077] The first driving voltage ELVDD may be a high potential voltage, and the second driving voltage ELVSS may be a low potential voltage. For example, the first driving voltage ELVDD may have a higher potential than the second driving voltage ELVSS.

[0078] Figure 3 One gate line GL shown in FIG. 1 may include Figure 5 , but the present disclosure may not be limited thereto.

[0079] Each of the plurality of pixels PX may include a light emitting element LEL (see Figure 5 ), and may include a plurality of transistors and at least one capacitor to constitute a pixel driving circuit PC for driving the light emitting element LEL (see Figure 5 ).

[0080] The timing controller 310 may receive the data signal DATA and the timing signal from the circuit board 120. The timing controller 310 may generate the data control signal DCS based on the timing signal, and control the operation timing of the data driver 340 using the data control signal DCS. The timing controller 310 may generate the gate control signal GCS based on the timing signal, and control the operation timing of the gate driver 320 using the gate control signal GCS. The timing controller 310 may generate the emission control signal ECS based on the timing signal, and control the operation timing of the emission control driver 330 based on the emission control signal ECS.

[0081] The data driver 340 may convert the data signal DATA into an analog data voltage and supply the analog data voltage to the pixel PX through the data line DL. The gate signal of the gate driver 320 may select the pixel PX to which the data voltage may be supplied, and the selected pixel PX may receive the data voltage through the data line DL.

[0082] The power supply component 130 may be provided on the circuit board 120 to supply a power supply voltage to the display driving circuit 210 and the display panel 110. The power supply component 130 may generate a driving voltage and may supply the driving voltage to the driving voltage line VDL or VSL. The power supply component 130 may generate a common voltage and may supply a common voltage to the second electrodes (e.g., Figure 6 The second electrode CAE) is supplied with a common voltage.

[0083] The gate driver 320 can supply gate signals GR and GW to the pixels PX through the gate lines GL (see Figure 5 ).

[0084] The emission control driver 330 may supply an emission control signal EM to the pixel PX through the emission control line EML (see Figure 5 ).

[0085] Figure 4 is a schematic block diagram configuration of a Joule heating driver 410 and a switching circuit 420 according to an embodiment.

[0086] Reference Figure 4 And combined with Figure 1 , Figure 2 , Figure 3 and Figure 6 , the display panel 110 of the display device 10 according to the embodiment further includes a Joule heating driver 410 and a switch circuit 420. The Joule heating driver 410 may be disposed in the non-display area NDA, and may be electrically connected to a plurality of heating scanning wirings HSL1 to HSLn (or simply the heating scanning wirings HSL) disposed in the display area DA. The switch circuit 420 may be disposed in the non-display area NDA, and may be electrically connected to a plurality of heating voltage supply wirings VHL disposed in the display area DA. In the display area DA, the plurality of heating voltage supply wirings VHL and the plurality of heating scanning wirings HSL may cross each other.

[0087] The Joule heating driver 410 may sequentially output a heating scanning signal HS to a plurality of heating scanning wirings HSL (see Figure 5 ). For example, the Joule heating driver 410 may output the heating scan signal HS to the first heating scan wiring HSL1 in a first period, and may output the heating scan signal HS to the second heating scan wiring HSL2 in a second period after the first period. The Joule heating driver 410 may output the heating scan signal HS to the third heating scan wiring HSL3 in a third period after the second period. The heating scan signal HS output from the Joule heating driver 410 is used to select a pixel PX to which the Joule heating voltage VJH may be supplied. The pixel PX receiving the heating scan signal HS may receive the Joule heating voltage VJH through the heating voltage supply wiring VHL.

[0088] According to an embodiment, the Joule heating driver 410 may set the scan on time (SOT) of each heating scan signal HS to be shorter than the gate signals GR and GW output from the gate driver 320 (see Figure 5 The Joule heating driver 410 may set the SOT of each heating scanning signal HS to be longer than the gate signals GR and GW (see Figure 5) is relatively long in order to ensure sufficient Joule heating time for heating wiring 910 (see Fig. 9 ) is heated. For example, the pixel PX selected by the heating scan signal HS may receive the Joule heating voltage VJH during the SOT of the heating scan signal HS. The SOT of the heating scan signal HS may be a time when the Joule heating voltage VJH may be supplied to the pixel PX. The Joule heating voltage VJH supplied to each pixel PX may be supplied through the first electrode ANE (see Figure 6 ) is transmitted to the heating wiring 910, and the heating wiring 910 can be heated by the transmitted Joule heating voltage VJH. Therefore, as the SOT of the heating scan signal HS increases, the time during which the heating wiring 910 can be heated also increases.

[0089] During the process of manufacturing the display panel 110, the heating wiring 910 may be heated to allow the intermediate layer ML (see FIG. 1 ) of the light emitting element LEL, which may be disposed around or on the heating wiring 910. Figure 6 ) is electrically disconnected. According to an embodiment of the present disclosure, the middle layer ML may be electrically disconnected in some areas between adjacent pixels PX to prevent leakage current from passing through the middle layer ML and prevent color crosstalk. Figure 7 and Figure 8 The electrical disconnection of the middle layer ML is described in detail.

[0090] The switch circuit 420 can supply the Joule heating voltage VJH to the heating voltage supply wiring VHL in synchronization with the timing at which the Joule heating driver 410 can output the heating scan signal HS. The switch circuit 420 can include a plurality of switch transistors SW electrically connected to the heating voltage supply wiring VHL one by one. The switch transistor SW can be turned on in response to the heating control signal HCS. When turned on, the switch transistor SW can supply the Joule heating voltage VJH to the heating voltage supply wiring VHL. Here, the heating control signal HCS can be synchronized with the heating scan signal HS output by the Joule heating driver 410.

[0091] According to an embodiment, each switching transistor SW may include a gate electrically connected to a supply wiring of a heating control signal HCS, a source (e.g., a first terminal) electrically connected to a power supply component 130 generating a Joule heating voltage VJH, and a drain (e.g., a second terminal) electrically connected to a heating voltage supply wiring VHL. Each switching transistor SW may be turned on in response to a heating control signal HCS input through a gate, and in the case of being turned on, each switching transistor SW may supply the Joule heating voltage VJH input from the source to the heating voltage supply wiring VHL through a drain. Although the switching transistor SW may be a P-type MOSFET in the example shown, the present disclosure may not be limited thereto.

[0092] Each of the plurality of pixels PX disposed in the display area DA may be electrically connected to a heating scan wiring HSL and a heating voltage supply wiring VHL. Each pixel PX may receive a heating scan signal HS output from the Joule heating driver 410 through the heating scan wiring HSL. Each pixel PX may receive a Joule heating voltage VJH through the heating voltage supply wiring VHL in synchronization with the timing of receiving the heating scan signal HS. The Joule heating voltage VJH input to each pixel PX may be transmitted to a first electrode (e.g., Figure 6 The first electrode ANE can be connected to the electrode 920 (see Figure 6 ) is electrically connected to the heating wiring 910. Therefore, the Joule heating voltage VJH supplied to the first electrode ANE can be transmitted to the heating wiring 910 via the connecting electrode 920. The heating wiring 910 can be heated by the transmitted Joule heating voltage VJH, so that the intermediate layer ML provided around the heating wiring 910 is electrically disconnected. The resistance of the heating wiring 910 can be greater than the resistance of the first electrode ANE and the resistance of each of the connecting electrode 920. Therefore, when the Joule heating voltage VJH is applied, the temperature of the heating wiring 910 can be higher than the temperature of each of the connecting electrode 920 and the first electrode ANE.

[0093] Figure 5 The display device 10 according to the embodiment (see Figure 1 ) is a schematic diagram of an equivalent circuit of a pixel PX.

[0094] Reference Figure 5 , the pixel PX may include a light emitting element LEL (e.g., an organic light emitting diode) and a pixel driving circuit PC electrically connected to the light emitting element LEL. The pixel driving circuit PC may include first to fifth transistors T1 to T5, a first capacitor C1 and a second capacitor C2, but the present disclosure may not be limited thereto. The first to fifth transistors T1 to T5 may be implemented as N-type MOSFETs and / or P-type MOSFETs. Although the first to fifth transistors T1 to T5 may be implemented as Figure 5 1 is shown as a P-type MOSFET, but the present disclosure may not be limited thereto.

[0095] The first transistor T1 may be a driving transistor in which the magnitude of the source-drain current may be determined according to the gate-source voltage. Each of the second to fourth transistors T2 to T4 may be a switching transistor that may be turned on / off according to the gate-source voltage or substantially the gate voltage. The fifth transistor T5 may be a transistor for supplying a first electrode ANE (see FIG. 1 ) of the light emitting element LEL to the first electrode ANE of the light emitting element LEL. Figure 6 )Heating transistor T5 that supplies Joule heating voltage VJH.

[0096] The first transistor T1 may include a gate electrically connected to the first node N1, a source electrically connected to the second node N2, and a drain electrically connected to the third node N3. The first transistor T1 may be turned on or off based on the voltage level of the first node N1. The turned-on first transistor T1 may connect the second node N2 and the third node N3. The second node N2 may be a node electrically connected to the drain of the third transistor T3, and the second node N2 is supplied with the first driving voltage ELVDD when the third transistor T3 is turned on in response to the emission control signal EM. The third node N3 may be a node to which the first electrode ANE of the light emitting element LEL and the source of the fourth transistor T4 may be connected. The third node N3 may be a node to which the second driving voltage ELVSS may be supplied when the fourth transistor T4 is turned on in response to the second gate signal GR.

[0097] The second transistor T2 may include a gate electrically connected to the first gate line GWL, a source electrically connected to the data line DL, and a drain electrically connected to the first node N1. The second transistor T2 may be turned on in response to the first gate signal GW supplied from the first gate line GWL. The turned-on second transistor T2 may supply the data signal Vdat supplied from the data line to the first node N1.

[0098] The third transistor T3 may include a gate electrically connected to the emission control line EML, a source electrically connected to the first driving voltage line VDL to which the first driving voltage ELVDD may be supplied, and a drain electrically connected to the second node N2. The third transistor T3 may be turned on in response to the emission control signal EM supplied from the emission control line EML. The turned-on third transistor T3 may supply the first driving voltage ELVDD to the second node N2.

[0099] The fourth transistor T4 may include a gate electrically connected to the second gate line GRL, a drain electrically connected to the second driving voltage line VSL to which the second driving voltage ELVSS may be supplied, and a source electrically connected to the third node N3. The fourth transistor T4 may be turned on in response to the second gate signal GR supplied from the second gate line GRL. The turned-on fourth transistor T4 may supply the second driving voltage ELVSS to the third node N3.

[0100] The fifth transistor T5 may include a gate electrically connected to the heating scan wiring HSL, a source electrically connected to the heating voltage supply wiring VHL, and a drain electrically connected to the third node N3. The fifth transistor T5 may be turned on in response to the heating scan signal HS supplied from the heating scan wiring HSL. The turned-on fifth transistor T5 may supply the Joule heating voltage VJH to the third node N3.

[0101] The first capacitor C1 may be disposed between the first node N1 and the second node N2. The second capacitor C2 may be disposed between the first node N1 and the third node N3. The first capacitor C1 and the second capacitor C2 are used to store the data signal Vdat input through the second transistor T2.

[0102] The light emitting element LEL may include a first electrode (eg, Figure 6 A first electrode ANE), a second electrode facing the first electrode (eg, Figure 6 a second electrode CAE), and an intermediate layer ML (see Figure 6 ). The middle layer ML may include an organic light emitting layer. The second electrode CAE may receive a second driving voltage ELVSS. The second electrode CAE may be electrically connected to a second driving voltage line VSL transmitting the second driving voltage ELVSS. The second electrode CAE may be electrically connected to a plurality of pixels PX in common.

[0103] Figure 6 The display device 10 according to the embodiment (see Figure 1 ) is a schematic cross-sectional view of a portion of a display panel 110. For example, Figure 6 A stack structure of each of the non-display area NDA and the display area DA of the display panel 110 according to the embodiment is schematically illustrated.

[0104] In reference Figure 6 In the description of the present invention, the expression "on" may refer to the front surface 201 of the substrate 200 (see Figure 2 ) faces the third direction DR3. The front surface 201 of the substrate 200 may refer to a direction in which each light emitting element LEL disposed in the display area DA emits light for displaying an image.

[0105] Reference Figure 6 And combined with Figure 2 , Figure 3 , Figure 5 , Figure 7 and Figure 8 , the display panel 110 according to the embodiment may include a substrate 200 , and the substrate 200 may be a semiconductor wafer substrate.

[0106] A driving element layer 601 including a display driving circuit 210 and a pixel driving circuit PC, at least one wiring layer 602, a light emitting element layer 603 including a light emitting element LEL, an encapsulation layer 604 covering the light emitting element LEL, a color filter layer 605 including a color filter CF, a light control layer 606 including a refractive layer MLA, and a covering layer 607 including a covering member CV may be sequentially stacked on one another on the front surface 201 of the substrate 200. At least some of the light emitting element layer 603, the encapsulation layer 604, the color filter layer 605, the light control layer 606, and the covering layer 607 may not be disposed in the non-display area NDA.

[0107] The substrate 200 may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The substrate 200 may be a substrate doped with first type impurities.

[0108] A driving element layer 601 including an N-type MOSFET and / or a P-type MOSFET may be disposed on the substrate 200. The first type impurity may be a P-type impurity, and the second type impurity may be an N-type impurity. The first type impurity may be an N-type impurity, and the second type impurity may be a P-type impurity.

[0109] In the present disclosure, an N-type MOSFET MOS included in the driving element layer 601 will be described as an example. The N-type MOSFET MOS (referred to as MOSFET MOS for short) may include a well region W1 doped with N-type impurities in a substrate 200 doped with P-type impurities.

[0110] The well region W1 may include a first low-concentration impurity region LDD1 and a second low-concentration impurity region LDD2 having a relatively low impurity concentration than other portions. The first low-concentration impurity region LDD1 may define a source region S1, and the second low-concentration impurity region LDD2 may define a drain region D1. A source electrode SE of the MOSFET MOS may be electrically connected to the source region S1, and a drain electrode DE of the MOSFET MOS may be electrically connected to the drain region D1.

[0111] The channel CH may be defined between the first low concentration impurity region LDD1 and the second low concentration impurity region LDD2 to overlap the gate G1. An oxide layer (not shown), which may be an insulating layer, may be disposed between the gate G1 and the well region W1.

[0112] MOSFET MOS constitutes the display driving circuit 210 (see Figure 2 ), and the display driving circuit 210 may be disposed in the non-display area NDA of the display panel 110. MOSFET MOS constitutes a transistor ( Figure 5The first transistor T1 to the fifth transistor T5 are provided, and the pixel driving circuit PC can be provided in the display area DA of the display panel 110. That is, each pixel driving circuit PC can be a circuit including a combination of MOSFET MOS provided in the driving element layer 601 to correspond to the display area DA. The display driving circuit 210 can be a circuit including a combination of MOSFET MOS provided in the driving element layer 601 to correspond to the non-display area NDA. For ease of description, Figure 6 Any one MOSFET MOS of the pixel driving circuit PC provided in the display area DA of the display panel 110 is shown as an example.

[0113] At least one wiring layer 602 may be disposed on the driving element layer 601. At least one wiring layer 602 may include an insulating layer VIA sequentially stacked on the driving element layer 601, and a connection electrode CE and a wiring (not shown) electrically connected to the MOSFET MOS through a contact hole CT1 at least partially penetrating the insulating layer VIA. The wiring layer 602 may include a connection electrode CE and a connection wiring for connecting the MOSFET MOS of the driving element layer 601 to each other, and an insulating layer VIA for insulating the MOSFET MOS of the driving element layer 601 from each other. The wiring layer 602 may include a plurality of signal wirings and a plurality of power wirings for driving the display panel 110.

[0114] Figure 6 The connection electrode CE shown in FIG. 1 connects a MOSFET MOS corresponding to the pixel driving circuit PC among a plurality of MOSFET MOS provided in the driving element layer 601 to a light emitting element LEL provided in a vertical direction on the wiring layer 602. Here, the vertical direction means a normal direction DR3 of the display panel 110.

[0115] Wiring (not shown) provided in the wiring layer 602 includes lines (eg, Figure 3 The lines GL, DL and EML and Figure 4 The wirings provided in the wiring layer 602 may further include fan-out lines (not shown) extending from the lines GL, DL, EML, and HSL electrically connected to the pixel driving circuit PC and provided in the non-display area NDA.

[0116] The wiring layer 602 may include pad electrodes PD1 to PD7 arranged to correspond to the non-display area NDA. The pad electrodes PD1 to PD7 include a first gate pad PD1 to which the first gate line GWL can be connected, a second gate pad PD2 to which the second gate line GRL can be connected, a Joule heating pad PD3 to which the Joule heating voltage VJH can be supplied, an emission pad PD4 to which the emission control line EML can be connected, a data pad PD5 to which the data line DL can be connected, a first drive voltage pad PD6 to which the first drive voltage line VDL can be connected, and a second drive voltage pad PD7 to which the second drive voltage line VSL can be connected. However, Figure 6 The pad electrodes PD1 to PD7 shown in FIG. 1 may be only examples, and the present disclosure is not limited thereto.

[0117] A planarization layer FL including an organic layer may be disposed on an uppermost layer among a plurality of insulating layers VIA included in the wiring layer 602 .

[0118] A pixel defining layer PDL defining a plurality of pixels PX and a light emitting element layer 603 including a light emitting element LEL may be disposed on the wiring layer 602. The light emitting element LEL may include a first electrode ANE electrically connected to a MOSFET MOS included in the pixel driving circuit PC through a contact hole CT2 and a connection electrode CE, an intermediate layer ML disposed on the first electrode ANE, and a second electrode CAE disposed on the intermediate layer ML. The pixel defining layer PDL may include a plurality of openings OP (see FIG. 1 ) corresponding to the plurality of pixels PX, respectively. Fig. 9 ), and a portion of the first electrode ANE may be exposed in each opening OP.

[0119] The middle layer ML may include a hole injection layer HIL, a hole transport layer HTL, a light emitting layer, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure may not be limited thereto. For example, the light emitting element LEL may be an RGB type light emitting element LEL that emits a first color of light (e.g., red light) in a first pixel PX1 (e.g., a red pixel), emits a second color of light (e.g., green light) in a second pixel PX2 (e.g., a green pixel), and emits a third color of light (e.g., blue light) in a third pixel PX3 (e.g., a blue pixel). The light emitting element LEL may be a white OLED (WOLED) type light emitting element LEL that emits white light in all first pixels PX1 (e.g., red pixels), second pixels PX2 (e.g., green pixels), and third pixels PX3 (e.g., blue pixels).

[0120] The stack structure of the organic material included in the middle layer ML may differ depending on whether the light emitting element LEL may be an RGB type or a WOLED type, but the present disclosure may not be limited thereto.

[0121] The heating wiring 910 may be disposed on the pixel defining layer PDL. The heating wiring 910 electrically disconnects the intermediate layer ML of the light emitting element LEL between adjacent pixels PX during the process. The electrical disconnection of the intermediate layer ML occurs in the process of applying the Joule heating voltage VJH to the heating wiring 910. The process of applying the Joule heating voltage VJH to the heating wiring 910 may be performed after depositing the intermediate layer ML. As will be described later, the process of applying the Joule heating voltage VJH to the heating wiring 910 may be performed before the process of depositing the second electrode CAE, or after the process of depositing the second electrode CAE.

[0122] According to an embodiment, the heating wiring 910 may be electrically connected to the first electrode ANE through a connection electrode 920 vertically penetrating the pixel defining layer PDL. The heating wiring 910 may be configured to receive a Joule heating voltage VJH through the first electrode ANE and the connection electrode 920, and generate heat in response to the received Joule heating voltage VJH. The temperature of the heating wiring 910 may be increased to a high temperature of about 400°C or higher by the received Joule heating voltage VJH, and the intermediate layer ML deposited on and around the heating wiring 910 may be removed by the high temperature.

[0123] In an embodiment, the middle layer ML of the light emitting element LEL may be electrically disconnected between adjacent pixels PX, thereby preventing leakage current between adjacent pixels PX and preventing color crosstalk. Color crosstalk refers to a phenomenon in which, for example, a red pixel (e.g., a first pixel PX1) adjacent to a blue pixel (e.g., a third pixel PX3) may be turned on unintentionally while the blue pixel may be emitting blue light. Color crosstalk occurs due to leakage current and may occur when a blue pixel and a red pixel having a large difference in voltage driving the pixel are adjacent to each other. For example, leakage current may be a phenomenon in which, when a driving current may be supplied to the light emitting element LEL of a blue pixel so as to turn on the blue pixel, a portion of the driving current may be transmitted to the red pixel (e.g., the first pixel PX1) through at least some conductive layers of the middle layer ML. In the case of generating leakage current, the red pixel may be turned on unintentionally while the blue pixel is being turned on.

[0124] An encapsulation layer 604 including at least one organic encapsulation layer and at least one inorganic encapsulation layer may be disposed on the light emitting element layer 603. For example, the encapsulation layer 604 may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3, but the present disclosure may not be limited thereto.

[0125] A color filter layer 605 including a color filter CF may be disposed on the encapsulation layer 604. The color filter CF may include a first color filter CF1 that transmits red light, a second color filter CF2 that transmits green light, or a third color filter CF3 that transmits blue light, but the present disclosure may not be limited thereto. In the case where the light-emitting element LEL of the light-emitting element layer 603 is a WOLED-type light-emitting element LEL, the color filter layer 605 may be provided. If the light-emitting element LEL of the light-emitting element layer 603 is an RGB-type light-emitting element LEL that emits (e.g., directly emits) red light, green light, or blue light, the color filter layer 605 may be omitted.

[0126] The light control layer 606 including the refraction layer MLA may be disposed on the color filter layer 605. The refraction layer MLA may refract light emitted from the light emitting element layer 603 and incident in the normal direction DR3 of the display panel 110. The refraction layer MLA may include a micro lens array.

[0127] A cover layer 607 serving as a cover of the display panel 110 may be disposed on the light control layer 606. The cover layer 607 may include a cover member CV made of glass, but the present disclosure may not be limited thereto. The cover layer 607 may include, for example, a protective film.

[0128] Figure 7 Schematically shows a light emitting element LEL according to an embodiment (for example, see Figure 6 ) is a cross-sectional view of a stacked structure. For example, Figure 7 The light emitting element layer 603 (see Figure 6 ) may be a stacked structure of intermediate layers ML in the case of a WOLED type light emitting element LEL.

[0129] Reference Figure 7 According to the display panel 110 of the embodiment (see Figure 2 ) may include a plurality of pixels PX, the plurality of pixels PX including a first pixel PX1 for displaying a first color (eg, red), a second pixel PX2 for displaying a second color (eg, green), and a third pixel PX3 for displaying a third color (eg, blue).

[0130] The light emitting element LEL disposed in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit white light. The display panel 110 may use a color filter CF (see Figure 6 ) displays a first color, a second color, and a third color. For example, white light emitted from a first pixel PX1 may pass through a first color filter CF1 to display a first color, white light emitted from a second pixel PX2 may pass through a second color filter CF2 to display a second color, and white light emitted from a third pixel PX3 may pass through a third color filter CF3 to display a third color.

[0131] A first electrode ANE (eg, a pixel electrode or an anode) may be disposed in each of the first, second, and third pixels PX1, PX2, and PX3. An intermediate layer ML and a second electrode CAE may be disposed on the first electrode ANE of each of the first, second, and third pixels PX1, PX2, and PX3.

[0132] The middle layer ML and the second electrode CAE may be common layers commonly stacked in the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 , and the middle layer ML and the second electrode CAE may be continuous in at least some regions between the pixels PX.

[0133] The middle layer ML may include a first emission part EU1, a charge generation layer CGL, a second emission part EU2, a charge generation layer CGL, and a third emission part EU3 sequentially stacked on the first electrode ANE of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, but the present disclosure may not necessarily be limited thereto. The stacking order and structure of the middle layer ML may be variously changed.

[0134] The first emission unit EU1 may include a hole injection layer HIL or a P-type doped layer PHIL doped with a P-type semiconductor, a blue light emitting layer BEML, and an electron transport layer ETL. The second emission unit EU2 may include a hole transport layer HTL, a green light emitting layer GEML, and an electron transport layer ETL. The third emission unit EU3 may include a hole transport layer HTL, a red light emitting layer REML, and an electron transport layer ETL.

[0135] The charge generation layer CGL may be disposed between the first emission component EU1 and the second emission component EU2. The charge generation layer CGL may be disposed between the second emission component EU2 and the third emission component EU3. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer.

[0136] The second electrode CAE may be disposed on the third emission unit EU3. The second electrode CAE may be a common layer commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3, and may be continuous in at least some regions between the pixels PX.

[0137] The cover layer CPL may be disposed on the second electrode CAE. Although not shown, the encapsulation layer 604 (see Figure 6 ) may be disposed on the cladding layer CPL, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the encapsulation layer 604. The cladding layer CPL may improve light emitting efficiency through the principle of constructive interference.

[0138] In the display panel 110 according to the embodiment, since the intermediate layer ML disposed between the first electrode ANE and the second electrode CAE may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and may be continuous in at least some regions between the pixels PX, leakage current may be generated. Figure 7 As indicated by arrows 701 in FIG. 7 , leakage current may flow between adjacent pixels PX through at least some conductive layers included in the middle layer ML.

[0139] The display panel 110 according to the embodiment may include a heating wiring 910 (see Figure 6 ) to prevent leakage current. For example, the heating wiring 910 can be set on the pixel defining layer PDL between adjacent pixels PX. The heating wiring 910 set between adjacent pixels PX can be driven before or after the process of depositing the second electrode CAE. When the heating wiring 910 is driven, high-temperature heat can be generated, and the generated high-temperature heat can cause at least some of the conductive layers included in the middle layer ML to be electrically disconnected. In the present disclosure, since at least some of the conductive layers included in the middle layer ML can be electrically disconnected around the heating wiring 910 between adjacent pixels PX, as Figure 7 As indicated by the solid line 702 in FIG. 8 , leakage current and color crosstalk can be prevented.

[0140] Figure 8 Schematically shows a light emitting element LEL according to an embodiment (for example, see Figure 6 ) is a cross-sectional view of a stacked structure. For example, Figure 8 In the light emitting element layer 603 (see Figure 6 ) may be a stacked structure of an intermediate layer ML in the case of an RGB type light emitting element LEL that emits (e.g., directly emits) red light in the first pixel PX1, emits (e.g., directly emits) green light in the second pixel PX2, and emits (e.g., directly emits) blue light in the third pixel PX3.

[0141] Reference Figure 8 According to the display panel 110 of the embodiment (see Figure 2 ) may include a plurality of pixels PX, the plurality of pixels PX including a first pixel PX1 for displaying a first color (eg, red), a second pixel PX2 for displaying a second color (eg, green), and a third pixel PX3 for displaying a third color (eg, blue).

[0142] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit (eg, directly emit) light of a designated color. Figure 6 ) may include a red light emitting layer REML for emitting red light from a first emission region, a light emitting element LEL in the second pixel PX2 may include a green light emitting layer GEML for emitting green light from a second emission region, and a light emitting element LEL in the third pixel PX3 may include a blue light emitting layer BEML for emitting blue light from a third emission region. Here, the first emission region may be a region where the first electrode ANE provided in the first pixel PX1 may be covered by the intermediate layer ML, the second emission region may be a region where the first electrode ANE provided in the second pixel PX2 may be covered by the intermediate layer ML, and the third emission region may be a region where the first electrode ANE provided in the third pixel PX3 may be covered by the intermediate layer ML.

[0143] A first electrode ANE (e.g., a pixel electrode or an anode) may be disposed in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. An intermediate layer ML and a second electrode CAE may be disposed on the first electrode ANE of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The intermediate layer ML may include a first common layer CL1 (e.g., a lower common layer), a light emitting layer, and a second common layer CL2 (e.g., an upper common layer), and the second electrode CAE may be disposed on the intermediate layer ML.

[0144] The first common layer CL1, the second common layer CL2, and the second electrode CAE may be common layers commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3, and the first common layer CL1, the second common layer CL2, and the second electrode CAE may be continuous in at least some areas between the pixels PX. On the other hand, different light-emitting layers REML, GEML, and BEML may be respectively arranged in the first pixel PX1, the second pixel PX2, and the third pixel PX3 between the first common layer CL1 and the second common layer CL2. For example, a red light-emitting layer REML may be arranged in the first pixel PX1, a green light-emitting layer GEML may be arranged in the second pixel PX2, and a blue light-emitting layer BEML may be arranged in the third pixel PX3. The light-emitting layers REML, GEML, and BEML may be discrete and electrically disconnected at the boundary of each pixel PX.

[0145] The first common layer CL1 may be a layer disposed below the light emitting layers REML, GEML, and BEML, and may include a hole injection layer HIL or a P-doped hole injection layer PHIL (P-type doped layer PHIL) doped with a P-type semiconductor and a hole transport layer HTL. However, the present disclosure may not be limited thereto. For example, the first common layer CL1 may include at least one hole injection layer HIL and at least one hole transport layer HTL.

[0146] The second common layer CL2 may be a layer disposed on the light emitting layers REML, GEML, and BEML, and may include an electron transport layer ETL and an electron injection layer EIL. However, the present disclosure may not be limited thereto. For example, the second common layer CL2 may include at least one electron transport layer ETL and at least one electron injection layer EIL.

[0147] The cladding layer CPL may be disposed on the second electrode CAE. The cladding layer CPL may improve light emitting efficiency through the principle of constructive interference.

[0148] and Figure 7 The embodiments are different. Figure 8 An embodiment does not include a color filter.

[0149] As in Figure 7 As in the embodiment of Figure 8 In the display panel 110 of the embodiment shown in , the first common layer CL1 and the second common layer CL2 disposed between the first electrode ANE and the second electrode CAE may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3, and the first common layer CL1 and the second common layer CL2 disposed between the first electrode ANE and the second electrode CAE may be continuous in at least some areas between the pixels PX. Therefore, leakage current may be generated through the first common layer CL1 and the second common layer CL2. Figure 8 As indicated by arrows 801 in FIG. 8 , leakage current may flow between adjacent pixels PX through at least some conductive layers included in the first common layer CL1 and the second common layer CL2 .

[0150] The display panel 110 according to an embodiment of the present disclosure may include a heating wiring 910 (see Figure 6 ) to prevent leakage current by separating and electrically disconnecting at least some conductive layers included in the middle layer ML from each other using the heating wiring 910. In the present disclosure, as Figure 8 As indicated by the solid line 802 in FIG. 1 , since at least some of the conductive layers included in the middle layer ML can become electrically disconnected around the heating wiring 910 between adjacent pixels PX, leakage current and color crosstalk can be prevented. In the present disclosure, at least some of the conductive layers of the middle layer ML that can be electrically disconnected around the heating wiring 910 may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0151] Fig. 9 is a schematic plan view of a portion of the display area DA of the display panel 110 according to an embodiment. For example, Fig. 9 It may be shown that the display panel 110 (or the substrate 200 (eg, see Figure 6 )) is in the normal direction DR3 of the upper surface (for example, see Figure 1 ) is a plan view of a portion of the display panel 110 observed on the surface.

[0152] Reference Fig. 9 , the display panel 110 may include a plurality of pixels PX, the plurality of pixels PX including a first pixel PX1, a second pixel PX2, and a third pixel PX3. The pixels PX may be arranged in a matrix form in the display area DA of the display panel 110. For example, the first pixel PX1 and the second pixel PX2 may be alternately arranged in each of the odd rows R1 and R3 in which the plurality of pixels PX may be arranged, and the second pixel PX2 and the third pixel PX3 may be alternately arranged in each of the even rows R2. The first pixel PX1 arranged in the odd rows R1 and R3 and the third pixel PX3 arranged in the even row R2 may be arranged adjacent to each other in the column direction (i.e., the vertical direction), and the second pixel PX2 arranged in the odd rows R1 and R3 and the second pixel PX2 arranged in the even row R2 may be arranged adjacent to each other in the column direction (i.e., the vertical direction). Fig. 9 At least some of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 shown in FIG. 5 may be replaced with a fourth pixel (not shown) displaying white light. Fig. 9 The arrangement of the pixels PX shown in FIG. 1 is merely an example, and the present disclosure may not be limited thereto.

[0153] exist Fig. 9 , solid lines (eg, Fig. 9 The first opening 901, the second opening 902, and the third opening 903 in the pixel defining layer PDL indicate openings OP of the pixel defining layer PDL that can be respectively set in the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, the first pixel PX1 can be defined in the first opening 901 of the pixel defining layer PDL, the second pixel PX2 can be defined in the second opening 902 of the pixel defining layer PDL, and the third pixel PX3 can be defined in the third opening 903 of the pixel defining layer PDL. Fig. 9 In the solid line (e.g., Fig. 9 The area outside the first opening 901, the second opening 902, and the third opening 903 in the image processing unit may be interpreted as an area in which the pixel defining layer PDL may be generally disposed.

[0154] According to an embodiment, the heating wiring 910 may be disposed between adjacent pixels PX. The heating wiring 910 may be disposed on the pixel defining layer PDL and may surround a corresponding one of a plurality of openings OP of the pixel defining layer PDL. For example, a first heating wiring 911 may be disposed around a first opening 901 corresponding to each of a plurality of first pixels PX1 and may surround the first opening 901. A second heating wiring 912 may be disposed around a second opening 902 corresponding to each of a plurality of second pixels PX2 and may surround the second opening 902. Similarly, a third heating wiring 913 may surround a third opening 903 corresponding to each of a plurality of third pixels PX3.

[0155] According to an embodiment, the heating wirings 910 may be driven independently of each other. The heating wirings 910 may be provided around the openings OP, respectively, and may be electrically connected to the first electrode ANE (eg, see FIG. 1 ) through the contact holes CT910 penetrating the pixel defining layer PDL. Figure 6 ). For example, the first heating wiring 911 surrounding the first opening 901 may be electrically connected to the first electrode ANE of the first pixel PX1 through the first contact hole CT911. The second heating wiring 912 surrounding the second opening 902 may be electrically connected to the first electrode ANE of the second pixel PX2 through the second contact hole CT912. The contact hole CT910 may be provided in a region surrounding each opening OP, and the position of the contact hole CT910 may not be limited to the example shown.

[0156] Although not shown, each heating wiring 910 may form a current path by being electrically connected to the ground via a dummy contact hole (not shown). Figure 5 ) is input to each heating wiring 910 with a Joule heating voltage VJH (see Figure 5 ) can form a current path that flows to the outside through the dummy contact hole. To this end, the present disclosure may further include a dummy contact hole (not shown) and a ground connection electrode (not shown) that connects the ground wiring (not shown) and the heating wiring 910 via the dummy contact hole.

[0157] Fig.10 It is schematically shown Fig. 9 , a cross-sectional view of the cross-sectional structure of adjacent pixels (eg, a first pixel PX1 and a second pixel PX2) shown in FIG. Fig.10 It can be along Fig. 9 1 is a cross-sectional view of the wiring layer 602 and the light emitting element layer 603 of the display panel 110 taken along line AA′.

[0158] Reference Fig.10, the pixel defining layer PDL may be disposed on the wiring layer 602 to separate adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). In the example shown, the pixel defining layer PDL may separate the first pixel PX1 and the second pixel PX2 adjacent to each other. For example, the first electrode ANE of the first pixel PX1 may be disposed in the first opening 901 of the pixel defining layer PDL, and the first electrode ANE of the second pixel PX2 may be disposed in the second opening 902. The pixel defining layer PDL may be disposed between the first opening 901 and the second opening 902.

[0159] The middle layer ML can be formed at the opening OP of the adjacent pixel (see Fig. 9 The intermediate layer ML is disposed on the first electrode ANE in the opening OP of the adjacent pixel (for example, the first opening 901 of the first pixel PX1 and the second opening 902 of the second pixel PX2). The intermediate layer ML disposed on the first electrode ANE in the opening OP of the adjacent pixel (for example, the first opening 901 of the first pixel PX1 and the second opening 902 of the second pixel PX2) may extend to the upper surface of the pixel defining layer PDL, but the intermediate layer ML may be electrically disconnected from each other on the pixel defining layer PDL, on the heating wiring 910 and / or around the heating wiring 910 on the pixel defining layer PDL. The intermediate layer ML commonly covers the first electrode ANE in the opening OP of the adjacent pixel (for example, the first opening 901 of the first pixel PX1 and the second opening 902 of the second pixel PX2) and may extend to the upper surface of the pixel defining layer PDL, but the intermediate layer ML may be electrically disconnected on the pixel defining layer PDL between the adjacent pixels (for example, the first pixel PX1 and the second pixel PX2) by the heating wiring 910.

[0160] The electrical disconnection of the middle layer ML described in the present disclosure can be explained as follows. The middle layer ML may include Figure 7 and Figure 8 The plurality of layers described above, and all the layers may be electrically disconnected on the heating wiring 910 (or around the heating wiring 910). However, the present disclosure may not be limited thereto. For example, at least some of the conductive layers among the plurality of layers included in the middle layer ML may be electrically disconnected on the heating wiring 910 (or around the heating wiring 910). At least some of the conductive layers may include Figure 7 At least one of the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL, the charge generation layer CGL and the P-type doped hole injection layer (P-type doped layer) PHIL shown in FIG.

[0161] The second electrode CAE may be disposed on the middle layer ML in the opening OP of the adjacent pixel (e.g., the first opening 901 of the first pixel PX1 and the second opening 902 of the second pixel PX2). The second electrode CAE disposed on the middle layer ML in the opening OP of the adjacent pixel (e.g., the first opening 901 of the first pixel PX1 and the second opening 902 of the second pixel PX2) may extend onto the pixel defining layer PDL to cover the middle layer ML and the heating wiring 910 exposed during the process by the electrical disconnection of the middle layer ML. Therefore, the second electrode CAE may be continuous while covering the middle layer ML in the opening OP of the pixel defining layer PDL and covering the heating wiring 910 and the middle layer ML between the adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2).

[0162] As described above, the second electrode CAE may be commonly provided in a plurality of pixels PX and may be continuously electrically connected between adjacent pixels (eg, the first pixel PX1 and the second pixel PX2). Fig. 9 ), but the adjacent pixels (eg, the first pixel PX1 and the second pixel PX2) may be electrically disconnected by the heating wiring 910.

[0163] The continuous electrical connection of the second electrode CAE and the electrical disconnection of the middle layer ML will now be described in more detail.

[0164] According to an embodiment, a heating wiring 910 surrounding each of a plurality of openings OP (e.g., a first opening 901 and a second opening 902) may be disposed on a pixel defining layer PDL disposed between adjacent pixels (e.g., a first pixel PX1 and a second pixel PX2). A first portion ML1 of the middle layer ML and a first portion CAE1 of the second electrode CAE covering the first portion ML1 of the middle layer ML may be disposed on the pixel defining layer PDL on which the heating wiring 910 is disposed. Here, the first portion ML1 of the middle layer ML may be electrically disconnected from a second portion ML2 of the middle layer ML disposed in the opening OP (e.g., the first opening 901 and the second opening 902) of the pixel defining layer PDL around the heating wiring 910. On the other hand, the first portion CAE1 of the second electrode CAE may be continuously electrically connected to the second portion CAE2 without being electrically disconnected from a second portion CAE2 of the second electrode CAE disposed in the opening OP (e.g., the first opening 901 and the second opening 902) of the pixel defining layer PDL near the heating wiring 910. Here, the second portion CAE2 of the second electrode CAE disposed in the opening OP (eg, the first and second openings 901 and 902 ) may be a portion covering the second portion ML2 of the middle layer ML disposed in the opening OP (eg, the first and second openings 901 and 902 ).

[0165] Since the heating wiring 910 surrounds each of the plurality of openings OP (e.g., the first opening 901 and the second opening 902) of the pixel defining layer PDL, a pair of heating wirings 911 and 912 can be arranged to be spaced apart from each other on the pixel defining layer PDL disposed between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). For example, the first heating wiring 911 surrounding the first opening 901 of the first pixel PX1 and the second heating wiring 912 surrounding the second opening 902 of the second pixel PX2 can be arranged on the pixel defining layer PDL disposed between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). The first heating wiring 911 and the second heating wiring 912 can be spaced apart by a distance (e.g., a predetermined or optional distance) on the pixel defining layer PDL disposed between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the intermediate layer ML on the pixel defining layer PDL, which can be electrically disconnected from the intermediate layer ML in the opening OP, can be substantially arranged between the first heating wiring 911 and the second heating wiring 912. For example, the first portion ML1 of the middle layer ML may be electrically disconnected from the second portion ML2 of the middle layer ML disposed in the opening OP (eg, the first and second openings 901 and 902 ) of the pixel defining layer PDL and may be disposed between the first and second heating wirings 911 and 912 .

[0166] According to the embodiment, the heating voltage supply wiring VHL (see Figure 5 ) can independently drive the first heating wiring 911 and the second heating wiring 912 surrounding the adjacent pixels PX1 and PX2, respectively. To this end, the heating wiring 910 can be electrically connected to the first electrode ANE of the pixel PX one by one. For example, the first heating wiring 911 surrounding the first pixel PX1 can be electrically connected to the first electrode ANE of the first pixel PX1 through the first connection electrode 921 provided in the first contact hole CT911. The second heating wiring 912 surrounding the second pixel PX2 can be electrically connected to the first electrode ANE of the second pixel PX2 through the second connection electrode 922 provided in the second contact hole CT912.

[0167] According to an embodiment, each of the plurality of first electrodes ANE may include a first portion ANE_P1 covered by a pixel defining layer PDL, and a second portion ANE_P2 extending from the first portion ANE_P1 and disposed in an opening of the pixel defining layer PDL. The first portion ANE_P1 of each of the plurality of first electrodes ANE may be electrically connected to the heating wiring 910 through a connection electrode 920 in the pixel defining layer PDL. The first portion ANE_P1 of each of the plurality of first electrodes ANE in the pixel defining layer PDL may be electrically connected to a wiring layer 602 included in a pixel driving circuit (e.g., Figure 5 A heating transistor (eg, Figure 5 Each of the plurality of first electrodes ANE may receive a Joule heating voltage VJH (see FIG. 1 ) from the heating transistor (or fifth transistor) T5. Figure 5 ), and the received Joule heating voltage VJH can be transmitted to the heating wiring 910 through the connecting electrode 920.

[0168] In order to electrically disconnect the middle layer ML by applying the Joule heating voltage VJH to the heating wiring 910, the heating wiring 910 needs to be heated to a high temperature of about 400°C or higher. To this end, the resistance of the heating wiring 910 may need to be designed to be relatively high. According to an embodiment, the first metal forming the heating wiring 910, the second metal forming the connecting electrode 920, and the third metal forming the first electrode ANE may be different metals. Here, the resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal.

[0169] Fig.11 It shows the manufacturing Fig. 9 Flow chart of the method of displaying panel 110 shown in FIG. Figures 12 to 15 is a diagram showing sequentially the manufacturing process of the display panel 110 according to the embodiment (see Fig. 9 ) is a schematic cross-sectional view of the method.

[0170] Now refer to Figures 11 to 15 Combined with Figures 1 to 10 A method of manufacturing the display panel 110 according to the embodiment is described. The following description may be about only some of the multiple processes of manufacturing the display panel 110, and the process for forming the elements described in the present disclosure may be additionally performed before or after each operation described below. The process of manufacturing the display panel 110 may be additionally performed before or after each operation described below.

[0171] Reference Fig.11 In operation 1110, a driving element layer 601 may be formed on the substrate 200. The driving element layer 601 may include a reference Figure 6 The driving element layer 601 may include a display driving circuit 210 (see Figure 2 ) and pixel driving circuit PC.

[0172] Reference Fig.11 In operation 1120, a wiring layer 602 may be formed on the driving element layer 601. The wiring layer 602 may include insulating layers VIA sequentially stacked on each other and on the driving element layer 601, connection electrodes CE at least partially penetrating the insulating layers VIA, and a plurality of wirings.

[0173] Reference Fig.11 In operation 1130, a first electrode ANE of each pixel (e.g., a first pixel PX1 or a second pixel PX2) and a pixel defining layer PDL defining the pixel may be formed on the wiring layer 602. A portion of each first electrode ANE (i.e., a second portion ANE_P2) may be exposed during a process of forming an opening OP in the pixel defining layer PDL. Both ends of each first electrode ANE (i.e., the first portion ANE_P1) may be covered by the pixel defining layer PDL.

[0174] Reference Fig.11 and Fig.12 , in operation 1140, a contact hole CT910 penetrating the pixel defining layer PDL may be formed, and a connection electrode 920 electrically connected to the first electrode ANE may be formed by filling the contact hole CT910. Then, a heating wiring 910 may be formed on the pixel defining layer PDL to cover the connection electrode 920 and surround each opening OP of the pixel defining layer PDL. Here, the first metal forming the heating wiring 910, the second metal forming the connection electrode 920, and the third metal forming the first electrode ANE may be different metals. The resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal.

[0175] Reference Fig.11 and Fig.13 In operation 1150, an intermediate layer ML may be deposited. For example, by using an opening mask (not shown), the intermediate layer ML may be deposited not only in the opening OP of the pixel defining layer PDL but also on the pixel defining layer PDL between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the intermediate layer ML may cover the first electrode ANE in each opening OP of the pixel defining layer PDL and the heating wiring 910 disposed on the pixel defining layer PDL.

[0176] Reference Fig.11 and Fig.14In operation 1160, all or at least a portion of the intermediate layer ML disposed between adjacent pixels (eg, the first pixel PX1 and the second pixel PX2) may be removed using the heating wiring 910. To this end, a heating transistor (eg, Figure 5 The fifth transistor T5 of the first electrode ANE may apply a Joule heating voltage VJH to the first electrode ANE, and the Joule heating voltage VJH applied to the first electrode ANE may be transmitted to the heating wiring 910 through the connection electrode 920. The heating wiring 910 may be heated to a high temperature of about 400° C. or higher by the received Joule heating voltage VJH. Due to the high temperature of the heating wiring 910, all or at least a portion of the intermediate layer ML deposited on the heating wire 910 may be removed.

[0177] Reference Fig.11 and Fig.15 , in operation 1170, the second electrode CAE may be deposited. For example, by using an opening mask, the second electrode CAE may be deposited not only in the opening OP of the pixel defining layer PDL, but also on the pixel defining layer PDL disposed between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the second electrode CAE may cover the middle layer ML in each opening OP of the pixel defining layer PDL, and cover the middle layer ML and the heating wiring 910 disposed on the pixel defining layer PDL.

[0178] In reference Figures 11 to 15 In the method of manufacturing the display panel 110 described above, a process of removing all or part of the middle layer ML using the heating wiring 910 may be performed before the operation of depositing the second electrode CAE. However, the present disclosure may not be limited thereto. For example, a process of removing all or part of the middle layer ML using the heating wiring 910 may also be performed after the operation of depositing the second electrode CAE.

[0179] A method of performing a process of removing all or part of the middle layer ML using the heating wiring 910 after the operation of depositing the second electrode CAE, and the display panel 110 manufactured using the method will now be described.

[0180] Fig.16 Shows Fig. 9 The heating wiring 910 shown in FIG. 1 may include an embodiment of an open slit area OA in a specific lateral direction of each pixel PX. Fig.16 In the following description of the embodiment of Fig. 9 The repeated description of the embodiment of Fig.16 Examples and Fig. 9 The differences between the embodiments.

[0181] Fig.16Examples and Fig. 9 The embodiment of the present invention is different in that the heating wiring 910 may include an open slit area OA, and not completely surround each opening OP of the pixel defining layer PDL. For example, in the normal direction DR3 (eg, see FIG. 2 ) perpendicular to the upper surface of the substrate 200, the heating wiring 910 may include an open slit area OA, and may not completely surround each opening OP of the pixel defining layer PDL. Figure 1 ), the heating wiring 910 may surround each opening OP of the pixel defining layer PDL, but may include an open slit area OA that is open in a specific lateral direction. In the example shown, the open slit area OA may be in a first lateral direction (e.g., Fig.16 The upper side of the structure is positioned in the embodiment of the present invention, but the present disclosure may not be limited to this.

[0182] According to the embodiment, the open slit area OA may be defined as an area where the heating wiring 910 may not be disposed. Since the heating wiring 910 may not be disposed in the open slit area OA, the light emitting element LEL (see Figure 6 ) of the middle layer M (see Figure 6 ) and the second electrode CAE (see Figure 6 ) can be continuous in the open slit area OA without being electrically disconnected. For example, the intermediate layer ML positioned outside each heating wiring 910 can be electrically connected to the intermediate layer ML positioned inside each heating wiring 910 (e.g., each opening OP of the pixel defining layer PDL) through the open slit area OA. Similarly, the second electrode CAE positioned outside each heating wiring 910 can be electrically connected to the second electrode CAE positioned inside each heating wiring 910 (e.g., each opening OP of the pixel defining layer PDL) through the open slit area OA. Therefore, the intermediate layer ML and the second electrode CAE can be continuous in the vicinity of the open slit area OA without being electrically disconnected.

[0183] Fig.17 It shows the manufacturing Fig.16 Flow chart of the method of displaying panel 110 shown in FIG. Figures 18 to 21 is a diagram sequentially showing the manufacturing process of the display panel 110 according to the embodiment (see Fig.16 ) is a schematic cross-sectional view of the method.

[0184] Now refer to Figures 17 to 21 Combined with Figures 1 to 10 A method of manufacturing the display panel 110 according to the embodiment is described. The following description may be only about some processes of manufacturing the display panel 110, and the process for forming the elements described in the present disclosure may be additionally performed before or after each operation described below. The process of manufacturing the display panel 110 may be additionally performed before or after each operation described below.

[0185] Reference Fig.17In operation 1710, a driving element layer 601 may be formed on the substrate 200. The driving element layer 601 may include a reference Figure 6 The driving element layer 601 may include a display driving circuit 210 (see Figure 2 ) and pixel driving circuit PC. Operation 1710 can be compared with reference Fig.11 The described operations 1110 are substantially the same.

[0186] Reference Fig.17 In operation 1720, a wiring layer 602 may be formed on the driving element layer 601. The wiring layer 602 may include an insulating layer VIA sequentially stacked on the driving element layer 601, a connection electrode CE at least partially penetrating the insulating layer VIA, and a plurality of wirings.

[0187] Reference Fig.17 In operation 1730, a first electrode of each pixel PX and a pixel defining layer PDL defining the pixel PX may be formed on the wiring layer 602. A portion of each first electrode ANE (i.e., the second portion ANE_P2) may be exposed in a process of forming an opening OP in the pixel defining layer PDL. Both ends of each first electrode ANE (i.e., the first portion ANE_P1) may be covered by the pixel defining layer PDL. Operation 1730 may be similar to the reference numeral 1730. Fig.11 The described operations 1130 are substantially the same.

[0188] Reference Fig.17 and Fig.18 , in operation 1740, a contact hole CT910 penetrating the pixel defining layer PDL may be formed, and a connection electrode 920 electrically connected to the first electrode ANE may be formed by filling the contact hole CT910. Then, a heating wiring 910 may be formed on the pixel defining layer PDL to cover the connection electrode 920 and surround each opening OP of the pixel defining layer PDL. Here, the first metal forming the heating wiring 910, the second metal forming the connection electrode 920, and the third metal forming the first electrode ANE may be different metals. The resistance of the first metal may be greater than the resistance of the second metal, and the resistance of the second metal may be greater than the resistance of the third metal. In operation 1740, the heating wiring 910 may be formed to have an open slit area OA without completely surrounding each opening OP of the pixel defining layer PDL.

[0189] Reference Fig.17 and Fig.19, in operation 1750, an intermediate layer ML may be deposited. For example, by using an opening mask (not shown), the intermediate layer ML may be deposited not only in the opening OP of the pixel defining layer PDL but also on the pixel defining layer PDL between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the intermediate layer ML may cover the first electrode ANE in each opening OP of the pixel defining layer PDL and the heating wiring 910 disposed on the pixel defining layer PDL. Operation 1750 may be similar to the reference 1750. Fig.11 The described operations 1150 are substantially the same.

[0190] Reference Fig.17 and Fig. 20 , in operation 1760, the second electrode CAE may be deposited. For example, by using an opening mask (not shown), the second electrode CAE may be deposited not only in the opening OP of the pixel defining layer PDL, but also on the pixel defining layer PDL disposed between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2). Therefore, the second electrode CAE may cover the middle layer ML in each opening OP of the pixel defining layer PDL, and cover the middle layer ML disposed on the pixel defining layer PDL.

[0191] Reference Fig.17 and Fig.21 In operation 1770, the middle layer ML and the second electrode CAE disposed between adjacent pixels (e.g., the first pixel PX1 and the second pixel PX2) may be removed in whole or in part using the heating wiring 910. To this end, the heating transistor (e.g., Figure 5 The fifth transistor T5) can apply a Joule heating voltage VJH to the first electrode ANE, and the Joule heating voltage VJH applied to the first electrode ANE can be transmitted to the heating wiring 910 through the connecting electrode 920. The received Joule heating voltage VJH can be heated to a high temperature of about 400°C or higher through the heating wiring 910. Due to the high temperature of the heating wiring 910, the intermediate layer ML and the second electrode CAE deposited on the heating wiring 910 can be removed. Therefore, the intermediate layer ML and the second electrode CAE can be electrically disconnected around the heating wiring 910. The second electrode CAE can be electrically disconnected around the heating wiring 910, but can be electrically continuous in the open slit area OA. Thus, the second electrode CAE includes a first portion CAE1 located on the pixel defining layer PDL and a second portion CAE2 located in the opening OP.

[0192] Fig. 22 is an example view of a wearable device including a display device according to an embodiment.

[0193] According to the display device 10 (see Figure 1 ) may be a display device 2260 included in a mobile electronic device. The display device 10 according to an embodiment may be included in a wearable device, which may be developed in the form of glasses or a helmet and forms a focus at a shorter distance from the user's eyes. For example, the wearable device may be an HMD or augmented reality (AR) glasses. Such a wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0194] Fig. 22 FIG. 2 shows a VR device 2200 to which a display device 2260 according to an embodiment has been applied. Here, the display device 2260 may be, for example, a device including the above-mentioned Figures 1 to 21 A display device 10 of an element.

[0195] Reference Fig. 22 The VR device 2200 according to the embodiment may be an AR device in the form of glasses. The VR device 2200 according to the embodiment may include a display device 2260, a left lens 2211, a right lens 2212, a support frame 2220, glasses frame legs 2231 and 2232, a reflective member 2240, and a receiving part 2250.

[0196] The receiving part 2250 may receive the display device 2260 and the reflective member 2240. The image displayed in the display device 2260 may be reflected by the reflective member 2240 and provided to the right eye of the user through the right lens 2212. Therefore, the user may observe the VR image displayed in the display device 2260 through the right eye.

[0197] Although the receiving member 2250 may be disposed Fig. 22 2200, but the present disclosure may not be limited thereto. For example, the accommodating part 2250 may also be disposed at the left end of the supporting frame 2220. The image displayed in the display device 2260 may be reflected by the reflective member 2240 and provided to the left eye of the user through the left lens 2211. Therefore, the user can observe the VR image displayed in the display device 2260 through the left eye. The accommodating part 2250 may be disposed at the right end and the left end of the supporting frame 2220. The user can observe the VR image displayed in the display device 2260 through both the left eye and the right eye.

[0198] In the display device and the mobile electronic device including the display device according to the embodiment, at least a portion of the intermediate layer disposed between the pixel electrode and the common electrode may be electrically disconnected between adjacent pixels, thereby preventing leakage current and color crosstalk.

[0199] However, the effects of the present disclosure may not be limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

[0200] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the invention. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, wherein: The display device comprises: substrate; a driving element layer, disposed on the substrate; and A light emitting element layer is disposed on the driving element layer, Wherein, the light emitting element layer comprises: A pixel defining layer including a plurality of openings respectively defining a plurality of pixels; a first electrode disposed in each of the plurality of pixels and including a first portion covered by the pixel defining layer and a second portion extending from the first portion and corresponding to one of the plurality of openings; a heating wiring disposed on an upper surface of the pixel defining layer to surround at least a portion of each of the plurality of openings; a connecting electrode, connecting the heating wiring and the first portion of the first electrode through a contact hole penetrating the pixel defining layer; an intermediate layer covering the second portion of the first electrode and the pixel defining layer provided between adjacent pixels among the plurality of pixels, the intermediate layer including an electrically disconnected portion corresponding to the heating wiring in a plan view; and A second electrode, which is continuous and covers a portion of the intermediate layer disposed in a corresponding one of the plurality of openings in each of the plurality of pixels, and covers a portion of the intermediate layer and the heating wiring disposed between the adjacent pixels among the plurality of pixels.

2. The display device according to claim 1, wherein: The driving element layer includes a Joule heating driver disposed to correspond to a non-display area of ​​the substrate and configured to sequentially supply a heating scanning signal to a plurality of heating scanning wirings disposed in a display area of ​​the substrate.

3. The display device according to claim 2, wherein: The driving element layer also includes a switching circuit, which is arranged to correspond to the non-display area of ​​the substrate, and the switching circuit is configured to supply a Joule heating voltage to a plurality of heating voltage supply wirings arranged in the display area of ​​the substrate in synchronization with the timing of the Joule heating driver outputting the heating scanning signal.

4. The display device according to claim 3, wherein: The switch circuit includes a plurality of switch transistors electrically connected one-to-one to the plurality of heating voltage supply wirings, and Each of the plurality of switching transistors is turned on in response to a heating control signal, and is configured to output the Joule heating voltage when turned on.

5. The display device according to claim 4, wherein: The heating control signal is synchronized with the heating scanning signal.

6. The display device according to claim 3, wherein: The plurality of heating voltage supply wirings cross the plurality of heating scanning wirings.

7. The display device according to claim 3, wherein: The driving element layer further includes a pixel driving circuit, which is disposed in the display area of ​​the substrate to correspond to each of the plurality of pixels, and The pixel driving circuit comprises: a driving transistor that supplies a designated driving current to a first node electrically connected to the first electrode based on a data signal input from a data line; and A heating transistor is turned on in response to the heating scan signal input from the plurality of heating scan wirings, and supplies the Joule heating voltage input from the plurality of heating voltage supply wirings to the first node when being turned on.

8. The display device according to claim 7, wherein: The heating wiring is configured to receive the Joule heating voltage via the first electrode and the connection electrode.

9. The display device according to claim 8, wherein: The resistance of the heating wiring is larger than each of the resistance of the first electrode and the resistance of the connection electrode.

10. The display device according to claim 1, wherein: The intermediate layer includes at least one conductive layer including a portion electrically disconnected at a position corresponding to the heating wiring, and The at least one conductive layer includes a layer selected from the group consisting of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a P-type doping layer.

11. The display device according to claim 1, wherein: In a plan view, the heating wiring surrounds each of the plurality of openings in the pixel defining layer, and The heating wiring includes an open slit region that is open in a specific transverse direction.

12. The display device according to claim 11, wherein: The intermediate layer and the second electrode are continuous without being electrically disconnected at a position corresponding to the open slit region.

13. A mobile electronic device comprising a display device, wherein: The display device comprises: substrate; a driving element layer, disposed on the substrate; and A light emitting element layer is disposed on the driving element layer, Wherein, the light emitting element layer comprises: A pixel defining layer including a plurality of openings respectively defining a plurality of pixels; a first electrode disposed in each of the plurality of pixels and including a first portion covered by the pixel defining layer and a second portion extending from the first portion and corresponding to one of the plurality of openings; a heating wiring disposed on an upper surface of the pixel defining layer to surround at least a portion of each of the plurality of openings; a connecting electrode, connecting the heating wiring and the first portion of the first electrode through a contact hole penetrating the pixel defining layer; an intermediate layer covering the second portion of the first electrode and the pixel defining layer provided between adjacent pixels among the plurality of pixels, the intermediate layer including an electrically disconnected portion corresponding to the heating wiring in a plan view; and A second electrode, which is continuous and covers a portion of the intermediate layer disposed in a corresponding one of the plurality of openings in each of the plurality of pixels, and covers a portion of the intermediate layer and the heating wiring disposed between the adjacent pixels among the plurality of pixels.

14. The mobile electronic device according to claim 13, wherein: The driving element layer includes a Joule heating driver disposed to correspond to a non-display area of ​​the substrate and configured to sequentially supply a heating scanning signal to a plurality of heating scanning wirings disposed in a display area of ​​the substrate.

15. The mobile electronic device according to claim 14, wherein: The driving element layer also includes a switching circuit, which is arranged to correspond to the non-display area of ​​the substrate and is configured to supply a Joule heating voltage to a plurality of heating voltage supply wirings arranged in the display area of ​​the substrate in synchronization with the timing of the Joule heating driver outputting the heating scanning signal.

16. The mobile electronic device according to claim 15, wherein The switch circuit includes a plurality of switch transistors electrically connected one-to-one to the plurality of heating voltage supply wirings, and Each of the plurality of switching transistors is turned on in response to a heating control signal, and is configured to output the Joule heating voltage when turned on.

17. The mobile electronic device according to claim 16, wherein: The heating control signal is synchronized with the heating scanning signal.

18. The mobile electronic device according to claim 15, wherein: The plurality of heating voltage supply wirings cross the plurality of heating scanning wirings.

19. The mobile electronic device according to claim 15, wherein: The driving element layer further includes a pixel driving circuit, which is disposed in the display area of ​​the substrate to correspond to each of the plurality of pixels, and The pixel driving circuit comprises: a driving transistor that supplies a designated driving current to a first node electrically connected to the first electrode based on a data signal input from a data line; and A heating transistor is turned on in response to the heating scan signal input from the plurality of heating scan wirings, and supplies the Joule heating voltage input from the plurality of heating voltage supply wirings to the first node when being turned on.

20. The mobile electronic device according to claim 19, wherein: The heating wiring is configured to receive the Joule heating voltage via the first electrode and the connection electrode.

Images