Pixel circuit, display device and driving method

Abstract

The invention discloses a pixel circuit, a display device and a driving method. The pixel circuit comprises a light emitting device (L); a driving transistor (M0) configured to generate a driving current for driving the light emitting device (L) to emit light according to the data voltage; the light-emitting control circuit (30) is coupled with the driving transistor (M0) and is configured to respond to the effective level of a light-emitting control signal end (EM), provide the driving current generated by the driving transistor (M0) for the light-emitting device (L) and drive the light-emitting device (L) to emit light; the data write-in circuit (10) is coupled with the first pole of the driving transistor (M0) and is configured to work in response to a plurality of effective levels (YX1 and YX2) appearing at intervals of the first scanning signal end (GA); and the threshold compensation circuit (20) is coupled with the driving transistor (M0) and is configured to input the threshold voltage of the driving transistor (M0) into the grid electrode of the driving transistor (M0) in response to the effective level of the compensation control signal end (CF).

Description

Pixel circuit, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display device, and a driving method. Background Art

[0002] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) offer advantages such as self-luminescence and low energy consumption, making them a hot topic in current display device application research. Display devices typically use pixel circuits to drive the light-emitting devices.

[0003] Summary of the Invention

[0004] The pixel circuit provided by the embodiment of the present disclosure includes:

[0005] Light-emitting devices;

[0006] a driving transistor configured to generate a driving current for driving the light emitting device to emit light according to a data voltage;

[0007] a light emitting control circuit coupled to the driving transistor and configured to, in response to an active level of a light emitting control signal terminal, provide the driving current generated by the driving transistor to the light emitting device to drive the light emitting device to emit light;

[0008] a data writing circuit coupled to the first electrode of the driving transistor and configured to operate in response to a plurality of valid levels of the first scanning signal terminal appearing at intervals in a data refresh phase;

[0009] a threshold compensation circuit coupled to the driving transistor and configured to input a threshold voltage of the driving transistor into a gate of the driving transistor in response to an active level of a compensation control signal terminal;

[0010] In which, in a data refresh phase, the time period of the invalid level of the light-emitting control signal end includes the time period of the valid level of the compensation control signal end and the time period of the valid level of the first scanning signal end, and the valid level in the first scanning signal end includes at least one first valid level and at least one second valid level, and the time period of the valid level of the compensation control signal end includes the time period of the first valid level.

[0011] In some possible implementations, in a data refresh phase, the at least one second effective level time period occurs after the effective level time period of the compensation control signal terminal.

[0012] In some possible implementations, in a data refresh phase, the at least one second effective level time period occurs before the effective level time period of the compensation control signal terminal.

[0013] In some possible implementations, the pixel circuit further includes: a first initialization circuit coupled to the first electrode of the driving transistor;

[0014] The first initialization circuit is configured to provide a signal from the first initialization signal terminal to the first electrode of the driving transistor in response to at least one valid level of the first reset control signal terminal in a data refresh phase;

[0015] In which, in a data refresh phase, the time period of the invalid level of the light-emitting control signal end also includes the time period of the valid level of the first reset control signal end; and the time period of the valid level of the first reset control signal end and the time periods of multiple valid levels in the first scanning signal end do not have overlapping durations.

[0016] In some possible implementations, the effective level of the first reset control signal terminal includes at least one third effective level;

[0017] In a data refresh phase, the at least one third active level time period occurs after a plurality of active level time periods at the first scan signal terminal.

[0018] In some possible implementations, the effective level of the first reset control signal terminal includes at least one fourth effective level;

[0019] In a data refresh phase, the effective level time period of the compensation control signal terminal includes the fourth effective level time period, and the fourth effective level time period occurs before the first effective level time period of the first scan signal terminal.

[0020] In some possible implementations, the pixel circuit further includes: a second initialization circuit, the second initialization circuit being coupled to the second electrode of the driving transistor;

[0021] The second initialization circuit is configured to provide a signal from the second initialization signal terminal to the second electrode of the driving transistor in response to at least one valid level of the second reset control signal terminal;

[0022] In which, in a data refresh phase, the time period of the invalid level of the light-emitting control signal terminal includes the time period of the valid level of the second reset control signal terminal; and the time period of the valid level of the second reset control signal terminal and the time periods of multiple valid levels in the first scanning signal terminal do not have overlapping durations.

[0023] In some possible implementations, the effective level of the second reset control signal terminal includes at least one fifth effective level;

[0024] In a data refresh phase, the time period of the effective level of the compensation control signal terminal includes the time period of the at least one fifth effective level, and the time period of the at least one fifth effective level occurs before the time period of the at least one first effective level of the first scan signal terminal.

[0025] In some possible implementations, in a data refresh phase, the time period of the fifth effective level occurs before or after the time period of the fourth effective level of the first reset control signal terminal.

[0026] In some possible implementations, the effective level of the second reset control signal terminal includes at least one sixth effective level;

[0027] In a data refresh phase, the at least one sixth effective level time period occurs after or before the effective level time period of the compensation control signal terminal.

[0028] In some possible implementations, the pixel circuit further includes: a third initialization circuit, the third initialization circuit being coupled to the light-emitting device;

[0029] The third initialization circuit is configured to provide a signal of a third initialization signal terminal to the light emitting device in response to an active level of a third reset control signal terminal.

[0030] In some possible implementations, one of the compensation control signal terminal, the first scan signal terminal, the first reset control signal terminal, and the second reset control signal terminal and the third reset control signal terminal are the same signal terminal.

[0031] In some possible implementations, a display frame corresponding to the pixel circuit includes a refresh subframe and a hold subframe, and the working process of the pixel circuit in the refresh subframe is the working process of the pixel circuit in one of the data refresh phases.

[0032] In some possible implementations, the compensation control signal terminal is at an invalid level in the holding subframe;

[0033] The light emitting control signal terminal has an invalid level and a valid level in at least one of the holding subframes;

[0034] The first scanning signal terminal has an inactive level and an active level in at least one of the holding subframes.

[0035] In some possible implementations, the first reset control signal terminal has an invalid level and a valid level in at least one of the holding subframes;

[0036] Alternatively, the first reset control signal terminal is at an invalid level in the holding subframe.

[0037] In some possible implementations, the second reset control signal terminal has an invalid level and a valid level in at least one of the holding subframes;

[0038] Alternatively, the second reset control signal terminal is at an invalid level in the holding subframe.

[0039] In some possible implementations, the third reset control signal terminal has an invalid level and a valid level in at least one of the holding subframes;

[0040] Alternatively, the third reset control signal terminal is at an invalid level in the holding subframe.

[0041] In some possible implementations, the data writing circuit includes: a first transistor; a gate of the first transistor is coupled to the first scan signal terminal, a first electrode of the first transistor is coupled to the data signal terminal, and a second electrode of the first transistor is coupled to the first electrode of the driving transistor;

[0042] The threshold compensation circuit includes: a second transistor and a storage capacitor; a gate of the second transistor is coupled to the compensation control signal terminal, a first electrode of the second transistor is coupled to the gate of the driving transistor, and a second electrode of the second transistor is coupled to the second electrode of the driving transistor; a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the first power supply terminal;

[0043] The light emitting control circuit includes: a third transistor and a fourth transistor; a gate of the third transistor is coupled to the light emitting control signal terminal, a first electrode of the third transistor is coupled to the first power supply terminal, a second electrode of the third transistor is coupled to the first electrode of the driving transistor, a gate of the fourth transistor is coupled to the light emitting control signal terminal, a first electrode of the fourth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the light emitting device;

[0044] The first initialization circuit includes: a fifth transistor; a gate of the fifth transistor is coupled to the first reset control signal terminal, a first electrode of the fifth transistor is coupled to the first initialization signal terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the driving transistor;

[0045] A second initialization circuit includes a sixth transistor; a gate of the sixth transistor is coupled to the second reset control signal terminal, a first electrode of the sixth transistor is coupled to the second initialization signal terminal, and a second electrode of the sixth transistor is coupled to the second electrode of the driving transistor;

[0046] The third initialization circuit includes a seventh transistor; a gate of the seventh transistor is coupled to the third reset control signal terminal, a first electrode of the seventh transistor is coupled to the third initialization signal terminal, and a second electrode of the seventh transistor is coupled to the light-emitting device.

[0047] The present disclosure also provides a pixel circuit, including:

[0048] Light-emitting devices;

[0049] a driving transistor configured to generate a driving current for driving the light emitting device to emit light according to a data voltage;

[0050] a light emitting control circuit coupled to the driving transistor and configured to, in response to an active level of a light emitting control signal terminal, provide the driving current generated by the driving transistor to the light emitting device to drive the light emitting device to emit light;

[0051] a functional circuit coupled to the driving transistor and configured to operate in response to a plurality of active levels of the second scanning signal terminal appearing at intervals in a data refresh phase;

[0052] a threshold compensation circuit coupled to the driving transistor and configured to input a threshold voltage of the driving transistor into a gate of the driving transistor in response to an active level of a compensation control signal terminal;

[0053] In which, in a data refresh phase, the time period of the invalid level of the light-emitting control signal terminal includes the time period of the valid level of the compensation control signal terminal and the time period of the valid level of the second scanning signal terminal, and the valid level in the second scanning signal terminal includes at least one seventh valid level and at least one eighth valid level, and the time period of the valid level of the compensation control signal terminal does not overlap with the time period of at least one eighth valid level.

[0054] In some possible implementations, the time period of the effective level of the compensation control signal terminal includes the time period of the seventh effective level.

[0055] In some possible implementations, in a data refresh phase, the at least one eighth effective level time period occurs before or after the effective level time period of the compensation control signal terminal.

[0056] The embodiment of the present disclosure also provides a display panel, comprising: a plurality of sub-pixels;

[0057] Each of the plurality of sub-pixels includes the aforementioned pixel path.

[0058] In some possible implementations, in a data refresh phase, the multiple valid levels at the first scan signal terminal of the pixel circuit include at least one second valid level;

[0059] When the time period of at least one of the at least one second effective level occurs after the time period of the effective level of the compensation control signal end, the time period of the second effective level corresponding to the pixel circuit in the nth row of sub-pixels overlaps with the time period of the first effective level corresponding to the pixel circuit in the n+mth row of sub-pixels, where n is an integer and n>0, and m is an integer and m>0.

[0060] In some possible implementations, in a data refresh phase, the multiple valid levels at the first scan signal terminal of the pixel circuit include at least one second valid level;

[0061] In one of the data refresh phases, when the time period of at least one of the at least one second effective levels occurs before the time period of the effective level of the compensation control signal end, the time period of the second effective level corresponding to the pixel circuit in the qth row of sub-pixels overlaps with the time period of the first effective level corresponding to the pixel circuit in the qkth row of sub-pixels, where q is an integer and q>0, and k is an integer and k>0.

[0062] In some possible implementations, the time period of the effective level of the compensation control signal terminal of the pixel circuit in the sth row of sub-pixels includes the time period of the first effective level corresponding to the pixel circuits in the sth row to the sath row, a is an integer and a>0.

[0063] In some possible implementations, the time period of the effective level of the compensation control signal terminal of the pixel circuit in the sth row of sub-pixels includes the time period of the first effective level corresponding to the pixel circuit in the sth row to the s+bth row, where b is an integer and b>0.

[0064] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel.

[0065] The embodiment of the present disclosure further provides a driving method for the above-mentioned single-channel pixel, including: a data refresh phase; the data refresh phase includes:

[0066] In the data threshold compensation stage, the data writing circuit provides the data voltage of the data signal terminal to the first electrode of the driving transistor in response to the first valid level of the first scanning signal terminal; the threshold compensation circuit inputs the threshold voltage of the driving transistor to the gate of the driving transistor in response to the valid level of the compensation control signal terminal;

[0067] In a first initialization auxiliary phase, the data writing circuit provides a data voltage at the data signal terminal to the first electrode of the driving transistor in response to the second valid level of the first scanning signal terminal;

[0068] In the light emitting stage, the light emitting control circuit provides the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

[0069] The embodiment of the present disclosure further provides a driving method for the above-mentioned single-channel pixel, including:

[0070] In a second initialization auxiliary phase, the data writing circuit provides a data voltage at the data signal terminal to the first electrode of the driving transistor in response to a third valid level of the first scanning signal terminal;

[0071] In the data threshold compensation stage, the data writing circuit provides the data voltage of the data signal terminal to the first electrode of the driving transistor in response to the first valid level of the first scanning signal terminal; the threshold compensation circuit inputs the threshold voltage of the driving transistor to the gate of the driving transistor in response to the valid level of the compensation control signal terminal;

[0072] In the light emitting stage, the light emitting control circuit provides the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, thereby driving the light emitting device to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0074] FIG2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0075] FIG3 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0076] FIG4 is a flowchart of some driving methods provided by an embodiment of the present disclosure;

[0077] FIG5 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0078] FIG6 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0079] FIG7 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0080] FIG8 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0081] FIG9 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0082] FIG10 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0083] FIG11 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0084] FIG12 is a flowchart of another driving method provided by an embodiment of the present disclosure;

[0085] FIG13 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0086] FIG14 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0087] FIG15 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0088] FIG16 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0089] FIG17 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0090] FIG18 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0091] FIG19 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0092] FIG20 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0093] FIG21 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0094] FIG22 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0095] FIG23a is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0096] FIG23 b is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0097] FIG23c is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0098] FIG23d is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0099] FIG24 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0100] FIG25 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0101] FIG26 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0102] FIG27 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0103] FIG28 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0104] FIG29 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0105] FIG30 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0106] FIG31 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0107] FIG32 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0108] FIG33 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0109] FIG34 is a further signal timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0110] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0111] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0112] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0113] The display device provided by the embodiment of the present disclosure includes: a display panel, the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0114] In the disclosed embodiments, each sub-pixel includes a pixel circuit comprising a driver transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to display images. Due to factors such as process technology and device aging, the threshold voltage Vth of the driver transistor can vary. This causes variations in the current flowing through different light-emitting devices, resulting in uneven display brightness and, consequently, affecting the overall image quality.

[0115] As shown in FIG1 , the pixel circuit provided by the embodiment of the present disclosure includes: a light-emitting device L, a driving transistor M0, a data writing circuit 10, a threshold compensation circuit 20, a light-emitting control circuit 30, a first initialization circuit 40, a second initialization circuit 50, and a third initialization circuit 60. The data writing circuit 10 is coupled to the first electrode of the driving transistor M0, the threshold compensation circuit 20 is coupled to the gate of the driving transistor M0, the second electrode of the driving transistor M0, and the first power supply terminal VDD, the light-emitting control circuit 30 is coupled to the first electrode of the driving transistor M0, the second electrode of the driving transistor M0, the first power supply terminal VDD, and the light-emitting device L, the first initialization circuit 40 is coupled to the first electrode of the driving transistor M0, the second initialization circuit 50 is coupled to the second electrode of the driving transistor M0, and the third initialization circuit 60 is coupled to the light-emitting device L.

[0116] Exemplarily, the driving transistor M0 is configured to generate a driving current that drives the light-emitting device L to emit light based on a data voltage. The data write circuit 10 is configured to operate in response to the active level of the first scan signal terminal GA (e.g., to provide the data voltage of the data signal terminal DA to the first electrode of the driving transistor M0). The threshold compensation circuit 20 is configured to input the threshold voltage of the driving transistor M0 to the gate of the driving transistor M0 in response to the active level of the compensation control signal terminal CF. The first initialization circuit 40 is configured to provide a signal from the first initialization signal terminal VINIT1 to the first electrode of the driving transistor M0 in response to the active level of the first reset control signal terminal RE1. The second initialization circuit 50 is configured to provide a signal from the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0 in response to the active level of the second reset control signal terminal RE2. The third initialization circuit 60 is configured to provide a signal from the third initialization signal terminal VINIT3 to the light-emitting device L in response to the active level of the third reset control signal terminal RE3. The light-emission control circuit 30 is configured to provide the driving current generated by the driving transistor M0 to the light-emitting device L in response to the active level of the light-emission control signal terminal EM, thereby driving the light-emitting device L to emit light.

[0117] The embodiment of the present disclosure provides a pixel circuit, which can avoid the influence of the threshold voltage drift of the driving transistor on the luminescence of the light-emitting device through the mutual cooperation of the light-emitting device, the driving transistor, the data writing circuit, the threshold compensation circuit, the light-emitting control circuit, the first initialization circuit, the second initialization circuit and the third initialization circuit.

[0118] The present disclosure is described in detail below in conjunction with specific embodiments. It should be noted that the embodiments are for better explanation of the present disclosure, but are not intended to limit the present disclosure.

[0119] In the embodiment of the present disclosure, as shown in FIG1 , the driving transistor M0 can be configured as an N-type transistor; wherein the first electrode of the driving transistor M0 can be its source electrode, and the second electrode of the driving transistor M0 can be its drain electrode. Of course, the driving transistor M0 can also be configured as a P-type transistor, which is not limited here.

[0120] In the embodiment of the present disclosure, as shown in Figure 1, the second electrode of the driving transistor M0 is coupled to the anode of the light-emitting device L through the light-emitting control circuit 30, and the cathode of the light-emitting device L is coupled to the second power supply terminal VSS. For example, the light-emitting device L may include at least one of: an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), and a mini light-emitting diode (Mini LED). For example, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In actual applications, the specific structure of the light-emitting device L can be designed and determined according to the actual application environment, and is not limited here.

[0121] In some embodiments of the present disclosure, as shown in Figure 2, the data writing circuit 10 may include: a first transistor M1; the gate of the first transistor M1 is coupled to the first scan signal terminal GA, the first electrode of the first transistor M1 is coupled to the data signal terminal DA, and the second electrode of the first transistor M1 is coupled to the first electrode of the driving transistor M0.

[0122] Exemplarily, the first transistor M1 can be turned on under the control of the active level of the scan signal ga at the first scan signal terminal GA, and turned off under the control of the inactive level of the scan signal ga. Optionally, the first transistor M1 can be an N-type transistor, in which case the active level of the scan signal ga is a high level, and the inactive level of the scan signal ga is a low level. Alternatively, the first transistor M1 can be a P-type transistor, in which case the active level of the scan signal ga is a low level, and the inactive level of the scan signal ga is a high level.

[0123] In some embodiments of the present disclosure, as shown in Figure 2, the threshold compensation circuit 20 may include: a second transistor M2 and a storage capacitor CST; the gate of the second transistor M2 is coupled to the compensation control signal terminal CF, the first electrode of the second transistor M2 is coupled to the gate of the driving transistor M0, and the second electrode of the second transistor M2 is coupled to the second electrode of the driving transistor M0; the first plate of the storage capacitor CST is coupled to the gate of the driving transistor M0, and the second plate of the storage capacitor CST is coupled to the first power supply terminal VDD.

[0124] For example, the second transistor M2 can be turned on under the control of the active level of the compensation control signal cf at the compensation control signal terminal CF, and turned off under the control of the inactive level of the compensation control signal cf. Optionally, the second transistor M2 can be an N-type transistor, in which case the active level of the compensation control signal cf is a high level, and the inactive level of the compensation control signal cf is a low level. Alternatively, the second transistor M2 can be a P-type transistor, in which case the active level of the compensation control signal cf is a low level, and the inactive level of the compensation control signal cf is a high level.

[0125] In some embodiments of the present disclosure, as shown in Figure 2, the light-emitting control circuit 30 includes: a third transistor M3 and a fourth transistor M4; the gate of the third transistor M3 is coupled to the light-emitting control signal terminal EM, the first electrode of the third transistor M3 is coupled to the first power supply terminal VDD, the second electrode of the third transistor M3 is coupled to the first electrode of the driving transistor M0, the gate of the fourth transistor M4 is coupled to the light-emitting control signal terminal EM, the first electrode of the fourth transistor M4 is coupled to the second electrode of the driving transistor M0, and the second electrode of the fourth transistor M4 is coupled to the light-emitting device L.

[0126] For example, the third transistor M3 can be turned on under the control of the active level of the light-emitting control signal em at the light-emitting control signal terminal EM, and turned off under the control of the inactive level of the light-emitting control signal em. Optionally, the third transistor M3 can be an N-type transistor, in which case the active level of the light-emitting control signal em is a high level, and the inactive level of the light-emitting control signal em is a low level. Alternatively, the third transistor M3 can be a P-type transistor, in which case the active level of the light-emitting control signal em is a low level, and the inactive level of the light-emitting control signal em is a high level.

[0127] For example, the fourth transistor M4 can be turned on under the control of the active level of the light-emitting control signal em at the light-emitting control signal terminal EM, and turned off under the control of the inactive level of the light-emitting control signal em. Optionally, the fourth transistor M4 can be an N-type transistor, in which case the active level of the light-emitting control signal em is a high level, and the inactive level of the light-emitting control signal em is a low level. Alternatively, the fourth transistor M4 can be a P-type transistor, in which case the active level of the light-emitting control signal em is a low level, and the inactive level of the light-emitting control signal em is a high level.

[0128] In some embodiments of the present disclosure, as shown in Figure 2, the first initialization circuit 40 includes: a fifth transistor M5; the gate of the fifth transistor M5 is coupled to the first reset control signal terminal RE1, the first electrode of the fifth transistor M5 is coupled to the first initialization signal terminal VINIT1, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the driving transistor M0.

[0129] For example, the fifth transistor M5 can be turned on under the control of the active level of the first reset control signal of the first reset control signal terminal RE1, and turned off under the control of the inactive level of the first reset control signal. Optionally, the fifth transistor M5 can be an N-type transistor, in which case the active level of the first reset control signal is a high level, and the inactive level of the first reset control signal is a low level. Alternatively, the fifth transistor M5 can be a P-type transistor, in which case the active level of the first reset control signal is a low level, and the inactive level of the first reset control signal is a high level.

[0130] In some embodiments of the present disclosure, as shown in Figure 2, the second initialization circuit 50: a sixth transistor M6; the gate of the sixth transistor M6 is coupled to the second reset control signal terminal RE2, the first electrode of the sixth transistor M6 is coupled to the second initialization signal terminal VINIT2, and the second electrode of the sixth transistor M6 is coupled to the second electrode of the driving transistor M0.

[0131] For example, the sixth transistor M6 can be turned on under the control of the active level of the second reset control signal at the second reset control signal terminal RE2, and turned off under the control of the inactive level of the second reset control signal. Optionally, the sixth transistor M6 can be an N-type transistor, in which case the active level of the second reset control signal is a high level, and the inactive level of the second reset control signal is a low level. Alternatively, the sixth transistor M6 can be a P-type transistor, in which case the active level of the second reset control signal is a low level, and the inactive level of the second reset control signal is a high level.

[0132] In some embodiments of the present disclosure, as shown in Figure 2, the third initialization circuit 60: a seventh transistor M7; the gate of the seventh transistor M7 is coupled to the third reset control signal terminal RE3, the first electrode of the seventh transistor M7 is coupled to the third initialization signal terminal VINIT3, and the second electrode of the seventh transistor M7 is coupled to the light-emitting device L.

[0133] For example, the seventh transistor M7 can be turned on under the control of the active level of the third reset control signal at the third reset control signal terminal RE3, and turned off under the control of the inactive level of the third reset control signal. Optionally, the seventh transistor M7 can be an N-type transistor, in which case the active level of the third reset control signal is a high level, and the inactive level of the third reset control signal is a low level. Alternatively, the seventh transistor M7 can be a P-type transistor, in which case the active level of the third reset control signal is a low level, and the inactive level of the third reset control signal is a high level.

[0134] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0135] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0136] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0137] Exemplarily, all transistors may be configured as LTPS transistors.

[0138] Alternatively, all transistors may be configured as oxide-type transistors.

[0139] Alternatively, some transistors may be configured as oxide-type transistors, and the remaining transistors may be configured as LTPS-type transistors. For example, as shown in FIG2 , the second transistor M2 may be an N-type oxide-type transistor, and the remaining transistors may be configured as P-type LTPS-type transistors. This may enable the pixel circuit to implement an LTPO pixel circuit, thereby improving the performance of the pixel circuit and the display effect.

[0140] At present, the display panel can support a variety of refresh frequency (for example, 1Hz, 10Hz, 30Hz, 60Hz, 120Hz) driving modes. When the display panel is in certain static images, it is usually driven by a lower refresh frequency (for example, 60Hz) to reduce power consumption. Moreover, the driving method of driving the display panel with different refresh frequencies can satisfy the requirement of using a higher refresh frequency (for example, 120Hz) to drive when displaying dynamic images, thereby improving the display effect. When displaying static images, a lower refresh frequency (for example, 60Hz) is used to drive and reduce power consumption. However, when displaying static images, due to the low refresh frequency, when switching between different refresh frequencies, the hysteresis effect of the driving transistor can easily lead to low grayscale flickering when switching between different refresh frequencies or when maintaining subframes and refreshing subframes when driving at a lower refresh frequency, affecting the display effect of the product.

[0141] In order to improve afterimages and hysteresis and achieve different refresh frequency drives, as shown in FIG2 , a third transistor M3 is provided to initialize the first electrode of the driving transistor M0 via the first initialization signal of the first initialization signal terminal VINIT1. However, the first initialization voltage of the first initialization signal is usually a static fixed voltage value, and the first initialization voltage is also a voltage with a relatively high voltage value. After the pixel circuit has been operating for a long time, the driving transistor M0 is biased in the same state, and the driving transistor M0 is prone to biasing in the same direction. This will cause the characteristics of the driving transistor M0 to change after the pixel circuit has been operating for a long time.

[0142] In order to improve the characteristic stability of the driving transistor, in an embodiment of the present disclosure, the data writing circuit can be configured to provide the data voltage of the data signal terminal to the first electrode of the driving transistor in response to multiple valid levels of the first scanning signal terminal. Furthermore, in a data refresh phase, the scanning signal of the first scanning signal terminal has multiple valid levels that appear at intervals, and the light-emitting control signal of the light-emitting control signal terminal has a time period of invalid level and a time period of valid level. Furthermore, in a data refresh phase, the time period of invalid level of the light-emitting control signal terminal includes a time period of valid level of the compensation control signal terminal and a time period of multiple valid levels of the first scanning signal terminal, and the multiple valid levels of the first scanning signal terminal include at least one first valid level and at least one second valid level, and the time period of valid level of the compensation control signal terminal includes a time period of the first valid level.

[0143] In the pixel circuit provided by the embodiment of the present disclosure, threshold compensation can be achieved by inputting a data voltage at a first effective level of the first scanning signal terminal through the data writing circuit. The data voltage input at a second effective level of the first scanning signal terminal is only input to the first electrode of the driving transistor, so that the voltage of the first electrode of the driving transistor at this time is the data voltage, thereby biasing the first electrode of the driving transistor through the data voltage. Furthermore, since the data voltages for different grayscales are different, while biasing the first electrode of the driving transistor, the bias voltage of the first electrode of the driving transistor can be different from the same bias voltage through the change of the data voltage, so that the bias state of the first electrode of the driving transistor changes with the change of the data voltage, thereby improving the problem of drift of the driving transistor characteristics caused by maintaining the same bias voltage and time for a long time, and improving the characteristic stability of the driving transistor.

[0144] In the embodiment of the present disclosure, the first scan signal terminal may have one first effective level. Alternatively, the first scan signal terminal may have two first effective levels. Alternatively, the first scan signal terminal may have three or more first effective levels. In actual applications, the number of first effective levels may be determined based on actual application requirements and is not limited herein.

[0145] In the disclosed embodiment, the first scan signal terminal may have one second effective level. Alternatively, the first scan signal terminal may have two second effective levels. Alternatively, the first scan signal terminal may have three or more second effective levels. In practical applications, the number of second effective levels may be determined based on the needs of the practical application and is not limited here.

[0146] In an embodiment of the present disclosure, the functional circuit in the pixel circuit may include a data writing circuit, and the second scan signal terminal may include the first scan signal terminal. Furthermore, the seventh active level of the second scan signal terminal may include the first active level of the first scan signal terminal, and the eighth active level of the second scan signal terminal may include the second active level of the first scan signal terminal.

[0147] In some examples, taking the structure of the pixel circuit shown in FIG2 as an example, the corresponding signal timing diagram is shown in FIG3 . As shown in FIG3 , SX represents a data refresh phase SX, em represents the light-emission control signal of the light-emission control signal terminal EM, cf represents the compensation control signal of the compensation control signal terminal CF, and ga represents the scan signal of the first scan signal terminal GA. tem represents the time period of the light-emission control signal em at an inactive level, tcf represents the time period of the compensation control signal cf at an active level, tyx1 represents the time period of the scan signal ga at a first active level YX1, and tyx2 represents the time period of the scan signal ga at a second active level YX2. The scan signal has a first active level YX1 and a second active level YX2, and there is an interval between the first active level YX1 and the second active level YX2. Furthermore, the time period tem of the light-emission control signal em at an inactive level (e.g., a high level) includes the time period tcf of the compensation control signal cf at an active level (e.g., a high level), the time period tyx1 of the scan signal ga at a first active level YX1 (e.g., a low level), and the time period tyx2 of the scan signal ga at a second active level YX2 (e.g., a low level). Furthermore, the time period tcf of the effective level (such as high level) of the compensation control signal cf includes the time period tyx1 of the first effective level YX1 (such as low level), while the time period tcf of the effective level (such as high level) of the compensation control signal cf does not include the time period tyx2 of the second effective level YX2 (such as low level).

[0148] In some embodiments of the present disclosure, during a data refresh phase, a time period of at least one of the at least one second active levels occurs after a time period of the active level of the compensation control signal terminal. For example, as shown in FIG3 , during a data refresh phase SX, a time period tyx2 of the second active level YX2 (e.g., a low level) can occur after a time period tcf of the active level of the compensation control signal cf (e.g., a high level).

[0149] In an embodiment of the present disclosure, during a data refresh phase, the time period of the inactive level of the light-emitting control signal terminal also includes the time period of the active level of the first reset control signal terminal; and the time period of the active level of the first reset control signal terminal does not overlap with the time periods of multiple active levels of the first scanning signal terminal. For example, as shown in FIG3 , re1 represents the first reset control signal of the first reset control signal terminal RE1, and the time period tem of the inactive level (e.g., high level) of the light-emitting control signal em also includes the time period of the active level (e.g., low level) of the first reset control signal re1; and the time period of the active level (e.g., low level) of the first reset control signal re1 does not overlap with the time period tyx1 of the first active level YX1 and the time period tyx2 of the second active level YX2 of the scanning signal ga.

[0150] In an embodiment of the present disclosure, in a data refresh phase, the effective level of the first reset control signal terminal includes at least one third effective level, and the time period of the at least one third effective level occurs after the time period of multiple effective levels in the first scan signal terminal. For example, as shown in FIG3 , in a data refresh phase SX, the effective level (e.g., low level) of the first reset control signal re1 includes a third effective level YX3, and the time period tyx3 of the third effective level YX3 (e.g., low level) occurs after the time period of multiple effective levels (e.g., low level) in the scan signal ga (e.g., the time period tyx2 of the second effective level YX2). Alternatively, in a data refresh phase SX, the effective level of the first reset control signal may include two, three, or more third effective levels, and the time periods of all third effective levels occur after the time periods of all effective levels in the scan signal.

[0151] In an embodiment of the present disclosure, during a data refresh phase, the active level of the first reset control signal terminal includes at least one fourth active level, the time period of the active level of the compensation control signal terminal includes a time period of the fourth active level, and the time period of the fourth active level occurs before the time period of the first active level of the first scan signal terminal. For example, as shown in FIG3 , during a data refresh phase SX, the active level (e.g., low level) of the first reset control signal re1 includes a fourth active level, the time period tcf of the active level (e.g., high level) of the compensation control signal cf includes a time period tyx4 of the fourth active level YX4 (e.g., low level), and the time period tyx4 of the fourth active level YX4 (e.g., low level) occurs before the time period tyx1 of the first active level YX1 (e.g., low level) of the scan signal ga. Alternatively, during a data refresh phase, the active level of the first reset control signal may include two, three, or more fourth active levels, and the time period of the active level of the compensation control signal cf includes time periods of all fourth active levels, and all time periods of the fourth active level occur before the time period of the first active level of the scan signal ga.

[0152] For example, the functional circuit may include a first initialization circuit, and the second scan signal terminal may include a first reset control signal terminal. Furthermore, the seventh active level of the second scan signal terminal may include a fourth active level of the first reset control signal terminal, and the eighth active level of the second scan signal terminal may include a third active level of the first reset control signal terminal.

[0153] In an embodiment of the present disclosure, during a data refresh phase, a time period of inactive level of the light-emitting control signal terminal includes a time period of active level of the second reset control signal terminal; furthermore, the time period of active level of the second reset control signal terminal does not overlap with the time periods of multiple active levels of the first scanning signal terminal. For example, as shown in FIG3 , re2 represents the second reset control signal of the second reset control signal terminal RE2. During a data refresh phase SX, a time period tem of inactive level (e.g., high level) of the light-emitting control signal em includes a time period of active level (e.g., low level) of the second reset control signal re2; furthermore, a time period of active level (e.g., low level) of the second reset control signal re2 does not overlap with the time periods of multiple active levels (e.g., low level) of the scanning signal ga.

[0154] In an embodiment of the present disclosure, the active level of the second reset control signal terminal includes at least one fifth active level. Furthermore, in a data refresh phase, the time period of the active level of the compensation control signal terminal includes at least one fifth active level time period, and at least one fifth active level time period occurs before the time period of the active level of the first scan signal terminal. For example, as shown in FIG3 , the active level of the second reset control signal includes one fifth active level. In a data refresh phase SX, the time period of the active level (e.g., low level) of the compensation control signal cf includes a time period tyx5 of the fifth active level YX5 (e.g., low level), and the time period tyx5 of the fifth active level YX5 (e.g., low level) occurs before the time period tyx1 of the first active level YX1 (e.g., low level) of the scan signal ga. Alternatively, the active level of the second reset control signal includes two, three, or more fifth active levels. In a data refresh phase, the time period of the active level of the compensation control signal cf includes all fifth active level time periods, and all fifth active level time periods occur before the time period of the first active level of the scan signal ga.

[0155] In an embodiment of the present disclosure, during a data refresh phase, a time period of the fifth active level occurs after a time period of the fourth active level of the first reset control signal terminal. For example, as shown in FIG3 , during a data refresh phase SX, a time period tyx5 of the fifth active level YX5 (e.g., a low level) occurs after a time period tyx4 of all fourth active levels YX4 (e.g., a low level) of the first reset control signal re1. Alternatively, when the active level of the second reset control signal includes two, three, or more fifth active levels, during a data refresh phase, time periods of all fifth active levels occur after time periods of all fourth active levels of the first reset control signal.

[0156] In the embodiment of the present disclosure, the timing of the third reset control signal at the third reset control signal terminal can be made the same as the timing of the first reset control signal at the first reset control signal terminal. For example, as shown in FIG3 , re3 represents the third reset control signal, wherein the timing of the third reset control signal re3 is the same as the timing of the first reset control signal re1.

[0157] In the disclosed embodiment, the third reset control signal terminal RE3 and the first reset control signal terminal RE1 can be the same signal terminal. For example, as shown in FIG3 , the gate of the seventh transistor M7 can also be directly coupled to the first reset control signal terminal RE1. This can reduce the number of signal traces and reduce wiring difficulty.

[0158] In the disclosed embodiment, the third reset control signal terminal and the compensation control signal terminal may be the same signal terminal. Alternatively, the third reset control signal terminal and the first scan signal terminal may be the same signal terminal. Alternatively, the third reset control signal terminal and the second reset control signal terminal may be the same signal terminal.

[0159] In the embodiment of the present disclosure, a voltage with a relatively high voltage value can be applied to the first initialization signal terminal. Moreover, the voltage value applied to the first initialization signal terminal can be determined according to actual application requirements and is not limited here.

[0160] In the disclosed embodiment, the third initialization signal terminal and the second initialization signal terminal can be independent signals. This allows the third initialization signal terminal and the second initialization signal terminal to be loaded with different voltage values. Of course, the third initialization signal terminal and the second initialization signal terminal can also be loaded with the same voltage value, which is not limited here.

[0161] In the embodiment of the present disclosure, at least two of the third initialization signal terminal, the second initialization signal terminal, and the second power terminal are the same signal terminal, which can reduce the number of signal traces and reduce wiring difficulty.

[0162] The present disclosure also provides a method for driving a pixel circuit, including a data refresh phase. For example, as shown in FIG4 , the data refresh phase includes the following steps:

[0163] S110, data threshold compensation stage, the data writing circuit operates in response to the first valid level of the first scanning signal terminal; the threshold compensation circuit inputs the threshold voltage of the driving transistor into the gate of the driving transistor in response to the valid level of the compensation control signal terminal;

[0164] S120, in a first initialization auxiliary stage, the data writing circuit operates in response to the second valid level of the first scanning signal terminal;

[0165] S130, in the light emitting stage, the light emitting control circuit provides the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

[0166] In the embodiment of the present disclosure, before the data threshold compensation phase, a first initialization phase is further included. In the first initialization phase, the first initialization circuit provides a signal from the first initialization signal terminal to the first electrode of the driving transistor in response to the fourth valid level of the first reset control signal terminal.

[0167] In the embodiment of the present disclosure, a second initialization phase is further included between the first initialization phase and the data threshold compensation phase. In the second initialization phase, the second initialization circuit is configured to provide a signal from the second initialization signal terminal to the second electrode of the driving transistor in response to a fifth active level of the second reset control signal terminal.

[0168] Optionally, in the first initialization stage, the method further includes: a third initialization circuit providing a signal from a third initialization signal terminal to the light emitting device in response to an effective level of a third reset control signal terminal.

[0169] Optionally, in the second initialization stage, the method further includes: a third initialization circuit providing a signal from a third initialization signal terminal to the light emitting device in response to an effective level of a third reset control signal terminal.

[0170] In the embodiment of the present disclosure, a third initialization auxiliary stage is further included between the first initialization auxiliary stage and the light emitting stage. In the third initialization auxiliary stage, the first initialization circuit provides a signal from the first initialization signal terminal to the first electrode of the driving transistor in response to a third valid level of the first reset control signal terminal.

[0171] Optionally, in the third initialization auxiliary stage, the method further includes: a third initialization circuit providing a signal from a third initialization signal terminal to the light emitting device in response to an effective level of a third reset control signal terminal.

[0172] The following describes the operation of the pixel circuit provided by the embodiment of the present disclosure, taking the pixel circuit shown in FIG2 as an example, in conjunction with the signal timing diagram shown in FIG3. The data refresh phase SX may include: a first initialization phase T1, a second initialization phase T2, a data threshold compensation phase T3, a first initialization auxiliary phase T4, a third initialization auxiliary phase T5, and a light-emitting phase T6.

[0173] In the first initialization stage T1, the first transistor M1 is turned off under the high level control of the scan signal ga, the second transistor M2 is turned on under the high level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned on under the low level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned on under the low level control of the third reset control signal re3.

[0174] The conductive fifth transistor M5 provides the first initialization signal from the first initialization signal terminal VINIT1 to the first electrode of the driving transistor M0, causing the voltage Vs at the first electrode of the driving transistor M0 to be the voltage Vinit1 of the first initialization signal, i.e., Vs=Vinit1, thereby initializing the first electrode of the driving transistor M0. The conductive seventh transistor M7 provides the third initialization signal from the third initialization signal terminal VINIT3 to the anode of the light-emitting device L, thereby initializing the anode of the light-emitting device L. The conductive second transistor M2 conducts between the gate and the second electrode of the driving transistor M0.

[0175] In the second initialization stage T2, the first transistor M1 is turned off under the high level control of the scan signal ga, the second transistor M2 is turned on under the high level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the emission control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned on under the low level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0176] The turned-on sixth transistor M6 provides the second initialization signal of the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0, so that the voltage Vd of the second electrode of the driving transistor M0 is the voltage Vinit2 of the second initialization signal, that is, Vd=Vinit2, thereby initializing the second electrode of the driving transistor M0. The turned-on second transistor M2 conducts between the gate and the second electrode of the driving transistor M0, so that the voltage Vg of the gate of the driving transistor M0 is the voltage Vinit2 of the second initialization signal, that is, Vg=Vinit2, thereby initializing the gate of the driving transistor M0.

[0177] In the data threshold compensation stage T3, the first transistor M1 is turned on under the low level control of the scan signal ga, the second transistor M2 is turned on under the high level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the emission control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0178] The conductive first transistor M1 supplies the data voltage Vda at the data signal terminal DA to the first electrode of the driving transistor M0, achieving Vs = Vda. The conductive second transistor M2 connects the gate and the second electrode of the driving transistor M0, forming a diode connection for the driving transistor M0, achieving Vg = Vda + Vth, and turning off the driving transistor M0. The data voltage Vda is the voltage of the grayscale to be displayed by the light-emitting device L.

[0179] In the first initialization auxiliary stage T4, the first transistor M1 is turned on under the low level control of the scan signal ga, the second transistor M2 is turned off under the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0180] The turned-on first transistor M1 supplies the data voltage Vda1 at the data signal terminal DA to the first electrode of the driving transistor M0, so that Vs = Vda1. The data voltage Vda1 is the voltage at which the light-emitting devices L in the sub-pixels in other rows are to display the grayscale. Because the second transistor M2 is turned off, the data voltage Vda1 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to continue to be maintained at Vda + Vth.

[0181] Furthermore, between the first initialization auxiliary phase T4 and the start of the third initialization auxiliary phase T5, the voltage at the first electrode of the driving transistor M0 is always Vda1, and the first electrode of the driving transistor M0 is biased by Vda1. Since the data voltages for different grayscales are different, while biasing the first electrode of the driving transistor M0, the bias voltage of the first electrode of the driving transistor M0 can be varied by varying the data voltage. This allows the bias state of the first electrode of the driving transistor M0 to vary with variations in the data voltage, thereby alleviating the problem of characteristic drift of the driving transistor M0 caused by maintaining the same bias voltage and time for a long time, and improving the characteristic stability of the driving transistor M0.

[0182] In the third initialization auxiliary stage T5, the first transistor M1 is turned off under the high level control of the scan signal ga, the second transistor M2 is turned off under the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned on under the low level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned on under the low level control of the third reset control signal re3.

[0183] The turned-on fifth transistor M5 provides the first initialization signal of the first initialization signal terminal VINIT1 to the first electrode of the driving transistor M0, so that the voltage Vs of the first electrode of the driving transistor M0 returns to the voltage Vinit1 of the first initialization signal, that is, Vs=Vinit1. Vs is unified to Vinit1 before driving the light-emitting device L to emit light. The turned-on seventh transistor M7 provides the third initialization signal of the third initialization signal terminal VINIT3 to the anode of the light-emitting device L, thereby initializing the anode of the light-emitting device L.

[0184] In the light-emitting stage T6, the first transistor M1 is turned off under the high-level control of the scanning signal ga, the second transistor M2 is turned off under the low-level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned on under the low-level control of the light-emitting control signal em, the fifth transistor M5 is turned off under the high-level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high-level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high-level control of the third reset control signal re3.

[0185] The turned-on third transistor M3 provides the voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor M0, making Vs=Vdd. The turned-on fourth transistor M4 connects the second electrode of the driving transistor M0 to the anode of the light-emitting device L. Furthermore, Vg=Vda+Vth, and the driving transistor M0 generates a driving current IL, and IL=K[Vda-Vdd]. 2 Wherein, K=1 / 2*μ*Cox*W / L, μ is the mobility of the driving transistor M0, Cox is the gate insulation layer capacitance, and W / L is the channel width-to-length ratio of the driving transistor M0.

[0186] As can be seen from the above, the driving current IL is not related to the threshold voltage of the driving transistor M0 . Therefore, the pixel circuit can solve the problem of uneven display caused by uneven compensation of the threshold voltage of the driving transistor M0 , thereby improving the display effect.

[0187] Furthermore, between the first initialization auxiliary phase T4 and the start of the third initialization auxiliary phase T5, the voltage at the first electrode of the driving transistor M0 is always Vda1, and the first electrode of the driving transistor M0 is biased by Vda1. Since the data voltages for different grayscales are different, while biasing the first electrode of the driving transistor M0, the bias voltage of the first electrode of the driving transistor M0 can be varied by varying the data voltage. This allows the bias state of the first electrode of the driving transistor M0 to vary with variations in the data voltage, thereby alleviating the problem of characteristic drift of the driving transistor M0 caused by maintaining the same bias voltage and time for a long time, and improving the characteristic stability of the driving transistor M0.

[0188] The pixel circuit provided by the present disclosure can support driving at a variety of different refresh rates, such as 1Hz, 10Hz, 30Hz, 60Hz, and 120Hz. This higher refresh rate can improve the effects of scenes in gaming and other fields, further enhance light emission stability, and improve the display quality of the display panel.

[0189] In the embodiment of the present disclosure, when the pixel circuit is driven to operate at a maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame is the operation process of the pixel circuit in one data refresh phase SX. For example, as shown in FIG5 , when the pixel circuit is driven to operate at a maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame FA in FIG5 is the operation process of the pixel circuit in the data refresh phase SX in FIG3 .

[0190] In the disclosed embodiment, when a refresh frequency lower than the maximum refresh frequency is used (e.g., 1 Hz, 30 Hz, 60 Hz), a display frame corresponding to the pixel circuit includes multiple consecutive sub-display frames, the first of which is defined as a refresh sub-frame fb1, and the remaining sub-display frames are defined as hold sub-frames fb2. The operation of the pixel circuit in a refresh sub-frame fb1 is the operation of the pixel circuit in a data refresh phase SX. For example, as shown in FIG6 , the pixel circuit has a refresh sub-frame fb1 and a hold sub-frame fb2 in a display frame FB. The operation of the pixel circuit in the refresh sub-frame fb1 in FIG6 is the operation of the pixel circuit in a data refresh phase SX in FIG3 .

[0191] In some embodiments of the present disclosure, the compensation control signal terminal is at an inactive level in the holding subframe. For example, as shown in FIG6 , the compensation control signal cf is at an inactive level (eg, a low level) in the holding subframe fb2.

[0192] In some embodiments of the present disclosure, the timing of the light control signal terminal in the hold subframe is the same as the timing of the light control signal terminal in the refresh subframe. For example, as shown in FIG6 , the timing of the light control signal em in the hold subframe fb2 is the same as the timing of the light control signal em in the refresh subframe fb1.

[0193] In some embodiments of the present disclosure, the timing of the first scan signal end in the hold subframe is the same as the timing of the first scan signal end in the refresh subframe. For example, as shown in FIG6 , the timing of the scan signal ga in the hold subframe fb2 is the same as the timing of the scan signal ga in the refresh subframe fb1.

[0194] In some embodiments of the present disclosure, the timing of the first reset control signal terminal in at least one hold subframe is the same as the timing of the first reset control signal terminal in the refresh subframe. For example, as shown in FIG6 , the timing of the first reset control signal re1 in each hold subframe fb2 is the same as the timing of the first reset control signal re1 in the refresh subframe fb1.

[0195] In some further embodiments of the present disclosure, the timing of the first reset control signal terminal in the partial hold subframe is the same as the timing of the first reset control signal terminal in the refresh subframe, and the number of valid levels of the first reset control signal terminal in the remaining partial hold subframe is less than the number of valid levels of the first reset control signal terminal in the refresh subframe.

[0196] In some other embodiments of the present disclosure, the timing of the first reset control signal terminal in a portion of the hold subframe is the same as the timing of the first reset control signal terminal in the refresh subframe, and the first reset control signal terminal is at an inactive level in the remaining hold subframes. For example, only in the hold subframe when the next display frame arrives is the timing of the first reset control signal terminal the same as the timing of the first reset control signal terminal in the refresh subframe, and the first reset control signal terminal is at an inactive level in the remaining hold subframes.

[0197] In some other embodiments of the present disclosure, the first reset control signal terminal may also be set to an invalid level in the holding subframe.

[0198] In some embodiments of the present disclosure, the timing of the second reset control signal terminal in at least one hold subframe is the same as the timing of the second reset control signal terminal in the refresh subframe. For example, as shown in FIG6 , the timing of the second reset control signal re2 in each hold subframe fb2 is the same as the timing of the second reset control signal re2 in the refresh subframe fb1.

[0199] In some further embodiments of the present disclosure, the timing of the second reset control signal terminal in the partial hold subframe is the same as the timing of the second reset control signal terminal in the refresh subframe, and the number of valid levels of the second reset control signal terminal in the remaining hold subframe is less than the number of valid levels of the second reset control signal terminal in the refresh subframe.

[0200] In some other embodiments of the present disclosure, the timing of the second reset control signal terminal in a portion of the hold subframe is the same as the timing of the second reset control signal terminal in the refresh subframe, and the second reset control signal terminal is at an inactive level in the remaining hold subframe. For example, only in the hold subframe when the next display frame arrives is the timing of the second reset control signal terminal the same as the timing of the second reset control signal terminal in the refresh subframe, and the second reset control signal terminal is at an inactive level in the remaining hold subframe.

[0201] In some embodiments of the present disclosure, the timing of the third reset control signal terminal in at least one hold subframe is the same as the timing of the third reset control signal terminal in the refresh subframe. For example, as shown in FIG6 , the timing of the third reset control signal re3 in each hold subframe fb2 is the same as the timing of the third reset control signal re3 in the refresh subframe fb1.

[0202] In some further embodiments of the present disclosure, the timing of the third reset control signal terminal in the partial hold subframe is the same as the timing of the third reset control signal terminal in the refresh subframe, and the number of valid levels of the third reset control signal terminal in the remaining partial hold subframe is less than the number of valid levels of the third reset control signal terminal in the refresh subframe.

[0203] In some other embodiments of the present disclosure, the timing of the third reset control signal terminal in a portion of the hold subframe is the same as the timing of the third reset control signal terminal in the refresh subframe, and the third reset control signal terminal is at an inactive level in the remaining hold subframes. For example, only in the hold subframe when the next display frame arrives is the timing of the third reset control signal terminal the same as the timing of the third reset control signal terminal in the refresh subframe, and the third reset control signal terminal is at an inactive level in the remaining hold subframes.

[0204] For example, as shown in FIG6 , when the pixel circuit is driven at a low refresh frequency, such as a 60 Hz refresh frequency, the operation process of the pixel circuit in the refresh subframe fb1 is the same as the operation process of the pixel circuit in the data refresh phase SX. The hold subframe fb2 includes phases H1, H2, H3, H4, H5, and H6.

[0205] In the H1 phase, the second transistor M2 is turned off under the low level control of the compensation control signal cf, and the rest of the operation process may be the same as the operation process of the first initialization phase T1, which will not be described in detail here.

[0206] In the H2 phase, the second transistor M2 is turned off under the low level control of the compensation control signal cf, and the rest of the operation process is the same as that of the second initialization phase T2, which will not be described in detail.

[0207] During phase H3, the second transistor M2 is turned off under the low-level control of the compensation control signal cf. The turned-on first transistor M1 supplies the data voltage Vda2 at the data signal terminal DA to the first electrode of the driving transistor M0, setting Vs = Vda2. The data voltage Vda2 represents the grayscale voltage to be displayed by the light-emitting devices L in the sub-pixels of the other rows. Because the second transistor M2 is turned off, the data voltage Vda2 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to continue to maintain Vda + Vth. The remaining operating process is the same as that of the second initialization phase T2 and is not further described here.

[0208] In the H4 stage, the working process may be the same as the working process of the first initialization auxiliary stage T4, and will not be described in detail here.

[0209] In the H5 stage, the working process may be the same as the working process of the third initialization auxiliary stage T5, and will not be described in detail here.

[0210] In the H6 stage, the working process may be the same as that in the light-emitting stage T6, and will not be described in detail here.

[0211] In the holding subframe, the first electrode of the driving transistor is biased by the data voltage. Since the data voltages of different grayscales are different, the bias voltage of the first electrode of the driving transistor can be changed to not be the same bias voltage while biasing the first electrode of the driving transistor. Therefore, the bias state of the first electrode of the driving transistor changes with the change of the data voltage, thereby improving the problem of driving transistor characteristic drift caused by maintaining the same time and voltage bias for a long time, and improving the characteristic stability of the driving transistor.

[0212] The present disclosure provides some further signal timing diagrams of the display panel, as shown in Figure 7, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0213] In some embodiments of the present disclosure, the multiple valid levels in the first scan signal terminal may also include two second valid levels. The time periods of the two second valid levels occur after the time period of the valid level of the compensation control signal terminal. For example, as shown in FIG7 , SX represents a data refresh phase SX, em represents the light emitting control signal of the light emitting control signal terminal EM, cf represents the compensation control signal of the compensation control signal terminal CF, ga represents the scan signal of the first scan signal terminal GA, re1 represents the first reset control signal of the first reset control signal terminal RE1, re2 represents the second reset control signal of the second reset control signal terminal RE2, and re3 represents the third reset control signal of the third reset control signal terminal RE3.

[0214] The scanning signal has a first active level and two second active levels YX2-1 and YX2-2, and there is an interval between the first active level and the second active level YX2-1, an interval between the second active level YX2-1 and the second active level YX2-2, and an interval between the first active level and the second active level YX2-2. Furthermore, the time period tem of the inactive level (e.g., high level) of the light-emitting control signal em includes the time period tcf of the active level (e.g., high level) of the compensation control signal cf, the time period tyx1 of the first active level YX1, the time period tyx2-1 of the second active level YX2-1, and the time period tyx2-2 of the second active level YX2-2 of the scanning signal ga. In addition, the time period tcf of the effective level (such as high level) of the compensation control signal cf includes the time period tyx1 of the first effective level YX1, while the time period tcf of the effective level (such as high level) of the compensation control signal cf does not include the time period tyx2-1 of the second effective level YX2-1 and the time period tyx2-2 of the second effective level YX2-2.

[0215] Also, in one data refresh phase SX, the period tyx2-1 of the second active level YX2-1 and the period tyx2-2 of the second active level YX2-2 may be made to appear after the period of the active level of the compensation control signal cf.

[0216] Also, in one data refresh phase SX, a period tyx2-1 of the second active level YX2-1 and a period tyx2-2 of the second active level YX2-2 may be made to appear before the third active level of the first reset control signal.

[0217] Of course, during a data refresh phase, the multiple active levels at the first scan signal terminal may include three or more second active levels. Furthermore, the time period of the three or more second active levels occurs after the time period of the active level of the compensation control signal. In actual applications, the number of second active levels that occurs after the time period of the active level of the compensation control signal can be determined based on the requirements of the actual application environment and is not limited here.

[0218] The following describes the operation of the pixel circuit provided by the embodiment of the present disclosure, taking the pixel circuit shown in FIG2 as an example, in conjunction with the signal timing diagram shown in FIG7 . The data refresh phase SX may include: a first initialization phase T1, a second initialization phase T2, a data threshold compensation phase T3, a first initialization auxiliary phase T4, a third initialization auxiliary phase T5, and a light-emitting phase T6. The first initialization phase T1, the second initialization phase T2, the data threshold compensation phase T3, the third initialization auxiliary phase T5, and the light-emitting phase T6 may refer to the description of the above embodiment and are not described in detail here.

[0219] Furthermore, the first initialization auxiliary phase T4 includes phases T41 and T42. In phase T41, the first transistor M1 is turned on by the low level control of the scan signal ga, the second transistor M2 is turned off by the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off by the high level control of the light emitting control signal em, the fifth transistor M5 is turned off by the high level control of the first reset control signal re1, the sixth transistor M6 is turned off by the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off by the high level control of the third reset control signal re3.

[0220] The turned-on first transistor M1 supplies the data voltage Vda1 at the data signal terminal DA to the first electrode of the driving transistor M0, so that Vs = Vda1. The data voltage Vda1 is the voltage at which the light-emitting devices L in the sub-pixels in other rows are to display the grayscale. Because the second transistor M2 is turned off, the data voltage Vda1 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to continue to be maintained at Vda + Vth.

[0221] In the T42 stage, the first transistor M1 is turned on under the low level control of the scan signal ga, the second transistor M2 is turned off under the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0222] The turned-on first transistor M1 supplies the data voltage Vda2 at the data signal terminal DA to the first electrode of the driving transistor M0, so that Vs = Vda2. The data voltage Vda2 is the voltage at which the light-emitting devices L in the sub-pixels in other rows are to display the grayscale. Because the second transistor M2 is turned off, the data voltage Vda2 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to continue to be maintained at Vda + Vth.

[0223] Since the data voltages for different grayscales are different, the first electrode of the driving transistor M0 can be biased in the first initialization auxiliary stage T4. At the same time, the bias voltage of the first electrode of the driving transistor M0 will not be the same bias voltage through the change of the data voltage. Therefore, the bias state of the first electrode of the driving transistor M0 changes with the change of the data voltage, thereby improving the problem of characteristic drift of the driving transistor M0 caused by maintaining the same time and voltage bias for a long time, and improving the characteristic stability of the driving transistor M0.

[0224] In the embodiment of the present disclosure, when the pixel circuit is driven to operate at the maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame is the operation process of the pixel circuit in one data refresh phase SX. For example, as shown in FIG8 , when the pixel circuit is driven to operate at the maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame FA in FIG8 is the operation process of the pixel circuit in the data refresh phase SX in FIG7 .

[0225] In the embodiment of the present disclosure, when other refresh frequencies less than the maximum refresh frequency are adopted (for example, 1 Hz, 30 Hz, 60 Hz), a display frame corresponding to the pixel circuit includes a plurality of consecutive sub-display frames, the first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame fb1, and the remaining sub-display frames are defined as hold sub-frames fb2, and the working process of the pixel circuit in a refresh sub-frame fb1 is the working process of the pixel circuit in a data refresh phase SX. For example, as shown in FIG9 , the pixel circuit has a refresh sub-frame fb1 and a hold sub-frame fb2 in a display frame FB, wherein the working process of the pixel circuit in the refresh sub-frame fb1 in FIG9 is the working process of the pixel circuit in a data refresh phase SX in FIG7 . In the hold sub-frame fb2, except for the H4 stage which is different from the above embodiment, the working process of the remaining stages is the same as that in the above embodiment, and will not be repeated here.

[0226] The H4 phase includes the H41 and H42 phases. In the H41 phase, the first transistor M1 is turned on by the low level control of the scan signal ga, the second transistor M2 is turned off by the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off by the high level control of the light emitting control signal em, the fifth transistor M5 is turned off by the high level control of the first reset control signal re1, the sixth transistor M6 is turned off by the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off by the high level control of the third reset control signal re3.

[0227] The turned-on first transistor M1 supplies the data voltage Vda3 at the data signal terminal DA to the first electrode of the driving transistor M0, so that Vs = Vda3. The data voltage Vda3 is the voltage at which the light-emitting devices L in the sub-pixels in other rows are to display the grayscale. Because the second transistor M2 is turned off, the data voltage Vda3 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to continue to be maintained at Vda + Vth.

[0228] In the H42 stage, the first transistor M1 is turned on under the low level control of the scanning signal ga, the second transistor M2 is turned off under the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0229] The turned-on first transistor M1 supplies the data voltage Vda4 at the data signal terminal DA to the first electrode of the driving transistor M0, so that Vs = Vda4. The data voltage Vda4 is the voltage at which the light-emitting devices L in the sub-pixels in other rows are to display the grayscale. Because the second transistor M2 is turned off, the data voltage Vda4 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to continue to be maintained at Vda + Vth.

[0230] The present disclosure provides some further signal timing diagrams of the display panel, as shown in Figure 10, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0231] In some embodiments of the present disclosure, the multiple valid levels in the first scan signal terminal may include a second valid level. The time period of the second valid level occurs before the time period of the valid level of the compensation control signal terminal. For example, as shown in FIG10 , SX represents a data refresh phase SX, em represents the light-emitting control signal of the light-emitting control signal terminal EM, cf represents the compensation control signal of the compensation control signal terminal CF, ga represents the scan signal of the first scan signal terminal GA, re1 represents the first reset control signal of the first reset control signal terminal RE1, re2 represents the second reset control signal of the second reset control signal terminal RE2, and re3 represents the third reset control signal of the third reset control signal terminal RE3. The time period tyx2 of the second valid level YX2 (e.g., a low level) of the scan signal ga occurs before the time period tcf of the valid level (e.g., a high level) of the compensation control signal cf.

[0232] In some embodiments of the present disclosure, the multiple active levels of the first scan signal terminal GA may include two second active levels YX2-1 and YX2-2. The time period tyx2-1 of the second active level YX2-1 and the time period tyx2-1 of the second active level YX2-1 both occur before the time period tcf of the active level of the compensation control signal terminal CF. For example, as shown in FIG11 , SX represents a data refresh phase SX, em represents the light-emission control signal of the light-emission control signal terminal EM, cf represents the compensation control signal of the compensation control signal terminal CF, ga represents the scan signal of the first scan signal terminal GA, re1 represents the first reset control signal of the first reset control signal terminal RE1, re2 represents the second reset control signal of the second reset control signal terminal RE2, and re3 represents the third reset control signal of the third reset control signal terminal RE3. The time period tyx2-1 of the second active level YX2-1 (e.g., low level) of the scan signal ga and the time period tyx2-1 of the second active level YX2-1 (e.g., low level) both occur before the time period tcf of the compensation control signal cf (e.g., high level).

[0233] Of course, during a data refresh phase, the multiple active levels at the first scan signal terminal may include three or more second active levels. Furthermore, the time period of the three or more second active levels occurs before the time period of the active level of the compensation control signal. In actual applications, the number of second active levels that occurs before the time period of the active level of the compensation control signal can be determined based on the requirements of the actual application environment and is not limited here.

[0234] The present disclosure also provides a method for driving a pixel circuit including a data refresh phase. For example, as shown in FIG12 , the data refresh phase includes the following steps:

[0235] S210, a second initialization auxiliary stage, the data writing circuit operates in response to the second valid level of the first scanning signal terminal;

[0236] S220, data threshold compensation stage, the data writing circuit operates in response to the first valid level of the first scanning signal terminal; the threshold compensation circuit inputs the threshold voltage of the driving transistor into the gate of the driving transistor in response to the valid level of the compensation control signal terminal;

[0237] S230, in the light emitting stage, the light emitting control circuit provides the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

[0238] In the embodiment of the present disclosure, before the data threshold compensation phase, a first initialization phase is further included. In the first initialization phase, the first initialization circuit provides a signal from the first initialization signal terminal to the first electrode of the driving transistor in response to the fourth valid level of the first reset control signal terminal.

[0239] In the embodiment of the present disclosure, a second initialization phase is further included between the first initialization phase and the data threshold compensation phase. In the second initialization phase, the second initialization circuit is configured to provide a signal from the second initialization signal terminal to the second electrode of the driving transistor in response to a fifth active level of the second reset control signal terminal.

[0240] Optionally, in the first initialization stage, the method further includes: a third initialization circuit providing a signal from a third initialization signal terminal to the light emitting device in response to an effective level of a third reset control signal terminal.

[0241] Optionally, in the second initialization stage, the method further includes: a third initialization circuit providing a signal from a third initialization signal terminal to the light emitting device in response to an effective level of a third reset control signal terminal.

[0242] In the embodiment of the present disclosure, a third initialization auxiliary phase is further included between the data threshold compensation phase and the light emitting phase. In the third initialization auxiliary phase, the first initialization circuit provides a signal from the first initialization signal terminal to the first electrode of the driving transistor in response to a third valid level of the first reset control signal terminal.

[0243] Optionally, in the third initialization auxiliary stage, the method further includes: a third initialization circuit providing a signal from a third initialization signal terminal to the light emitting device in response to an effective level of a third reset control signal terminal.

[0244] The following describes the operation of the pixel circuit provided by the embodiment of the present disclosure, taking the pixel circuit shown in FIG2 as an example, in conjunction with the signal timing diagram shown in FIG10 . The data refresh phase SX may include: a second initialization auxiliary phase T7, a first initialization phase T1, a second initialization phase T2, a data threshold compensation phase T3, a third initialization auxiliary phase T5, and a light-emitting phase T6. The first initialization phase T1, the second initialization phase T2, the data threshold compensation phase T3, the third initialization auxiliary phase T5, and the light-emitting phase T6 may refer to the description of the above embodiment and are not described in detail here.

[0245] In the second initialization auxiliary stage T7, the first transistor M1 is turned on under the low level control of the scan signal ga, the second transistor M2 is turned off under the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0246] The turned-on first transistor M1 supplies the data voltage Vda5 at the data signal terminal DA to the first electrode of the driving transistor M0, setting Vs = Vda5. The data voltage Vda5 is the grayscale voltage to be displayed by the light-emitting devices L in the sub-pixels in other rows. Because the second transistor M2 is turned off, the data voltage Vda5 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to remain at its original voltage.

[0247] In the embodiment of the present disclosure, when the pixel circuit is driven to operate at a maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame is the operation process of the pixel circuit in one data refresh phase SX. For example, as shown in FIG13 , when the pixel circuit is driven to operate at a maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame FA in FIG13 is the operation process of the pixel circuit in the data refresh phase SX in FIG10 .

[0248] In the embodiment of the present disclosure, when other refresh frequencies less than the maximum refresh frequency are adopted (for example, 1 Hz, 30 Hz, 60 Hz), a display frame corresponding to the pixel circuit includes a plurality of consecutive sub-display frames, the first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames, and the working process of the pixel circuit in a refresh sub-frame is the working process of the pixel circuit in a data refresh phase. For example, as shown in FIG14 , the pixel circuit has a refresh sub-frame fb1 and a hold sub-frame fb2 in a display frame FB, wherein the working process of the pixel circuit in the refresh sub-frame fb1 in FIG14 is the working process of the pixel circuit in a data refresh phase SX in FIG10 . In the hold sub-frame fb2, except for the H7 stage which is different from the above embodiment, the working process of the remaining stages is the same as that in the above embodiment, and will not be repeated here.

[0249] In the H7 stage, the first transistor M1 is turned on under the low level control of the scanning signal ga, the second transistor M2 is turned off under the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off under the high level control of the light emitting control signal em, the fifth transistor M5 is turned off under the high level control of the first reset control signal re1, the sixth transistor M6 is turned off under the high level control of the second reset control signal re2, and the seventh transistor M7 is turned off under the high level control of the third reset control signal re3.

[0250] The turned-on first transistor M1 supplies the data voltage Vda6 at the data signal terminal DA to the first electrode of the driving transistor M0, setting Vs = Vda6. The data voltage Vda6 represents the grayscale voltage to be displayed by the light-emitting devices L in the sub-pixels in the other rows. Since the second transistor M2 is turned off, the data voltage Vda6 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to remain at its original voltage.

[0251] The present disclosure provides some further signal timing diagrams of the display panel, as shown in Figure 15, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0252] In some embodiments of the present disclosure, in a data refresh phase, a time period of a first part of the second valid level in at least one second valid level occurs before a time period of the valid level of the compensation control signal end, and a time period of a second part of the second valid level in at least one second valid level occurs before a time period of the valid level of the compensation control signal end.

[0253] For example, as shown in FIG15 , SX represents a data refresh phase SX, em represents the light-emission control signal of the light-emission control signal terminal EM, cf represents the compensation control signal of the compensation control signal terminal CF, ga represents the scan signal of the first scan signal terminal GA, re1 represents the first reset control signal of the first reset control signal terminal RE1, re2 represents the second reset control signal of the second reset control signal terminal RE2, and re3 represents the third reset control signal of the third reset control signal terminal RE3. The multiple active levels of the first scan signal terminal GA may include two second active levels YX2-1 and YX2-2. The time period tyx2-1 of the second active level YX2-1 occurs before the time period tcf of the active level of the compensation control signal terminal CF, and the time period tyx2-2 of the second active level YX2-2 occurs after the time period tcf of the active level of the compensation control signal terminal CF. That is, the second active level period tyx2-1 of the scanning signal ga occurs before the active level period tcf of the compensation control signal cf, and the second active level period tyx2-2 occurs after the active level period tcf of the compensation control signal cf.

[0254] For example, as shown in FIG16 , SX represents a data refresh phase SX, em represents the emission control signal of the emission control signal terminal EM, cf represents the compensation control signal of the compensation control signal terminal CF, ga represents the scan signal of the first scan signal terminal GA, re1 represents the first reset control signal of the first reset control signal terminal RE1, re2 represents the second reset control signal of the second reset control signal terminal RE2, and re3 represents the third reset control signal of the third reset control signal terminal RE3. The multiple active levels of the first scan signal terminal GA may include four second active levels YX2-1 to YX2-4. The time period tyx2-1 of the second active level YX2-1 and the time period tyx2-1 of the second active level YX2-1 both occur before the time period tcf of the active level of the compensation control signal terminal CF. The time period tyx2-3 of the second active level YX2-3 and the time period tyx2-4 of the second active level YX2-4 both occur after the time period tcf of the active level of the compensation control signal terminal CF. That is, the time period tyx2-1 of the second active level YX2-1 of the scanning signal ga and the time period tyx2-1 of the second active level YX2-1 both occur before the time period tcf of the active level of the compensation control signal cf. Furthermore, the time period tyx2-3 of the second active level YX2-3 of the scanning signal ga and the time period tyx2-4 of the second active level YX2-4 both occur after the time period tcf of the active level of the compensation control signal cf.

[0255] For example, in a data refresh phase, the number of second active levels that appear before the time period when the compensation control signal terminal is active and the number of active levels that appear after the time period when the compensation control signal terminal is active can be made equal. For example, as shown in FIG15 , in a data refresh phase SX, the number of second active levels that appear before the time period tcf when the compensation control signal terminal CF is active and the number of active levels that appear after the time period tcf when the compensation control signal terminal CF is active are both one. Alternatively, as shown in FIG16 , in a data refresh phase SX, the number of second active levels that appear before the time period tcf when the compensation control signal terminal CF is active and the number of active levels that appear after the time period tcf when the compensation control signal terminal CF is active are both two.

[0256] For example, in a data refresh phase, the number of second active levels that appear before the time period of the active level of the compensation control signal terminal may be greater than the number of active levels that appear after the time period of the active level of the compensation control signal terminal. For example, in a data refresh phase, the number of second active levels that appear before the time period of the active level of the compensation control signal terminal may be two, and the number of active levels that appear after the time period of the active level of the compensation control signal terminal may be one. Alternatively, in a data refresh phase, the number of second active levels that appear before the time period of the active level of the compensation control signal terminal may be three, and the number of active levels that appear after the time period of the active level of the compensation control signal terminal may be one or two.

[0257] For example, in a data refresh phase, the number of second active levels that appear before the time period of the active level of the compensation control signal terminal can be smaller than the number of active levels that appear after the time period of the active level of the compensation control signal terminal. For example, in a data refresh phase, the number of second active levels that appear before the time period of the active level of the compensation control signal terminal can be one, and the number of active levels that appear after the time period of the active level of the compensation control signal terminal can be two. Alternatively, in a data refresh phase, the number of second active levels that appear before the time period of the active level of the compensation control signal terminal can be one or two, and the number of active levels that appear after the time period of the active level of the compensation control signal terminal can be three.

[0258] The following describes the operation of the pixel circuit provided by the embodiment of the present disclosure, taking the pixel circuit shown in FIG2 as an example, in conjunction with the signal timing diagram shown in FIG15 . The data refresh phase SX may include: a second initialization auxiliary phase T7, a first initialization phase T1, a second initialization phase T2, a data threshold compensation phase T3, a first initialization auxiliary phase T4, a third initialization auxiliary phase T5, and a light-emitting phase T6. The second initialization auxiliary phase T7, the first initialization phase T1, the second initialization phase T2, the data threshold compensation phase T3, the first initialization auxiliary phase T4, the third initialization auxiliary phase T5, and the light-emitting phase T6 may refer to the description process in the above-mentioned embodiment and are not described in detail here.

[0259] In the embodiment of the present disclosure, when the pixel circuit is driven to operate at the maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame is the operation process of the pixel circuit in one data refresh phase SX. For example, as shown in FIG17 , when the pixel circuit is driven to operate at the maximum refresh frequency (e.g., 120 Hz), the operation process of the pixel circuit in one display frame FA in FIG17 is the operation process of the pixel circuit in the data refresh phase SX in FIG15 .

[0260] In the embodiment of the present disclosure, when other refresh frequencies less than the maximum refresh frequency are adopted (for example, 1 Hz, 30 Hz, 60 Hz), a display frame corresponding to the pixel circuit includes a plurality of consecutive sub-display frames, the first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame fb1, and the remaining sub-display frames are defined as hold sub-frames fb2, and the working process of the pixel circuit in a refresh sub-frame fb1 is the working process of the pixel circuit in a data refresh phase SX. For example, as shown in FIG18 , the pixel circuit has a refresh sub-frame fb1 and a hold sub-frame fb2 in a display frame FB, wherein the working process of the pixel circuit in the refresh sub-frame fb1 in FIG18 is the working process of the pixel circuit in a data refresh phase SX in FIG15 . The hold sub-frame fb2 also includes the H4 stage and the H7 stage, and the remaining stages are the same as the working process in the above-mentioned embodiment, and are not described in detail here. Moreover, the working process of the H4 stage and the H7 stage is also the same as the working process in the above-mentioned embodiment, and are not described in detail here.

[0261] The present disclosure provides some further signal timing diagrams of the display panel, as shown in Figure 19, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0262] In some embodiments of the present disclosure, in a data refresh phase, at least one time period of a third effective level occurs after a plurality of time periods of effective levels in the first scan signal terminal. For example, as shown in FIG19 , in a data refresh phase SX, the effective level (e.g., low level) of the first reset control signal re1 includes a third effective level YX3, and the time period tyx3 of the third effective level YX3 occurs after a plurality of time periods of effective levels (e.g., low level) in the scan signal ga (e.g., the time period tyx2 of the second effective level YX2). Alternatively, in a data refresh phase, the effective level (e.g., low level) of the first reset control signal may include two, three, or more third effective levels, and the time periods of all third effective levels occur after all time periods of effective levels in the scan signal.

[0263] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure, taking the pixel circuit shown in FIG2 as an example, in combination with the signal timing diagram shown in FIG19. The data refresh phase SX may include: a second initialization phase T2, a data threshold compensation phase T3, a first initialization auxiliary phase T4, a third initialization auxiliary phase T5, and a light-emitting phase T6. The working process of the second initialization phase T2, the data threshold compensation phase T3, the first initialization auxiliary phase T4, the third initialization auxiliary phase T5, and the light-emitting phase T6 are the same as the working process of the second initialization phase T2, the data threshold compensation phase T3, the first initialization auxiliary phase T4, the third initialization auxiliary phase T5, and the light-emitting phase T6 in the above-mentioned embodiment, and will not be described in detail here.

[0264] In the disclosed embodiment, when the pixel circuit is driven to operate at a maximum refresh rate (e.g., 120 Hz), the operation process of the pixel circuit in one display frame is the operation process of the pixel circuit in one data refresh phase. For example, as shown in FIG20 , when the pixel circuit is driven to operate at a maximum refresh rate (e.g., 120 Hz), the operation process of the pixel circuit in one display frame FA in FIG20 is the operation process of the pixel circuit in the data refresh phase SX in FIG19 .

[0265] In the embodiment of the present disclosure, when a refresh frequency other than the maximum refresh frequency is adopted (for example, 1 Hz, 30 Hz, 60 Hz), a display frame corresponding to the pixel circuit includes a plurality of consecutive sub-display frames, the first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames. The working process of the pixel circuit in a refresh sub-frame is the working process of the pixel circuit in a data refresh phase. For example, as shown in FIG21 , the pixel circuit has a refresh sub-frame fb1 and a hold sub-frame fb2 in a display frame FB, wherein the working process of the pixel circuit in the refresh sub-frame fb1 in FIG21 is the working process of the pixel circuit in a data refresh phase SX in FIG19 . The working process in the hold sub-frame fb2 is the same as the working process in the above-mentioned embodiment and will not be described in detail here.

[0266] The present disclosure provides some further signal timing diagrams of the display panel, as shown in Figure 22, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0267] In some other embodiments of the present disclosure, the first reset control signal terminal may be set to an inactive level in the holding subframe. For example, as shown in FIG22 , taking the active level as a low level and the inactive level as a high level as an example, the first reset control signal re1 is set to a high level in the holding subframe fb2.

[0268] In some other embodiments of the present disclosure, the second reset control signal terminal may be set to an inactive level in the hold subframe. For example, as shown in FIG22 , with the active level being a low level and the inactive level being a high level, the second reset control signal re2 is set to a high level in the hold subframe fb2.

[0269] In some other embodiments of the present disclosure, the third reset control signal terminal may be set to an inactive level in the hold subframe. For example, as shown in FIG22 , with the active level being a low level and the inactive level being a high level, the third reset control signal re3 is set to a high level in the hold subframe fb2.

[0270] For example, as shown in FIG22 , when the pixel circuit is driven at a low refresh frequency, such as a 60 Hz refresh frequency, the pixel circuit operates in the refresh subframe fb1 in the same manner as it does in the data refresh phase SX. In the hold subframe fb2, the first transistor M1 is turned on and supplies the data voltage Vda7 at the data signal terminal DA to the first electrode of the driving transistor M0, such that Vs = Vda7. Data voltage Vda7 is the grayscale voltage to be displayed by the light-emitting devices L in the subpixels of other rows. Because the second transistor M2 is turned off, data voltage Vda7 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to remain at its original voltage.

[0271] Afterwards, the turned-on first transistor M1 supplies the data voltage Vda8 at the data signal terminal DA to the first electrode of the driving transistor M0, setting Vs = Vda8. The data voltage Vda8 is the voltage at which the light-emitting devices L in the sub-pixels in the other rows are to display the grayscale. Because the second transistor M2 is turned off, the data voltage Vda8 does not affect the voltage at the gate of the driving transistor M0, causing the gate of the driving transistor M0 to remain at its original voltage.

[0272] Afterwards, the turned-on first transistor M1 supplies the data voltage Vda9 at the data signal terminal DA to the first electrode of the driving transistor M0, setting Vs = Vda9. The data voltage Vda9 represents the grayscale voltage to be displayed by the light-emitting devices L in the sub-pixels in the other rows. Because the second transistor M2 is turned off, the data voltage Vda9 does not affect the gate voltage of the driving transistor M0, causing the gate voltage of the driving transistor M0 to remain at its original voltage.

[0273] After that, it enters the light-emitting stage.

[0274] The present disclosure provides some further signal timing diagrams of the display panel, as shown in FIG23a, which is a modification of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0275] In some embodiments of the present disclosure, the effective level of the second reset control signal terminal includes at least one sixth effective level. For example, the effective level of the second reset control signal terminal includes one, two, three, or more sixth effective levels. Moreover, in a data refresh phase, the time periods of all the sixth effective levels can be made to appear before the time period of the effective level of the compensation control signal terminal. For example, as shown in FIG23 a , taking the example that the effective level (e.g., low level) of the second reset control signal terminal RE2 includes a sixth effective level YX6, in a data refresh phase SX, the time period tyx6 of the sixth effective level YX6 appears before the time period tcf of the effective level (e.g., high level) of the compensation control signal cf.

[0276] Alternatively, in some embodiments of the present disclosure, the active level of the second reset control signal terminal includes at least one sixth active level. For example, the active level of the second reset control signal terminal includes one, two, three, or more sixth active levels. Furthermore, in a data refresh phase, the time periods of all sixth active levels may also occur after the time period of the active level of the compensation control signal terminal.

[0277] Alternatively, in some embodiments of the present disclosure, the active level of the second reset control signal terminal includes multiple sixth active levels. For example, the active level of the second reset control signal terminal includes two, three, or more sixth active levels. Furthermore, during a data refresh phase, some of the time periods of the sixth active levels may occur before the time period of the active level of the compensation control signal terminal, and some of the time periods of the sixth active level may occur after the time period of the active level of the compensation control signal terminal, without limitation herein.

[0278] For example, the functional circuit may include a second initialization circuit, and the second scan signal terminal may include a second reset control signal terminal. The seventh valid level of the second scan signal terminal may include the second reset control signal terminal returning to the fifth valid level, and the eighth valid level of the second scan signal terminal may include the second reset control signal terminal returning to the sixth valid level.

[0279] The following describes the operation of the pixel circuit provided by the embodiment of the present disclosure, taking the pixel circuit shown in FIG2 as an example, in conjunction with the signal timing diagram shown in FIG23a. The data refresh phase SX may include: a fourth initialization auxiliary phase T8, a first initialization phase T1, a second initialization phase T2, a data threshold compensation phase T3, a first initialization auxiliary phase T4, a third initialization auxiliary phase T5, and a light-emitting phase T6. The first initialization phase T1, the second initialization phase T2, the data threshold compensation phase T3, the first initialization auxiliary phase T4, the third initialization auxiliary phase T5, and the light-emitting phase T6 may refer to the description of the above embodiment and are not described in detail here.

[0280] In the fourth initialization auxiliary phase T8, the first transistor M1 is turned off by the high level control of the scan signal ga, the second transistor M2 is turned off by the low level control of the compensation control signal cf, the third transistor M3 and the fourth transistor M4 are turned off by the high level control of the light-emitting control signal em, the fifth transistor M5 is turned off by the high level control of the first reset control signal re1, the sixth transistor M6 is turned on by the low level control of the second reset control signal RE2, and the seventh transistor M7 is turned off by the high level control of the third reset control signal re3. The turned-on sixth transistor M6 provides the second initialization signal at the second initialization signal terminal VINIT2 to the second electrode of the driving transistor M0, causing the voltage Vd at the second electrode of the driving transistor M0 to be the voltage Vinit2 of the second initialization signal, i.e., Vd=Vinit2, thereby initializing the second electrode of the driving transistor M0.

[0281] In the disclosed embodiment, when the pixel circuit is driven to operate at a maximum refresh rate (e.g., 120 Hz), the operation process of the pixel circuit in a display frame is the operation process of the pixel circuit in a data refresh phase. For example, as shown in FIG24 , when the pixel circuit is driven to operate at a maximum refresh rate (e.g., 120 Hz), the operation process of the pixel circuit in a display frame FA in FIG24 is the operation process of the pixel circuit in the data refresh phase SX in FIG23 a.

[0282] In the embodiment of the present disclosure, when other refresh frequencies less than the maximum refresh frequency are adopted (for example, 1 Hz, 30 Hz, 60 Hz), a display frame corresponding to the pixel circuit includes a plurality of continuous sub-display frames, the first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames. The working process of the pixel circuit in a refresh sub-frame is the working process of the pixel circuit in a data refresh phase. For example, as shown in FIG25 , the pixel circuit has a refresh sub-frame fb1 and a hold sub-frame fb2 in a display frame FB. Among them, the working process of the pixel circuit in the refresh sub-frame fb1 in FIG25 is the working process of the pixel circuit in a data refresh phase SX in FIG23 a. The working process in the hold sub-frame fb2 is the same as the working process in the above-mentioned embodiment and will not be described in detail here.

[0283] The present disclosure provides some further signal timing diagrams of the display panel, as shown in Figures 23b to 23d, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0284] In some embodiments of the present disclosure, during a data refresh phase, the active level of the first reset control signal terminal includes at least one third active level, and a time period of the at least one third active level occurs before a time period of the active level of the compensation control signal terminal. For example, as shown in Figures 23b to 23d, taking the example of the active level (e.g., a low level) of the first reset control signal terminal RE1 including a third active level YX3, during a data refresh phase SX, a time period tyx3 of the third active level YX3 occurs before a time period tcf of the active level (e.g., a high level) of the compensation control signal cf.

[0285] For example, as shown in FIG. 23 b to FIG. 23 d , the third effective level YX3 is set in the fourth initialization auxiliary stage T8 .

[0286] For example, referring to Figures 7 and 23b to 23d, the third active level YX3 included in the first reset control signal terminal RE1 is set before the time period tcf of the active level (e.g., high level) of the compensation control signal cf, for example, during the fourth initialization auxiliary phase T8; and the fourth active level YX4 is set after the time period of the first active level YX1, for example, during the first initialization auxiliary phase T4 and / or the time period of the third initialization auxiliary phase T5. This ensures that the source and drain electrode potentials of the driver transistor are uniform before or after the data voltage is written. Similarly, the third reset control signal terminal RE3 can also adopt the same design as the first reset control signal terminal RE1, which will not be further described here. In some embodiments of the present disclosure, the active level of the second reset control signal terminal includes at least one sixth active level. For example, the active level of the second reset control signal terminal includes one, two, three, or more sixth active levels. Furthermore, in a data refresh phase, the time periods of all sixth active levels can occur after the time period of the active level of the compensation control signal terminal. For example, as shown in Figures 23b and 23c, taking the example that the effective level (such as a low level) of the second reset control signal terminal RE2 includes a sixth effective level YX6, in a data refresh phase SX, the time period tyx6 of the sixth effective level YX6 appears after the time period tcf of the effective level (such as a high level) of the compensation control signal cf.

[0287] For example, as shown in FIG. 23 b , the sixth effective level YX6 may be set in the third initialization auxiliary stage T5 .

[0288] For example, as shown in FIG. 23 c , the sixth effective level YX6 may be set in the first initialization auxiliary stage T4 .

[0289] For example, as shown in Figure 23d, taking the example that the effective level (such as low level) of the second reset control signal terminal RE2 includes two sixth effective levels YX6-1 and YX6-2, the sixth effective level YX6-1 can be set in the first initialization auxiliary stage T4, and the sixth effective level YX6-2 can be set in the third initialization auxiliary stage T5.

[0290] The present disclosure also provides a display panel. As shown in FIG26 , the display panel 100 includes: a plurality of pixel units arranged in an array. For example, each pixel unit includes a plurality of sub-pixels spx. Each sub-pixel spx includes any of the above-mentioned pixel circuits provided in the present disclosure. The principle of solving the problem of this display panel is similar to that of the aforementioned pixel circuit. Therefore, the implementation of this display panel can refer to the implementation of the aforementioned pixel circuit, and the repeated parts will not be repeated here.

[0291] In some embodiments of the present disclosure, as shown in FIG26 , the display panel 100 further includes: a plurality of scanning signal lines GAL; wherein one scanning signal line GAL among the plurality of scanning signal lines GAL is coupled to the first scanning signal terminal GA of the pixel circuit in a row of sub-pixels.

[0292] In some embodiments of the present disclosure, as shown in FIG26 , the display panel 100 further includes: a gate driving circuit 110, which is respectively coupled to a plurality of scanning signal lines GAL; wherein the gate driving circuit 110 is configured to input scanning signals to the plurality of scanning signal lines GAL.

[0293] In some embodiments of the present disclosure, as shown in FIG26 , the display panel 100 further includes: a plurality of compensation control signal lines CSL; wherein one compensation control signal line CSL among the plurality of compensation control signal lines CSL is coupled to the compensation control signal terminal CF of the pixel circuit in a row of sub-pixels.

[0294] In some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes: a compensation control driving circuit 130, which is respectively coupled to multiple compensation control signal lines CSL; wherein the compensation control driving circuit 130 is configured to input corresponding compensation control signals to the multiple compensation control signal lines CSL.

[0295] In some embodiments of the present disclosure, as shown in FIG26 , the display panel 100 further includes: a plurality of light-emitting control signal lines EML; wherein, one light-emitting control signal line EML among the plurality of light-emitting control signal lines EML is coupled to the light-emitting control signal terminal EM of the pixel circuit in a row of sub-pixels.

[0296] In some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes: a light-emitting driving circuit 120, which is respectively coupled to multiple light-emitting control signal lines EML; wherein the light-emitting driving circuit 120 is configured to input corresponding light-emitting control signals to the multiple light-emitting control signal lines EML.

[0297] In some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes: multiple first reset control signal lines REL1; wherein, one first reset control signal line REL1 among the multiple first reset control signal lines REL1 is coupled to the first reset control signal terminal RE1 of the pixel circuit in a row of sub-pixels.

[0298] In some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes: a first control circuit 140, which is respectively coupled to multiple first reset control signal lines REL1; wherein the first control circuit 140 is configured to input corresponding first reset control signals to the multiple first reset control signal lines REL1.

[0299] In some embodiments of the present disclosure, one first reset control signal line REL1 among the plurality of first reset control signal lines REL1 is coupled to the third reset control signal terminal RE3 of the pixel circuit in a row of sub-pixels.

[0300] In some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes: multiple second reset control signal lines REL2; wherein, one second reset control signal line REL2 among the multiple second reset control signal lines REL2 is coupled to the second reset control signal terminal RE2 of the pixel circuit in a row of sub-pixels.

[0301] In some embodiments of the present disclosure, as shown in Figure 26, the display panel 100 also includes: a second control circuit 160, which is respectively coupled to multiple second reset control signal lines REL2; wherein the second control circuit 160 is configured to input corresponding second reset control signals to the multiple second reset control signal lines REL2.

[0302] In some embodiments of the present disclosure, as shown in FIG26 , the display panel 100 further includes: a plurality of data lines DL and a plurality of first power lines VDDL. The plurality of data lines DL and the plurality of first power lines VDDL extend along the columns of sub-pixels. Optionally, one of the plurality of data lines DL is coupled to a data signal terminal DA of a pixel circuit in a column of sub-pixels. One of the plurality of first power lines VDDL is coupled to a first power terminal VDD of a pixel circuit in a column of sub-pixels.

[0303] In some embodiments of the present disclosure, as shown in FIG26 , the display panel 100 further includes: a source driver circuit 150. The source driver circuits 150 are respectively coupled to a plurality of data lines DL. For example, the source driver circuit 150 can be set to one. Alternatively, the source driver circuit can also be set to two, wherein one source driver circuit is connected to half the number of data lines DL, and the other source driver circuit is connected to the other half of the number of data lines DL. Of course, the source driver circuits can also be set to three, four, or more, which can be designed and determined according to the needs of actual applications, and the present disclosure does not limit this.

[0304] In the embodiment of the present disclosure, a thin film transistor (TFT) can be prepared on the array substrate of the display panel using the Gate Driver on Array (GOA) technology to form a gate drive circuit 110, a light-emitting drive circuit 120, a compensation control circuit 130, a first control circuit 140, and a second control circuit 160. In this way, the gate drive circuit 110, the light-emitting drive circuit 120, the compensation control circuit 130, the first control circuit 140, and the second control circuit 160 are all equivalent to GOA circuits. In addition, in the embodiment of the present disclosure, by sharing the signal end of the pixel circuit, only five groups of GOA circuits are required, that is, the operation of the pixel circuit can be controlled. This can reduce the number of GOA circuits, which is conducive to achieving a narrow frame.

[0305] In some embodiments of the present disclosure, in a data refresh phase, the multiple valid levels in the first scanning signal terminal of the pixel circuit include at least one second valid level; when the time period of at least one second valid level in the at least one second valid level occurs after the time period of the valid level of the compensation control signal terminal, the time period of the second valid level corresponding to the pixel circuit in the nth row of sub-pixels overlaps with the time period of the first valid level corresponding to the pixel circuit in the n+mth row of sub-pixels, where n is an integer and n>0, and m is an integer and m>0.

[0306] For example, taking m=2 as an example, when the pixel circuit is driven at the maximum refresh frequency (e.g., 120 Hz), the signal timing diagrams corresponding to the sub-pixels in the nth row to the sub-pixels in the n+2th row are shown in Figures 27 and 29. In Figures 27 and 29, em_n represents the light-emitting control signal corresponding to the pixel circuit in the nth row of sub-pixels, cf_n represents the compensation control signal corresponding to the pixel circuit in the nth row of sub-pixels, re1_n represents the first reset control signal corresponding to the pixel circuit in the nth row of sub-pixels, re2_n represents the second reset control signal corresponding to the pixel circuit in the nth row of sub-pixels, re3_n represents the third reset control signal corresponding to the pixel circuit in the nth row of sub-pixels, and ga_n represents the scan signal corresponding to the pixel circuit in the nth row of sub-pixels. em_n+1 represents the light-emitting control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, cf_n+1 represents the compensation control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, re1_n+1 represents the first reset control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, re2_n+1 represents the second reset control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, re3_n+1 represents the third reset control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, and ga_n+1 represents the scanning signal corresponding to the pixel circuit in the n+1th row of sub-pixels. em_n+2 represents the light emission control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, cf_n+2 represents the compensation control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, re1_n+2 represents the first reset control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, re2_n+2 represents the second reset control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, re3_n+2 represents the third reset control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, and ga_n+2 represents the scan signal corresponding to the pixel circuit in the sub-pixel in the n+2th row. As shown in Figures 27 and 29, the time period tyx2 of the second active level YX2 corresponding to the pixel circuit in the nth row overlaps with the time period tyx1 of the first active level YX1 corresponding to the pixel circuit in the n+2th row. In this way, for the sub-pixels in the same column, the first electrode of the driving transistor M0 of the pixel circuit in the sub-pixel in the nth row can be biased by the data voltage corresponding to the pixel circuit in the sub-pixel in the n+2th row, so that the bias state of the first electrode of the driving transistor M0 changes with the change of the data voltage, thereby improving the characteristic stability of the driving transistor M0.

[0307] Exemplarily, m may be 1, 3, 4, 5, or more, which is not limited here.

[0308] For example, taking m=2 as an example, when the pixel circuit is driven to operate at a refresh frequency lower than the maximum refresh frequency (e.g., 1 Hz, 30 Hz, or 60 Hz), the signal timing diagrams corresponding to the sub-pixels in the nth row to the sub-pixels in the (n+2)th row are shown in FIG28 and FIG30. In FIG28 and FIG30, em_n represents the light-emitting control signal corresponding to the pixel circuit in the sub-pixels in the nth row, cf_n represents the compensation control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re1_n represents the first reset control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re2_n represents the second reset control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re3_n represents the third reset control signal corresponding to the pixel circuit in the sub-pixels in the nth row, and ga_n represents the scan signal corresponding to the pixel circuit in the sub-pixels in the nth row. em_n+1 represents the light-emitting control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, cf_n+1 represents the compensation control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, re1_n+1 represents the first reset control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, re2_n+1 represents the second reset control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, re3_n+1 represents the third reset control signal corresponding to the pixel circuit in the n+1th row of sub-pixels, and ga_n+1 represents the scanning signal corresponding to the pixel circuit in the n+1th row of sub-pixels. em_n+2 represents the light emission control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, cf_n+2 represents the compensation control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, re1_n+2 represents the first reset control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, re2_n+2 represents the second reset control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, re3_n+2 represents the third reset control signal corresponding to the pixel circuit in the sub-pixel in the n+2th row, and ga_n+2 represents the scan signal corresponding to the pixel circuit in the sub-pixel in the n+2th row. As shown in Figures 28 and 30, the time period tyx2 of the second active level YX2 corresponding to the pixel circuit in the nth row overlaps with the time period tyx1 of the first active level YX1 corresponding to the pixel circuit in the n+2th row. In this way, for the sub-pixels in the same column, the first electrode of the driving transistor M0 of the pixel circuit in the sub-pixel in the nth row can be biased by the data voltage corresponding to the pixel circuit in the sub-pixel in the n+2th row, so that the bias state of the first electrode of the driving transistor M0 changes with the change of the data voltage, thereby improving the characteristic stability of the driving transistor M0.

[0309] Exemplarily, m may be 1, 3, 4, 5, or more, which is not limited here.

[0310] In some embodiments of the present disclosure, in a data refresh phase, the multiple valid levels in the first scanning signal terminal of the pixel circuit include at least one second valid level; in a data refresh phase, when the time period of at least one second valid level of the at least one second valid level occurs before the time period of the valid level of the compensation control signal terminal, the time period of the second valid level corresponding to the pixel circuit in the qth row of sub-pixels overlaps with the time period of the first valid level corresponding to the pixel circuit in the qkth row of sub-pixels, where q is an integer and q>0, and k is an integer and k>0.

[0311] For example, when the pixel circuit is driven at the maximum refresh rate (e.g., 120 Hz), the signal timing diagrams corresponding to the sub-pixels in the nth row to the (n+2)th row are shown in Figures 31 and 33. In Figures 31 and 33, em_n represents the light-emitting control signal corresponding to the pixel circuit in the sub-pixels in the nth row, cf_n represents the compensation control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re1_n represents the first reset control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re2_n represents the second reset control signal corresponding to the pixel circuit in the nth row, re3_n represents the third reset control signal corresponding to the pixel circuit in the nth row, and ga_n represents the scan signal corresponding to the pixel circuit in the nth row. em_n-k represents the light emission control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, cf_n-k represents the compensation control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, re1_n-k represents the first reset control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, re2_n-k represents the second reset control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, re3_n-k represents the third reset control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, and ga_n-k represents the scan signal corresponding to the pixel circuit in the nk-th row of sub-pixels. As shown in Figures 31 and 33, the time period tyx2 of the second active level YX2 corresponding to the pixel circuit in the n-th row of sub-pixels overlaps with the time period tyx1 of the first active level YX1 corresponding to the pixel circuit in the nk-th row of sub-pixels. Thus, for sub-pixels in the same column, the first electrode of the driving transistor M0 in the pixel circuit in the n-th row of sub-pixels can be biased by the data voltage corresponding to the pixel circuit in the nk-th row of sub-pixels. This allows the bias state of the first electrode of the driving transistor M0 to change with changes in the data voltage, thereby improving the characteristic stability of the driving transistor M0.

[0312] Exemplarily, k may be 1, 2, 3, 4, 5, or more, which is not limited here.

[0313] For example, when the pixel circuit is driven to operate at a refresh rate lower than the maximum refresh rate (e.g., 1 Hz, 30 Hz, or 60 Hz), the signal timing diagrams corresponding to the sub-pixels in the nth row to the (n+2)th row are shown in FIG32 and FIG34. In FIG32 and FIG34, em_n represents the light emission control signal corresponding to the pixel circuit in the sub-pixels in the nth row, cf_n represents the compensation control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re1_n represents the first reset control signal corresponding to the pixel circuit in the sub-pixels in the nth row, re2_n represents the second reset control signal corresponding to the pixel circuit in the nth row, re3_n represents the third reset control signal corresponding to the pixel circuit in the nth row, and ga_n represents the scan signal corresponding to the pixel circuit in the nth row. em_n-k represents the light emission control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, cf_n-k represents the compensation control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, re1_n-k represents the first reset control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, re2_n-k represents the second reset control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, re3_n-k represents the third reset control signal corresponding to the pixel circuit in the nk-th row of sub-pixels, and ga_n-k represents the scan signal corresponding to the pixel circuit in the nk-th row of sub-pixels. As shown in Figures 32 and 34, the time period tyx2 of the second active level YX2 corresponding to the pixel circuit in the n-th row of sub-pixels overlaps with the time period tyx1 of the first active level YX1 corresponding to the pixel circuit in the nk-th row of sub-pixels. Thus, for sub-pixels in the same column, the first electrode of the driving transistor M0 of the pixel circuit in the n-th row of sub-pixels can be biased by the data voltage corresponding to the pixel circuit in the nk-th row of sub-pixels, so that the bias state of the first electrode of the driving transistor M0 changes with changes in the data voltage, thereby improving the characteristic stability of the driving transistor M0.

[0314] Exemplarily, k may be 1, 2, 3, 4, 5, or more, which is not limited here.

[0315] In some embodiments of the present disclosure, the time period of the effective level of the compensation control signal terminal of the pixel circuit in the sub-pixel in the sth row includes the time period of the first effective level corresponding to the pixel circuit in the sth to sath rows, a is an integer and a>0. Exemplarily, a can be 1, 2, 3, 4, 5, or more, which is not limited here. For example, as shown in Figures 27 and 28, the time period tcf of the effective level of the compensation control signal cf of the pixel circuit in the sub-pixel in the n+2th row includes the time period tyx1 of the first effective level YX1 corresponding to the pixel circuit in the n+2th to nth rows, a is an integer and a>0.

[0316] In some embodiments of the present disclosure, the time period tcf of the active level of the compensation control signal terminal CF of the pixel circuit in the s-th row of sub-pixels includes the time period tyx1 of the first active level YX1 corresponding to the pixel circuits in the s-th row to the s+b-th row, where b is an integer and b>0. Exemplarily, b can be 1, 2, 3, 4, 5, or more, which is not limited here. For example, as shown in Figures 29 and 30, the time period tcf of the active level of the compensation control signal cf of the pixel circuit in the n-th row of sub-pixels includes the time period tyx1 of the first active level YX1 corresponding to the pixel circuits in the n-th row to the n+1-th row.

[0317] The present disclosure also provides a display device, as shown in FIG26 . The display device may include a display panel 100 and a timing controller 200. For example, the timing controller 200 may receive display data of an image to be displayed for a display frame and input corresponding control signals to the gate driver circuit 110, the light driver circuit 120, the compensation control circuit 130, the first control circuit 140, and the second control circuit 160, respectively. This causes the gate driver circuit 110 to output a corresponding scan signal to the scan signal line GAL, the light driver circuit 120 to output a corresponding light control signal to the light control signal line EML, the compensation control circuit 130 to output a corresponding compensation control signal to the compensation control signal line CSL, the first control circuit 140 to output a corresponding first reset control signal to the first reset control signal line REL1, and the second control circuit 160 to output a corresponding second reset control signal to the second reset control signal line REL2. Furthermore, the timing controller 200 may process the received display data and send the processed data to the source driver circuit 150. The source driving circuit 150 can input corresponding data voltages to the data lines DL according to the received display data, so that the pixel circuits can input corresponding data voltages to realize the picture display function of the display frame.

[0318] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0319] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0320] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A pixel circuit, include: Light emitting device; a driving transistor configured to generate a driving current for driving the light emitting device to emit light according to a data voltage; a light emitting control circuit, coupled to the driving transistor, configured to provide the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, so as to drive the light emitting device to emit light; A data writing circuit is coupled to the first electrode of the driving transistor and is configured to operate in response to a plurality of valid levels of the first scanning signal terminal that appear at intervals in a data refresh phase; a threshold compensation circuit coupled to the driving transistor and configured to input a threshold voltage of the driving transistor into a gate of the driving transistor in response to an effective level of a compensation control signal terminal; Among them, in a data refresh phase, the time period of the invalid level of the light-emitting control signal terminal includes the time period of the valid level of the compensation control signal terminal and the time period of the valid level of the first scanning signal terminal, and the valid level in the first scanning signal terminal includes at least one first valid level and at least one second valid level, and the time period of the valid level of the compensation control signal terminal includes the time period of the first valid level.

2. The pixel circuit according to claim 1, in, In one of the data refresh phases, the at least one second effective level time period occurs after the effective level time period of the compensation control signal terminal.

3. The pixel circuit according to claim 1 or 2, in, In one of the data refresh phases, the time period of the at least one second effective level occurs before the time period of the effective level of the compensation control signal terminal.

4. The pixel circuit according to any one of claims 1 to 3, in, The pixel circuit further includes: a first initialization circuit, the first initialization circuit being coupled to the first electrode of the driving transistor; The first initialization circuit is configured to respond to the first reset control in a data refresh phase. at least one effective level of the control signal terminal, and providing the signal of the first initialization signal terminal to the first electrode of the driving transistor; In which, in a data refresh phase, the time period of the invalid level of the light-emitting control signal terminal also includes the time period of the valid level of the first reset control signal terminal; and the time period of the valid level of the first reset control signal terminal and the time periods of multiple valid levels in the first scanning signal terminal do not have overlapping durations.

5. The pixel circuit according to claim 4, in, The effective level of the first reset control signal terminal includes at least one third effective level; In a data refresh phase, the at least one third effective level time period occurs after a plurality of effective level time periods in the first scan signal terminal.

6. The pixel circuit according to claim 4 or 5, in, The effective level of the first reset control signal terminal includes at least one fourth effective level; In a data refresh phase, the time period of the effective level of the compensation control signal terminal includes the time period of the fourth effective level, and the time period of the fourth effective level occurs before the time period of the first effective level of the first scan signal terminal.

7. The pixel circuit according to any one of claims 1 to 6, in, The pixel circuit further includes: a second initialization circuit, the second initialization circuit being coupled to the second electrode of the driving transistor; The second initialization circuit is configured to provide a signal of the second initialization signal terminal to the second electrode of the driving transistor in response to at least one valid level of the second reset control signal terminal; Among them, in a data refresh phase, the time period of the invalid level of the light-emitting control signal terminal includes the time period of the valid level of the second reset control signal terminal; and the time period of the valid level of the second reset control signal terminal and the time periods of multiple valid levels in the first scanning signal terminal do not have overlapping durations.

8. The pixel circuit according to claim 7, in, The effective level of the second reset control signal terminal includes at least one fifth effective level; In a data refresh phase, the time period of the effective level of the compensation control signal terminal includes the time period of the at least one fifth effective level, and the time period of the at least one fifth effective level The segment occurs before a time period of the at least one first active level of the first scanning signal terminal.

9. The pixel circuit according to claim 8, in, In a data refresh phase, the time period of the fifth effective level occurs before or after the time period of the fourth effective level of the first reset control signal terminal.

10. The pixel circuit according to any one of claims 7 to 9, in, The effective level of the second reset control signal terminal includes at least one sixth effective level; In a data refresh phase, the at least one sixth effective level time period occurs after or before the effective level time period of the compensation control signal terminal.

11. The pixel circuit according to any one of claims 1 to 10, in, The pixel circuit further includes: a third initialization circuit, the third initialization circuit being coupled to the light emitting device; The third initialization circuit is configured to provide a signal at a third initialization signal terminal to the light emitting device in response to an active level of a third reset control signal terminal.

12. The pixel circuit according to claim 11, in, One of the compensation control signal terminal, the first scanning signal terminal, the first reset control signal terminal and the second reset control signal terminal and the third reset control signal terminal are the same signal terminal.

13. The pixel circuit according to any one of claims 1 to 12, in, A display frame corresponding to the pixel circuit includes a refresh subframe and a hold subframe, and the working process of the pixel circuit in the refresh subframe is the working process of the pixel circuit in a data refresh phase.

14. The pixel circuit according to claim 13, in, The compensation control signal terminal is at an invalid level in the holding subframe; The light emitting control signal terminal has an invalid level and a valid level in at least one of the holding subframes; The first scanning signal terminal has an inactive level and an active level in at least one of the holding subframes.

15. The pixel circuit according to claim 14, in, The first reset control signal terminal has an invalid level and a valid level in at least one of the holding subframes; Alternatively, the first reset control signal terminal is at an invalid level in the holding subframe.

16. The pixel circuit according to claim 14 or 15, in, The second reset control signal terminal has an invalid level and a valid level in at least one of the holding subframes; Alternatively, the second reset control signal terminal is at an invalid level in the holding subframe.

17. The pixel circuit according to any one of claims 14 to 16, in, The third reset control signal terminal has an invalid level and a valid level in at least one of the holding subframes; Alternatively, the third reset control signal terminal is at an invalid level in the holding subframe.

18. The pixel circuit according to any one of claims 1 to 17, in, The data writing circuit comprises: a first transistor; a gate of the first transistor is coupled to the first scanning signal terminal, a first electrode of the first transistor is coupled to the data signal terminal, and a second electrode of the first transistor is coupled to the first electrode of the driving transistor; The threshold compensation circuit includes: a second transistor and a storage capacitor; the gate of the second transistor is coupled to the compensation control signal terminal, the first electrode of the second transistor is coupled to the gate of the driving transistor, and the second electrode of the second transistor is coupled to the second electrode of the driving transistor; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the first power supply terminal; The light emitting control circuit comprises: a third transistor and a fourth transistor; a gate of the third transistor is coupled to the light emitting control signal terminal, a first electrode of the third transistor is coupled to the first power supply terminal, a second electrode of the third transistor is coupled to the first electrode of the driving transistor, a gate of the fourth transistor is coupled to the light emitting control signal terminal, a first electrode of the fourth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the light emitting device; The first initialization circuit includes: a fifth transistor; a gate of the fifth transistor is coupled to the first reset control signal terminal, a first electrode of the fifth transistor is coupled to the first initialization signal terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the driving transistor; A second initialization circuit: a sixth transistor; a gate of the sixth transistor is coupled to the second reset control signal terminal, a first electrode of the sixth transistor is coupled to the second initialization signal terminal, and a second electrode of the sixth transistor is coupled to the second electrode of the driving transistor; The third initialization circuit: a seventh transistor; a gate of the seventh transistor and the third A reset control signal terminal is coupled, a first electrode of the seventh transistor is coupled to the third initialization signal terminal, and a second electrode of the seventh transistor is coupled to the light emitting device.

19. A pixel circuit, include: Light emitting device; a driving transistor configured to generate a driving current for driving the light emitting device to emit light according to a data voltage; a light emitting control circuit, coupled to the driving transistor, configured to provide the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, so as to drive the light emitting device to emit light; A functional circuit, coupled to the driving transistor, is configured to operate in response to a plurality of valid levels of the second scanning signal terminal that appear at intervals from each other during a data refresh phase; a threshold compensation circuit coupled to the driving transistor and configured to input a threshold voltage of the driving transistor into a gate of the driving transistor in response to an effective level of a compensation control signal terminal; In which, in a data refresh phase, the time period of the invalid level of the light-emitting control signal terminal includes the time period of the valid level of the compensation control signal terminal and the time period of the valid level of the second scanning signal terminal, and the valid level in the second scanning signal terminal includes at least one seventh valid level and at least one eighth valid level, and the time period of the valid level of the compensation control signal terminal does not overlap with the time period of at least one eighth valid level.

20. The pixel circuit according to claim 19, in, The time period of the effective level of the compensation control signal terminal includes the time period of the seventh effective level.

21. The pixel circuit according to claim 19 or 20, in, In one of the data refresh phases, the at least one eighth effective level time period occurs before or after the effective level time period of the compensation control signal terminal.

22. A display panel, include: Multiple sub-pixels; Each of the plurality of sub-pixels comprises a pixel circuit as described in any one of claims 1-21.

23. The display panel according to claim 22, in, In a data refresh phase, the plurality of valid levels in the first scan signal terminal of the pixel circuit include at least one second valid level; When the time period of at least one of the at least one second effective level occurs after the time period of the effective level at the compensation control signal end, the time period of the second effective level corresponding to the pixel circuit in the nth row of sub-pixels overlaps with the time period of the first effective level corresponding to the pixel circuit in the n+mth row of sub-pixels, where n is an integer and n>0, and m is an integer and m>0.

24. The display panel according to claim 22 or 23, in, In a data refresh phase, the plurality of valid levels in the first scan signal terminal of the pixel circuit include at least one second valid level; In one of the data refresh phases, when the time period of at least one of the at least one second effective level occurs before the time period of the effective level of the compensation control signal end, the time period of the second effective level corresponding to the pixel circuit in the qth row of sub-pixels overlaps with the time period of the first effective level corresponding to the pixel circuit in the qkth row of sub-pixels, where q is an integer and q>0, and k is an integer and k>0.

25. The display panel according to any one of claims 22 to 24, in, The time period of the effective level of the compensation control signal terminal of the pixel circuit in the sth row of sub-pixels includes the time period of the first effective level corresponding to the pixel circuit in the sth row to the sath row, a is an integer and a>0.

26. The display panel according to any one of claims 22 to 25, in, The effective level time period of the compensation control signal terminal of the pixel circuit in the sth row of sub-pixels includes the first effective level time period corresponding to the pixel circuit in the sth row to the s+bth row, where b is an integer and b>0.

27. A display device comprising the display panel according to any one of claims 22 to 26.

28. A driving method for a pixel circuit as claimed in any one of claims 1 to 18, include: Data refresh phase; The data refresh phase includes: In the data threshold compensation stage, the data writing circuit operates in response to the first effective level of the first scanning signal terminal; the threshold compensation circuit inputs the threshold voltage of the driving transistor into the gate of the driving transistor in response to the effective level of the compensation control signal terminal; In a first initialization auxiliary stage, the data writing circuit operates in response to a second effective level of the first scanning signal terminal; In the light emitting stage, the light emitting control circuit provides the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, so as to drive the light emitting device to emit light.

29. A driving method for a pixel circuit according to any one of claims 1 to 18, include: In a second initialization auxiliary stage, the data writing circuit operates in response to a second effective level of the first scanning signal terminal; In the data threshold compensation stage, the data writing circuit operates in response to the first effective level of the first scanning signal terminal; The threshold compensation circuit inputs the threshold voltage of the driving transistor into the gate of the driving transistor in response to the effective level of the compensation control signal terminal; In the light emitting stage, the light emitting control circuit provides the driving current generated by the driving transistor to the light emitting device in response to the effective level of the light emitting control signal terminal, so as to drive the light emitting device to emit light.

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