Descriptor-based PCIe bus DMA high-speed data transmission method and device

Abstract

The present invention provides a descriptor-based PCIe bus DMA high-speed data transmission method and device, the device includes a DMA module, the DMA module includes: a packet receiving unit, a packet sending unit, a tag queue unit, a RAM and a descriptor FIFO unit; the descriptor FIFO unit is connected to the packet receiving unit and stores the descriptor received from the packet receiving unit; the descriptor FIFO unit is connected to the packet sending unit, and the packet sending unit obtains the request data address and the request data length based on the analysis of the descriptor in the descriptor FIFO unit; the tag queue unit is connected to the packet receiving unit and the packet sending unit; the RAM is connected to the packet sending unit and the packet receiving unit; the packet sending unit and the packet receiving unit are respectively connected to the PCIe bus. This solution reduces the CPU intervention time, effectively improves the data moving efficiency, improves the utilization rate of the bus bandwidth and the utilization rate of the RAM, saves hardware resources while ensuring performance, and can cope with different transmission scenarios.

Description

Technical Field

[0001] The present invention relates to the field of point data transmission processing, integrated circuits and PCIe bus data control, and in particular to a descriptor-based PCIe bus DMA high-speed data transmission method and device, which can be applied to data handling and transmission scenarios of various different complex scenarios to achieve high-speed data transmission. Background Art

[0002] PCIe (PCI-Express) bus is the third generation high-speed I / O interface bus, and has become an important interface on servers and PCs. In recent years, PCIe bus technology has been increasingly used in many high-performance, low-latency integrated systems. Using DMA (Direct Memorty Access) to move data between I / O and memory is a common data transmission method that can minimize CPU load and speed up data transmission.

[0003] As chip integration becomes increasingly larger, the amount of interactive data becomes larger and more complex, and the data movement rate requirements become higher and higher. DMA movement increasingly uses descriptor linked lists to control DMA to move data, further reducing the time for the CPU to configure DMA internal registers and obtain DMA completion status.

[0004] Frequent configuration and interruption will increase CPU load and channel throughput, increasing the delay time of data transfer. In the prior art, the DMA channel is completely idle during each descriptor reading and waiting for descriptor reply, each data reading and waiting for data reply, which will waste bus bandwidth and increase data transmission delay.

[0005] At the same time, DMA transfer often faces more complex scenarios, such as switching between different bus protocols, writing scattered data to continuous addresses or continuous data to scattered addresses, etc. When facing complex application scenarios, the standard linked list mode in the existing technology cannot optimize the transmission for different scenarios, which will affect the transmission efficiency. Summary of the invention

[0006] In view of this, in order to solve at least some of the problems existing in the above-mentioned prior art, the present invention provides the following technical solutions:

[0007] First, the present invention provides a descriptor-based PCIe bus DMA high-speed data transmission method, the method comprising:

[0008] S1. After completing the first descriptor address configuration and DMA startup, DMA actively initiates a descriptor read request;

[0009] S2, the host returns a descriptor based on the descriptor read request, the DMA parses the descriptor content, initiates a data read request according to the source data address in the descriptor content, and simultaneously initiates a next descriptor read request according to the next descriptor address in the descriptor content; the descriptor is received by the DMA in the form of a descriptor message;

[0010] S3. After receiving the message, DMA determines whether it is a descriptor message or a data message; if it is a descriptor message, the descriptor is stored in the descriptor FIFO unit in DMA, waiting for the next step of parsing; if it is a data message, the tag in the data message is matched with the tag in the RAM set in DMA, and the data content in the data message is stored in RAM after the match is successful; the tag is managed and allocated by the tag queue unit set in DMA;

[0011] S4. If the descriptor FIFO unit is full, or the current descriptor is the last descriptor in the linked list, stop initiating the next descriptor read request; otherwise, continue initiating the next descriptor read request and execute S3.

[0012] Preferably, in S1, when DMA initiates a descriptor read request, the tag queue unit configures a fixed tag for the corresponding descriptor to form a descriptor-specific tag.

[0013] Preferably, in S2, when DMA initiates a data read request, a packet sending unit arranged in DMA applies for tags from the tag queue unit in the order of data read requests, and assembles the tags into a data read request message and sends it to the PCIe bus.

[0014] Preferably, the RAM is divided into a plurality of storage units, and the tag queue unit is a tag assigned to a read data request, and is set in one-to-one correspondence with a storage unit in the RAM;

[0015] The tag queue unit stores the tag value and its corresponding RAM start address;

[0016] Each of the storage units is provided with a ram_valid flag to mark whether the storage unit is empty.

[0017] Preferably, when DMA finishes parsing the descriptor and is ready to initiate a data read request to the source address, it applies for an idle tag from the tag queue unit and reports the length of the data read this time;

[0018] Based on the starting address in the RAM corresponding to the requested free tag and the data length, the ending address is calculated and stored in the register temporarily; the register is updated based on the ending address of the data currently to be read in the RAM, that is, the ending address of the data currently to be read in the RAM is stored.

[0019] Preferably, if the termination address is greater than the maximum address of the RAM, starting from the first tag in the tag queue unit, it is determined in turn whether there are released tags and corresponding storage units; if so, the released tags and corresponding storage units are reallocated; if not, the construction of the read data request is stopped, and the tag value at this time is recorded in the tag_max register.

[0020] Preferably, if all tags in the tag queue unit are used up, starting from the first tag in the tag queue unit, determine in turn whether there are released tags and corresponding storage units. If there are released tags and the storage space of the storage unit is sufficient, continue to send read data requests, otherwise suspend sending read data requests and record the tag value at this time in the tag_max register.

[0021] Preferably, when DMA sends a write request to the destination address, it sequentially determines whether the ram_valid flag in the storage unit in the RAM is valid. If it is valid, the data in the corresponding storage unit is read out, and the ram_valid flag is cleared. At the same time, it determines whether the tag value corresponding to the read storage unit is equal to the value in the tag_max register. If they are equal, a new round of reading cycle starts from the storage unit corresponding to the first tag value in the tag queue unit. If they are not equal, the reading of the next storage unit continues.

[0022] Preferably, the content of the descriptor initialization includes: DMA transfer status, DMA transfer control, next descriptor address, descriptor availability, start and end conditions, source data address, and destination data address.

[0023] Preferably, the step S1 also includes initializing the descriptor, and the initialization includes at least one of the following types:

[0024] Type 1: a source descriptor is set for the source data address, and a destination descriptor is set for the destination data address. If the source data address in the source descriptor is valid, the destination data address is ignored. If the destination data address in the destination descriptor is valid, the source data address is ignored; or

[0025] Type 2: Set the source descriptor on the source data side and write it into the continuous address space on the destination side; or

[0026] Type 3: Set the destination descriptor on the destination data side to control the data write operation, use the continuous address space on the source data side, and configure the first address of the data to be read in the DMA register; or

[0027] Type 4: Set a common descriptor, write the source data address and the destination data address into the common descriptor at the same time, and DMA can obtain the source data address and the destination data address at the same time by reading the common descriptor.

[0028] Preferably, in type one, the DMA register is configured during initialization, the first source descriptor address is written into the source address register, and the first destination descriptor address is written into the destination address register; the DMA reads the first source descriptor and the first destination descriptor according to the initial address for processing, and initiates a read data request.

[0029] Preferably, in the type two, the destination address in the source descriptor is invalid; the DMA register is configured during initialization, the first source descriptor address is written into the source address register, and the destination address register is written into the first address of the continuous address space; the DMA reads the first source descriptor for processing, and initiates a read data request, and the read data is written according to the first address of the continuous address space of the destination address register.

[0030] Preferably, in the type three, the source address in the destination descriptor is invalid; the DMA register is configured during initialization, the first destination descriptor address is written into the destination address register, and the source address register is written into the starting address of the continuous address space; the DMA reads the first destination descriptor for processing, and initiates a read data request, the host returns the DMA according to the starting address of the continuous address space in the source address register, and writes according to the destination address in the destination descriptor.

[0031] Preferably, in the type 4, the DMA register is configured during initialization, the address of the first common descriptor is written into the source address register, and the destination address register is invalid.

[0032] Secondly, the present invention also provides a descriptor-based PCIe bus DMA high-speed data transmission device, the device includes a DMA module, the DMA module includes: a packet receiving unit, a packet sending unit, a tag queue unit, a RAM and a descriptor FIFO unit;

[0033] The descriptor FIFO unit is connected to the packet receiving unit and stores the descriptors received from the packet receiving unit; the descriptor FIFO unit is connected to the packet sending unit, and the packet sending unit obtains the request data address and the request data length based on the analysis of the descriptor in the descriptor FIFO unit;

[0034] The tag queue unit is used for tag management and allocation; the tag queue unit is connected to the packet receiving unit and the packet sending unit;

[0035] The RAM is used to store data in the data message, and the RAM is connected to the packet sending unit and the packet receiving unit;

[0036] The packet sending unit and the packet receiving unit are respectively connected to the PCIe bus;

[0037] The DMA module is used to execute the descriptor-based PCIe bus DMA high-speed data transmission method as described above.

[0038] Compared with the prior art, this solution has at least the following beneficial effects:

[0039] 1. This solution uses a linked list descriptor to control DMA data movement, which reduces CPU intervention time and effectively improves data movement efficiency.

[0040] 2. This solution adopts the descriptor prefetching method, which saves the time of fetching the next descriptor and waiting for the return after the previous descriptor is completed, and improves the utilization of bus bandwidth.

[0041] 3. This solution can support the simultaneous sending of up to 16 read data messages, which improves the utilization of the bus and avoids bandwidth waste caused by factors such as bus delay. At the same time, the tag management method used has no fixed mapping relationship with the data RAM storage address, which improves the utilization rate of RAM and saves hardware resources while ensuring performance.

[0042] 4. This solution supports 4 different modes of DMA descriptor transmission, which can cope with different transmission scenarios. For the case of continuous addresses when reading or writing data on the source or destination side, descriptor configuration is not performed to avoid multiple descriptor readings affecting the transmission rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 It is a block diagram of the internal structure of a DMA controller according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of tag queue management and data RAM management according to an embodiment of the present invention;

[0046] Figure 3This is a schematic diagram of SG mode type 1 according to an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of SG mode type 2 according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of SG mode type 3 according to an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of SG mode type 4 according to an embodiment of the present invention;

[0050] Figure 7 The structure and data transmission path of the DMA module in the NTB according to the embodiment of the present invention;

[0051] Figure 8 The figure is a schematic diagram of a method flow of an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Those skilled in the art should know that the following specific embodiments or specific implementations are a series of optimized settings listed by the present invention to further explain the specific content of the invention, and these settings can be combined or used in association with each other, unless the present invention clearly states that some or a specific embodiment or implementation cannot be associated or used together with other embodiments or implementations. At the same time, the following specific embodiments or implementations are only used as the most optimized settings, and are not to be understood as limiting the scope of protection of the present invention.

[0054] The purpose of the present invention is to provide a descriptor-based PCIe bus DMA high-speed data transmission solution, such as a DMA communication method for a PCIE4.0 X4 channel. The present invention adopts a descriptor to control DMA data transmission, maximizes the use of channel bandwidth, improves data movement flow, and reduces CPU load.

[0055] Combination Figure 1As shown, in this embodiment, the DMA controller structure mainly includes a packet receiving unit, a packet sending unit, a descriptor FIFO, a tag queue unit and a RAM, which realizes the management and control of descriptors and completes the rapid data transmission of multiple modes. Of course, in a more preferred embodiment, the DMA controller can further include a DMA state machine unit, a DMA state judgment unit and a register analysis unit. These three units are used to realize the most basic DMA functions.

[0056] Combination Figure 1 , Figure 2 As shown, the PCIe bus uses the transaction ID and tag field to mark a unique transfer event. The transaction ID is a fixed value for DMA, while the tag field is used to assign a unique label to the read transaction. The linked list descriptor adopted in this solution uses a proprietary tag label. After the CPU completes the configuration of the first descriptor address and starts DMA, DMA will actively initiate a descriptor read request. The host will address and return the first descriptor content according to the read request message. DMA will parse the first descriptor content, initiate a read data request according to the source data address in the descriptor, and initiate a read descriptor request again according to the address of the next descriptor in the descriptor. In this embodiment, the behavior of initiating a read descriptor again when the previous descriptor has not been processed is called descriptor prefetching. This solution supports prefetching of up to 3 descriptors. The prefetching of descriptors is related to the time when the host returns the data message. Even if the host does not respond to the request to read data initiated after the DMA parses the descriptor, the DMA can still initiate a request to read the descriptor. Each prefetched descriptor will be stored in the FIFO (First In First Out) in order and wait for the next step of processing until the FIFO is full or the current descriptor is the last descriptor item in the linked list. Due to the first-in-first-out feature of the FIFO, the parsing order of the descriptors can be guaranteed not to be disrupted. In this embodiment, the FIFO that stores the descriptors is an independently set descriptor FIFO unit. The descriptor prefetching method can effectively save the waiting time from the completion of a descriptor to the waiting time for the next descriptor to be retrieved.

[0057] For data transmission, DMA supports up to 32 tags (i.e., tags), which are marked in the order of data read requests. It is understandable that tags can be arranged in order, and when the last tag is used up, the tags can be released based on different usage requirements and scenarios. When reading data, DMA can initiate the next data read request without waiting for the previous read request data to return, until all tags are used up or the internal data storage space is exhausted, which effectively improves the utilization of the bus and avoids bandwidth waste caused by factors such as bus delay.

[0058] Because the PCIe bus supports out-of-order returns between different tags and unpacked returns between the same tag, in this embodiment, a tag management queue (i.e., tag queue unit) and a data storage RAM (Random Access Memory) are also provided inside the DMA controller to maintain the read and write order of DMA. Figure 1 The basic logic block diagram of the DMA controller of this solution is shown. The DMA controller includes a packet receiving unit, a descriptor FIFO, a packet sending unit, a tag queue unit and a RAM, wherein the packet sending unit and the packet receiving unit are respectively connected to the PCIe bus.

[0059] The packet receiving unit is responsible for receiving the message signal returned by the PCIe bus. If the received message signal is a descriptor return message signal, the descriptor in the data message received by the bus is stored in the descriptor FIFO. According to the above, the descriptor FIFO can be implemented using the existing FIFO in the DMA. In this case, the depth of the existing FIFO in the DMA is 4. Therefore, in general use, considering the actual data storage and usage requirements, this embodiment stores 3 descriptors. Therefore, in this example, pre-fetching of 3 descriptors can be achieved; if the received message signal is a data message, at this time, the tag in the message is directly matched with the tag in the RAM space. After the match is successful, it is stored in the corresponding RAM space for subsequent writing and other operations.

[0060] The packet sending unit is responsible for generating pre-fetch read requests for descriptors, read requests for source address data, and write requests for destination address. If it is a read descriptor request, the tag is set to a fixed value to form a descriptor-specific tag. After the packet sending unit assembles the packet according to the ID and the descriptor-specific tag, it initiates a read descriptor request, and the packet receiving unit recovers the message signal containing the descriptor content into the descriptor FIFO; if the packet sending unit sends a read data request, the packet sending unit applies for a tag from the tag queue unit. After obtaining the tag allocation from the tag queue unit, the packet sending unit is responsible for assembling the packet to form a read request message. To the PCIe bus, when the host returns the data message corresponding to the read data request, the data storage space is applied to the RAM based on the data information in the received data message (i.e., the tag in the data message); it can be understood that the tag in the data read request message sent by the packet sending unit is consistent with the tag in the corresponding read return message (i.e., the corresponding data message received by the packet receiving unit) to determine the consistency between the data read request and the returned data message. In addition, each tag assigned to the data read request is set in a one-to-one correspondence with each divided storage unit in the RAM. The write request sent by the packet sending unit will be reordered and generated in sequence according to the destination address in the descriptor and the storage address of the data in the RAM. It can be understood that the reordering here can be performed in sequence according to the order stored in the RAM. The tag queue unit stores at least each tag value and its corresponding RAM start address. The tag queue unit is mainly used for tag storage and allocation, that is, assigning tags to descriptors as needed to form descriptor tags, or assigning tags to data packets to form data packet tags; RAM is used to store message data.

[0061] When DMA finishes parsing the descriptor and is ready to initiate a read data request to the source address, it needs to apply for a free tag from the tag queue unit and report the data size (i.e., data length) of this read request. The tag queue unit is responsible for managing the application and release of 32 tags and recording the RAM address where each read data reply message is stored. RCB (Read Completion Boundary) is a parameter defined in the PCIe bus. It specifies the maximum aligned byte boundary of a data packet that can be returned when completing a PCIe memory read request, with a maximum of 128 bytes. Combined with Figure 2 As shown, in this embodiment, the minimum unit of RAM is set to 128 bits, so that each minimum unit can store a maximum data reply message. At the same time, in order to manage the RAM space, a ram_valid flag with a bit width of 1 bit is set to mark each unit to ensure that the subsequent data reply messages can be stored in sequence according to the correct address.

[0062] In a specific embodiment, reference Figure 2 , Figure 7 , Figure 8 The following is an example to illustrate the specific implementation process of this solution:

[0063] (1) In the initial stage, the DMA controller will first send a read descriptor request through the packet sending unit, using a fixed ID value and a descriptor-specific tag number to form a descriptor read request message. At this time, the address contained in the descriptor read request message is the address where the descriptor is located, and the length is the total length of the descriptor. In this embodiment, a fixed length of 32 bytes is used. The host will package the content of the descriptor into the reply message according to the read descriptor request initiated by the DMA. After the packet receiving unit in the DMA receives the reply message corresponding to the read descriptor request, it will store it in the descriptor FIFO queue, and then take out the message from the descriptor FIFO queue in sequence for parsing. The read-back descriptor will record the length of the data to be moved, as well as the source address and destination address. According to the above information in the descriptor, the DMA will re-initiate a read data request to read the data that needs to be moved corresponding to the descriptor.

[0064] In this embodiment, since an independent descriptor FIFO is set up, there is no need to wait for the return message of the read data request corresponding to the descriptor, but at least three descriptor read requests, for example, can be directly sent continuously, so that the read back descriptors can be stored in the descriptor FIFO and processed one by one.

[0065] (2) When the DMA controller sends the first read data request through the packet sending unit, the tag field requested by the packet sending unit to the tag queue unit is tag0, and the packet sending unit obtains the requested data length length0 from the descriptor content in the descriptor FIFO. Here, in a special case, if the data length exceeds the maximum data transmission length requirement that the message can support, since the PCIe message supports the transmission of up to 256 bytes of data, if length0 exceeds this value, the data to be read must be split into multiple requests according to the maximum length of 256 bytes to read the data; the tag queue unit calculates the end address ram_addr1 based on the starting address ram_addr0 of the RAM, stores ram_addr0 in the unit corresponding to tag0 in the tag queue unit, and temporarily stores the end address ram_addr1 using a register.

[0066] (3) When sending the second read data request, the requested tag field is tag1, the requested data length is length1, and the tag queue unit calculates the final address ram_addr2 based on ram_addr1, stores ram_addr1 in the unit corresponding to tag1 in the tag queue unit, and updates the register value to ram_addr2.

[0067] (4) When sending the nth read data request, if the calculated ram_addr(n+1) is greater than the maximum address of the RAM, it is determined whether there are released tags and storage spaces starting from tag0. If there are released tags and corresponding storage spaces, the released tags and corresponding storage spaces are reallocated. If there are no released tags or storage spaces, the construction of the read data request is stopped and the tag value at this time is recorded in the tag_max register. It can be understood that the tag_max register can be a register set in the DMA controller.

[0068] If the 32nd tag has been used up, check whether tag0 is released. If tag0 is released and there is enough storage space, send a new round of read data requests starting from tag0. Otherwise, stop sending read data requests. At this time, the value in the tag_max register is tag30.

[0069] When the packet receiving unit receives a data reply message for a read data request, the controller queries the corresponding RAM storage address in the tag queue unit according to the tag signal in the data reply message, and stores the data in the specified RAM address space. Each return message occupies a minimum storage unit of RAM, and the ram_valid flag corresponding to this minimum unit is set to valid. When the next tag data return message is received, the operation is similar to the previous one. According to the tag and the corresponding RAM storage address, as well as the corresponding ram_valid flag, the received reply message data can be stored in the correct RAM location.

[0070] The DMA controller sends a write request to the destination address. First, the RAM space address is judged from small to large to see whether the ram_valid flag is valid. If ram_valid is valid, it means that the corresponding RAM storage unit stores valid data. If it is valid, the data of the corresponding unit is read out and the ram_valid flag is cleared. At the same time, it is judged whether the tag value of the current read storage unit is equal to the value in the tag_max register. If they are equal, the next read starts the next cycle from the storage unit corresponding to tag0. The DMA controller organizes the sending of the memory write request message through the destination address and the amount of data to be moved (i.e., the data length) stored in the descriptor FIFO, and completes a data move from the source address to the destination address. Here, it should be noted that write requests and read requests can be performed at the same time, not after the tag is full or the RAM is full.

[0071] Based on the above design of this embodiment, this solution can execute four types of scatter-gather (SG) modes. Figures 3 to 6 , and elaborates on different execution modes.

[0072] The use of the Scatter-Gather (SG) mode first requires the initialization of the descriptor. The descriptor needs to be written into a fixed memory space, read through the DMA internal tag queue allocation method, and pre-fetch the descriptor according to the actual transmission requirements. The descriptor content includes: (1) DMA transfer status. After completing a data transfer, the DMA will write back the completion status, error, and the total length of the descriptor currently transferred to the status descriptor address, so that the user can observe the DMA transfer status; (2) DMA transfer control, including: Status record enable is used to define whether the DMA engine's transfer status is written back to the first descriptor when the SG mode is started and the current descriptor is being processed. Interrupt enable is used to determine whether to report an interrupt when all descriptors are processed or when an error occurs in the DMA. The page length indicates the length of the data corresponding to the current descriptor; (3) The address, availability, and start and end conditions of the next descriptor. The address of the next descriptor is used to identify the address space where the next descriptor is located, so that the DMA can automatically read the next descriptor. Availability indicates whether the next descriptor is available. If it is in a paused state, the user needs to reactivate it. The start and end conditions are to identify the last descriptor so that the DMA can end the transfer normally after reading the last descriptor. (4) Source data address and destination data address. Record the address space where the data to be transferred is located.

[0073] In this embodiment, when the descriptor is initialized, four modes may be used, that is, the SG mode may include four types:

[0074] The first type, such as Figure 3 As shown, when the descriptor is initialized, there are two different descriptors for the source address and the destination address, namely the source descriptor (i.e., the descriptor on the source side) and the destination descriptor (i.e., the descriptor on the destination side), wherein the source address in the source descriptor is valid, the destination address will be ignored, and the address of the next descriptor points to the address space where the next source descriptor is located; similarly, the destination address of the destination description is valid, the source address will be ignored, and the address of the next descriptor points to the address space where the next destination descriptor is located. In the first type of SG mode DMA transmission, the DMA register will be configured, the address of the first source descriptor will be written into the source address register, and the address of the first destination descriptor will be written into the destination address register. The DMA reads the first group of descriptors according to the initial address value for processing and initiates a read data request. At the same time, the descriptor is continuously obtained through the address of the next descriptor until the last descriptor is read. After the above initialization setting of the first type, the pre-fetching of the descriptors and the transmission of data mentioned in this embodiment can be continued. In this embodiment, two separate descriptors are set to facilitate the acquisition of data nearby between two different hosts, which can cope with the scenario of cross-domain transmission and greatly improve the efficiency of existing DMA transmission.

[0075] The second type, such as Figure 4 As shown, the source side uses the descriptor to obtain data, and only sets the source descriptor (that is, the descriptor on the source side), and the destination side writes it into the continuous address space. At this time, the destination address in the source descriptor is invalid. In the second type of SG mode DMA transmission, the DMA register will still be configured, and the address of the first source descriptor will be written into the source address register, and the destination address register will be written into the first address of the continuous address space. The DMA reads the first source descriptor according to the initial source address value for processing and sends a read data request. The returned data is written into the continuous space according to the first address value of the continuous address space of the destination address register. The data read back by the next descriptor will continue to be written into the space until all descriptors are processed. This type of SG does not require the configuration of the destination descriptor. It only needs to configure the first address of the data to be written into the corresponding DMA control register. It is suitable for scenarios where scattered data is integrated and written into continuous addresses.

[0076] The third type, such as Figure 5As shown, the destination side uses descriptors to control write operations, that is, only the destination descriptor (that is, the destination side descriptor) is set, and the source side uses a continuous address space. At this time, the source address in the destination descriptor is invalid. In the third type of SG mode DMA transmission, the DMA registers will still be configured, and the address of the first destination descriptor will be written into the destination address register, and the source address register will be written into the first address of the continuous address space. The DMA reads the first destination descriptor according to the initial destination address value for processing and sends a read data request. The host returns the data to the DMA according to the source data address in the DMA register and writes it according to the destination address in the destination descriptor. The address carried by the next descriptor will be used as the space for the next data to be written until all descriptors are processed. This initialization method is suitable for scenarios where continuous data is written to scattered and different address spaces. This type does not require the configuration of the source descriptor. It only needs to configure the first address of the data to be read into the corresponding DMA control register.

[0077] The fourth type, such as Figure 6 As shown in the figure, it is a relatively standard SG mode. A common descriptor is set to write the data content to the same address. DMA can obtain the source address and the destination address at the same time by reading the descriptor. One read can complete a DMA transfer. In the fourth type of SG mode DMA transfer, the address of the first common descriptor is written into the source address register. The destination address register is invalid at this time. DMA reads the first common descriptor to obtain the source data address and the destination data address at the same time and complete the transfer. This type is suitable for decentralized address reading and writing scenarios that do not require cross-domain transmission, which can improve the overall transmission efficiency.

[0078] Combination Figure 7 As shown, the present invention supports cross-domain transmission. In some transmission scenarios, such as non-transparent bridge (NTB) structures, data transmission between different bus domains is required. The source and destination ports of DMA transmission can be selected by register configuration to achieve the effect of cross-domain transmission. The path of DMA cross-domain transmission in NTB is as follows Figure 7 If the DMA on the NTB virtual side is used to transfer data on this side, the path marked by the light-colored line is used. If cross-domain transmission is involved, the path marked by the black line is used. In this application scenario, the overall DMA transmission process is as follows:

[0079] First, the DMA on the virtual side will send a read data request to the upstream host. If the direct transfer mode is used, the upstream host will return a CPLD message with data, and then the DMA will initiate a message with a data write request to write the data to the destination address (i.e. write it back to the downstream port). If the first type of SG mode is used, the upstream host will initiate two read requests to read the pre-stored source descriptor and destination descriptor contents. The virtual side DMA will re-initiate a read data request based on the source descriptor content and receive the real data, store it in the cache, and then issue a write request with data based on the destination descriptor content; if the second type of Sg mode is used, the upstream host will only read the source descriptor and write the data of each descriptor to the destination address in sequence according to the configured destination address; similarly, the third type of SG mode will only read the destination descriptor and write the continuous data to different addresses according to the descriptor; the fourth type of SG mode only needs to read the descriptor content once to perform the data reading and writing process.

[0080] In addition, in another implementation manner, the transmission method proposed in this embodiment can determine whether to execute in SG mode or in DMA direct transmission model by performing hardware configuration in advance. When configured as DMA direct transmission mode, DMA data transmission is performed in direct transmission mode, and data transmission is no longer performed through descriptor prefetching and SG mode.

[0081] In the direct transfer mode of DMA, each data movement of DMA generally requires the CPU to access the internal register to configure the source address, destination address, transfer length and other information of the transfer. After completion, the DMA generates an interrupt to notify the CPU to query the status and perform the next operation configuration, or the CPU configures the descriptor address, and the DMA controller initiates a descriptor read access. After retrieving the descriptor, the source address data is read and the destination address data is written. After completion, the next descriptor read access is initiated again until the last descriptor item.

[0082] In another implementation mode, the present solution can be implemented by a device, which may include one or more modules in the system modules in the above embodiments. The module may be one or more hardware modules specially configured to perform the corresponding steps, or implemented by a processor configured to perform the corresponding steps, or stored in a computer-readable medium for implementation by a processor, or implemented by some combination.

[0083] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A descriptor-based PCIe bus DMA high-speed data transmission method, characterized in that: The method comprises: S1. After completing the first descriptor address configuration and DMA startup, DMA actively initiates a descriptor read request; S2, the host returns a descriptor based on the descriptor read request, the DMA parses the descriptor content, initiates a data read request according to the source data address in the descriptor content, and simultaneously initiates a next descriptor read request according to the next descriptor address in the descriptor content; the descriptor is received by the DMA in the form of a descriptor message; S3. After receiving the message, DMA determines whether it is a descriptor message or a data message; if it is a descriptor message, the descriptor is stored in the descriptor FIFO unit in DMA, waiting for the next step of parsing; if it is a data message, the tag in the data message is matched with the tag in the RAM set in DMA, and the data content in the data message is stored in RAM after the match is successful; the tag is managed and allocated by the tag queue unit set in DMA; S4. If the descriptor FIFO unit is full, or the current descriptor is the last descriptor in the linked list, stop initiating the next descriptor read request; otherwise, continue initiating the next descriptor read request and execute S3.

2. The method according to claim 1, characterized in that In S1, when DMA initiates a descriptor read request, the tag queue unit configures a fixed tag for the corresponding descriptor to form a descriptor-specific tag.

3. The method according to claim 1, characterized in that: In S2, when DMA initiates a data read request, a packet sending unit in DMA applies for tags from a tag queue unit in the order of data read requests, and assembles the tags into a data read request message and sends it to the PCIe bus.

4. The method according to claim 3, characterized in that The RAM is divided into a plurality of storage units, and the tag queue unit is a tag assigned to a read data request, and is set in one-to-one correspondence with a storage unit in the RAM; The tag queue unit stores the tag value and its corresponding RAM start address; Each of the storage units is provided with a ram_valid flag to mark whether the storage unit is empty.

5. The method according to claim 4, characterized in that When DMA finishes parsing the descriptor and is ready to initiate a read data request to the source address, it requests an idle tag from the tag queue unit and reports the length of the data read this time; Based on the starting address in the RAM corresponding to the requested free tag and the data length, the ending address is calculated and stored in the register temporarily; the register is updated based on the ending address in the RAM of the data currently to be read.

6. The method according to claim 5, characterized in that If the end address is greater than the maximum address of the RAM, starting from the first tag in the tag queue unit, determine whether there are released tags and corresponding storage units in turn; if so, reallocate the released tags and corresponding storage units; if not, stop constructing the read data request and record the tag value at this time in the tag_max register.

7. The method according to claim 5, characterized in that If all tags in the tag queue unit are used up, starting from the first tag in the tag queue unit, determine whether there are released tags and corresponding storage units in turn. If there are released tags and the storage unit has sufficient storage space, continue to send read data requests, otherwise suspend sending read data requests and record the tag value at this time in the tag_max register.

8. The method according to any one of claims 6 or 7, characterized in that: When DMA sends a write request to the destination address, it checks the ram_valid flag of the storage units in the RAM in sequence to see if it is valid. If it is valid, it reads the data in the corresponding storage unit and clears the ram_valid flag. At the same time, it checks whether the tag value corresponding to the read storage unit is equal to the value in the tag_max register. If they are equal, it starts a new round of reading cycle from the storage unit corresponding to the first tag value in the tag queue unit. If they are not equal, it continues to read the next storage unit.

9. The method according to claim 1, characterized in that: The S1 also includes initializing the descriptor, and the initialization includes at least one of the following types: Type 1: Set a source descriptor for the source data address, and set a destination descriptor for the destination data address. If the source data address in the source descriptor is valid, the destination data address is ignored. If the destination data address in the destination descriptor is valid, the source data address is ignored. or Type 2: Set the source descriptor on the source data side and write it into the continuous address space on the destination side; or Type 3: Set the destination descriptor on the destination data side to control the data write operation. The source data side uses a continuous address space and configures the first address of the data to be read into the DMA register. or Type 4: Set a common descriptor, write the source data address and the destination data address into the common descriptor at the same time, and DMA can obtain the source data address and the destination data address at the same time by reading the common descriptor.

10. A descriptor-based PCIe bus DMA high-speed data transmission device, characterized in that: The device includes a DMA module, and the DMA module includes: a packet receiving unit, a packet sending unit, a tag queue unit, a RAM and a descriptor FIFO unit; The descriptor FIFO unit is connected to the packet receiving unit and stores the descriptors received from the packet receiving unit; the descriptor FIFO unit is connected to the packet sending unit, and the packet sending unit obtains the request data address and the request data length based on the analysis of the descriptor in the descriptor FIFO unit; The tag queue unit is used for tag management and allocation; the tag queue unit is connected to the packet receiving unit and the packet sending unit; The RAM is used to store data in the data message, and the RAM is connected to the packet sending unit and the packet receiving unit; The packet sending unit and the packet receiving unit are respectively connected to the PCIe bus; The DMA module is used to execute the descriptor-based PCIe bus DMA high-speed data transmission method described in any one of claims 1-8.

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