Integrated circuit design method and device based on agent iteration training of large model

Abstract

The application provides an integrated circuit design method and device based on agent iteration training of a large model, including: obtaining an integrated circuit design requirement described in natural language; taking an instruction for generating the integrated circuit design requirement as a question, taking a knowledge base as a knowledge reference, inputting the question and the knowledge reference into a question and answer model based on a large language model to obtain instruction description; inputting the instruction description into a code generation model based on the large language model to obtain intermediate HDL code and scoring to obtain a syntax score, constructing a loss function based on the intermediate HDL code and the syntax score of the intermediate HDL code, and training the code generation model; scoring power consumption, performance and area of the intermediate HDL code through a synthesis tool to obtain a performance score, constructing a loss function based on the intermediate HDL code and the performance score of the intermediate HDL code, and training the question and answer model; inputting a target circuit design requirement into the trained question and answer model, inputting obtained instruction description into the trained code generation model, and obtaining final HDL code.

Description

Technical Field

[0001] The present invention relates to the technical fields of computer-aided chip design, large model application, and electronic design automation (EDA), and in particular to an integrated circuit design automation method, device, storage medium, electronic device, and computer program product based on a multi-agent iterative training large model. Background Art

[0002] Electronic design automation (EDA) is used for integrated circuit design, including requirements analysis, function definition, design, synthesis, verification, layout, routing, layout and design rule checking.

[0003] Tools such as question-answering models, code generation models, synthesis tools, and syntax checkers are referred to as "agents" because they act as autonomous entities, or "agents," in the design workflow, performing specific tasks or making decisions on behalf of users or systems. In the field of artificial intelligence, the term "agent" generally refers to an entity that autonomously achieves a specific goal by processing inputs and producing outputs. These agents operate in complex environments, making decisions or performing actions based on predefined rules or learned knowledge. In the context of chip design, question-answering models act as agents by interpreting user queries and providing answers based on available data or knowledge.

[0004] Code generation models act as agents, automating the traditional manual coding process by receiving design specifications or high-level descriptions and converting them into code (such as hardware description languages ​​like Verilog or VHDL). Synthesis tools are agents that convert high-level design code into low-level representations and optimize the design to meet performance, area, or power requirements, which is crucial in chip design. Syntax checkers act as agents, analyzing the generated code for errors or inconsistencies to ensure that the code adheres to the grammatical rules of the programming or hardware description language. These systems are called agents because they interact with the design environment and take actions based on input (user instructions, design specifications, etc.) without often requiring direct human intervention. Their ability to make autonomous decisions and perform tasks at various stages of chip design, from code generation to verification, earns them the designation "agent." In summary, the aforementioned tools are called agents because they can autonomously perform various tasks and make decisions on behalf of the user or system during the design process.

[0005] Large language models (LLMs), such as GPT-4, have achieved remarkable success in natural language processing and have shown great potential in code generation for languages ​​like C and Python. Large multimodal models (LMMs) have also achieved breakthroughs in processing data that integrates diverse types. The application of LLMs and LMMs in automated hardware design processes has achieved initial success and has the potential to revolutionize traditional chip design methods. By increasing the automation level of EDA processes, these technologies are gradually driving the transition to "fully automated" chip design.

[0006] Traditional manual coding of Hardware Description Language (HDL) code is not only time-consuming but also prone to errors. Currently, LLMs still face challenges in generating HDL code, including compilation failures, functional errors, and power, performance, and area (PPA) optimization. The application of large-model techniques such as iterative optimization, model fine-tuning, and multi-agent collaboration in EDA has yet to be fully explored. There is an urgent need to integrate emerging technologies to improve the accuracy of EDA-specific models to a level that is practical for practical application.

[0007] Expert question-and-answer systems based on large models can provide accurate technical support and solutions instantly, reducing the time spent searching for help and decisions based on incorrect assumptions, thereby reducing design errors and rework. However, current EDA expert question-and-answer systems have not yet been effectively integrated with HDL generation.

[0008] For example, the existing technology uses the compilation errors and simulation information in the Verilog code generated by LLMs as feedback to add prompt words to improve the code generation performance, but does not update the optimization model. Or proposes LLM training with code quality feedback, but does not have an iterative optimization model, which limits the model performance and requires a relatively large amount of training data. Or proposes to guide the Transformer to generate compilable, functionally correct and PPA-optimized code by integrating Monte Carlo tree search, but because a tree search needs to be performed on each new module generated, it takes a long time. The present invention further proposes to use the supervisory feedback provided by the EDA tool to iteratively fine-tune the LLMs and update their parameters to generate a chip design with the desired PPA.

[0009] During the research on large-scale model-assisted chip design, the applicant discovered that the implementation of automated integrated circuit design faced the following problems:

[0010] (1) Small amount of data: High-quality register transfer level (RTL) code is mostly not publicly available, which results in a lack of high-quality datasets available in key technical areas such as circuit synthesis and physical design. In addition, the performance differences of integrated circuit processes and the confidentiality of process libraries further increase the difficulty of dataset construction. Existing benchmarks typically only evaluate the performance of models in generating single-file Verilog code, which cannot accurately reflect the real-world scenarios of generating code in large and complex code bases. The limited number of samples in these benchmarks limits the diversity of tasks and may cause models to rely too much on specific solutions rather than truly generalize.

[0011] (2) Auxiliary tools: In the field of chip design, there are a large number of compilation and simulation tools that can provide automatic feedback, eliminating the need for manual feedback, which is an advantage in this field.

[0012] (3) The quality of the natural language description of HDL code has a great impact on the accuracy of code generation. Summary of the Invention

[0013] To address the problems of insufficient code generation accuracy, insufficient PPA performance, and insufficient training data in large-model assisted chip design, the present invention proposes an integrated circuit design automation method and device based on multi-agent iterative training of a large model.

[0014] Specifically, in view of the shortcomings of existing technologies, such as Figure 8 As shown, the present invention proposes an integrated circuit design method based on agent iterative training of a large model, comprising:

[0015] A construction step includes constructing a knowledge base in the EDA field to obtain integrated circuit design requirements described in natural language; using an instruction for generating the integrated circuit design requirement as a question and the knowledge base as a knowledge reference, inputting the question and the knowledge reference into a question-answering model based on a large language model to obtain an instruction description;

[0016] The training step includes inputting the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scoring the intermediate HDL code to obtain a syntax score, constructing a loss function based on the intermediate HDL code and its syntax score, and training the code generation model; scoring the power consumption, performance, and area of ​​the intermediate HDL code using a synthesis tool to obtain a performance score, constructing a loss function based on the intermediate HDL code and its performance score, and training the question-answering model; and after each round of training, using the obtained new model to regenerate and score the HDL code for the next round of training, thereby iteratively improving the model performance; during each round of generation, screening out non-self-contained HDL code or assigning it a low score to guide the model to generate high-quality self-contained HDL code;

[0017] The design steps are to input the target circuit design requirements into the trained question-answering model, and input the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the preliminary integrated circuit design result of the target circuit design.

[0018] The integrated circuit design method based on agent iterative training of a large model, wherein the training step includes:

[0019] The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

[0020] or

[0021] The training step includes: calculating the power consumption, performance, and area corresponding to the intermediate HDL code by a synthesis tool as a performance score.

[0022] The integrated circuit design method based on agent iterative training of a large model, wherein the teacher model, question-answering model and code generation model are usable open source or commercial models, an implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

[0023] like Figure 9 As shown, the present invention also proposes an integrated circuit design device based on agent iterative training large model, which includes:

[0024] A construction module is provided to construct a knowledge base in the EDA field and obtain integrated circuit design requirements described in natural language. The instruction for generating the integrated circuit design requirement is used as a question and the knowledge base is used as a knowledge reference. The question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description.

[0025] The training module inputs the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scores the intermediate HDL code to obtain a syntax score, constructs a loss function based on the intermediate HDL code and its syntax score, and trains the code generation model; scores the power consumption, performance, and area of ​​the intermediate HDL code using a synthesis tool to obtain a performance score, constructs a loss function based on the intermediate HDL code and its performance score, and trains the question-answering model;

[0026] The design module inputs the target circuit design requirements into the trained question-answering model, and inputs the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the integrated circuit design result of the target circuit design.

[0027] The integrated circuit design device based on agent iterative training large model, wherein the training module includes:

[0028] The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

[0029] or

[0030] The training module includes: calculating the power consumption, performance and area corresponding to the intermediate HDL code by a synthesis tool as a performance score.

[0031] The integrated circuit design device based on the agent iterative training large model, wherein the teacher model, question-answering model and code generation model are usable open source or commercial models, an implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

[0032] The present invention also proposes an electronic device, which includes the integrated circuit design device based on the agent iterative training large model.

[0033] The electronic device may be connected to an information display device, which is used to display the integrated circuit design results using display parameters and attributes set by the user or through an artificial intelligence model.

[0034] The present invention also proposes a storage medium for storing a computer program for executing any of the above-mentioned integrated circuit design methods based on agent iterative training large models.

[0035] The present invention also provides a computer program product, comprising a computer program, wherein the computer program implements the steps of any of the methods when executed by a processor.

[0036] From the above scheme, it can be seen that the advantages of the present invention are: reducing the amount of training data, improving the accuracy of model code generation and PPA quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a flow chart of an embodiment of the present invention;

[0038] Figure 2Generate large model iterative optimization diagrams for Verilog code;

[0039] Figure 3 Iteratively optimize graphs for large question-answering models;

[0040] Figure 4 A schematic diagram of an implementation method for iterative tuning of large models for Verilog code generation;

[0041] Figure 5 This is a comparison chart of the model effects;

[0042] Figure 6 A graph showing the relationship between the number of iterations and the model effect;

[0043] Figure 7 The architecture diagram of the EDA question-answering model for retrieval enhancement;

[0044] Figure 8 It is the overall flow chart of the present invention;

[0045] Figure 9 This is a module diagram of the device of the present invention;

[0046] Figure 10 This is a schematic structural diagram of a first electronic device of the present invention;

[0047] Figure 11 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0048] Figure 12 This is a schematic structural diagram of a second electronic device according to the present invention;

[0049] Figure 13 This is a schematic diagram of the screening code.

[0050] Reference numerals:

[0051] A-First electronic device;

[0052] B-IC design device based on agent-based iterative training of large models;

[0053] C-data acquisition equipment;

[0054] D-information display device;

[0055] 1000- second electronic device;

[0056] Ⅰ-computing unit;

[0057] II-ROM;

[0058] III-RAM;

[0059] IV-bus;

[0060] V-interface;

[0061] VI-input unit;

[0062] VII-output unit;

[0063] VIII-Storage medium;

[0064] IX-Communication unit. DETAILED DESCRIPTION

[0065] It should be noted that, in this application, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0066] Without further constraints, an element defined by the phrase "comprises a..." does not preclude the existence of additional identical elements in the process, method, article or apparatus that includes the element.

[0067] The processor described in the present invention is the control center of an electronic device and can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs) or one or more field programmable gate arrays (FPGAs).

[0068] Optionally, the processor can perform various functions of the electronic device by running or executing a software program stored in the memory, and calling data stored in the memory.

[0069] In a specific implementation, as an embodiment, the processor may include one or more CPUs. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include: servers, desktop computers, laptops, smartphones, tablet computers, embedded computers, etc., wherein the embedded computers include vehicles and robots, etc.

[0070] The memory is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0071] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0072] The above embodiments can be implemented in whole or in part through software, hardware (such as circuits), firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired method (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, or magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0073] It should also be understood that the term "and / or" in this document simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " in this document generally indicates an "or" relationship between the related objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0074] In this disclosure, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0075] It should also be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0076] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0078] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0080] Based on the above situation, the present invention proposes solutions including:

[0081] (1) In terms of model optimization, it is necessary to make full use of existing simulation tools to improve algorithms to reduce data requirements and optimize efficiency, thereby improving the correctness of HDL code generation and further improving performance to achieve the best performance in terms of power, performance and area.

[0082] (2) Retrieval-Augmented Generation (RAG) technology improves code quality by enhancing the accuracy of question descriptions in the question-answering model. In the RAG retrieval-enhanced EDA question-answering model, a domain-adaptive algorithm is developed to enable the model to provide accurate and relevant answers within the chip design domain, thereby improving code generation quality.

[0083] Therefore, the present invention proposes an integrated circuit design automation method and system based on a multi-agent iterative training large model to improve the accuracy of hardware description language (HDL) code generation and optimize performance, power consumption and area (PPA) indicators. The method uses automated tools such as syntax checkers and synthesis tools (regarded as agents) to iteratively train large models. In each iterative cycle, samples are extracted from the model trained in the previous cycle and used to train the current cycle, thereby minimizing the mismatch between the model and the training samples. In addition, a plug-and-play data filtering strategy is introduced to ensure the quality of the generated code and allow the model to explore in a wider generation space and receive more comprehensive feedback. In the instruction part, the professionalism of the instructions is improved by combining the question-and-answer large model with the EDA knowledge base, and the question-and-answer large model is iteratively optimized through relevant tools. Through the above-mentioned iterative method, the system improves the professionalism and practicality of the generated code, making the design process more efficient and automated. Specifically, the present invention includes the following key technical points:

[0084] Key point 1, question answering model and code generation model, both are large language models, open source code generation model such as DeepSeek, open source question answering model such as Llama3. Figure 1 As shown, the Verilog code generated by the code generation model is syntactically checked for correctness using syntax checking tools like PyVerilog. Synthesis tools like DC calculate the PPA, which serves as a supervisory signal for iterative training of the Verilog code generation model, improving the accuracy and PPA quality of the generated code. Through multiple iterations of data generation, syntax checking, and model training, model performance is gradually improved. Supervisory signals can be provided by a single tool or by combining them.

[0085] Calculation of loss function: You can use the teacher model to generate code to provide a supervision signal to calculate the loss function, or you can use only the syntax checker and synthesis tool to calculate the loss function without using the teacher model.

[0086] The loss function consists of two parts, cross entropy loss and ranking loss.

[0087]

[0088] The cross entropy loss is obtained by calculating the cross entropy between the model generation results and the answers generated by the teacher model.

[0089] The calculation of ranking loss requires the use of feedback from a grammar checker or synthesis tool to encourage the model to generate higher-quality answers. First, the code is scored based on the tool. Taking the grammar checker as an example, if the grammar is correct, the score is 1. If the grammar is incorrect, the score is between 0 and 1 based on the Rouge-L indicator between the code and the reference code generated by the teacher model. If a synthesis tool is used, the PPA performance is used as the score. The better the performance, the higher the score. The specific ranking loss calculation formula is as follows:

[0090]

[0091] α and β are hyperparameters. z represents the score. p represents the log-likelihood of the generated answer:

[0092] s stands for design instructions and a stands for answer.

[0093] According to the calculation formula of ranking loss, if the probability corresponding to the low-scoring answer is higher than the high-scoring answer, the loss function is positive and the model will automatically perform gradient descent optimization.

[0094] Key point 2, such as Figure 3As shown, the Verilog code generated by the large model is checked for syntax correctness using syntax checking tools such as PyVerilog. Synthesis tools such as DC calculate the PPA and use this as a supervisory signal. Higher PPA performance is assigned a higher score. If a high-scoring answer has a low probability of generation, the model automatically optimizes based on the ranking loss to increase the probability of the answer corresponding to the high score. This supervisory signal is used to iteratively train the instruction descriptions generated by the large question-answering model, improving the professionalism of the instruction descriptions and, in turn, the quality of the generated code.

[0095] The instruction description is the function that the RTL code needs to implement. For example, the instruction of a 4-bit full adder is as follows: Implement a 4-bit adder with full adders. The output sum should include the overflow bit.

[0096] Key point 3: Before using syntax checkers and synthesis tools to calculate PPA, screening out low-quality code can effectively improve model training results. Screening out low-quality code means screening out non-self-contained modules in the reference code generated by the teacher model, that is, the modules in the code cannot contain instantiations of other modules. For example, you need to delete Figure 13 The code shown here is because the full_adder external module is instantiated in the module. Our model focuses on generating self-contained code. At the same time, for non-self-contained code generated by the student model (the model to be trained), we score it as -1, thereby suppressing the network from generating corresponding code through the ranking loss.

[0097] To illustrate the above-mentioned features and effects of the present invention more clearly and easily, the following embodiments are specifically described below with reference to the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are for illustrative purposes only. The scope of protection of the present invention is not limited to the disclosed embodiments; the present invention is defined by the appended claims.

[0098] The overall flow chart of this application is as follows Figure 1 shown.

[0099] EDA Knowledge Base: This systematically collects various EDA knowledge, including but not limited to design specifications, best practices, FAQs, and technical documentation. This knowledge base is built to systematically organize and present the collected knowledge points for easy access.

[0100] Table 1 Multimodal information of EDA knowledge base:

[0101]

[0102] The present invention adopts Figure 7 The RAG retrieval enhancement technology shown in the figure implements the EDA question-answering model based on RAG retrieval enhancement. This includes using retrieval enhancement to generate RAG methods to improve the accuracy of question answers. First, internal design documents and other data are collected and organized to create a comprehensive knowledge base. This data is then classified, annotated, and indexed for efficient retrieval. Second, engineers' queries and knowledge base content are parsed through language model training, intent recognition, entity extraction, and question parsing.

[0103] Syntax Checker: Use the PyVerilog syntax checker to check the syntax correctness of the Verilog code generated by large models. This is used as a supervisory signal to iteratively train the model and improve the accuracy of the generated code. By performing multiple rounds of data generation, syntax checking, and model training, with the same user input instructions in each round, model performance is gradually improved. In addition to full adder instructions, user instructions can also be state machine instructions:

[0104] This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-highsynchronous reset to state OFF.

[0105] / / OFF(out=0)--j=0-->OFF

[0106] / / OFF(out=0)--j=1-->ON

[0107] / / ON(out=1)--k=0-->ON

[0108] / / ON(out=1)--k=1-->OFF

[0109] And the reverse vector instruction:

[0110] Build a circuit that reverses the byte order of a 32-bit vector.

[0111] Synthesis tools: The Design Compiler synthesis tool calculates the PPA metrics (performance, power consumption, and area). These metrics are used as supervisory signals to iteratively train the model, guide the Verilog code generation model, and optimize design quality. This ensures that the generated code achieves optimal performance, power consumption, and area, making it practical for real hardware design.

[0112] An iterative training scheme. Since the teacher model can only provide guidance in the textual sense (cross entropy loss), and the teacher model is often closed source, such as GPT-3.5, this is not conducive to deployment in a real production environment and may result in expensive costs. Therefore, the present invention combines the data generated by the model itself and the data generated by the teacher model to train the model, and uses the trained model to update the training data, forming an iterative loop. The training scheme of the present invention combines text and tool feedback (ranking loss) to make the trained student model more suitable for RTL code generation.

[0113] Furthermore, we introduced data screening strategies to improve data quality;

[0114] When using a stronger base model, the teacher model is no longer capable of providing guidance. In this case, we abandon the teacher model and only rely on the feedback signal provided by the grammar checker to further improve the generation accuracy.

[0115] In each iteration, the model generates K-1 different codes for each instruction, plus one code generated by the teacher model, for a total of K codes for each instruction. Each code is fed into a syntax checker for scoring. Syntactically correct codes receive a score of 1, while syntactically incorrect codes receive a score between 0 and 1 based on their similarity to the code generated by the teacher model. The model is trained using instruction-code pairs and their corresponding scores to maximize the probability of generating high-scoring answers. Once the model converges, the updated model is used to generate code again, and the training process repeats.

[0116] Through this iterative process, the model can continuously update its training data, leveraging better data to improve performance. Furthermore, since most of the data is generated by the model itself, errors caused by the mismatch between the data distribution and the model distribution are mitigated, making the optimization direction more accurate.

[0117]

[0118] As shown in the table above, relying solely on iterative training, our model surpasses the baseline method with a smaller reference sample size. Compared to GPT-3.5, our model demonstrates significant advantages and approaches the level of GPT4. Further experimental results show that by introducing a data filtering mechanism, our model achieves a Pass@1 accuracy of 45.5% on VerilogEval-Human with only 7B parameters, surpassing GPT4.

[0119] Experiments have shown that the iterative training method can gradually reduce the loss function and improve the model performance by regenerating training samples. Figure 5 As shown in Figure 3, although the loss function has reached convergence within each iteration, the loss function continues to decrease in the next iteration due to the new supervision signal brought by the regenerated samples.

[0120] Figure 6 The results show that as the number of iterations increases, the performance of our model first increases and then decreases. The increasing phase demonstrates that iterative training can significantly improve model performance by continuously generating new training samples. However, as iterations continue, the model overfits, resulting in performance degradation. This reminds us to use the right number of iterations to avoid overfitting.

[0121] Building on this iterative training, we significantly improved the model's capabilities by introducing a data filtering mechanism. By analyzing the data generated by the model, we found that the model often generates irrelevant modules (if the code contains references and instantiations to external modules, the sample is directly deleted and not included in the training set). We want the model to focus on the high-quality generation of a single module. Therefore, we introduced a data filtering mechanism during the fine-tuning phase to directly remove samples containing redundant modules from the code generated by the teacher model. For samples containing redundant modules generated by the to-be-trained model, negative scores are assigned during the scoring phase to inhibit the model from generating the corresponding code.

[0122] By simply introducing a data filtering mechanism, the model achieved a single-shot generation accuracy of 43% after a single round of training. Combined with the previously proposed iterative training strategy, the accuracy on the benchmark was further improved to 45%, surpassing GPT4. The model we used was only 7 bytes in size, significantly smaller than the GPT series.

[0123] To further improve performance, we switched to a 16B base model for fine-tuning. Since the 16B model's capabilities surpassed those of the teacher model, GPT-3.5, we abandoned the use of reference data from the teacher model and trained solely on the feedback provided by syntax checking. Experimental results showed that the single-shot accuracy of the model-generated code increased to 50.6%. This demonstrates that when a sufficiently powerful teacher model is lacking, Verilog-based code tools can provide feedback, which is of great significance given the increasing capabilities of base models.

[0124] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiment.

[0125] like Figure 9 As shown, the present invention also proposes an integrated circuit design device based on agent iterative training large model, which includes:

[0126] A construction module is provided to construct a knowledge base in the EDA field and obtain integrated circuit design requirements described in natural language. The instruction for generating the integrated circuit design requirement is used as a question and the knowledge base is used as a knowledge reference. The question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description.

[0127] The training module inputs the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scores the intermediate HDL code to obtain a syntax score, constructs a loss function based on the intermediate HDL code and its syntax score, and trains the code generation model; scores the power consumption, performance, and area of ​​the intermediate HDL code using a synthesis tool to obtain a performance score, constructs a loss function based on the intermediate HDL code and its performance score, and trains the question-answering model;

[0128] The design module inputs the target circuit design requirements into the trained question-answering model, and inputs the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the integrated circuit design result of the target circuit design.

[0129] The integrated circuit design device based on agent iterative training large model, wherein the training module includes:

[0130] The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

[0131] The integrated circuit design device based on the agent iterative training large model, wherein the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

[0132] like Figure 10 As shown, the present invention further proposes a first electronic device A in another embodiment, including the above-mentioned integrated circuit design device based on agent iterative training large model.

[0133] like Figure 11 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect integrated circuit design requirements, and the information display device D is used to display the integrated circuit design results obtained by the analysis of the present invention.

[0134] The information display device D can organize and process the data output by the first electronic device A based on the information display mechanism to improve the readability of the data output by the first electronic device A. The information display mechanism can be manually preset, for example, the data output by the first electronic device A is visually displayed, which can be based on the display parameters and / or attributes set by the user. The display parameters can be, for example, the display data range, and the display attributes can be, for example, the display font, color, whether to scroll, etc. The user is presented with the key information specified by the user, and the user can understand this information more promptly without having to access the secondary page or scroll the page, saving the user's operation. Or the information display mechanism can be an artificial intelligence AI display model, which can learn the user's key information based on the user's previous usage habits, such as viewing time, number of clicks, number of edits, etc., and then automatically present the user with rich and necessary key information.

[0135] The present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the integrated circuit design method based on the agent iterative training large model provided by the above methods.

[0136] The present invention also proposes a storage medium VIII in another embodiment for storing a computer program for executing the integrated circuit design method based on the agent iterative training large model. It should be understood that the storage medium in the embodiment of the present invention can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM).

[0137] Figure 12 A schematic block diagram of a second electronic device 1000 that can be used to implement an embodiment of the present invention is shown. The second electronic device 1000 electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0138] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from a storage medium VIII into a random access memory (RAM) III. Various programs and data required for the operation of the device 1000 can also be stored in the RAM III. The computing unit I, ROM II, and RAM III are connected to each other via a bus IV. An input / output (I / O) interface V is also connected to the bus IV.

[0139] Multiple components in the second electronic device 1000 are connected to the I / O interface V, including: an input unit VI, such as a keyboard and mouse; an output unit VII, such as various types of displays and speakers; a storage medium VIII, such as a magnetic disk and optical disk; and a communication unit IX, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit IX allows the second electronic device 1000 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0140] Computing unit I can be various general and / or special processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. Computing unit I performs the various methods and processes described above, such as method steps S1-S3. For example, in some embodiments, the method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as a storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the method described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to execute the method in any other appropriate manner (e.g., by means of firmware).

[0141] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. An integrated circuit design method based on agent iterative training of a large model, characterized in that: include: Construction steps,build a knowledge base in the EDA field to obtain integrated circuit design requirements described in natural language; The instruction for generating the integrated circuit design requirement is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description; The training step includes inputting the instruction description into a code generation model based on a large language model to obtain an intermediate HDL code, scoring the intermediate HDL code to obtain a syntax score, constructing a loss function based on the intermediate HDL code and its syntax score, and training the code generation model; scoring the power consumption, performance, and area of ​​the intermediate HDL code using a synthesis tool to obtain a performance score, constructing a loss function based on the intermediate HDL code and its performance score, and training the question-answering model; and after each round of training, using the obtained new model to regenerate and score the HDL code for the next round of training, thereby iteratively improving the model performance; during each round of generation, screening out non-self-contained HDL code or assigning it a low score to guide the model to generate high-quality self-contained HDL code; The design steps are to input the target circuit design requirements into the trained question-answering model, and input the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the preliminary integrated circuit design result of the target circuit design.

2. The integrated circuit design method based on agent iterative training large model according to claim 1, characterized in that: The training steps include: The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

3. The integrated circuit design method based on agent iterative training large model according to claim 2, characterized in that: The teacher model, question-answering model, and code generation model are available open source or commercial models. An implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

4. An integrated circuit design device based on agent iterative training of a large model, characterized in that: include: Build modules and knowledge base in the EDA field to obtain integrated circuit design requirements described in natural language; The instruction for generating the integrated circuit design requirement is used as a question, and the knowledge base is used as a knowledge reference, and the question and the knowledge reference are input into a question-answering model based on a large language model to obtain an instruction description; The training module inputs the instruction description into a code generation model based on a large language model to obtain intermediate HDL code, scores the intermediate HDL code to obtain a syntax score, constructs a loss function based on the intermediate HDL code and its syntax score, and trains the code generation model; scores the power consumption, performance, and area of ​​the intermediate HDL code using a synthesis tool to obtain a performance score, constructs a loss function based on the intermediate HDL code and its performance score, and trains the question-answering model; after each round of training, uses the obtained new model to regenerate and score the HDL code for the next round of training, thereby iteratively improving the model performance; during each round of generation, screens out non-self-contained HDL code or assigns it a low score to guide the model to generate high-quality self-contained HDL code; The design module inputs the target circuit design requirements into the trained question-answering model, and inputs the obtained instruction description into the trained code generation model to obtain the final HDL code, which is used as the integrated circuit design result of the target circuit design.

5. The integrated circuit design device based on agent iterative training large model according to claim 4, characterized in that: This training module includes: The instruction description is input into the teacher network to obtain the standard code; and the syntax checker is used to determine whether the intermediate HDL code has errors. If so, the similarity between the intermediate HDL code and the standard code is determined, and the similarity is converted to a value between 0 and 1 to obtain the syntax score. Otherwise, the syntax score is 1.

6. The integrated circuit design device based on agent iterative training large model according to claim 5, characterized in that: The teacher model, question-answering model, and code generation model are available open source or commercial models. An implementation example is that the teacher network is GPT-3.5, the question-answering model is Llama3, and the code generation model is DeepSeek.

7. An electronic device, characterized in that: An integrated circuit design device based on an agent iterative training large model as described in any one of claims 4-6.

8. The electronic device according to claim 7, wherein: The electronic device may be connected to an information display device, which is used to display the integrated circuit design results using display parameters and attributes set by the user or through an artificial intelligence model.

9. A storage medium for storing a computer program for executing the integrated circuit design method based on agent iterative training of a large model as described in any one of claims 1 to 3.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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