Time synchronization method and communication device

Abstract

The invention discloses a time synchronization method and a communication device, and relates to the technical field of communication. In the communication process of different single boards, data frames are transmitted in the form of differential signals, and the data frames are borne in effective information segments (the difference between two common signals with the same signal edge and opposite overturning directions) of the differential signals, so that the data frames are transmitted in the form of the differential signals. The single board can analyze the time information carried by the data frame without comparing the time information carried by the data frame with the overturning threshold value of the single board, and the analyzed time does not change due to the temperature, aging, device process and the like of the single board. The precision that the single board executes time synchronization by using the analyzed time and the time when the data frame is sent can be improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a time synchronization method and a communication device. Background Art

[0002] Time synchronization refers to the process of making the clocks of multiple devices have a unified time scale by comparing the local clocks in multiple devices. After multiple devices perform time synchronization operations, the maximum relative time error between two clocks in different devices is the accuracy of time synchronization. Taking time synchronization between two devices as an example, the first device sends a single-ended signal to the second device, and the single-ended signal carries the time information of the first device; after the second device parses the single-ended signal to obtain the time information, it synchronizes the local clock in the second device based on the time information.

[0003] During the signal transmission process, the bandwidth of the transmission channel used by the single-ended signal is low, and the loss of the high-frequency component of the single-ended signal during the transmission process is large, which slows down the rising edge of the voltage determined by the second device for parsing the single-ended signal (the slope becomes lower). Since the second device uses level sampling to parse the single-ended signal, if the level is higher than the flip threshold, it is a high level, and if the level is lower than the flip threshold, it is a low level. The flip threshold will vary with temperature, aging, device process, etc. Therefore, when the rising edge of the voltage slows down, the time for the low level to flip to the high level is not controlled, and the accuracy of time synchronization is reduced. Summary of the invention

[0004] The present application provides a time synchronization method and a communication device, which solve the problem of reduced time synchronization accuracy when the loss of a single-ended signal is large and the threshold is not controlled.

[0005] In the first aspect, the present application provides a time synchronization method. The method is executed by a first single board, and the first single board and the second single board are connected by two differential signal lines. The time synchronization method provided by the present application includes: the first single board receives multiple continuous data frames sent by the second single board through two differential signal lines, and each data frame includes: the time of generating each data frame based on the local clock record in the second single board. And, the first single board determines the first data frame from the multiple continuous data frames, and adjusts the clock in the first single board according to the time carried by the first data frame, so that the difference between the clock in the first single board and the clock in the second single board is reduced, and the first data frame is any one of the multiple continuous data frames.

[0006] Since the differential signal is determined by comparing the difference between two ordinary signals with the same signal edge and opposite flipping directions, the differential signal includes a valid information segment (or valid information) and an invalid information segment (or common mode signal). During the communication process, different boards transmit data frames in the form of differential signals. The board can parse the time carried by the data frame without comparing the time carried by the data frame with the flipping threshold of the board, and the parsed time will not change due to the temperature, aging, device process, etc. of the board, which is conducive to improving the accuracy of the board using the parsed time to perform time synchronization, thereby reducing the difference between the clock in the first board and the clock in the second board.

[0007] In the present application, the differential signal lines between the first single board and the second single board may include: a first group of differential signal lines and a second group of differential signal lines, each group of differential signal lines including two differential signal lines. The first group of differential signal lines is used to: transmit the aforementioned multiple continuous data frames; the second group of differential signal lines is used to: transmit the aforementioned multiple continuous data frames in the event that the first group of differential signal lines fails. In some possible situations, the first group of differential signal lines is referred to as the main differential signal lines (main lines) between the first single board and the second single board, and the second group of differential signal lines is referred to as the spare differential signal lines (spare differential signal lines or spare lines) between the first single board and the second single board.

[0008] Compared with the use of single-ended signals for time synchronization in different boards, where the flip threshold of the boards is affected by the temperature, aging, device process, etc. of different boards, the present application uses differential signal lines to transmit data frames. The boards parse the data frames without considering the differences in hardware or operating environments of different boards, so that the boards can obtain more accurate time based on the data frames, thereby improving the accuracy of time synchronization.

[0009] In an optional implementation, the time carried by the first data frame includes: the sending time of a specified bit in the frame header of the first data frame.

[0010] In some possible examples, the designated bit in the frame header is the first bit in the frame header.

[0011] In some other possible examples, the designated bit in the frame header is other bits in the frame header, such as the last bit or the i-th bit, where i is a positive integer greater than or equal to 2.

[0012] During the communication process between different boards, the internal data of the chip is sent to the signal line between the boards one by one according to the bit width. Therefore, the specified position (specified bit) in the frame header represents the time corresponding to the time carried by the first data frame, so that the first board can realize the time synchronization between different boards according to the time obtained by parsing the data frame and the time corresponding to the specified bit, thereby achieving the bit-level time synchronization effect and improving the time synchronization accuracy between different boards.

[0013] In addition, as a feasible scenario, a specified bit in the frame header of the current data frame can also be used to indicate the time of the next data frame.

[0014] In an optional implementation, the time used by the second board to generate each data frame is carried in the time information field in each data frame, and the time information field includes: an information field and a check field. The information field is used to describe the time when the second board generates each data frame based on the local clock record, and the check field is used to check the accuracy of the data in the information field. In the process of generating data frames, the board uses a fixed field to record the time carried by the data frame, so that the board receiving the data frame can quickly locate the fixed field, thereby parsing the time carried by the data frame, which is conducive to improving the time synchronization efficiency between different boards, and also avoids the problem of low synchronization accuracy caused by the board traversing all fields in the data frame to output the time.

[0015] In a possible scenario, the aforementioned time information field also includes at least one of a type field and a domain field. The domain field is used to describe the domain of the time stored in the information field. The type field is used to describe the type of time stored in the information field. For example, the type of time is standard time, first deviation time, or second deviation time, the first deviation time indicates the time delay compensation value of the second single board, and the second deviation time indicates the difference between the acquisition time and the sending time of each data frame generated by the second single board. The single board can quickly determine the required parsing method for the time information recorded in the aforementioned information field by the type of time recorded in the type field, which is conducive to improving the time synchronization efficiency and time synchronization accuracy between different single boards.

[0016] In an optional implementation, the first board adjusts the clock in the first board according to the time carried by the first data frame, including: the first board parses the time carried by the first data frame to obtain the first time, and obtains the second time when the first data frame is received; and the first board determines the first difference between the first time and the second time. Afterwards, the first board sends a calibration data frame to the second board, and obtains the second difference fed back by the second board; the calibration data frame carries: the time when the calibration data frame is generated by the first board based on the local clock record, and the second difference indicates: the difference between the time when the calibration data frame is received by the second board and the time carried by the calibration data frame. The first board also determines the calibration time according to the first difference and the second difference, and adjusts the clock in the first board to the clock in the second board according to the calibration time. The calibration time indicates the difference between the clock in the first board and the clock in the second board.

[0017] Exemplarily, the manner in which the first board obtains the second difference may include, but is not limited to: the first board receives a return data frame fed back by the second board according to the calibration data frame, and parses the return data frame to obtain the second difference.

[0018] In the present application, the first single board can obtain the calibration time according to the line delay between different single boards and comprehensively consider the line delay of the receiving and transmitting lines, such as the difference between the clock in the first single board and the clock in the second single board. Then, the first single board can realize the time calibration between the first single board and the second single board based on the calibration time, which is beneficial to improve the accuracy of time synchronization between different single boards.

[0019] In an optional implementation, the frame lengths of any two data frames among the multiple consecutive data frames received by the first board are the same. When the bandwidth between different boards is determined, the frame lengths of the data frames transmitted between different boards are the same, and the communication duration of each data frame between different boards is consistent, so that the intervals between any two adjacent data frames received by the board are consistent, which is conducive to improving the accuracy of the board in achieving time synchronization based on the time carried by the data frame.

[0020] In an optional implementation, each data frame also includes at least one of a channel information field and a frame allocation information field. The channel information field includes: one or more channel data, each channel data includes: control information, service data or Ethernet packet information, and a channel number, a sequence number and a channel check number. The channel number is used to describe the first stream to which the channel data belongs, and the sequence number is used to describe the position of the channel data in the first stream. The frame allocation information field is used to record: the channel number of each channel in each data frame and the data length of each channel. The channel check number is a verification method used to verify that the data does not change during the communication process. Different types of data can be transmitted through the data frame provided by the present application. Since the data frame can be transmitted through the differential signal lines between each single board, each single board multiplexes different channels in the differential signal to transmit different types of data, and the total number of signal lines required for each single board to realize data communication is reduced, which is conducive to reducing the hardware cost of a communication device containing multiple single boards.

[0021] In an optional implementation, each data frame further includes: a calibration value between the time when the second board generates each data frame and the time when each data frame is sent. It is worth noting that there is inevitably a delay between the time collected by the board in the process of generating the data frame and the time when the data frame is sent. In the process of time synchronization, the board takes this delay into account in the time carried by the data frame, which is beneficial to the accuracy of time synchronization performed by other boards according to the data frame.

[0022] In a second aspect, the present application provides a time synchronization method. The method is executed by a second single board, and the second single board is connected to the first single board through two differential signal lines. The time synchronization method includes: the second single board generates a data frame to be sent based on the time recorded by the local clock of the second single board. And, the second single board sends a data frame to the first single board through the two differential signal lines, and the data frame instructs the first single board to adjust the clock in the first single board so that the difference between the clock in the first single board and the clock in the second single board is reduced.

[0023] During the communication process, different boards transmit data frames in the form of differential signals. The board can parse the time carried by the data frame without comparing the time carried by the data frame with the flip threshold of the board, and the parsed time will not change due to the temperature, aging, device process, etc. of the board, which is beneficial to improving the accuracy of the board using the parsed time to achieve time synchronization.

[0024] In an optional implementation, the time information carried by the data frame includes: the sending time of a specified bit in a frame header of the data frame. Exemplarily, the specified bit in the frame header is the first bit in the frame header.

[0025] In an optional implementation manner, the frame lengths of any two data frames in a plurality of consecutive data frames are the same.

[0026] In an optional implementation, the time synchronization method provided by the present application further includes: the second single board receives the calibration data frame sent by the first single board according to the data frame; the calibration data frame carries: the time when the first single board generates the calibration data frame based on the local clock record. And, the second single board sends a data frame carrying calibration difference information to the first single board, and the calibration difference information indicates the difference between the time when the second single board receives the calibration data frame and the time carried by the calibration data frame.

[0027] In a third aspect, the present application provides a time synchronization method. The time synchronization method is applied to a communication device including a first single board and a second single board, and the first single board and the second single board are connected by two differential signal lines. The time synchronization method includes: the second single board generates multiple continuous data frames to be sent, and each data frame includes: the time of generating each data frame based on the local clock record in the second single board. The first single board receives multiple continuous data frames sent by the second single board through two differential signal lines. And, the first single board determines a first data frame from multiple continuous data frames, and adjusts the clock in the first single board according to the time carried by the first data frame, so that the difference between the clock in the first single board and the clock in the second single board is reduced, and the first data frame is any one of the multiple continuous data frames.

[0028] In a fourth aspect, the present application provides a communication device. The communication device includes: a processor and a transceiver. The transceiver is used to receive multiple consecutive data frames, and the transceiver and the processor are used to be included in a first single board and cooperate to execute the method of the first aspect or any optional implementation method of the first aspect.

[0029] In a fifth aspect, the present application provides a communication device. The communication device includes: a processor and a transceiver. The transceiver and the processor are used to be included in a second single board and cooperate to execute the method of the second aspect or any optional implementation manner of the second aspect.

[0030] It is worth noting that when the communication devices provided in the fourth aspect and the fifth aspect are in the same communication system, the communication system can also be used to implement the time synchronization method provided in the third aspect.

[0031] Regarding the beneficial effects of any implementation of the third to fifth aspects, reference may be made to the description of the first aspect, the second aspect, or any optional implementation of the first aspect and the second aspect, which will not be repeated here. Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a communication device provided by the present application;

[0033] Figure 2 A schematic diagram of the structure of a time synchronization system provided by this application;

[0034] Figure 3 A schematic diagram of a time synchronization method provided in this application Figure 1 ;

[0035] Figure 4 A schematic diagram of the data frame transmission process provided by this application;

[0036] Figure 5 A time synchronization schematic diagram provided for this application;

[0037] Figure 6 A schematic diagram of a time synchronization method provided in this application Figure 2 ;

[0038] Figure 7 The format of the data frame provided for this application is shown in FIG. Figure 1 ;

[0039] Figure 8 The format of the data frame provided for this application is shown in FIG. Figure 2 ;

[0040] Fig. 9 The format of the data frame provided for this application is shown in FIG. Figure 3 ;

[0041] Fig.10 A schematic diagram of a data frame transmission provided by this application;

[0042] Fig.11 A time synchronization diagram provided for this application Figure 2 ;

[0043] Fig.12 A schematic diagram of the structure of a communication device provided in this application. DETAILED DESCRIPTION

[0044] In order to make the embodiments of the present application clearer, explanations of relevant terms are given below.

[0045] Time synchronization: The time indicated by the internal real-time clock (RTC) of each device must be consistent, and the time difference between the RTCs must be less than a certain value, as well as the actions or processes that each device must perform to achieve this time difference.

[0046] Time accuracy: The maximum time difference between the RTCs of each device after they perform time synchronization.

[0047] Data frame: The data unit transmitted by different boards for data communication.

[0048] In order to make the description of the following embodiments clear and concise, a brief introduction to the related technology is first given.

[0049] Figure 1 A schematic diagram of the structure of a communication device provided in the present application. The communication device 100 includes multiple boards and differential signal lines connecting the boards. For example, the multiple boards include: board 101, board 102, board 103 and other boards; for example, board 101 and board 102 are connected via differential signal line 10, and board 101 and board 103 are connected via differential signal line 20.

[0050] The single board provided in the embodiment of the present application may include but is not limited to: a main control board, a service board or a single board realizing other functions. The main control board (main processing unit, MPU) is responsible for the control plane and management plane of the communication device 100. The control plane can be used to complete the functions of protocol processing, service processing, routing calculation, forwarding control, service scheduling, traffic statistics and system security of the communication system. The management plane can be used to complete the functions of operation status monitoring, environmental monitoring, log and alarm information processing, system loading and upgrading of the communication system. The service board can be used to realize different service types according to different user needs, such as optical interface, electrical interface, firewall wireless board, etc.

[0051] In one possible approach, Figure 1 Each single board in the device can be integrated into one device, and each single board can be fixed on a printed circuit board (PCB), and the PCB has a signal line. Each single board can be fixed to the PCB through a slot provided by the signal line in the PCB, so as to realize data communication between each single board. When each single board is located in one device, the communication device 100 can refer to a multi-core processor or chip, or a router, switch, server, mobile phone, personal computer, tablet computer, smart TV or other electronic device including the chip.

[0052] In another possible approach, Figure 1 Each single board in the communication device 100 may be in different devices, such as single board 101 is a main control board in a first device, and single board 102 is a main control board in a second device. The first device and the second device may communicate via a serializer / deserializer (SERializer / DESerializer, Serdes) interface and a signal line connecting the Serdes interface. When each single board is located in a different device, the communication device 100 may refer to a frame device provided with multiple slots, and each single board is connected to the frame device in a pluggable manner. The frame device may include, but is not limited to: a network device with its own external frame, which may also be generally installed in a network cabinet.

[0053] As an optional example, different boards may be connected via differential signal lines, which are used to transmit data frames between different boards.

[0054] Exemplarily, the differential signal line 10 may include at least one of a first group of differential signal lines and a second group of differential signal lines, each group of differential signal lines includes at least two signal lines. For example, the first group of differential signal lines includes signal line 1 and signal line 2, and the second group of differential signal lines includes signal line 3 and signal line 4.

[0055] For example, the first group of differential signal lines is used to transmit data frames between the single board 101 and the single board 102; the second group of differential signal lines is used to transmit data frames between the single board 101 and the single board 102 when the first group of differential signal lines is in a fault state.

[0056] In some possible scenarios, the first group of differential signal lines are called main differential signal lines or main lines between single board 101 and single board 102, and the second group of differential signal lines are called spare differential signal lines, spare differential signal lines or spare lines between single board 101 and single board 102.

[0057] Compared with the use of single-ended signals for time synchronization in different boards, where the flip threshold of the boards is affected by the temperature, aging, device process, etc. of different boards, the present application uses differential signal lines to transmit data frames. The boards parse the data frames without considering the differences in hardware or operating environments of different boards, so that the boards can obtain more accurate time information based on the data frames, thereby improving the accuracy of time synchronization.

[0058] Figure 1 This is only an example provided in the embodiment of the present application. The communication device may include more or fewer hardware components, and the present application is not limited to this.

[0059] by Figure 1 The single board 101 is a main control board, and the single board 102 is a service board. Figure 2 As shown, Figure 2 The main control board 210 can be used to implement the functions of the single board 101, and the business board 220 can be used to implement the functions of the single board 102. The main control board 210 and the business board 220 communicate with each other through two differential signal lines. For the specific implementation of the differential signal line, please refer to Figure 1 The relevant description is not repeated here.

[0060] The main control board 210 and the service board 220 can realize various types of signal communication through differential signal lines, such as data frames carrying time to be synchronized, control information, service data or other Ethernet packet information, etc. For example, the common technical solution is to use one line to transmit a pulse per second (pps) signal (single-ended signal), and the technical solution provided in this embodiment is to use a pair of lines to transmit a pps signal (differential signal), and the differential signal line can transmit a higher rate signal.

[0061] It is worth noting that the main control board 210 and the service board 220 also provide different types of interfaces to other devices or hardware: Figure 2 The main control board 210 and the service board 220 may further transmit control information through the control interface and transmit the status information of the single board through the status interface.

[0062] Compared with the main control board 210 and the business board 220 that use different types of signal lines to transmit single-ended signals, and the flip threshold of the boards is affected by the temperature, aging, device process, etc. of different boards, in the present application, differential signal lines can be used to transmit data frames, and the boards parse the data frames without considering the differences in hardware or operating environment of different boards, so that the boards can obtain more accurate time information based on the data frames, thereby improving the accuracy of time synchronization.

[0063] As a possible specific implementation method, Figure 2 As shown, taking the main control board 210 as an example, the main control board 210 includes: a framer 211, a local real-time clock (RTC 1), a data sending terminal Serdes tx based on a Serdes interface, and a data receiving terminal Serdes rx. The framer 211 generates a data frame for implementing time synchronization in response to a time synchronization request. RTC 1 is used to provide timing time for the main control board 210, and to provide the time of the main control board 210 when the framer 211 generates a data frame. Serdestx is used to send data to other boards or devices outside the main control board 210, and Serdes rx is used to receive data sent to the main control board 210 by other boards or devices.

[0064] In some cases, the RTC 1 is also called a time counter, a timing clock, or a local clock of the main control board 210. In hardware implementation, the RTC 1 may refer to a unit or entity that outputs time like a clock.

[0065] The service board 220 includes: a framer 211, RTC 2, Serdes tx and Serdes rx. For the hardware implementation of the service board 220, reference can be made to the description of the main control board 210, which will not be described in detail here. After the service board 220 receives the data frame sent by the main control board 210 through the differential signal line, it parses the data frame to obtain time information and realizes time synchronization between RTC 1 and RTC 2. It is worth noting that, depending on the difference in the service functions that can be realized, the service board 220 may include more or fewer devices, which is not limited in this application.

[0066] above Figure 2 The scenes of the main control board 210 and the service board 220 shown are only examples provided in this embodiment, and it should not be understood that the time synchronization method provided in this application can only be applied to Figure 2 For example, the time synchronization method provided in the present application can also be applied between two main control boards or between two service boards, and the present application does not limit this.

[0067] The time synchronization method provided in the present application is described in detail below, assuming that the main control board 210 is the master time board and the service board 220 is the slave time board. Figure 3 A schematic diagram of a time synchronization method provided in this application Figure 1 , single board 310 can be used to implement Figure 2 Central control board 210 or Figure 1 The function of single board 101, single board 320 can be used to achieve Figure 2 Medium business board 220 or Figure 1 The function of the middle board 102.

[0068] The single board 310 and the single board 320 are connected by two differential signal lines. For the specific implementation of the differential signal lines, please refer to Figure 1 and Figure 2 The relevant description will not be repeated here.

[0069] like Figure 3 As shown, the time synchronization method provided by this embodiment includes the following steps S301 to S304.

[0070] S301. The board 310 generates a plurality of continuous data frames to be sent.

[0071] Each data frame carries the time when the data frame is generated as recorded by the local clock in the board 310 .

[0072] Exemplarily, the time of generating the data frame recorded by the local clock in the single board 310 includes: the time recorded by the local clock (such as RTC 1) collected by the single board 310 to generate each data frame, and the calibration value between the time and the second time of sending each data frame.

[0073] Combination Figure 2 For example, the time collected by the single board 310 for generating each data frame refers to: the framer 211 collects the time recorded by RTC 1 in response to the request for executing time synchronization to obtain the time. In a possible specific example, the framer 211 continuously generates data frames of fixed frame length in sequence, and obtains the time recorded by the local real-time clock (such as RTC 1) of the single board before sending the data frame, and fills the recorded time into the time information position (or time information field) of the data frame.

[0074] In the single board 310, there is inevitably a delay between the time of generating a data frame and the time of sending the data frame, and the time of the delay is called a calibration value. For example, the calibration value is 5 nanoseconds (ns). It is worth noting that the hardware components of different single boards are different, and the values ​​of the calibration values ​​are also different. In the process of time synchronization, the single board takes this delay into account in the time information carried by the data frame, which is beneficial to the accuracy of time synchronization performed by other single boards according to the data frame.

[0075] As an optional implementation, the frame lengths of any two data frames in the multiple continuous data frames provided by S301 are the same. The frame length refers to the data length of the data frame. Exemplarily, the frame length is 19.44 million bytes (MB) or other values. In some feasible situations, the length of each data frame can be determined based on the bandwidth and communication frequency between the boards, where the bandwidth refers to the maximum amount of data that can be transmitted per unit time, and the communication frequency refers to the maximum frequency of communication that can be performed per unit time.

[0076] When the bandwidth between different boards is determined, the frame lengths of data frames transmitted between different boards are the same, and the communication duration of each data frame between different boards is consistent, so that the intervals between any two adjacent data frames received by the boards are consistent, which is beneficial to improving the accuracy of time synchronization performed by the boards according to the time carried by the data frames.

[0077] S302 . The board 310 sends the generated multiple continuous data frames through two differential signal lines.

[0078] Since the differential signal is determined by comparing the difference between two ordinary signals with the same signal edge and opposite flipping directions, the differential signal includes a valid information segment (or valid information) and an invalid information segment (or common mode signal). Figure 3As shown, in a set of differential signals, a difference signal between two common signals with the same edge and opposite flipping directions is used to transmit a data frame.

[0079] During the communication process, different boards transmit data frames in the form of differential signals, and the data frames are carried in the valid information segment of the differential signals. Therefore, the board can parse the time carried by the data frame without comparing the time carried by the data frame with the flip threshold of the board, which is beneficial to improving the time synchronization accuracy between boards.

[0080] Corresponding to step S302, the single board 320 on the receiving side executes step S303.

[0081] S303 , the single board 320 receives multiple continuous data frames sent by the single board 310 through two differential signal lines.

[0082] Corresponding to the content of S302, each data frame carries a valid information segment of the differential signal, and the valid information segment includes: the time when each data frame is generated as recorded by the local clock in the single board 310. For the content of the time when each data frame is generated as recorded by the local clock in the single board 310, reference can be made to the relevant description of S301, which will not be repeated here.

[0083] S304 , the board 320 determines a first data frame from a plurality of continuous data frames, and adjusts a clock in the board 320 according to a time carried in the first data frame, so that a difference between a clock in the board 310 and a clock in the board 320 is reduced.

[0084] The first data frame is any one of a plurality of continuous data frames received by the single board 320 .

[0085] To avoid confusion, the time carried by the data frame and the clock in the board are distinguished here: the clock in the board is used to record the local time of the board (absolute time value), and the clock in the board will keep counting as time changes; the time carried by the data frame includes: the time when the data frame is generated as recorded by the local clock in the board.

[0086] In some optional implementations, the time carried by the first data frame also includes: the sending time of a specified bit in the frame header of the first data frame.

[0087] In some possible examples, the designated bit in the frame header of the first data frame is the first bit in the frame header.

[0088] In some other possible examples, the designated bit in the frame header of the first data frame is other bits in the frame header, such as the last bit or the i-th bit, where i is a positive integer greater than or equal to 2 and less than the maximum bit width of the frame header.

[0089] Combined with the data frame generation process provided by S301 and Figure 2 The content of the main control board 210 in the data frame header is illustrated by an example of the sending time of the specified bit, such as Figure 4 As shown, Figure 4 The schematic diagram of the data frame transmission process provided for this application. Take two boards inside a chip as an example. Inside the chip, the data is sent to the differential signal line corresponding to the Serdes interface one by one according to the bit width. Since the frame length of each data frame is the same, the Serdes sends the data to other boards in sequence according to the bit width of 1 bit. Therefore, the frame header of each data frame represents the transmission time corresponding to the time in the data frame.

[0090] In the master time board (master control board 210), in order to accurately indicate the time when the specified bit in the frame header of the entire data frame is sent by the master time board, a calibration value is also added. For example, the framer 211 reads the time in RTC 1 (the time of the specified bit locked, such as Figure 4 The time from 1 in the figure to the sending time of the specified bit (such as Figure 4 The delay time of time 2) in the first data frame is 5 ns, and the calibration value = 5 ns, thereby realizing that the time information carried in the first data frame is the sending time of the specified bit in the frame header of the first data frame.

[0091] Among them, the frame header of the data frame of the first beat includes 01011010, the frame header of the data frame of the second beat includes 11011010, and the frame header of the data frame of the third beat includes 11010010.

[0092] In the slave time board (service board 220), the service board 220 receives each beat of data in sequence and performs a matching comparison on the frame header time. In this embodiment, the bit width for each frame header time judgment is 4, and A is the position of the first byte of the match. The value of A is determined based on the result of the frame header matching comparison, such as Figure 4 1 bit, 2 bits or 3 bits in the frame header. When judging the moment of finding the frame header, the following two methods can be used.

[0093] Method 1: time = X*10.

[0094] Method 2: time = X*10+A.

[0095] Among them, X indicates that the frame header of the data frame is found in the Xth beat, 10 refers to the bit width of each beat of data, and A refers to the position of the first byte matched to the frame header. Both method 1 and method 2 can be used to determine the moment of the frame header, but method 2 introduces A, so that the determination of the frame header moment can be accurate to the bit level, which is conducive to further improving the time synchronization accuracy between different boards.

[0096] It is worth noting that the time synchronization operation described in S304 makes the clock in the single board 320 consistent with the clock in the single board 310.

[0097] like Figure 5 As shown, Figure 5 A schematic diagram of time synchronization provided by this application. From the time board (such as Figure 3 After detecting the frame header of the first data frame, the board 320 locks the local clock (RTC) of the board 320 to: TL, and parses the time information carried by the first data frame as x, and obtains the first difference (or difference T1). In addition, the board 320 determines the delay correction T2=db based on the line delay d, the moment of the specified bit, and the difference b between the time of completely receiving a beat of data to which the specified bit belongs. Furthermore, the board 320 determines the time adjustment value △T=T2-T1 required for time synchronization based on the first difference T1 and the delay correction T2. ​​Finally, the board 320 adjusts the clock (RTC) in the board 320 based on the time adjustment value △T, so that the difference between the clock in the board 320 and the clock in the board 310 is reduced or the clock in the board 320 and the clock in the board 310 are kept consistent.

[0098] During the communication process, different boards transmit data frames in the form of differential signals, and the data frames are carried in the valid information segment of the differential signals. Therefore, the board can parse the time information carried by the data frame without comparing the time information carried by the data frame with the flip threshold of the board, and the parsed time information will not change due to the temperature, aging, device process, etc. of the board, which is beneficial to improving the accuracy of the board using the parsed time information and the sending time of the specified bit in the frame header of the data frame to perform time synchronization.

[0099] In common technology, when a single-ended signal is used to achieve time synchronization on a single board, the single-ended signal has a low channel bandwidth, a large loss of high-frequency components, and a slow slope on the rising edge during transmission. T The voltage (threshold voltage) is high and is lower than V T The voltage is low, V T The voltage will vary slightly due to different environments and devices. Under this sampling method, the rising edge of this voltage will slow down and the moment when it reverses to a high level will change, resulting in a loss of time synchronization accuracy within ±2ns.

[0100] In contrast, in the time synchronization method provided in this embodiment, the board performs serial-to-parallel conversion on the differential signal, separates the clock and data, and determines the sending time by locating the frame header of the data frame. Since the differential signal speed is very high, the frame header can be located to 1 bit, for example, the 1 bit accuracy of 10G is ±0.05ns, which improves the accuracy of time synchronization.

[0101] exist Figure 3 Based on this, the time synchronization process between boards is described in detail below in combination with the line delay between different boards. Figure 6 As shown, Figure 6 A schematic diagram of a time synchronization method provided in this application Figure 2 , the above S304 may include the following S610 to S650.

[0102] S610. The board 320 parses the time carried in the first data frame to obtain a first time, and acquires a second time when the first data frame is received.

[0103] The first time is also referred to as time 1 when the master time board (board 310) sends the first data frame, and the second time is also referred to as time 2 when the slave time board (board 320) receives the first data frame.

[0104] S620. The board 320 determines a first difference between the first time and the second time.

[0105] The first difference is also called the downlink delay from the master time board (board 310) to the slave time board (board 320).

[0106] S630: The board 320 sends a calibration data frame to the board 310, and obtains a second difference value fed back by the board 310 according to the calibration data frame.

[0107] The calibration data frame includes: the time when the single board 320 generates the calibration data frame based on the local clock record in the single board 320.

[0108] The second difference indicates: the difference between the time when the calibration data frame is received by the single board 310 and the time carried by the calibration data frame. The time information carried by the calibration data frame is also called the time 3 of the slave time single board (single board 320), and the time when the single board 310 receives the calibration data frame is also called the time 4 of the master time single board. The second difference is also called the uplink delay from the time single board (single board 320) to the master time single board (single board 310).

[0109] With respect to the process of the single board 310 feeding back the second difference, this embodiment provides an optional implementation method: the single board 310 receives the calibration data frame sent by the single board 320 according to the data frame, and sends a data frame carrying calibration difference information to the single board 320. The calibration data frame carries the time information used by the first single board to generate the calibration data frame (such as the time of generating the calibration data frame recorded by the local clock in the single board 320 and the time between), and the calibration difference information indicates the difference between the time when the second single board receives the calibration data frame and the time carried by the calibration data frame.

[0110] S640. The board 320 determines a calibration time according to the first difference and the second difference.

[0111] The calibration time indicates the difference between the clock in the board 320 and the clock in the board 310 .

[0112] For example, for the two determined boards, the lengths of the receiving and transmitting lines between the boards are equal, so the delays of the receiving and transmitting lines should also be the same. The following is an example of the calibration time determination process in conjunction with the above time 1 to time 4.

[0113] Step ①: Set the delay time from single board 310 to single board 320 to be equal.

[0114] Step ②: Set the time difference between the RTC in the board 320 and the RTC in the board 310 to x, where x is the calibration time.

[0115] Step ③: Downlink delay = (time 2-x)-time 1.

[0116] Step ④: Uplink delay = time 4 - (time 3 - x).

[0117] Step ⑤: Uplink delay = downlink delay, that is: (time 2-x)-time 1 = time 4-(time 3-x), and the calibration time x = (time 2-time 1+time 4-time 3) / 2.

[0118] For moments 1 to 4 and the calibration time x in this embodiment, a possible specific example is provided: Moment 1 = 8:05:2.0000000009 seconds on j-month-1, 200i, Moment 2 = 8:05:2.00000000019 seconds on j-month-1, 200i, Moment 3 = 8:05:3.00000000031 seconds on j-month-1, 200i, Moment 4 = 8:05:3.00000000039 seconds on j-month-1, 200i, then the calibration time x = (2.0000000019-2.0000000009+3.00000000039-3.00000000031) / 2 = 0.9ns.

[0119] The above steps are only a possible determination process of the calibration time provided in this embodiment and should not be understood as a limitation of the present application. In some possible situations, the user may also manually set the compensation value of the calibration time, which is not limited in the present application.

[0120] S650 , the board 320 adjusts the clock in the board 320 to the clock in the board 310 according to the calibration time.

[0121] In this embodiment, the slave time board can obtain the calibration time according to the line delay between different boards and comprehensively consider the line delay of the receiving and sending lines, and obtain the difference between the clock in the slave time board and the clock in the master time board (such as the calibration time mentioned above). Furthermore, the slave time board can realize the time calibration between the clock in the slave time board and the clock in the master time board based on the calibration time, which is beneficial to improve the accuracy of time synchronization between different boards.

[0122] In an optional implementation, the data frame includes multiple fields: frame header, frame count, time information, frame allocation information, channel information, frame check and other fields. The format of the data frame is described in detail below in conjunction with the accompanying drawings. Figure 7 As shown, Figure 7 The format of the data frame provided for this application is shown in FIG. Figure 1 The frame header field is 64 bytes, the frame count field is 64 bytes, the time information field is 128 bits, and the frame allocation information field is 4 bytes × 256.

[0123] The frame header is used to identify the starting position of the data frame, and the information recorded in the frame count field is used to record the sequence number of the data frame.

[0124] The time information field is used to carry the time carried by the data frame. Figure 7 As shown, the time information field includes: type field, domain field, information field and check field. Among them, the information field and check field are mandatory fields. The information field includes a 48-bit specific field, and the check field includes a 13-bit specific character; the type field (11 bits) and the domain field (8 bits) are optional fields, and the domain field is used to describe the domain of the time information stored in the information field.

[0125] When generating a data frame, the board uses a fixed field to record the time carried by the data frame, so that the board that receives the data frame can quickly locate the fixed field and parse the time carried by the data frame. This is beneficial to improving the time synchronization efficiency between different boards and avoids the problem of low synchronization accuracy caused by the board traversing all fields in the data frame to output time information.

[0126] The Type field is used to describe the type of time stored in the Information field. Several possible examples are given below for the content described by the Type field.

[0127] In the first possible example, the content described in the type field is 0×0, which indicates that the time type is standard time, and the standard time indicates the time when the single board 310 sends the data frame. For example, the standard time includes: 48-bit seconds + 32-bit nanoseconds + 16-bit nanosecond fractions.

[0128] In the second possible example, the content described in the type field is 0×1, which indicates that the time type is the first deviation time, and the first deviation time indicates the time delay compensation value of the single board 310. For example, the highest bit in the first deviation time is used to determine whether the time delay compensation value is positive or negative.

[0129] In the third possible example, the content described in the type field is 0×2, which indicates that the type of time is the second deviation time, and the second deviation time indicates the difference between the acquisition time and the sending time of each data frame generated by the single board 310. In some possible situations, the second deviation time can also be used to monitor the synchronization state of the slave time single board.

[0130] In this embodiment, the board can quickly determine the required parsing method for the time information recorded in the aforementioned information field through the type of time information recorded in the type field, which is beneficial to improving the time synchronization efficiency and time synchronization accuracy between different boards.

[0131] Below Figure 7 Based on the content shown, the frame allocation information field is described in detail, such as Figure 8 As shown, Figure 8 The format of the data frame provided for this application is shown in FIG. Figure 2 The frame allocation information field is used to record: the channel number of each channel in each data frame and the data length of each channel. The frame allocation information field is a continuous 4-byte × 256. Taking the content of one of the 4 bytes as an example, the first byte is the channel number, and the next 3 bytes indicate the data length of the channel information corresponding to the channel number. The channel number is used to describe the data stream to which the channel data in the channel information belongs.

[0132] Below Figure 7 and Figure 8 Based on the content shown, the channel information field is described in detail, such as Fig. 9 As shown, Fig. 9 The format of the data frame provided for this application is shown in FIG. Figure 3 The channel information field includes one or more channel data, each of which includes control information, service data or Ethernet packet information, such as Fig. 9 Data 1 or data 2 in .

[0133] Optionally, the channel data also includes: a channel number, a serial number and a channel check number.

[0134] The channel number is used to describe the first stream to which the channel data belongs. Taking channel information 1 as an example, the 1-byte channel number is used to describe: the first stream indicates the data stream to which data 1 belongs.

[0135] The sequence number is used to describe the position of the channel data in the first stream. Taking channel information 1 as an example, the 2-byte sequence number is used to describe: the specific position of data 1 in the first stream.

[0136] The channel check number is a check method used to check that data does not change during the communication process. For example, the channel check number may refer to a cyclic redundancy check (CRC) code or other codewords with check data.

[0137] For example, in Figure 2 Based on the signals corresponding to the interfaces in the embodiment, this embodiment provides a possible example, such as Fig.10 As shown, Fig.10 A schematic diagram of a data frame transmission provided by the present application. The master time board may refer to Figure 2 The main control board 210 or Figure 3 In the single board 310, the single board can refer to Figure 2 Business board 220 or Figure 3 The board 320 in the data frame. The status signal is carried on the channel 1 of the data frame, the control information is carried on the channel 2 of the data frame, the SMI signal is carried on the channel 3 of the data frame, and the UART signal is carried on the channel 4 of the data frame. The master time board and the slave time board are connected through Serdes; the slave time board parses the received data frame to obtain the data transmitted by each channel: the status signal, the control information, the SMI signal and the UART signal.

[0138] Different types of data can be transmitted through the data frames provided in the present application. Since the data frames can be transmitted through the differential signal lines between the single boards, each single board transmits different types of data by multiplexing different channels in the differential signal. The signal lines required for each single board to achieve data communication are reduced, which is conducive to reducing the hardware cost of the communication device including multiple single boards.

[0139] In the present application, high-precision time information is transmitted between single boards through high-speed differential signals. The bandwidth occupancy rate of high-precision time + time information is very low, and the remaining bandwidth can be reused for the transmission of other signals and information. For example, the remaining bandwidth can transmit control signals, Ethernet packet information, and peripheral component interconnect express (PCIe) control information. In addition, compared with the conventional technology, different single boards require 35 signal lines to complete the transmission of various signals. This embodiment uses differential signal lines and only requires 8 signal lines (2 signal lines for sending and receiving, and with master and backup), which reduces the hardware cost of the chip.

[0140] Combined with the time synchronization method provided in the above embodiment and Figure 2 The architecture of the present invention provides a specific example of a possible time synchronization method, taking the main control board 210 as the master time board and the business board 220 as the slave time board as an example. Fig.11 As shown, Fig.11 A time synchronization diagram provided for this application Figure 2 The function of synchronizing the time of the master time board to the slave time board so that the time of the slave RTC (RTC 2) is equal to the time of the master RTC (RTC 1) is called time synchronization. The final difference between the master and slave RTCs is the synchronization accuracy. The time synchronization method includes the following steps 1 to 6.

[0141] Step 1: The control information of the main control board 210 is transmitted to the service board 220 through channel x, and the control information (status information) of the slave is transmitted to the master device through channel x. The Ethernet packet is transmitted between the master and slave boards through another channel.

[0142] Step 2: RTC 1 is a local time counter of the main control board 210, and the framer 211 obtains time information from RTC 1 to form a specified data frame.

[0143] The time information acquired by the framer 211 may include time 1 and calibration value. Figure 4 The relevant description will not be repeated here.

[0144] The framer 211 can perform scrambling processing on other data in the data frame except the frame header, and the scrambling code can be set.

[0145] Step 3: The Serdes transmitter (Serdes tx) in the main control board 210 sequentially reads the data frame data from the framer 211 and sends it out serially.

[0146] Step 4: The Serdes receiver (Serdes rx) in the service board 220 receives the serial data.

[0147] The service board 220 performs frame delimitation on the received serial data. Frame delimitation means that the service board 220 determines the starting position and the ending position of a data frame in the serial data by marking the beginning and the end of the frame. The frame delimitation method may include but is not limited to: at least one of the character counting method, the head and tail delimiter method with character filling, the head and tail flag method with bit filling, and the physical layer coding violation method.

[0148] Taking the head and tail marking method with bit filling as an example, the process of frame delimitation is exemplified. The frame header of each data frame carries a string of specific bits (such as 0101). If the service board 220 recognizes the specific bits, the service board 220 determines to recognize the frame header of a data frame, and regards the data before the next frame header in the serial data as the data of the data frame, thereby realizing the frame delimitation of the data frame. In some possible situations, frame delimitation is also called "frame synchronization".

[0149] In this embodiment, since the frame length of each data frame is the same, after the service board 220 finds the frame header of data frame 1 (such as the specific bits at the starting position of the frame header are 0101), it can delay the frame length of one data frame and then identify the frame header of the next data frame.

[0150] For example, if the starting position of the frame header of the next data frame is a specific bit (such as 0101), the service board 220 determines that the frame delimitation of the data frame 1 is correct;

[0151] For another example, if the starting position of the frame header of the next data frame is not a specific bit (such as 0101), the service board 220 determines that the frame delimitation of data frame 1 is wrong. For example, the bits at the starting position of the frame header are 1111, and the specific bits are 0101. In the case where the service board 220 determines that the frame delimitation of data frame 1 is wrong (also called frame desynchronization), the service board 220 re-executes the above frame delimitation process, thereby selecting a data frame with a correct frame delimitation to perform the time synchronization process.

[0152] The above examples are only a possible implementation of the head and tail mark method with bit padding for this embodiment, and should not be understood as limiting the present application. The service board 220 may also use other frame delimiting methods to implement the frame delimiting of the data frame. The specific implementation methods of the character counting method, the head and tail delimiter method with character padding, and the physical layer coding violation method can refer to the description of the general technology, which will not be repeated here.

[0153] Step 5: The service board 220 descrambles the data frame that has been frame-delimited, and parses it according to the frame format to obtain control information, time information, Ethernet packet information, etc.

[0154] Step 6: The service board 220 adjusts the RTC 2 according to the sending time of the specified bit in the frame header of the data frame and the time carried by the data frame.

[0155] For the specific implementation of step 6, please refer to Figure 5The difference lies in the different execution entities. In step 6: the business board 220 makes a first difference (such as the aforementioned T1) between the local time of RTC 2 and the time when the data frame is received, and then transmits it back to the other end (main control board 210). When the other end (main control board 210) sends it again, it sends the second difference (such as the aforementioned T2) determined by the other end (main control board 210) to the business board 220. The business board 220 can analyze the difference between the two RTCs (calibration time, such as the aforementioned △T) by analyzing the difference between the first difference and the second difference, as well as the line delay of the receiving and sending lines. Furthermore, the business board 220 implements time calibration between the two RTCs according to the determined calibration time.

[0156] Optionally, the time difference information between the two RTCs caused by line delay can also be manually compensated by the user according to actual time synchronization requirements, avoiding the problem of inaccurate calibration time caused by misjudgment of the single board.

[0157] The above example is explained using the example of the main control board 210 as the master time board and the business board 220 as the slave time board, but the main control board 210 can also be a slave time board and the business board 220 can also be a master time board. The time synchronization method is the same as the above embodiment and can achieve the same beneficial effect. The difference lies in the interchange of the execution subjects, which will not be repeated here.

[0158] It is understandable that in order to implement the functions in the above embodiments, the computing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0159] like Fig.12 As shown, Fig.12 The present invention provides a schematic diagram of a communication device. The communication device may be a terminal device or a network device, or may be a chip (system) or other components or assemblies that can be set in the terminal device or the network device. Fig.12 As shown, the communication device 1200 may include a processor 1201. Optionally, the communication device 1200 may further include a memory 1202 and / or a transceiver 1203. The processor 1201 is coupled to the memory 1202 and the transceiver 1203, such as being connected via a communication bus.

[0160] Combine the following Fig.12 The components of the communication device 1200 are described in detail:

[0161] The processor 1201 is the control center of the communication device 1200, and may be a processor or a general term for multiple processing elements. For example, the processor 1201 is one or more central processing units (CPUs), or may be an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application, such as one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs).

[0162] Optionally, the processor 1201 may execute various functions of the communication device 1200 by running or executing a software program stored in the memory 1202 and calling data stored in the memory 1202. In a specific implementation, as an embodiment, the processor 1201 may include one or more CPUs, such as Fig.12 CPU0 and CPU1 are shown in FIG.

[0163] Optionally, the communication device 1200 may also include multiple processors, such as Fig.12 1 and 1204. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0164] The memory 1202 is used to store the software program for executing the solution of the present application, and is controlled by the processor 1201 to execute. The specific implementation method can refer to the above method embodiment, which will not be repeated here. Exemplarily, the memory 1202 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory 1202 can be integrated with the processor 1201, or it can exist independently and be accessed through the interface circuit ( Fig.12 ) is coupled to the processor 1201, which is not specifically limited in the embodiment of the present application.

[0165] The transceiver 1203 is used for communication with other communication devices. For example, the communication device 1200 is a terminal device, and the transceiver 1203 can be used to communicate with a network device, or with another terminal device. For another example, the communication device 1200 is a network device, and the transceiver 1203 can be used to communicate with a terminal device, or with another network device. For another example, the communication device 1200 is a multi-core chip, and the transceiver 1203 can be used to communicate with another multi-core chip.

[0166] Optionally, the transceiver 1203 may include a receiver and a transmitter ( Fig.12 The receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0167] Optionally, the transceiver 1203 may be integrated with the processor 1201, or may exist independently and communicate with the processor 1201 through the interface circuit ( Fig.12 ) is coupled to the processor 1201, which is not specifically limited in the embodiment of the present application.

[0168] Exemplarily, the communication device 1200 may refer to any of the aforementioned boards, such as board 101, board 102, board 103, board 310, board 320, main control board 210 or business board 220, etc.

[0169] It should be noted that Fig.12 The structure of the communication device 1200 shown in the figure does not constitute a limitation on the communication device. The actual communication device may include more or fewer components than those shown in the figure, or combine certain components, or arrange the components differently.

[0170] In addition, the technical effects of the communication device 1200 can refer to the technical effects of the time synchronization method described in the above method embodiment, and will not be repeated here.

[0171] The embodiment of the present application provides a communication system. The communication system includes at least two communication devices mentioned above. Optionally, the communication system may also include: one or more forwarding devices, which are used to forward data packets sent by the source communication device until the data packets reach the destination communication device.

[0172] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0173] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0174] The present application also provides a chip system, which includes a processor for implementing the functions of the data processing unit in the above method. In one possible design, the chip system also includes a memory for storing program instructions and / or data. The chip system can be composed of a chip, or can include a chip and other discrete devices.

[0175] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc (DVD); it may also be a semiconductor medium, for example, a solid state drive (SSD).

[0176] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A time synchronization method, characterized in that: The method is performed by a first single board, the first single board is connected to a second single board via two differential signal lines, and the method includes: Receiving a plurality of continuous data frames sent by the second single board through the two differential signal lines, each data frame including: a time of generating each data frame recorded based on a local clock in the second single board; Determine a first data frame from the multiple consecutive data frames, and adjust the clock in the first board according to the time carried by the first data frame, so that the difference between the clock in the first board and the clock in the second board is reduced, and the first data frame is any one of the multiple consecutive data frames.

2. The method according to claim 1, characterized in that: The time carried by the first data frame includes: the sending time of a specified bit in the frame header of the first data frame.

3. The method according to claim 2, characterized in that The designated bit in the frame header is the first bit in the frame header.

4. The method according to claim 1, characterized in that The time of generating the first data frame recorded by the clock in the second board is carried in the time information field of the first data frame, and the time information field includes: an information field and a check field; Alternatively, the time information field includes: at least one of a type field and a domain field, and an information field and a check field; The type field is used to describe the type of time stored in the information field, the type being standard time, first deviation time, or second deviation time, the first deviation time indicating a time delay compensation value of the second board, and the second deviation time indicating a difference between a collection time and a sending time of each data frame generated by the second board; The domain field is used to describe the domain of the time stored in the information field.

5. The method according to claim 1, characterized in that The adjusting the clock in the first board according to the time carried by the first data frame includes: Parsing the first time carried by the first data frame to obtain a first time, and acquiring a second time when the first data frame is received; determining a first difference between the first time and the second time; Send a calibration data frame to the second single board, and obtain a second difference value fed back by the second single board; the calibration data frame carries: the time when the calibration data frame is generated by the first single board based on the local clock record, and the second difference value indicates: the difference between the time when the second single board receives the calibration data frame and the time carried by the calibration data frame; determining a calibration time according to the first difference and the second difference; the calibration time indicating a difference between a clock in the first board and a clock in the second board; The clock in the first board is adjusted toward the clock in the second board according to the calibration time.

6. The method according to any one of claims 1 to 5, characterized in that The frame lengths of any two data frames in the multiple consecutive data frames are the same.

7. The method according to any one of claims 1 to 6, characterized in that Each of the data frames comprises at least one of a channel information field and a frame allocation information field; The channel information field includes: one or more channel data, each of which includes: control information, service data or Ethernet packet information, as well as a channel number, a sequence number and a channel check number; the channel number is used to describe the first stream to which the channel data belongs, and the sequence number is used to describe the position of the channel data in the first stream; The frame allocation information field is used to record: the channel number of each channel in each data frame and the data length of each channel.

8. The method according to any one of claims 1 to 7, characterized in that Each of the data frames further includes: a calibration value between the time when the second board generates each of the data frames and the time when the second board sends each of the data frames.

9. A time synchronization method, characterized in that: The method is performed by a second single board, the second single board is connected to the first single board via two differential signal lines, and the method includes: Generate a data frame to be sent based on the time recorded by the local clock of the second board; The data frame is sent to the first single board through the two differential signal lines, and the data frame instructs the first single board to adjust the clock in the first single board so that the difference between the clock in the first single board and the clock in the second single board is reduced.

10. The method according to claim 9, characterized in that The time carried by the data frame includes: the sending time of a specified bit in the frame header of the data frame.

11. The method according to claim 10, characterized in that The designated bit in the frame header is the first bit in the frame header.

12. The method according to any one of claims 9 to 11, characterized in that: The method further comprises: receiving a calibration data frame sent by the first board according to the data frame; the calibration data frame carries: a time when the calibration data frame is generated by the first board based on a local clock record; A data frame carrying calibration difference information is sent to the first board, where the calibration difference information indicates a difference between a time when the second board receives the calibration data frame and a time carried by the calibration data frame.

13. A time synchronization method, characterized in that: Applied to a communication device including a first single board and a second single board, the first single board and the second single board are connected via two differential signal lines, the method comprising: The second single board generates a plurality of continuous data frames to be sent; each data frame includes: the time of generating each data frame recorded in the second single board based on the local clock; The first single board receives a plurality of continuous data frames sent by the second single board through the two differential signal lines; The first single board determines a first data frame from the multiple consecutive data frames, and adjusts the clock in the first single board according to the time carried by the first data frame, so that the difference between the clock in the first single board and the clock in the second single board is reduced, and the first data frame is any one of the multiple consecutive data frames.

14. A communication device, characterized in that: include: A processor and a transceiver; the transceiver is used to receive multiple consecutive data frames, the transceiver and the processor are used to be included in a first single board, and cooperate to execute the method described in any one of claims 1-8.

15. A communication device, characterized in that: include: processors and transceivers; The processor and the transceiver are used to be included in a second single board and cooperate to execute the method of any one of claims 9-12.

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